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Infineon Ice3rbr0665jz Ds v02 00 en
Infineon Ice3rbr0665jz Ds v02 00 en
0, 7 Jun 2013
®
CoolSET -F3R
ICE3RBR0665JZ
N e v e r s t o p t h i n k i n g .
ICE3RBR0665JZ
Revision History: 2013-6-7 Version 2.0
Previous Version: 0.0
Page Subjects (major changes since last revision)
3 add applications
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
Edition 2013-6-7
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2013 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ICE3RBR0665JZ
Typical Application
+
Snubber Converter
CBulk DC Output
85 ... 270 VAC
-
CVCC
VCC Drain
Startup Cell
Power Management
PWM Controller
Current Mode
CS
Precise Low Tolerance Peak CoolMOS®
Current Limitation
RSense
FB
Active Burst Mode
GND Control
Unit BA
Auto Restart Mode
CoolSET®-F3R
(Jitter Mode)
Type Package Marking VDS FOSC RDSon1) 230VAC ±15%2) 85-265 VAC2)
ICE3RBR0665JZ PG-DIP-7 3RBR0665JZ 650V 65kHz 0.65 71W 47W
1)
typ @ Tj=25°C
2)
Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink. Refer to input power curve for other Ta.
GND (Ground)
GND pin is the ground of the controller.
n.c. 4 5 Drain
Figure 2
+
Version 2.0
Converter
CBulk Snubber DC Output
85 ... 270 VAC VOUT
-
CVCC
VCC Drain
5.0V Power Management CoolMOS®
3.25k
Startup Cell
Internal Bias Voltage 5.0V
Reference
IBK
Auto-restart T2
Enable BA T3 0.6V
GND
Signal Power-Down
#1 C BK Undervoltage Lockout
T1 Reset 18V
0.72 PWM
#2 10.5V
TAE VCC Oscillator Section
&
C1 G1
Duty Cycle
20.5V max
Representative Blockdiagram
0.9V 1 ms
VCC counter
C2 120us Blanking Time Soft Start Soft-Start Clock
25.5V Comparator
Thermal Shutdown Freq. jitter
Soft
Tj >130°C & Gate
Start
0.33V C7 G7 FF1 Driver
C9 Block
1 S
R Q &
S1 G8
1 G9
G2
7
C3
4.0V PWM
5.0V Comparator
& C8
4.0V Spike Auto
RFB C4 20ms G5 Blanking Restart
Blanking 30us Mode Propagation-Delay
Compensation
25k Time
Representative Blockdiagram
7 Jun 2013
Representative Blockdiagram
ICE3RBR0665JZ
ICE3RBR0665JZ
Functional Description
3 Functional Description
All values which are used in the functional description conditions. This is necessary for a prolonged fault
are typical values. For calculating the worst cases the condition which could otherwise lead to a destruction of
min/max values which can be found in section 4 the SMPS over time. Once the malfunction is removed,
Electrical Characteristics have to be considered. normal operation is automatically retained after the
next Start Up Phase. To make the protection more
flexible, an external auto-restart enable pin is provided.
3.1 Introduction When the pin is triggered, the switching pulse at gate
ICE3RBR0665JZ (ICE3RBRxx65JZ series) is derived will stop and the IC enters the auto-restart mode after
from ICE3BRxx65J in DIP-7 package. It has more the pre-defined spike blanking time.
robust design and can work to -40°C. The internal precise peak current control reduces the
A high voltage Startup Cell is integrated into the IC costs for the transformer and the secondary diode. The
which is switched off once the Undervoltage Lockout influence of the change in the input voltage on the
on-threshold of 18V is exceeded. This Startup Cell is maximum power limitation can be avoided together
part of the integrated CoolMOS®. The external startup with the integrated Propagation Delay Compensation.
resistor is no longer necessary as this Startup Cell is Therefore the maximum power is nearly independent
connected to the Drain. Power losses are therefore on the input voltage, which is required for wide range
reduced. This increases the efficiency under light load SMPS. Thus there is no need for the over-sizing of the
conditions drastically. SMPS, e.g. the transformer and the output diode.
The particular features are the active burst mode, Furthermore, it implements the frequency jitter mode to
propagation delay compensation, modulated gate the switching clock such that the EMI noise will be
driving, auto-restart protection for Vcc overvoltage, effectively reduced.
over temperature, over load, open loop, built-in soft
start, blanking window and frequency jitter. It provides 3.2 Power Management
the flexibility to increase the blanking window by simply
addition of a capacitor in BA pin. In order to further Drain VCC
increase the flexibility of the protection feature, an
external auto-restart enable features are added. Startup Cell
The intelligent Active Burst Mode can effectively obtain
the lowest Standby Power at light load and no load
conditions. After entering the burst mode, there is still a
CoolMOS ®
full control of the power conversion to the output
through the optocoupler, that is used for the normal
PWM control. The response on load jumps is optimized
and the voltage ripple on Vout is minimized. The Vout is Power Management
3.3.1 PWM-OP
Soft-Start Comparator The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
PWM Comparator RSense connected to pin CS. RSense converts the source
current into a sense voltage. The sense voltage is
FB
amplified with a gain of 3.3 by PWM OP. The output of
C8 the PWM-OP is connected to the voltage source V1.
Oscillator PWM-Latch The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
VOSC Figure 6).
time delay
circuit (156ns)
Gate Driver 3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
0.67V signal of the integrated CoolMOS® with the feedback
10kΩ signal VFB (see Figure 8). VFB is created by an external
X3.3 optocoupler or external transistor in combination with
T2 R1 the internal pull-up resistor RFB and provides the load
V1 information of the feedback circuitry. When the
PWM OP amplified current signal of the integrated CoolMOS®
exceeds the signal VFB the PWM-Comparator switches
off the Gate Driver.
Voltage Ramp
5V
Figure 6 Improved Current Mode
RFB Soft-Start Comparator
FB
VOSC PWM-Latch
C8
max.
Duty Cycle
PWM Comparator
0.67V
Voltage Ramp t
Optocoupler
PWM OP
CS
0.67V
X3.3
FB
Improved
Gate Driver t Current Mode
156ns time delay
3.4 Startup Phase When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
S o ft S ta rt The function is realized by an internal Soft Start
c o u n te r resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
Soft Start finish
S o ftS
S o ft S ta rt
5V
S o ft S ta rt
S o ft-S ta rt RSoftS
C o m p a ra to r SoftS
G a te D riv e r
C7 &
G7
Soft Start 32I 8I 4I 2I I
0 .6 7 V
Counter
x 3 .3 CS
PW M OP
VSoftS
tSoft-Start
VSOFTS32
VSoftS
t
VSoftS2 Gate
VSoftS1 Driver
t
Figure 10 Soft Start Phase
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period, the duty cycle is increasing 3.5 PWM Section
from zero to maximum gradually (see Figure 12).
In addition to Start-Up, Soft-Start is also activated at
0.75
each restart attempt during Auto Restart. PWM Section
Oscillator
VSoftS
Duty Cycle
tSoft-Start max
VSOFTS32
Clock
Frequency
Jitter
VFB t
Soft Start
4.0V Block FF1
S Gate Driver
Soft Start 1
Comparator R &
G8 Q
PWM
V OUT t G9
Comparator
Current
VOUT Limiting
tStart-Up CoolMOS®
Gate
t
Figure 14 PWM Section Block
Figure 13 Start Up Phase
3.5.1 Oscillator
The Start-Up time TStart-Up before the converter output The oscillator generates a fixed frequency of 65KHz
voltage VOUT is settled, must be shorter than the Soft- with frequency jittering of ±4% (which is ±2.6KHz) at a
Start Phase TSoft-Start (see Figure 13). jittering period of 4ms.
By means of Soft-Start there is an effective A capacitor, a current source and current sink which
minimization of current and voltage stresses on the determine the frequency are integrated. In order to
integrated CoolMOS®, the clamp circuit and the output achieve a very accurate switching frequency, the
overshoot and it helps to prevent saturation of the charging and discharging current of the implemented
transformer during Start-Up. oscillator capacitor are internally trimmed. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 65KHz ± 2.6KHz at period of 4ms.
PWM Latch
FF1
VCC
Current Limiting
PWM-Latch
1
Propagation-Delay
Compensation
Gate
CoolMOS® Vcsth
C10 Leading
Edge
Blanking
PWM-OP 220ns
Gate Driver
&
G10 C12
Figure 15 Gate Driver 0.34V
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. The switch on speed is
1pF
slowed down before it reaches the integrated Active Burst 10k
CoolMOS® turn on threshold. That is a slope control of Mode D1
the rising edge at the output of the driver (see Figure
16).
CS
(internal)
Figure 17 Current Limiting Block
VGate
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS® is sensed
ca. t = 130ns via an external sense resistor RSense. By means of
RSense the source current is transformed to a sense
voltage VSense which is fed into the CS pin. If the voltage
5V VSense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
t A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
Figure 16 Gate Rising Slope CoolMOS® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
Thus the leading switch on spike is minimized.
output power can be reduced to minimal.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage. In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
During power up, when VCC is below the undervoltage
Blanking is integrated in the current sense path for the
lockout threshold VVCCoff, the output of the Gate Driver
comparators C10, C12 and the PWM-OP.
is set to low in order to disable power transfer to the
secondary side. The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.34V. This
voltage level determines the maximum power level in
Active Burst Mode.
3.6.1 Leading Edge Blanking For example, Ipeak = 0.5A with RSense = 2. The current
sense threshold is set to a static voltage level Vcsth=1V
VSense without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a
propagation delay time of tPropagation Delay =180ns leads
Vcsth
tLEB = 220ns to an Ipeak overshoot of 14.4%. With the propagation
delay compensation, the overshoot is only around 2%
(see Figure 20).
V
1,3
t 1,25
1,2
VSense
Figure 18 Leading Edge Blanking 1,15
1,1
Whenever the integrated CoolMOS® is switched on, a
1,05
leading edge spike is generated due to the primary-
1
side capacitances and reverse recovery time of the
0,95
secondary-side rectifier. This spike can cause the gate
drive to switch off unintentionally. In order to avoid a 0,9
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V
premature termination of the switching pulse, this spike
dVSense μs
is blanked out with a time constant of tLEB = 220ns.
dt
3.6.2 Propagation Delay Compensation Figure 20 Overcurrent Shutdown
In case of over-current detection, there is always The Propagation Delay Compensation is realized by
propagation delay to switch off the integrated
means of a dynamic threshold voltage Vcsth (see Figure
CoolMOS®. An overshoot of the peak current Ipeak is 21). In case of a steeper slope the switch off of the
induced to the delay, which depends on the ratio of dI/ driver is earlier to compensate the delay.
dt of the peak current (see Figure 19).
ILimit
V Sense Propagation Delay t
IOvershoot1
V csth
t
Figure 19 Current Limiting
The overshoot of Signal2 is larger than of Signal1 due Signal1 Signal2
to the steeper rising waveform. This change in the
t
slope depends on the AC input voltage. Propagation Figure 21 Dynamic Voltage Threshold Vcsth
Delay Compensation is integrated to reduce the
overshoot due to dI/dt of the rising primary current.
Thus the propagation delay time between exceeding
the current sense threshold Vcsth and the switching off
of the integrated CoolMOS® is compensated over
temperature within a wide range. Current Limiting is
then very accurate.
3.7 Control Unit After the 30us spike blanking time, the Auto Restart
Mode is activated.
The Control Unit contains the functions for Active Burst For example, if CBK = 0.22uF, IBK = 13uA
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode both have 20ms internal Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 72ms
Blanking Time. For the Auto Restart Mode, a further In order to make the startup properly, the maximum CBK
extendable Blanking Time is achieved by adding capacitor is restricted to less than 0.65uF.
external capacitor at BA pin. By means of this Blanking The Active Burst Mode has basic blanking mode only
Time, the IC avoids entering into these two modes while the Auto Restart Mode has both the basic and the
accidentally. Furthermore those buffer time for the extendable blanking mode.
overload detection is very useful for the application that
works in low current but requires a short duration of 3.7.2 Active Burst Mode
high current occasionally.
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
3.7.1 Basic and Extendable Blanking Mode increases significantly at light load conditions while still
maintaining a low ripple on VOUT and a fast response on
load jumps. During Active Burst Mode, the IC is
5.0V
controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
IBK
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
BA Auto
Restart Internal Bias
C3
# CBK Mode
4.0V
Current
0.9V Limiting
&
1 Spike
&
S1 G5 Blanking 4.0V
G2 8.0us
G10
C4
Active
4.0V 20ms FB & Burst
C4 Blanking
C5 Mode
Time G6
1.35V
20 ms
FB & Blanking
20ms Active
Burst Time
C5 Blanking G6
1.35V Time Mode
C6a
Control Unit 3.5V
&
Figure 22 Basic and Extendable Blanking Mode G11
C6b
There are 2 kinds of Blanking mode; basic mode and 3.0V
Control Unit
the extendable mode. The basic mode is just an
internal set 20ms blanking time while the extendable
Figure 23 Active Burst Mode
mode has an extra blanking time by connecting an
external capacitor to the BA pin in addition to the pre-
set 20ms blanking time. For the extendable mode, the The Active Burst Mode is located in the Control Unit.
gate G5 is blocked even though the 20ms blanking time Figure 23 shows the related components.
is reached if an external capacitor CBK is added to BA
pin. While the 20ms blanking time is passed, the switch 3.7.2.1 Entering Active Burst Mode
S1 is opened by G2. Then the 0.9V clamped voltage at
The FB signal is kept monitoring by the comparator C5.
BA pin is charged to 4.0V through the internal IBK During normal operation, the internal blanking time
constant current. G5 is enabled by comparator C3.
counter is reset to 0. Once the FB signal falls below
1.35V, it starts to count. When the counter reach 20ms
VOUT t
3.7.3.2 Auto Restart without extended blanking up cell will turn on automatically. And this leads to Auto
time Restart Mode.
Short Optocoupler also leads to VCC undervoltage as
there is no self supply after activating the internal
reference and bias.
1ms
UVLO
counter Auto Restart
Auto-restart BA
Mode Reset
Enable
VVCC < 10.5V
8us Stop
Signal C9 gate
0.33V Blanking
Time drive
Auto Restart
TAE 25.5V mode
120us
C2 Blanking
VCC
Time
softs_period
Spike
VCC & Blanking
30us
C1
G1
20.5V
Voltage
4.0V Reference
C4
FB Thermal Shutdown
Tj >130°C
Control Unit
4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.3 Characteristics
1)
The parameter is not subjected to production test - verified by design/characterization
Charging current at BA pin IBK 9.5 13.0 16.9 μA Charge starts after the
built-in 20ms blanking
time elapsed
Thermal Shutdown1) TjSD 130 140 150 °C Controller
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP.
10
1
ID [A]
0.1
0.01
tp = 0.1ms
tp = 1ms
tp = 10ms
tp = 100ms
0.001 tp = 1000ms
DC
0.0001
1 10 100 1000
VDS [V]
100
SOA temperature derating coefficient [%]
80
60
40
20
0
0 20 40 60 80 100 120 140
Ambient/Case temperature Ta/Tc [deg.C]
Ta : DIP, Tc : TO220
1.4
1.2
Allowable Power Dissipation, Ptot [W]
1.0
0.8
0.6
0.4
0.2
0.0
0 20 40 60 80 100 120 140
Ambient temperature, T A [deg.C]
700
660
V BR(DSS) [V]
620
580
540
-60 -20 20 60 100 140 180
T j [°C]
7 Outline Dimension
PG-DIP-7
(Plastic Dual In-Line Outline)
8 Marking
Marking
TR1
C13 C15
* C14 C23
R24
IC12 IC21
R25
F3 CoolSET schematic for recommended PCB layout
General guideline for PCB layout design using F3/F3R CoolSET® (refer to Figure 35):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET® device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET® device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET® IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)
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