EEE 1011- Automated Test Engineering Lab

Digital Assignment-5
Name: Kanav Bhasin
Register Number: 18BEE0068
Slot: L31+L32
Faculty: Prof. Karthikeyan A

Experiment-5
Title: Boundary scan test using QT-2251
Aim: To perform boundary scan using QT-2251
Apparatus Used:
• Pc with Interactive software
• QT-2251 equipment
• Board having BSD devices
• Power cable, USB and JTAG
Description: The boundary scan architecture provides a means to test interconnects
(including clusters of logic, memories, etc.) without using physical test probes. Each test cell
may be programmed via the JTAG scan chain to drive a signal onto a pin and thus across an
individual trace on the board; the cell at the destination of the board trace can then be
read, verifying that the board trace properly connects the two pins. If the trace is shorted to
another signal or if the trace is open, the correct signal value does not show up at the
destination pin, indicating a fault. QT2251 system is designed as a combination board tester
capable of testing highly complex and PCBs employing various techniques on a single
platform
Output:

The board to be tested

 Board under test

Software learnt about the IC

Test passed on clicking the verify button

Result: Boundary Scan using QT-2251 was performed and completed successfully