A B C D E

ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6

PCB PCB Power Switch Left LED Right LED Touch Sensor

1 DAZ@ DAZ@ DAZ@ DAZ@ DAZ@ 1

2
JIWA3/A4 2

Compal confidential Schematics Document

3
Mobile Penryn uFCPGA 3

Intel Cantiga_GM/PM+ICH9-M
Wednesday, May 14, 2008
REV:1.0
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

A B C D
Date:
E
Sheet 1 of 53
 A B C D E

ZZZ1
Compal confidential
File Name : Right LED Board Swithch & CAP SENSE LEDs Board Left LED Board
15W_PCB_LA4212P

VRAM 16*16 Mobile Penryn

1 VRAM 32*16 uFCPGA-478 CPU
1

page20,21
PCI-E X16 Clock Gen.
nVIDIA NB9M page5,6,7 SLG8SP556VTR
ICS9LPRS387AKLFT
page16,19 page22
H_A#(3..35)
FSB
H_D#(0..63) 667/800/1066MHz

HDMI Level Shifter PCI-E DDR2 -667 (1.8V)

CONN PS8101T page23 DDR2-SO-DIMM X2
page23
Intel Cantiga GMCH DDR2 -800 (1.8V) BANK 0, 1, 2, 3 page 14,15

CRT & TV OUT PCBGA 1329 Dual Channel

LVDS I/F
page25
page 8,9,10,11,12,13
2 2
LVDS
Connector page24 DMI C-Line
AMP&Audio Jack
AZALIA page24

PCI Express 6*PCI-E BUS 12*USB2.0

Mini card Slotpage32
1 Intel ICH9-M Audio Codec
mBGA-676 AMOM_CX20561 MODEM_CX20548
page30

page26,27,28,29
4*SATA serial

BCM5906 Card Reader New Card Camera Conn

10/100/LAN page33 JMB 385 LPC BUS page40
page36 page40
3 3
BlueTooth Conn
page32

RJ45 CONN EC
page34 USB conn X4
ENE KB926 page43
C version page35

Card reader(XD/SD
MMC/MS/MS-Pro Int.KBD
HD SD) page36 page37
SATA HDD
page32,36 BIOS page38
Connector page39
SUB Board Touch Pad
page37
*Right LED SATA CDROM
*Left LED Connector page39
4
*SWITCH & CAP sensor 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA-4212P 1.0

gratuito - free of charge.

A B C D
Date: Monday, May 12, 2008
E
Sheet 2 of 53
 A B C D E

1
Voltage Rails 1
SMBUS Control Table

Power Plane Description S1 S3 S5 THERMAL

SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD CAP BRD
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF
SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X X
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X V
SMB_CK_CLK1
+1.5VS
+1.8V
1.5V switched power rail
1.8V power rail for DDR
ON
ON
OFF
ON
OFF
OFF
SMB_CK_DAT1 ICH9 X X X X V V V X X
+1.8VS 1.8V switched power rail ON OFF OFF LCD_CLK
+2.5VS 2.5V switched power rail ON OFF OFF
LCD_DAT Cantiga
X X X X X X X V X
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2 2
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

3 3

PM@
GM@
X76@
CARD@
WLAN@
HDMI@
HDMI_PM@
HDMI_GM@
BT@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

A B C D
Date: Monday, May 12, 2008
E
Sheet 3 of 53
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+VGA_CORE Core voltage for GPU ON OFF OFF
+1.1VS 1.1V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF POWER SQUENCE
+VSB VSB always on power rail ON ON ON*
The ramp time for any rail must be more than 40us
+RTCVCC RTC power ON ON ON

EDP at Tj = 97C*
Power Supply Rail NB9M-GS NB9M-GE
(V) GDDR3 DDR2 GDDR3 DDR2 (+3VS) VDD33
NVVDD Variable 12.68A 11.57A 10.52A 9.59A

2
FB_DLLAVDD 1.1 25mA 2

FB_PLLAVDD 1.1 10mA PEX_VDD can ramp up any time

IFPC_IOVDD 1.1 385mA
IFPD_IOVDD 1.1 385mA (1.1VS) PEX_VDD
IFPE_IOVDD 1.1 385mA
tNVVDD>=0
IFPF_IOVDD 1.1 385mA
PEX_IOVDD/Q 1.1 1400mA
PEX_PLLVDD 1.1 110mA (+VGA_CORE) NVVDD
PLLVDD 1.1 65mA tNV-FB

SP_PLLVDD 1.1 25mA

tFBVDDQ>=0
VID_PLLVDD 1.1 50mA
TOTAL 1.1 3.225A
(1.8VS) FBVDDQ
FBVDD/Q 1.8 3080mA 1720mA 3010mA 1680mA
IFPA_IOVDD 1.8 50mA
IFPB_IOVDD 1.8 50mA
IFPAB_PLLVDD 1.8 100mA
3 3
IFPCD_PLLVDD 1.8 160mA
IFPEF_PLLVDD 1.8 160mA
TOTAL 1.8 3.6A 2.24A 3.53A 2.2A

DACA_VDD 3.3 130mA

DACB_VDD 3.3 255mA
DACC_VDD 3.3 130mA
MIOA_VDDQ 3.3 10mA
MIOB_VDDQ 3.3 10mA
VDD33 3.3 110mA
TOTAL 3.3 0.645A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

A B C D
Date: Monday, May 12, 2008
E
Sheet 4 of 53
 5 4 3 2 1

XDP Reserve +3VS

XDP_DBRESET# 1 2 @ 1K_0402_5%
R43
+VCCP

XDP_TDI R11 1 2 54.9_0402_1%

D XDP_TMS R14 1 2 54.9_0402_1% D

ME@ +VCCP XDP_TDO R12 1 @ 2 54.9_0402_1%

<8> H_A#[3..16]
JCPUA
H_A#3 J4 H1 H_ADS# R13 1 2 54.9_0402_1%
A[3]# ADS# H_ADS# <8>

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# <8> reserved by XDP_BPM#5
H_A#5 L4 G5 H_BPRI# @
A[5]# BPRI# H_BPRI# <8>

1
H_A#6 K5 R83
H_A#7 A[6]# H_DEFER# 56_0402_5%
M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY# XDP_TRST# R16 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# <8>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <8>
H_A#10 N3 XDP_TCK R15 1 2 54.9_0402_1%

2
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <27>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <8>
H_ADSTB#0 M1
<8> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# <8>
H_REQ#0 K3 F3 H_RS#0
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8> +3VS
H_REQ#1 H2 F4 H_RS#1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8> +3VS
H_REQ#2 K2 G3 H_RS#2
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY#
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>

2
H_REQ#4 L1
<8> H_REQ#4 REQ[4]# H_HIT# R95

0.1U_0402_16V4Z
<8> H_A#[17..35] HIT# G6 H_HIT# <8> 1
H_A#17 Y2 E4 H_HITM# 10K_0402_5%
A[17]# HITM# H_HITM# <8> C89
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 AD4

1
A[19]# BPM[0]# 2
ADDR GROUP_1

C H_A#20 W6 AD3 XDP_BPM#1 C

H_A#21 A[20]# BPM[1]# XDP_BPM#2 U5
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3 1 8 EC_SMB_CK2 EC_SMB_CK2 <16,35,41>
H_A#23 A[22]# BPM[3]# XDP_BPM#4 VDD SCLK
XDP/ITP SIGNALS

U1 A[23]# PRDY# AC2

H_A#24 R4 AC1 XDP_BPM#5 XDP_BPM#5 reserve a via for debuging H_THERMDA 2 7 EC_SMB_DA2
A[24]# PREQ# D+ SDATA EC_SMB_DA2 <16,35,41>
H_A#25 T5 AC5 XDP_TCK C95
H_A#26 A[25]# TCK XDP_TDI H_THERMDC
T3 A[26]# TDI AA6 1 2 3 D- ALERT/THERM2 6
H_A#27 W2 AB3 XDP_TDO 2200P_0402_50V7K
H_A#28 A[27]# TDO XDP_TMS THERM#
W5 A[28]# TMS AB5 4 THERM GND 5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# R94
U2 A[30]# DBR# C20 XDP_DBRESET# <28>
H_A#31 V4 1 2 S IC EMC1402-1-ACZL-TR MSOP 8P
A[31]# +3VS
H_A#32 W3 2 1 10K_0402_5%
H_A#33 A[32]# R84 68_0402_5% +VCCP
AA4 A[33]# THERMAL Address:100_1100
H_A#34 AB2 H_PROCHOT#
A[34]# H_PROCHOT#
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
<27> H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
<27> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,27>
H_IGNNE# C4
<27> H_IGNNE# IGNNE#
H_STPCLK# D5
<27> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<27> H_INTR
<27> H_NMI
H_NMI
H_SMI#
B4
A3
LINT0
LINT1 BCLK[0] A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK <22> FAN1 Conn
<27> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <22>
M4 +5VS +5VS
RSVD[01] C594 10U_0805_10V4Z
B
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, B
T2 RSVD[03] 1 2

1
V3 Trace width / Spacing = 10 / 10 mil
RSVD[04] D17
B2
RESERVED

RSVD[05] U24 @ 1SS355TE-17_SOD323-2

RSVD pins on the CPU D2 RSVD[06]
should be left as NO D22 RSVD[07] 1 VEN GND 8
D3 2 VIN 7 D16

2
CONNECT F6
RSVD[08] +VCC_FAN1 3 VO
GND
6 @ BAS16_SOT23-3
RSVD[09] EN_FAN1 1K_0402_5% GND
<35> EN_FAN1 1 2 4 VSET GND 5 1 2
R726 1
G990P11U_SO8
C808 C595
Penryn 0.1U_0402_16V4Z 1U_0603_10V4Z
2
1 2
+3VS C597
0.1U_0402_16V4Z
1 2

1
R469
10K_0402_5%
40mil JP13

2
+VCC_FAN1 1 1
<35> FAN_SPEED1 2 2
3 3
1
C596 4
1000P_0402_50V7K GND
5 GND
A 2 A
E&T_3801-F03N-01R

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008 Sheet
1
5 of 53
 5 4 3 2 1

+CPU_CORE +CPU_CORE
ME@
JCPUC
<8> H_D#[0..15] ME@ A7 AB20
H_D#[32..47] <8> VCC[001] VCC[068]
JCPUB A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]

DATA GRP 2
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
H_DSTBN#0 J26 Y26 H_DSTBN#2 C9 AE10
<8> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <8> VCC[019] VCC[086]
H_DSTBP#0 H26 AA26 H_DSTBP#2 C10 AE12
<8> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <8> VCC[020] VCC[087]
H_DINV#0 H25 U22 H_DINV#2 C12 AE13
<8> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <8> VCC[021] VCC[088]
<8> H_D#[16..31] H_D#[48..63] <8> C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
D[21]# D[53]# VCC[029] VCC[096]

DATA GRP 3
H_D#22 L22 AD20 H_D#54 D15 AF15
H_D#23 D[22]# D[54]# H_D#55 VCC[030] VCC[097]
M23 D[23]# D[55]# AE22 D17 VCC[031] VCC[098] AF17 For testing purpose only
H_D#24 P25 AF23 H_D#56 D18 AF18
C H_D#25 D[24]# D[56]# H_D#57 VCC[032] VCC[099] +VCCP C
P23 D[25]# D[57]# AC25 E7 VCC[033] VCC[100] AF20
H_D#26 P22 AE21 H_D#58 E9 R47 0_0402_5%
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 2 1
H_D#28 R24 AC22 H_D#60 E12 V6 2 1
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02] R8 0_0402_5%
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6
H_D#30 T25 AF22 H_D#62 E15 K6
H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E18 J21
<8> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <8> VCC[040] VCCP[06]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E20 K21
<8> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <8> VCC[041] VCCP[07]
H_DINV#1 N24 AC20 H_DINV#3 F7 M21
<8> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <8> VCC[042] VCCP[08]
F9 VCC[043] VCCP[09] N21
+CPU_GTLREF AD26 R26 COMP0 R63 1 2 27.4_0402_1% F10 N6
R45 GTLREF COMP[0] VCC[044] VCCP[10]
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R64 1 2 54.9_0402_1% F12 VCC[045] VCCP[11] R21
R46 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R10 1 2 27.4_0402_1% F14 R6
T16 TEST3 TEST2 COMP[2] COMP3 R9 1 54.9_0402_1% VCC[046] VCCP[12]
C24 TEST3 COMP[3] Y1 2 F15 VCC[047] VCCP[13] T21
T15 TEST4 AF26 F17 T6 Near pin B26
T14 TEST5 TEST4 H_DPRSTP# VCC[048] VCCP[14]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,27,51> F18 VCC[049] VCCP[15] V21
T17 TEST6 A26 B5 H_DPSLP# F20 W21
TEST6 DPSLP# H_DPSLP# <27> VCC[050] VCCP[16]
T10 TEST7 C3 D24 H_DPWR# AA7 20mils
TEST7 DPWR# H_DPWR# <8> VCC[051]
CPU_BSEL0 B22 D6 H_PWRGOOD AA9 B26
<22> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <27> VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K
Trace Close CPU < 0.5' CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
<22> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <8> VCC[053] VCCA[02]

10U_0805_10V4Z
CPU_BSEL2 C21 AE6 H_PSI# AA12
<22> CPU_BSEL2 BSEL[2] PSI# H_PSI# <51> VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 <51>
Penryn AA15 AF5 1 1
VCC[056] VID[1] CPU_VID1 <51>
Width=4 mil , AA17 VCC[057] VID[2] AE5 CPU_VID2 <51>

C599

C598
AA18 AF4 CPU_VID3 <51>
Spacing: 15mil AA20
VCC[058] VID[3]
AE3 CPU_VID4 <51>
VCC[059] VID[4] 2 2
(55Ohm) AB9 VCC[060] VID[5] AF3 CPU_VID5 <51>
B TRACE CLOSELY CPU < 0.5' AC10 VCC[061] VID[6] AE2 CPU_VID6 <51> B
AB10 VCC[062]
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB12 VCC[063]
AB14 AF7 VCCSENSE
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AB15
VCC[064] VCCSENSE VCCSENSE <51>
VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE
VCC[067] VSSSENSE VSSSENSE <51>
Penryn
.
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP
FSB BCLK BSEL2 BSEL1 BSEL0 Length match within 25 mils. +CPU_CORE
1

The trace width/space/other is R23

100_0402_1%
533 133 0 0 1
R471 16/7/25. 1 2 VCCSENSE
1K_0402_1%
667 166 0 1 1 R24
2

Layout note: Z0=55 ohm +CPU_GTLREF 100_0402_1%

1 2 VSSSENSE
0.5" max for GTLREF.
800 200 0 1 0 Layout Note:
1

Route VCCSENSE and VSSSENSE traces at

R470 1067 266 0 0 0 27.4 Ohms with 50 mil spacing.
2K_0402_1% Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.
2

A Close to CPU pin A

within 500mils.
Close to CPU pin AD26
within 500mils.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008 Sheet
1
6 of 53
 5 4 3 2 1

ME@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
+CPU_CORE
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
D AF2 VSS[008] VSS[089] T1 1 1 1 1 1 1 1 1 D
B6 VSS[009] VSS[090] T4
B8 T23 Place these capacitors on L8 C13 C39 C36 C30 C27 C19 C14 C12
VSS[010] VSS[091] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B11 VSS[011] VSS[092] T26
2 2 2 2 2 2 2 2
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
+CPU_CORE
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25 1 1 1 1 1 1 1 1
C14 VSS[020] VSS[101] W1
C16 W4 Place these capacitors on L8 C28 C24 C40 C37 C31 C26 C20 C15
VSS[021] VSS[102] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C19 VSS[022] VSS[103] W23
2 2 2 2 2 2 2 2
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
+CPU_CORE
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
D13 VSS[030] VSS[111] AA8 1 1 1 1 1 1 1 1
D16 VSS[031] VSS[112] AA11
D19 AA14 Place these capacitors on L8 C583 C585 C586 C589 C591 C593 C582 C584
VSS[032] VSS[113] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D23 VSS[033] VSS[114] AA16
2 2 2 2 2 2 2 2
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
C E8 AB1 C
VSS[037] VSS[118] +CPU_CORE
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13 1 1 1 1 1 1 1 1
E21 VSS[042] VSS[123] AB16
E24 AB19 Place these capacitors on L8 C588 C587 C590 C592 C35 C29 C25 C33
VSS[043] VSS[124] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
F5 VSS[044] VSS[125] AB23
2 2 2 2 2 2 2 2
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14 Mid Frequence Decoupling
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
+CPU_CORE
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
J5 AD22
VSS[062] VSS[143]
ESR <= 1.5m ohm

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9
J22 VSS[063] VSS[144] AD25 1 1 1 1
J25 VSS[064] VSS[145] AE1
+ + + +
Capacitor > 1980uF

C47

C17

C41

C16
K1 VSS[065] VSS[146] AE4 North Side Secondary
B B
K4 VSS[066] VSS[147] AE8 South Side Secondary
K23 VSS[067] VSS[148] AE11
2 2 2 @ 2
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 AF21 +VCCP
VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
VSS[163] AF25
1
Penryn 1 1 1 1 1 1
. C8 + Place these inside
C11 C10 C51 C50 C48 C9 socket cavity on L8
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.5 4 3 2

Date: Monday, May 12, 2008 Sheet
1
7 of 53
 5 4 3 2 1

U26B
<6> H_D#[0..63] H_A#[3..35] <5>
U26A T69 M36 AP24 M_CLK_DDR0 M_CLK_DDR0 <14>
H_A#3 RSVD1 SA_CK_0 M_CLK_DDR1
H_A#_3 A14 T70 N36 RSVD2 SA_CK_1 AT21 M_CLK_DDR1 <14>
H_D#0 F2 C15 H_A#4 T58 R33 AV24 M_CLK_DDR2 M_CLK_DDR2 <15>
H_D#_0 H_A#_4 +1.8V RSVD3 SB_CK_0

0.01U_0402_25V7K
H_D#1 H_A#5 M_CLK_DDR3

2.2U_0603_6.3V4Z
G8 F16 T33 AU20

COMPENSATION
H_D#_1 H_A#_5 T66 RSVD4 SB_CK_1 M_CLK_DDR3 <15>
H_D#2 F8 H13 H_A#6 T23 AH9
H_D#3 H_D#_2 H_A#_6 H_A#7 RSVD5 M_CLK_DDR#0
E6 H_D#_3 H_A#_7 C18 2 2 T25 AH10 RSVD6 SA_CK#_0 AR24 M_CLK_DDR#0 <14>

1
H_D#4 G2 M16 H_A#8 T27 AH12 AR21 M_CLK_DDR#1
H_D#_4 H_A#_8 RSVD7 SA_CK#_1 M_CLK_DDR#1 <14>

C641
H_D#5 H6 J13 H_A#9 R502 T30 AH13 AU24 M_CLK_DDR#2
H_D#_5 H_A#_9 RSVD8 SB_CK#_0 M_CLK_DDR#2 <15>

C640
H_D#6 H2 P16 H_A#10 T26 K12 AV20 M_CLK_DDR#3
H_D#_6 H_A#_10 1 1 RSVD9 SB_CK#_1 M_CLK_DDR#3 <15>
H_D#7 F6 R16 H_A#11 1K_0402_1% T62 AL34
H_D#8 H_D#_7 H_A#_11 H_A#12 RSVD10 DDR_CKE0_DIMMA +1.8V
D4 N17 T61 AK34 BC28 DDR_CKE0_DIMMA <14>

2
H_D#9 H_D#_8 H_A#_12 H_A#13 SMRCOMP_VOH RSVD11 SA_CKE_0 DDR_CKE1_DIMMA
H3 H_D#_9 H_A#_13 M13 T67 AN35 RSVD12 SA_CKE_1 AY28 DDR_CKE1_DIMMA <14>
H_D#10 M9 E17 H_A#14 T68 AM35 AY36 DDR_CKE2_DIMMB
H_D#_10 H_A#_14 RSVD13 SB_CKE_0 DDR_CKE2_DIMMB <15>

1
H_D#11 M11 P17 H_A#15 T44 T24 BB36 DDR_CKE3_DIMMB
H_D#_11 H_A#_15 RSVD14 SB_CKE_1 DDR_CKE3_DIMMB <15>
H_D#12 J1 F17 H_A#16 R501
H_D#13 H_D#_12 H_A#_16 H_A#17 3.01K_0402_1% DDR_CS0_DIMMA#
J2 H_D#_13 H_A#_17 G20 SA_CS#_0 BA17 DDR_CS0_DIMMA# <14>

2
D NA lead free D
H_D#14 N12 B19 H_A#18 AY16 DDR_CS1_DIMMA#
H_D#_14 H_A#_18 SA_CS#_1 DDR_CS1_DIMMA# <14>
H_D#15 J6 J16 H_A#19 T56 B31 AV16 DDR_CS2_DIMMB# R498
DDR_CS2_DIMMB# <15>

2
H_D#16 H_D#_15 H_A#_19 H_A#20 SMRCOMP_VOL RSVD15 SB_CS#_0 DDR_CS3_DIMMB#
P2 H_D#_16 H_A#_20 E20 T84 B2 RSVD16 AR13 DDR_CS3_DIMMB# <15> 80.6_0402_1%

DDR CLK/ CONTROL/

H_D#17 H_A#21 SB_CS#_1
L2 H_D#_17 H_A#_21 H16 T83 M1 RSVD17

RSVD
H_D#18 H_A#22 M_ODT0

0.01U_0402_25V7K
2.2U_0603_6.3V4Z
R2 J20 BD17 M_ODT0 <14>

1
H_D#19 H_D#_18 H_A#_22 H_A#23 R500 SA_ODT_0 M_ODT1
N9 H_D#_19 H_A#_23 L17 1 1 SA_ODT_1 AY17 M_ODT1 <14>
H_D#20 L6 A17 H_A#24 T40 AY21 BF15 M_ODT2 M_ODT2 <15>
H_D#_20 H_A#_24 RSVD20 SB_ODT_O

C635
H_D#21 M5 B17 H_A#25 1K_0402_1% AY13 M_ODT3 M_ODT3 <15>20mil
H_D#_21 H_A#_25 SB_ODT_1

C636
H_D#22 J3 L16 H_A#26

2
H_D#23 H_D#_22 H_A#_26 H_A#27 2 2 SMRCOMP
N2 H_D#_23 H_A#_27 C21 SM_RCOMP BG22 For Crestline: 20ohm
H_D#24 R1 J17 H_A#28 T87 BG23 BH21 SMRCOMP# R497 1 2 80.6_0402_1% For Calero: 80.6ohm
H_D#25 H_D#_24 H_A#_28 H_A#29 RSVD22 SM_RCOMP#
N5 H_D#_25 H_A#_29 H20 T88 BF23 RSVD23 For Cantiga: 80.6ohm
H_D#26 N6 B18 H_A#30 T34 BH18 BF28 SMRCOMP_VOH
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD24 SM_RCOMP_VOH SMRCOMP_VOL
P13 H_D#_27 H_A#_31 K17 T35 BF18 RSVD25 SM_RCOMP_VOL BH28
H_D#28 N8 B20 H_A#32
H_D#29 H_D#_28 H_A#_32 H_A#33 +DDR_MCH_REF
L7 H_D#_29 H_A#_33 F21 SM_VREF AV42
H_D#30 N10 K21 H_A#34 AR36 SM_PWROK R148 1 2 10K_0402_5%
H_D#31 H_D#_30 H_A#_34 H_A#35 SM_PWROK SM_REXT
M3 H_D#_31 H_A#_35 L20 SM_REXT BF17 1 2
H_D#32 Y3 BC36 R111 499_0402_1%
H_D#33 H_D#_32 H_ADS# SM_DRAMRST#
AD14 H_D#_33 H_ADS# H12 H_ADS# <5>
H_D#34 Y6 B16 H_ADSTB#0 DDR3
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <5>
H_D#35 Y10 G17 H_ADSTB#1 B38 CLK_MCH_DREFCLK
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <5> DPLL_REF_CLK CLK_MCH_DREFCLK <22>
H_D#36 Y12 A9 H_BNR# A38 CLK_MCH_DREFCLK#
H_D#_36 H_BNR# H_BNR# <5> DPLL_REF_CLK# CLK_MCH_DREFCLK# <22>
HOST

H_D#37 Y14 F11 H_BPRI# E41 MCH_SSCDREFCLK

H_D#_37 H_BPRI# H_BPRI# <5> DPLL_REF_SSCLK MCH_SSCDREFCLK <22>
H_D#38 Y7 G12 H_BR0# F41 MCH_SSCDREFCLK#
H_D#_38 H_BREQ# H_BR0# <5> DPLL_REF_SSCLK# MCH_SSCDREFCLK# <22>
H_D#39 H_DEFER#

CLK
W2 H_D#_39 H_DEFER# E9 H_DEFER# <5>
H_D#40 AA8 B10 H_DBSY# F43 CLK_MCH_3GPLL
H_D#_40 H_DBSY# H_DBSY# <5> PEG_CLK CLK_MCH_3GPLL <22>
H_D#41 Y9 AH7 CLK_MCH_BCLK E43 CLK_MCH_3GPLL#
H_D#_41 HPLL_CLK CLK_MCH_BCLK <22> PEG_CLK# CLK_MCH_3GPLL# <22>
H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <22>
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# <6>
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <5>
H_D#45 AD11 H9 H_HIT# AE41 DMI_TXN0
H_D#_45 H_HIT# H_HIT# <5> DMI_RXN_0 DMI_TXN0 <28>
H_D#46 AD10 E12 H_HITM# AE37 DMI_TXN1
H_D#_46 H_HITM# H_HITM# <5> DMI_RXN_1 DMI_TXN1 <28>
H_D#47 AD13 H11 H_LOCK# AE47 DMI_TXN2
H_D#_47 H_LOCK# H_LOCK# <5> DMI_RXN_2 DMI_TXN2 <28>
H_D#48 AE12 C9 H_TRDY# H_TRDY# <5> AH39 DMI_TXN3
H_D#_48 H_TRDY# DMI_RXN_3 DMI_TXN3 <28>
H_D#49 AE9
H_D#50 H_D#_49 DMI_TXP0
AA2 H_D#_50 DMI_RXP_0 AE40 DMI_TXP0 <28>
C H_D#51 AD8 MCH_CLKSEL0 T25 AE38 DMI_TXP1 C
H_D#_51 <22> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <28>
H_D#52 AA3 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_52 <22> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <28>
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_53 H_DINV#_0 H_DINV#0 <6> <22> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <28>
H_D#54 AD7 L3 H_DINV#1 P20
H_D#_54 H_DINV#_1 H_DINV#1 <6> CFG_3
H_D#55 AE14 Y13 H_DINV#2 P24 AE35 DMI_RXN0
H_D#_55 H_DINV#_2 H_DINV#2 <6> CFG_4 DMI_TXN_0 DMI_RXN0 <28>
H_D#56 H_DINV#3 CFG5 DMI_RXN1

DMI
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 <6> CFG5 C25 CFG_5 DMI_TXN_1 AE43 DMI_RXN1 <28>
H_D#57 AC1 T48 CFG6 N24 AE46 DMI_RXN2
H_D#_57 CFG_6 DMI_TXN_2 DMI_RXN2 <28>
H_D#58 AE3 L10 H_DSTBN#0 T47 CFG7 M24 AH42 DMI_RXN3
H_D#_58 H_DSTBN#_0 H_DSTBN#0 <6> CFG_7 DMI_TXN_3 DMI_RXN3 <28>

CFG
H_D#59 AC3 M7 H_DSTBN#1 T45 CFG8 E21
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <6> CFG_8
H_D#60 AE11 AA5 H_DSTBN#2 T41 CFG9 C23 AD35 DMI_RXP0
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <6> CFG_9 DMI_TXP_0 DMI_RXP0 <28>
H_D#61 AE8 AE6 H_DSTBN#3 T50 CFG10 C24 AE44 DMI_RXP1
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <6> CFG_10 DMI_TXP_1 DMI_RXP1 <28>
H_D#62 AG2 T49 CFG11 N21 AF46 DMI_RXP2
H_D#_62 CFG_11 DMI_TXP_2 DMI_RXP2 <28>
H_D#63 AD6 L9 H_DSTBP#0 T39 CFG12 P21 AH43 DMI_RXP3
H_D#_63 H_DSTBP#_0 H_DSTBP#0 <6> CFG_12 DMI_TXP_3 DMI_RXP3 <28>
M8 H_DSTBP#1 T43 CFG13 T21
H_DSTBP#_1 H_DSTBP#1 <6> CFG_13
AA6 H_DSTBP#2 +3VS T38 CFG14 R20
H_DSTBP#_2 H_DSTBP#2 <6> CFG_14
H_SWNG C5 AE5 H_DSTBP#3 T37 CFG15 M20
H_SWING H_DSTBP#_3 H_DSTBP#3 <6> CFG_15
H_RCOMP E3 T46 CFG16 L21
H_RCOMP H_REQ#0 CFG17 CFG_16
H_REQ#_0 B15 H_REQ#0 <5> T42 H21 CFG_17
1

K13 H_REQ#1 T55 CFG18 P29

GRAPHICS VID
H_REQ#_1 H_REQ#1 <5> CFG_18
F13 H_REQ#2 R206 R217 T53 CFG19 R28
H_REQ#_2 H_REQ#2 <5> CFG_19
B13 H_REQ#3 10K_0402_5% 10K_0402_5% T54 CFG20 T28 B33
H_REQ#_3 H_REQ#3 <5> CFG_20 GFX_VID_0
<5> H_RESET# H_RESET# C12 B14 H_REQ#4 B32 T90 PAD MCH_HDA_BCLK
H_CPURST# H_REQ#_4 H_REQ#4 <5> GFX_VID_1
<6> H_CPUSLP# H_CPUSLP# E11 G33 T89 PAD connect to power CPU_CORE
2

H_CPUSLP# H_RS#0 PM_EXTTS#0 GFX_VID_2 T65 PAD

H_RS#_0 B6 H_RS#0 <5> GFX_VID_3 F33 1
F12 H_RS#1 H_RS#1 <5> <28> PM_BMBUSY# PM_BMBUSY# R29 E33 T64 PAD
H_VREF H_RS#_1 H_RS#2 PM_EXTTS#1 H_DPRSTP# PM_SYNC# GFX_VID_4 T63 PAD C646
A11 H_AVREF H_RS#_2 C8 H_RS#2 <5> <6,27,51> H_DPRSTP# B7 PM_DPRSTP#
B11 PM_EXTTS#0 N33 10P_0402_50V8J
H_DVREF <14> PM_EXTTS#0 PM_EXT_TS#_0 2

PM
PM_EXTTS#1 P32 @
<15> PM_EXTTS#1 PM_EXT_TS#_1
CANTIGA ES_FCBGA1329 PM_POK_R AT40 C34 T91
PLT_RST#_R PWROK GFX_VR_EN
AT11 RSTIN#
H_THERMTRIP# T20 +VCCP
GM@ <5,27> H_THERMTRIP# THERMTRIP#
<28,51> DPRSLPVR DPRSLPVR R32 DPRSLPVR
layout note: For AMT function

1
Route H_SCOMP and H_SCOMP# with trace width BG48 AH37 CL_CLK0 CL_CLK0 <28> R143
NC_1 CL_CLK CL_DATA0
spacing and impedance (55 ohm) same as FSB data traces BF48 NC_2 CL_DATA AH36 CL_DATA0 <28>

ME
BD48 AN36 1K_0402_1%
NC_3 CL_PWROK M_PWROK <28>
2 1 PM_POK_R BC48 AJ35 CL_RST#
<28,35> ICH_POK CL_RST# <28>

2
B
R177 0_0402_5% NC_4 CL_RST# CL_VREF B
BH47 NC_5 CL_VREF AH34
Layout Note: 2 1 0309 add BG47
<28,51> VGATE NC_6

1
R178 @ 0_0402_5% BE47 0.1U_0402_16V4Z 1
H_RCOMP / H_VREF / H_SWNG 1 2 PLT_RST#_R BH46
NC_7
N28 R147
<16,26,32,33,36,40> PLT_RST# NC_8 DDPC_CTRLCLK T52

NC
trace width and spacing is 10/20 R103 100_0402_5% BF46 M28 T51 C238 499_0402_1%
NC_9 DDPC_CTRLDATA HDMICLK_NB
BG45 NC_10 SDVO_CTRLCLK G36 HDMICLK_NB <23>
HDMIDAT_NB 2
BH44 E36 HDMIDAT_NB <23> check list 511ohm 1%

2
NC_11 SDVO_CTRLDATA MCH_CLKREQ#
BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# <22> ISPD only 510ohm 5%

MISC
BH6 H36 MCH_ICH_SYNC#
+VCCP NC_13 ICH_SYNC# MCH_ICH_SYNC# <28>
BH5 NC_14
+VCCP BG4 NC_15 TSATN# <35>
BH3 NC_16 TSATN# B12 1 2 +VCCP
1K_0402_1%

221_0603_1%

Layout Note: BF3 NC_17 R105 56_0402_5%

1

V_DDR_MCH_REF BH2 NC_18

+1.8V
R482

BG2 NC_19
trace width and
R493

BE2 B28 MCH_HDA_BCLK R80 1 GM@ 2 33_0402_5%

NC_20 HDA_BCLK HDA_BITCLK_CODEC <16,27,30>
spacing is 20/20. BG1 B30 MCH_HDA_RST# R82 1 GM@ 2 33_0402_5% HDA_RST_CODEC# <16,27,30>
NC_21 HDA_RST#
1

0.1U_0402_16V4Z BF1 B29 MCH_HDA_SDIN R79 1 GM@ 2 33_0402_5%

HDA_SDIN0 <27>
2

H_VREF H_RCOMP H_SWNG R160 NC_22 HDA_SDI MCH_HDA_SDOUT R85 GM@ 33_0402_5%
BD1 NC_23 HDA_SDO C29 1 2 HDA_SDOUT_CODEC <16,27,30>
MCH_HDA_SYNC R81 GM@ 33_0402_5%

HDA
10K_0402_5% BC1 NC_24 HDA_SYNC A28 1 2 HDA_SYNC_CODEC <16,27,30>
24.9_0402_1%

0.1U_0402_16V4Z

F1 NC_25
1

1
2K_0402_1%

100_0402_1%

1 1 A47
2

+DDR_MCH_REF NC_26
+DDR_MCH_REF
R488

C623

R89

R484

C616

CANTIGA ES_FCBGA1329 Notice: Please check HDA power rail to select HDA controller.
0.1U_0402_16V4Z

2 2 R162
1 GM@
2

10K_0402_5%
C273

2
within 100 mils from NB Near B3 pin

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
Cantiga GMCH(1/6)-GTL
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
C
Document Number
JIWA3/A4_LA4212P
Rev
1.0

gratuito - free of charge. 5 4 3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
Date: Wednesday, May 14, 2008
1
Sheet 8 of 53
 5 4 3 2 1

D D

<14> DDR_A_D[0..63] <15> DDR_B_D[0..63]

U26D U26E
DDR_A_D0 AJ38 BD21 DDR_A_BS#0 DDR_B_D0 AK47 BC16 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 <14> SB_DQ_0 SB_BS_0 DDR_B_BS#0 <15>
DDR_A_D1 AJ41 BG18 DDR_A_BS#1 DDR_B_D1 AH46 BB17 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 <14> SB_DQ_1 SB_BS_1 DDR_B_BS#1 <15>
DDR_A_D2 AN38 AT25 DDR_A_BS#2 DDR_B_D2 AP47 BB33 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 <14> SB_DQ_2 SB_BS_2 DDR_B_BS#2 <15>
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# <14> AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# <14> SB_DQ_5 SB_RAS# DDR_B_RAS# <15>
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_WE# <14> SB_DQ_6 SB_CAS# DDR_B_CAS# <15>
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE#
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# <15>
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
SA_DQ_12 DDR_A_DM[0..7] <14> SB_DQ_12
DDR_A_D13 AN39 AM37 DDR_A_DM0 DDR_B_D13 AR47
DDR_A_D14 SA_DQ_13 SA_DM_0 DDR_A_DM1 DDR_B_D14 SB_DQ_13
AU44 SA_DQ_14 SA_DM_1 AT41 BA47 SB_DQ_14 DDR_B_DM[0..7] <15>
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
C DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4 C
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] <14> SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] <15>
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0

MEMORY
DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48

DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 DDR_A_DQS#[0..7] <14> BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D34 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 BH11 SB_DQ_34 DDR_B_DQS#[0..7] <15>
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0

SYSTEM
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM

DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1

DDR_A_D37 SA_DQ_36 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
AV13 SA_DQ_37 SA_DQS#_4 AY12 BF11 SB_DQ_37 SB_DQS#_2 BH41
DDR_A_D38 BD12 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
DDR_A_D39 SA_DQ_38 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
BC12 SA_DQ_39 SA_DQS#_6 AU9 BG7 SB_DQ_39 SB_DQS#_4 BG9
DDR_A_D40 BB9 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 BC2 DDR_B_DQS#5
DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
BA9 SA_DQ_41 BC6 SB_DQ_41 SB_DQS#_6 AT2
DDR_A_D42 AU10 DDR_B_D42 AY3 AN5 DDR_B_DQS#7
SA_DQ_42 DDR_A_MA[0..14] <14> SB_DQ_42 SB_DQS#_7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] <15>
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDR_A_D48 DDR_A_MA4 DDR_B_D48 DDR_B_MA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDR_A_D49 AV7 BA24 DDR_A_MA5 DDR_B_D49 AU3 AW25 DDR_B_MA4
DDR_A_D50 SA_DQ_49 SA_MA_5 DDR_A_MA6 DDR_B_D50 SB_DQ_49 SB_MA_4 DDR_B_MA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDR_A_D51 AN8 BG27 DDR_A_MA7 DDR_B_D51 AN2 AU28 DDR_B_MA6
DDR_A_D52 SA_DQ_51 SA_MA_7 DDR_A_MA8 DDR_B_D52 SB_DQ_51 SB_MA_6 DDR_B_MA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDR_A_D53 AU6 AW24 DDR_A_MA9 DDR_B_D53 AV1 AT33 DDR_B_MA8
DDR_A_D54 SA_DQ_53 SA_MA_9 DDR_A_MA10 DDR_B_D54 SB_DQ_53 SB_MA_8 DDR_B_MA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDR_A_D55 AN10 BG26 DDR_A_MA11 DDR_B_D55 AR1 BB16 DDR_B_MA10
DDR_A_D56 SA_DQ_55 SA_MA_11 DDR_A_MA12 DDR_B_D56 SB_DQ_55 SB_MA_10 DDR_B_MA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDR_A_D57 AM5 BH17 DDR_A_MA13 DDR_B_D57 AL2 AY33 DDR_B_MA12
DDR_A_D58 SA_DQ_57 SA_MA_13 DDR_A_MA14 DDR_B_D58 SB_DQ_57 SB_MA_12 DDR_B_MA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDR_A_D59 AJ8 DDR_B_D59 AH1 AU33 DDR_B_MA14
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDR_A_D61 AM13 DDR_B_D61 AM3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDR_A_D63 AJ12 DDR_B_D63 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

GM@ GM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (2/6)-DDRII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Wednesday, May 14, 2008 Sheet
1
9 of 53
 5 4 3 2 1

Strap Pin Table

000 = FSB 1066MHz
CFG[2:0] FSB Freq select
010 = FSB 800MHz
011 = FSB 667MHz
PCIE_MTX_C_GRX_N[0..15]
Others = Reserved
PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15] CFG[4:3] Reserved
PCIE_MTX_C_GRX_P[0..15] <16>
PCIE_GTX_C_MRX_N[0..15] 0 = DMI x 2
D PCIE_GTX_C_MRX_N[0..15] <16> D
CFG5 (DMI select) 1 = DMI x 4
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P[0..15] <16> *
0 = The iTPM Host Interface is enable
CFG6
1 = The iTPM Host Interface is disable
Place the resistor within 500mils
*
0 =(TLS)chiper suite with no confidentiality
CFG7 (Intel Management
(1.27mm)of the (G)MCH 1 =(TLS)chiper suite with confidentiality
Engine Crypto strap)
U26C
PEGCOMP trace width
and spacing is 20/25 mils. CFG8 Reserved
L32 +VCC_PEG
T1 L_BKLT_CTRL
GMCH_ENBKL G32 T37 49.9_0402_1%
<24> GMCH_ENBKL L_BKLT_EN PEG_COMPI
+3VS R213 1 2 10K_0402_5% M32 T36 PEGCOMP R1631 2 CFG9 0 = Reverse Lane,15->0, 14->1
R159 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% M33 L_CTRL_DATA
<24> LVDS_SCL LVDS_SCL K33 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
LVDS_SDA L_DDC_CLK PCIE_GTX_C_MRX_N0
J33 H44 Please check Power
<24> LVDS_SDA
<24> GM_ENVDD GM_ENVDD M29
L_DDC_DATA
L_VDD_EN
PEG_RX#_0
PEG_RX#_1 J46
L44
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
source if want
0 = Enable
*
PEG_RX#_2 PCIE_GTX_C_MRX_N3 support IAMT
2 1 C44 LVDS_IBG PEG_RX#_3 L40 CFG10 (PCIE Lookback enable)
R167 2.37K_0402_1% B43 N41 PCIE_GTX_C_MRX_N4 1 = Disable
For Cantiga:2.37kohm E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_4
PEG_RX#_5 P48
N44
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6 CFG11 Reserved
*
For Crestline:2.4kohm LVDS_VREFL PEG_RX#_6
T43 PCIE_GTX_C_MRX_N7
LVDS_ACLK# PEG_RX#_7 PCIE_GTX_C_MRX_N8
For Calero: 1.5Kohm <24> LVDS_ACLK# C41 LVDSA_CLK# PEG_RX#_8 U43 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDS_ACLK C40 Y43 PCIE_GTX_C_MRX_N9 01 = XOR Mode Enabled
<24> LVDS_ACLK LVDSA_CLK PEG_RX#_9
B37 Y48 PCIE_GTX_C_MRX_N10 10 = All Z Mode Enabled
LVDSB_CLK# PEG_RX#_10 PCIE_GTX_C_MRX_N11
Note: All LVDS data A37 Y36 11 = Normal Operation(Default)
LVDSB_CLK PEG_RX#_11
*

LVDS
AA43 PCIE_GTX_C_MRX_N12
C signals/and it's compliments LVDS_A0# PEG_RX#_12 PCIE_GTX_C_MRX_N13 C
should be routed <24> LVDS_A0# H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 CFG[15:14] Reserved
LVDS_A1# E46 AC47 PCIE_GTX_C_MRX_N14
<24> LVDS_A1# LVDSA_DATA#_1 PEG_RX#_14
Differentially <24> LVDS_A2#
LVDS_A2# G40 AD39 PCIE_GTX_C_MRX_N15
LVDSA_DATA#_2 PEG_RX#_15
T93 A40 LVDSA_DATA#_3 CFG16 (FSB Dynamic ODT) 0 = Disabled
H43 PCIE_GTX_C_MRX_P0
LVDS_A0 PEG_RX_0 PCIE_GTX_C_MRX_P1
H48 J44 1 = Enabled
Layout Note: Place 150
<24> LVDS_A0
<24> LVDS_A1
LVDS_A1
LVDS_A2
D45
LVDSA_DATA_0
LVDSA_DATA_1
PEG_RX_1
PEG_RX_2 L43 PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
*

GRAPHICS
<24> LVDS_A2 F40 LVDSA_DATA_2 PEG_RX_3 L41
B40 N40 PCIE_GTX_C_MRX_P4 CFG[18:17] Reserved
Ohmtermination resistors T94 LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
P47
close to GMCH A41
PEG_RX_5
N43 PCIE_GTX_C_MRX_P6
LVDSB_DATA#_0 PEG_RX_6 PCIE_GTX_C_MRX_P7
H38 T42 CFG19 (DMI Lane Reversal) 0 = Normal Operation
T72
G37
J37
LVDSB_DATA#_1
LVDSB_DATA#_2
PEG_RX_7
PEG_RX_8 U42
Y42
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9 (Lane number in Order)
*
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
B42 Y37 PCIE_GTX_C_MRX_P11 1 = Reverse Lane
LVDSB_DATA_0 PEG_RX_11 PCIE_GTX_C_MRX_P12
G38 LVDSB_DATA_1 PEG_RX_12 AA42
F37 AD36 PCIE_GTX_C_MRX_P13
T73 K37
LVDSB_DATA_2
LVDSB_DATA_3
PEG_RX_13
PEG_RX_14 AC48 PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
PCI-EXPRESS
PEG_RX_15 AD40
1 = PCIE/SDVO are operating simu.
J41 PCIE_MTX_GRX_N0 C277 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
GM@ PEG_TX#_0 PCIE_MTX_GRX_N1 C303 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
PEG_TX#_1 M46 1 2
R127 2 1 75_0402_5% TVA_DAC TVA_DAC F25 M47 PCIE_MTX_GRX_N2 C317 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
TVB_DAC TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C315 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
H25 TVB_DAC PEG_TX#_3 M40 1 2
R121 2 GM@ 1 75_0402_5% TVB_DAC TVC_DAC K25 M42 PCIE_MTX_GRX_N4 C325 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C343 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 R48 1 2
TV

R122 2 1 75_0402_5% TVC_DAC H24 N38 PCIE_MTX_GRX_N6 C358 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6
GM@ TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C349 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
PEG_TX#_7 T40 1 2
U37 PCIE_MTX_GRX_N8 C368 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C354 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N9
PEG_TX#_9 U40 1 2
B C31 Y40 PCIE_MTX_GRX_N10 C371 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10 B
TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C356 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 1 2
AA37 PCIE_MTX_GRX_N12 C372 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C364 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
PEG_TX#_13 AA40 1 2
AD43 PCIE_MTX_GRX_N14 C375 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C348 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
PEG_TX#_15 AC46 1 2

1 GM@ 2 GMCH_CRT_R GMCH_CRT_B E28 J42 PCIE_MTX_GRX_P0 C271 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
<25> GMCH_CRT_B CRT_BLUE PEG_TX_0
R132 150_0402_1% L46 PCIE_MTX_GRX_P1 C296 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
GMCH_CRT_G GMCH_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 PCIE_MTX_C_GRX_P2
1 GM@ 2 <25> GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 C314 1 2 PM@ 0.1U_0402_10V7K
R124 150_0402_1% M39 PCIE_MTX_GRX_P3 C311 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PEG_TX_3
VGA

1 GM@ 2 GMCH_CRT_B GMCH_CRT_R J28 M43 PCIE_MTX_GRX_P4 C322 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
<25> GMCH_CRT_R CRT_RED PEG_TX_4
R123 150_0402_1% R47 PCIE_MTX_GRX_P5 C336 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
PEG_TX_5 PCIE_MTX_GRX_P6 C352 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
G29 CRT_IRTN PEG_TX_6 N37 1 2
T39 PCIE_MTX_GRX_P7 C344 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
GMCH_CRT_CLK H32 PEG_TX_7 PCIE_MTX_GRX_P8 C363 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
<25> GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8 U36 1 2
<25> GMCH_CRT_DATA GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C346 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
CRT_DDC_DATA PEG_TX_9 PCIE_MTX_GRX_P10 C366 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
<25> GMCH_CRT_HSYNC 1 2 J29 CRT_HSYNC PEG_TX_10 Y39 1 2
R203 30_0402_1% E29 Y46 PCIE_MTX_GRX_P11 C351 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C367 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
GM@ 20mil PEG_TX_12 AA36 1 2
AA39 PCIE_MTX_GRX_P13 C359 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
PEG_TX_13 PCIE_MTX_GRX_P14 C373 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
<25> GMCH_CRT_VSYNC 1 2 L29 CRT_VSYNC PEG_TX_14 AD42 1 2
R204 30_0402_1% AD46 PCIE_MTX_GRX_P15 C347 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PEG_TX_15
GM@
1

R139 R140 CANTIGA ES_FCBGA1329

0_0402_5% 0_0402_5% R138 PCIE_MTX_GRX_P3 C670 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_CLK <23>
PM@ PM@ GM@ PCIE_MTX_GRX_N3 C674 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_CLK# <23>
1.02K_0402_1% PCIE_MTX_GRX_P2 C669 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA0 <23>
2

PCIE_MTX_GRX_N2 C673 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA0# <23>

PCIE_MTX_GRX_P1 C662 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA1 <23>
A PCIE_MTX_GRX_N1 C663 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA1# <23> A
For Cantiga:1.02kohm PCIE_MTX_GRX_P0 C658 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA2 <23>
For Crestline:1.3kohm PCIE_MTX_GRX_N0 C661 1 2 HDMI_GM@ 0.1U_0402_10V7K TMDS_B_DATA2# <23>
For Calero: 255ohm
PCIE_GTX_C_MRX_P3 C306 1 2 HDMI_GM@ 0_0402_5% TMDS_B_HPD# <23>
R
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

Cantiga GMCH (3/6)-VGA/LVDS/TV

hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom JIWA3/A4_LA4212P
Rev
1.0
gratuito - free of charge. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 14, 2008 Sheet 10 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_DAC_CRT
R120
1 2
+VCCP
VCC_AXF: 321.35mA

0.022U_0402_16V7K
0_0603_5%
(10UF*1, 1UF*1)

0.1U_0402_16V4Z

10U_0805_10V4Z
GM@ U26H
+1.05VS_DPLLA
1 1 1 R151 +VCCP

C681
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +V1.05VS_AXF

C206

C213
GM@ GM@ U13 1 2 +VCCP
VTT_1

4.7U_0805_10V4Z

0.1U_0402_16V4Z
GM@ +3VS_DAC_CRT B27 T13 1
2 2 2 VCCA_CRT_DAC_1 VTT_2

220U_D2_4VM

10U_0805_10V4Z
A26 U12 1 10U_FLC-453232-100K_0.25A_10% 1 2
VCCA_CRT_DAC_2 VTT_3

10U_0805_10V4Z

1U_0603_10V4Z
T12 +
VTT_4 1 1
GM@

C278
C606

C265
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1) U11 C278 R495
VTT_5

C275
T11 1 1 0_0603_5%
VTT_6 2 2

C629

C631
CRT
+3VS_DAC_BG A25 VCCA_DAC_BG VTT_7 U10
2 2
+3VS_DAC_BG VTT_8 T10
+3VS B25 U9 GM@ GM@
D VSSA_DAC_BG VTT_9 2 2 D
VTT_10 T9
1R115 2 VTT_11 U8 0_0402_5% +1.05VS_DPLLA
0.022U_0402_16V7K
0_0603_5% T8 PM@ VCC_SM_CK: 119.85mA
VTT_12 +1.05VS_DPLLB: 64.8mA
0.1U_0402_16V4Z

10U_0805_10V4Z

4.7U_0805_10V4Z
VTT
GM@ +1.05VS_DPLLA F47 U7
VCCA_DPLLA VTT_13 (470UF*1, 0.1UF*1) (10UF*1, 0.1UF*1)

0.47U_0402_6.3V6K
1 1 GM@ 1 T7 1 1
VTT_14
C639

+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6 +1.8V_SM_CK

+1.05VS_DPLLB
C637

C638

C126

C136
GM@ GM@ T6 +1.8V
VTT_16 R191

PLL
+1.05VS_HPLL AD1 U5 R496
2 2 2 VCCA_HPLL VTT_17 2 2
VTT_18 T5 1 2 +VCCP 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 V3 0_0805_5%
VCCA_MPLL VTT_19

10U_0805_10V4Z
U3 C312 10U_FLC-453232-100K_0.25A_10% 1
+1.8V_TXLVDS VTT_20

C627
VTT_21 V2 1 1 1
GM@

C312

C628
A PEG A LVDS
J48 VCCA_LVDS VTT_22 U2

C310
1 VTT_23 T2
1000P_0402_50V7K 2
J47 VSSA_LVDS VTT_24 V1
C300 2 2 2
VTT_25 U1
C637 C206 GM@ 0_0402_5% GM@ GM@
2 PM@
+1.5VS_PEG_BG: 0.414mA AD48 VCCA_PEG_BG
(0.1UF*1) +1.5VS_PEG_BG
R166 20 mils
+1.05VS_HPLL +1.5VS_TVDAC +1.5VS
+1.5VS 2 1 AA48 VCCA_PEG_PLL +1.05VS_HPLL: 24mA R136
0_0402_5% 0_0402_5% 0_0603_5% +1.05VS_PEGPLL
PM@ PM@ R474 (4.7UF*1, 0.1UF*1) 2 1
1

0.022U_0402_16V7K

0.1U_0402_16V4Z
C301 2 1 +VCCP 0_0603_5%

10U_0805_10V4Z
MBK2012121YZF_0805 GM@
0.1U_0402_16V4Z
2 POWER 1 1 1

C198
AR20 VCCA_SM_1 1 1

C180

C195
AP20 C609 C604
+1.05VS_A_SM VCCA_SM_2
AN20 VCCA_SM_3
+VCCP R108 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2 2 2
AR17 VCCA_SM_4 2 2

A SM
1 2 AP17 VCCA_SM_5 VCCD_TVDAC: 58.696mA
VCCA_SM:720mA 1 0_0805_5% AN17 B22 +V1.05VS_AXF GM@ GM@ GM@
VCCA_SM_6 VCC_AXF_1 (0.1UF*1, 0.01UF*1)

AXF
1 1 1 AT16 B21
(22UF*2, 4.7UF*1, 1UF*1) C605 + C87 4.7U_0805_10V4Z C102 AR16
VCCA_SM_7 VCC_AXF_2
A21
C96 VCCA_SM_8 VCC_AXF_3 C180
AP16 VCCA_SM_9
C 150U_D_6.3VM 10U_0805_10V4Z 1U_0603_10V4Z C
2 2 2 2

VCC_SM_CK_1 BF21 +1.8V_SM_CK +1.05VS_MPLL +1.8V_TXLVDS

SM CK
+1.05VS_A_SM_CK VCC_SM_CK_2 BH20 1.05VS_MPLL: 139.2mA 40 mils
VCCA_SM_CK: 220mA BG20 R473 0_0402_5%
R134 VCC_SM_CK_3
BF20
(22UF*1, 0.1UF*1) R208 PM@
(22UF*1, 2.2UF*1, 0.1UF*1) 2 1 AP28
VCC_SM_CK_4
2 1 1000P_0402_50V7K 2 1
VCCA_SM_CK_1 +VCCP +1.8V
1U_0402_6.3V4Z

1U_0603_10V4Z

0_0603_5% AN28 MBK2012121YZF_0805 0_0603_5%

VCCA_SM_CK_2
10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
AP25 GM@ +1.8V_TXLVDS: 118.8mA
VCCA_SM_CK_3
1 1 1 1 AN25 +1.8V_TXLVDS 1 1 1 1
VCCA_SM_CK_4 (22UF*1, 1000PF*1)
C194

C214

C370
AN24 K47 C608 C603 C299
VCCA_SM_CK_5 VCC_TX_LVDS
C211

A CK
GM@ GM@
C210

AM28 VCCA_SM_CK_NCTF_1 +3VS_HV

AM26 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z C299
2 2 2 2 VCCA_SM_CK_NCTF_2 2 2 2 2

0.1U_0402_16V4Z
AM25 VCCA_SM_CK_NCTF_3
AL25 VCCA_SM_CK_NCTF_4 VCC_HV_1 C35 1
AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35

C649
HV
AL24 VCCA_SM_CK_NCTF_6 VCC_HV_3 A35
AM23 VCCA_SM_CK_NCTF_7 2
AL23 VCCA_SM_CK_NCTF_8 0_0402_5%
PM@
+3VS_TVDAC: 40mA VCC_PEG_1 V48 +VCC_PEG +VCCP
(0.1UF*1, 0.01UF*1 for VCC_PEG_2 U48
+1.05VS_PEGPLL
+1.5VS_PEG_PLL: 50mA +VCC_PEG

PEG
V47
GM@ each DAC) VCC_PEG_3
U47 L17 (0.1UF*1) R186
+3VS R117 +3VS_TVDAC VCC_PEG_4 BLM18PG121SN1D_0603
+3VS_TVDAC B24 VCCA_TV_DAC_1 VCC_PEG_5 U46 2 1
1 2 A24 2 1 +VCCP 0_0805_5%
VCCA_TV_DAC_2

10U_0805_10V4Z
TV 1 change to 0805 size 1/04

0.1U_0402_16V4Z

220U_D2_4VM
0_0603_5% 1

C339

C323
+
1 1 1 1

C342
C181 C171 VCC_HDA: 50mA +1.5VS A32 AH48 +VCC_DMI C355
VCC_HDA VCC_DMI_1
HDA

0.022U_0402_16V7K 0.1U_0402_16V4Z AF48

(0.1UF*1) VCC_DMI_2 2 2
DMI
AH47 VCC_DMI: 456mA 2.2U_0603_6.3V4Z
2 2 VCC_DMI_3 2 2
AG47
C181 GM@ GM@ VCC_DMI_4 (0.1UF*1) 0316 add
+1.5VS_TVDAC M25 VCCD_TVDAC
D TV/CRT

B +1.5VS_QDAC L28 VCCD_QDAC 20mils B

+VCCP
0_0402_5% +1.05VS_HPLL AF1 VCCD_HPLL
PM@ A8 +VCC_DMI
VTTLF1 R202
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VTTLF2 L1
+VCCP_D
VTTLF

VTTLF3 AB2 2 1
0_0805_5%
C94

C611 0.47U_0402_6.3V6K

C618 0.47U_0402_6.3V6K

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
+1.8V_LVDS M38 1 1 1 @ @
VCCD_LVDS_1
LVDS

L37 D1 R158 R157 1 1 1

VCCD_LVDS_2

C337

C353

C787
+VCCP 2 1 2 1 2 1 +3VS_HV
0.47U_0402_6.3V6K

10_0402_5% 0_0402_5%
2 2 2 CH751H-40PT_SOD323-2 add one more cap 1/2
CANTIGA ES_FCBGA1329 2 2 2
+3VS
U26
0316 add
GM@

PM
PM@

VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA

+1.5VS_QDAC (0.1UF*1, 0.01UF*1) +1.8V_LVDS (1UF*1)
R142
R137
2 1 +1.5VS
1U_0402_6.3V4Z

10U_0805_10V4Z

0_0603_5% 2 1 +1.8V
0.1U_0402_16V4Z

10U_0805_10V4Z

0_0603_5%
1U_0603_10V4Z

1 1 1 1 1 GM@
C237
C208

C207

C221

C226

A A
2 2 2 2 2 GM@

GM@ C237
GM@ GM@

0_0603_5%
PM@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (4/6)-VCC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom JIWA3/A4_LA4212P 1.0
gratuito - free of charge. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 14, 2008 Sheet 11 of 53
5 4 3 2 1
 5 4 3 2 1

U26F

+AXG_CORE
Check : power
VCC_AXG_NTCF_1 W28
AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
VCC_SM_2 VCC_AXG_NCTF_3
+1.8V BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25 1 C197 1 1

10U_0805_10V4Z

0.01U_0402_16V7K

C129
BF32 V25 C99
+VCCP VCC_SM_5 VCC_AXG_NCTF_6

220U_D2_4VM_R15
1 BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24
U26G 1 2 BC32 V24
VCC_SM_7 VCC_AXG_NCTF_8 2 2 2

C177

C643

C645
D + BB32 W23 D
VCC_SM_8 VCC_AXG_NCTF_9

VCC
AG34 VCC_1 BA32 VCC_SM_9 VCC_AXG_NCTF_10 V23
AC34 AY32 AM21 0.22U_0402_10V4Z
VCC_2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_11
AB34 VCC_3 AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21
AA34 VCC_4 AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21 GM@ GM@
Y34 AU32 W21 GM@
VCC_5 VCC_SM_13 VCC_AXG_NCTF_14
V34 AT32 V21

VCC CORE

SM
VCC_6 VCC_SM_14 VCC_AXG_NCTF_15
U34 VCC_7 AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21
AM33 VCC_8 AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20
AK33 VCC_9 AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20
AJ33 BH31 W20 C99
VCC_10 VCC_SM_18 VCC_AXG_NCTF_19
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AG33 VCC_11 BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20

10U_0805_10V4Z

AF33 VCC_12 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19

1 1 1 1 BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19
C193

C175

C220

BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19

C178

BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19

2 2 2 2
AE33 VCC_13 BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19 0_0603_5%
AC33 BD29 AG19 PM@
VCC_14 VCC_SM_25 VCC_AXG_NCTF_26
AA33 VCC_15 BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
Y33 +VCCP +AXG_CORE BB29 AE19
VCC_16 @ VCC_SM_27 VCC_AXG_NCTF_28
W33 VCC_17 J4 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19

POWER
V33 VCC_18 AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19

GFX NCTF
U33 VCC_19 1 1 2 2 AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19
AH28 VCC_20 AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19
AF28 VCC_21 JUMP_43X118 AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19
AC28 VCC_22 AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19
AA28 VCC_23 AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17
AJ26 VCC_24 AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17
AG26 VCC_25 VCC_AXG_NCTF_37 AH17
AE26 VCC_26 VCC_AXG_NCTF_38 AG17
AC26 VCC_27 VCC_AXG_NCTF_39 AF17
AH25 +VCCP BA36 AE17
C VCC_28 VCC_SM_36/NC VCC_AXG_NCTF_40 C
AG25 VCC_29 BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17

VCC
AF25 VCC_30 BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17
AG24 VCC_31 VCC_NCTF_1 AM32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17
AJ23 VCC_32 VCC_NCTF_2 AL32 AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17
AH23 VCC_33 VCC_NCTF_3 AK32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
AF23 VCC_34 VCC_NCTF_4 AJ32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16
T32 VCC_35 VCC_NCTF_5 AH32 VCC_AXG_NCTF_47 AL16
AG32 AK16

POWER
VCC_NCTF_6 VCC_AXG_NCTF_48
VCC_NCTF_7 AE32 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_8 AC32 VCC_AXG_NCTF_50 AH16
VCC_NCTF_9 AA32 VCC_AXG_NCTF_51 AG16
VCC_NCTF_10 Y32 VCC_AXG_NCTF_52 AF16
VCC_NCTF_11 W32 Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16
U32 +AXG_CORE AE25 AC16
VCC_NCTF_12 VCC_AXG_2 VCC_AXG_NCTF_54
VCC_NCTF_13 AM30 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16
VCC_NCTF_14 AL30 AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16
VCC_NCTF_15 AK30 AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16
AH30 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 W16
VCC_NCTF_16 VCC_AXG_6 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AA24 VCC_AXG_7 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16
VCC_NCTF_19 AE30 1 1 1 1 AE23 VCC_AXG_9
AC30 C149 C84 + C104 C157 C167 AC23
NCTF

VCC_NCTF_20 VCC_AXG_10
VCC_NCTF_21 AB30 AB23 VCC_AXG_11
AA30 1U_0603_10V4Z AA23
VCC_NCTF_22 2 2 2 2 2 VCC_AXG_12
VCC_NCTF_23 Y30 AJ21 VCC_AXG_13
VCC_NCTF_24 W30 AG21 VCC_AXG_14
V30 220U_D2_4VM_R15 10U_0805_10V4Z AE21
VCC_NCTF_25 VCC_AXG_15
VCC_NCTF_26 U30 AC21 VCC_AXG_16
VCC

AL29 GM@ GM@ GM@ GM@ GM@ AA21

VCC_NCTF_27 VCC_AXG_17
VCC_NCTF_28 AK29 Y21 VCC_AXG_18

VCC
VCC_NCTF_29 AJ29 AH20 VCC_AXG_19
VCC_NCTF_30 AH29 AF20 VCC_AXG_20
B B
VCC_NCTF_31 AG29 AE20 VCC_AXG_21
AE29 C104 C157 AC20
VCC_NCTF_32 VCC_AXG_22
VCC_NCTF_33 AC29 AB20 VCC_AXG_23
AA29 AA20

GFX
VCC_NCTF_34 VCC_AXG_24
VCC_NCTF_35 Y29 T17 VCC_AXG_25
VCC_NCTF_36 W29 T16 VCC_AXG_26
VCC_NCTF_37 V29 AM15 VCC_AXG_27
VCC_NCTF_38 AL28 0_0805_5% 0_0805_5% AL15 VCC_AXG_28
AK28 PM@ PM@ AE15
VCC_NCTF_39 VCC_AXG_29
VCC_NCTF_40 AL26 AJ15 VCC_AXG_30
VCC_NCTF_41 AK26 AH15 VCC_AXG_31
VCC_NCTF_42 AK25 AG15 VCC_AXG_32
VCC_NCTF_43 AK24 AF15 VCC_AXG_33
VCC_NCTF_44 AK23 AB15 VCC_AXG_34
AA15 VCC_AXG_35
Y15 VCC_AXG_36
V15 VCC_AXG_37
U15 VCC_AXG_38
AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1

VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
CANTIGA ES_FCBGA1329
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
GM@ T32 AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10 VCCSM_LF6
T31 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7

C121 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z

C101 0.22U_0402_10V4Z

C159 0.22U_0402_10V4Z

C264 0.47U_0402_6.3V6K

C243 1U_0402_6.3V4Z

C297 1U_0402_6.3V4Z
1 1 1 1 1 1 1

2 2 2 2 2 2 2
A A
CANTIGA ES_FCBGA1329

GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (5/6)-VCC
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008
1
Sheet 12 of 53
 5 4 3 2 1

U26I U26J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
NC_40
NC_41 C48
GM@ NC_42 B48

CANTIGA ES_FCBGA1329

A A
GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (6/6)-GND
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Wednesday, May 14, 2008
1
Sheet 13 of 53
 5 4 3 2 1

Layout Note:
+1.8V +1.8V
+DDR_MCH_REF
<9> DDR_A_DQS#[0..7]
trace width and +DDR_MCH_REF1
+DDR_MCH_REF1 <15>
spacing is 20/20.
<9> DDR_A_D[0..63] JP17

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<9> DDR_A_DM[0..7] +1.8V VSS DQ4

C388

C402
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<9> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
VSS DM0

1
DDR_A_DQS#0 2 2
<9> DDR_A_MA[0..13] 11 DQS0# VSS 12
R225 DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
100_0402_1% DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 20

2
+DDR_MCH_REF1 DQ3 DQ12 DDR_A_D12
<15> +DDR_MCH_REF1 21 VSS DQ13 22

0.1U_0402_16V4Z
DDR_A_D8 23 24
DQ8 VSS

1
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
R232 DQ9 DM1
1 27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <8>
DQS1# CK0

C404
100_0402_1% DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 <8>
33 34

2
2 DDR_A_D9 VSS VSS DDR_A_D11
35 DQ10 DQ14 36
DDR_A_D15 37 38 DDR_A_D10
DQ11 DQ15
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <8>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C235

C152

C644

C268

C151

C218

C219

C653

C650
+ C215 53 54
470U_D2_2.5VM_R15 DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
@ DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
<15,35,37> EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<8> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <8>
81 VDD VDD 82
<15,35,37> EC_RX_P80_CLK 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
<9> DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 <9>
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <9>
DDR_A_BS#0 107 108 DDR_A_RAS#
<9> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <9>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS <9> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<9> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<8> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<8> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D33
DDR_A_D36 DQ32 DQ36 DDR_A_D39
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C170

C179

C209

C228

C236

C161

C230

C162

C223

C217

C163

C242

C164

133 134 DDR_A_D35

DDR_A_D38 VSS DQ38 DDR_A_D34
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
+0.9VS DDR_A_D48 DQ48 DQ52 DDR_A_D53
Layout Note: 159 DQ49 DQ53 160
Place these resistor 161 VSS VSS 162
RP1 RP2 EC_RX_P80_CLK_R 163 164 M_CLK_DDR1
closely JP41,all <15> EC_RX_P80_CLK_R NC,TEST CK1 M_CLK_DDR1 <8>
DDR_A_WE# 1 8 8 1 DDR_A_RAS# 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <8>
DDR_A_CAS# 2 7 7 2 M_ODT0 trace length Max=1.5" DDR_A_DQS#6 167 168
M_ODT1 DDR_A_MA13 DDR_A_DQS6 DQS6# VSS DDR_A_DM6
3 6 6 3 169 DQS6 DM6 170
DDR_CS1_DIMMA# 4 5 5 4 DDR_CS0_DIMMA# 171 172
DDR_A_D54 VSS VSS DDR_A_D51
173 DQ50 DQ54 174
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
DDR_A_BS#0 R128 1 2 RP5 DDR_A_D61 179 180 DDR_A_D57
56_0402_5% DDR_A_BS#1 DDR_A_D60 DQ56 DQ60 DDR_A_D56
5 4 181 DQ57 DQ61 182
DDR_A_MA10 R133 1 2 6 3 DDR_A_MA0 183 184
56_0402_5% DDR_A_MA2 DDR_A_DM7 VSS VSS DDR_A_DQS#7
7 2 185 DM7 DQS7# 186
DDR_A_MA14 R146 1 2 8 1 DDR_A_MA4 187 188 DDR_A_DQS7
56_0402_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
56_0804_8P4R_5% DDR_A_D58 191 192 DDR_A_D62
DQ59 DQ62 DDR_A_D63
193 VSS DQ63 194
RP6 RP9 CLK_SMBDATA 195 196
<15,22> CLK_SMBDATA SDA VSS
DDR_A_MA1 4 5 5 4 DDR_A_MA6 CLK_SMBCLK 197 198
<15,22> CLK_SMBCLK SCL SA0
DDR_A_MA3 3 6 6 3 DDR_A_MA7 199 200
+3VS VDDSPD SA1
DDR_A_MA5 2 7 7 2 DDR_A_MA11

1
10K_0402_5%

10K_0402_5%
DDR_A_MA8 1 8 8 1 DDR_CKE1_DIMMA 1
C83 FOX_ASOA426-M2RN-7F

R73

R77
A 56_0804_8P4R_5% 56_0804_8P4R_5% A
ME@
0.1U_0402_16V4Z
RP10 2
SO-DIMM A

2
DDR_A_MA9 4 5
DDR_A_MA12 3 6
DDR_A_BS#2 2 7
DDR_CKE0_DIMMA 1 8 Top side
56_0804_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 14 of 53
 5 4 3 2 1

+1.8V +1.8V
<9> DDR_B_DQS#[0..7]

<9> DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 <14>
<9> DDR_B_DM[0..7] JP16

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<9> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D5
<9> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C403

C407
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 <8>
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 <8>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C232

C150

C387

C156

C241

C192

C188

C199

C191
+ C155 47 48
470U_D2_2.5VM_R15 DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 <8>
@ DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D25 61 62 DDR_B_D26
DDR_B_D28 DQ24 DQ28 DDR_B_D24
T80 63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
<14,35,37> EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<8> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <8>
81 VDD VDD 82
Layout Note: <14,35,37> EC_RX_P80_CLK
DDR_B_BS#2
83 NC NC/A15 84
DDR_B_MA14
<9> DDR_B_BS#2 85 BA2 NC/A14 86 DDR_B_MA14 <9>
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 <9>
DDR_B_BS#0 107 108 DDR_B_RAS#
<9> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <9>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<9> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<9> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<8> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<8> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C244

C240

C227

C216

C196

C187

C247

C246

C229

C222

C204

C185

C176

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
T22 DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Place these resistor 161 VSS VSS 162
+0.9VS EC_RX_P80_CLK_R 163 164 M_CLK_DDR3
closely JP42,all <14> EC_RX_P80_CLK_R NC,TEST CK1 M_CLK_DDR3 <8>
165 166 M_CLK_DDR#3
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#3 <8>
RP3 RP4 trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_CAS# 8 1 4 5 DDR_B_MA13 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_WE# M_ODT2 DQS6 DM6
7 2 3 6 171 VSS VSS 172
DDR_CS3_DIMMB# 6 3 2 7 DDR_CS2_DIMMB# DDR_B_D51 173 174 DDR_B_D54
M_ODT3 DDR_B_RAS# DDR_B_D50 DQ50 DQ54 DDR_B_D55
5 4 1 8 175 DQ51 DQ55 176
177 VSS VSS 178
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
DDR_B_BS#0 R135 1 2 RP7 183 184
56_0402_5% DDR_B_BS#1 DDR_B_DM7 VSS VSS DDR_B_DQS#7
4 5 185 DM7 DQS7# 186
DDR_B_MA10 R131 1 2 3 6 DDR_B_MA0 187 188 DDR_B_DQS7
56_0402_5% DDR_B_MA2 DDR_B_D58 VSS DQS7
2 7 189 DQ58 VSS 190
DDR_B_MA14 R152 1 2 1 8 DDR_B_MA4 DDR_B_D59 191 192 DDR_B_D62
DQ59 DQ62 DDR_B_D63
193 VSS DQ63 194
56_0804_8P4R_5% CLK_SMBDATA 195 196
<14,22> CLK_SMBDATA SDA VSS
CLK_SMBCLK 197 198 R74
<14,22> CLK_SMBCLK SCL SAO
RP8 RP11 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_MA1 5 4 4 5 DDR_B_MA7

1
10K_0402_5%
DDR_B_MA3 6 3 3 6 DDR_B_MA6 1 10K_0402_5%

R78
A DDR_B_MA5 DDR_B_MA11 C82 FOX_AS0A426-NARN-7F~N A
7 2 2 7
DDR_B_MA9 8 1 1 8 DDR_CKE3_DIMMB ME@
0.1U_0402_16V4Z
56_0804_8P4R_5% 56_0804_8P4R_5% 2 SO-DIMM B

2
RP12
DDR_CKE2_DIMMB 8 1
DDR_B_BS#2 7 2
DDR_B_MA12
DDR_B_MA8
6 3
Security Classification Compal Secret Data Compal Electronics, Inc.
5 4 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

56_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 15 of 53
 5 4 3 2 1

U27A
L39 PM@ MBK1608121YZF_0603
PCIE_MTX_C_GRX_P0 AE12 Part 1 of 5 N1 VGA_DDCCLK_C 1 2 VGA_DDCCLK <25>
PCIE_MTX_C_GRX_N0 PEX_RX0 GPIO0 VGA_DDCDATA_C
AF12 PEX_RX0_N GPIO1 G1 HDMI_DETECT_VGA <23> 1 2 VGA_DDCDATA <25>
PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P1 AG12 C1 NV_INVTPWM L40 PM@ MBK1608121YZF_0603
<10> PCIE_MTX_C_GRX_N[0..15] PEX_RX1 GPIO2 PAD T86
PCIE_MTX_C_GRX_N1 AG13 M2 VGA_ENVDD PM@ MBK1608121YZF_0603
PCIE_MTX_C_GRX_P[0..15] PEX_RX1_N GPIO3 VGA_ENVDD <24>
PCIE_MTX_C_GRX_P2 AF13 M3 VGA_ENBKL VGA_LVDS_SCL_C L41
1 2 VGA_LVDS_SCL <24>
<10> PCIE_MTX_C_GRX_P[0..15] PEX_RX2 GPIO4 VGA_ENBKL <24>
PCIE_MTX_C_GRX_N2 AE13 K3 VGA_LVDS_SDA_C 1 2 VGA_LVDS_SDA <24>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P3 PEX_RX2_N GPIO5 L42 PM@ MBK1608121YZF_0603
<10> PCIE_GTX_C_MRX_N[0..15] AE15 PEX_RX3 GPIO6 K2
PCIE_MTX_C_GRX_N3 AF15 J2
PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P4 PEX_RX3_N GPIO7
AG15 C2

GPIO
<10> PCIE_GTX_C_MRX_P[0..15] PEX_RX4 GPIO8 1 1 1 1
PCIE_MTX_C_GRX_N4 AG16 M1 C770C771C772C773
D PCIE_MTX_C_GRX_P5 PEX_RX4_N GPIO9 12P_0402_50V8J 12P_0402_50V8J D
AF16 PEX_RX5 GPIO10 D2
PCIE_MTX_C_GRX_N5 AE16 D1 12P_0402_50V8J 12P_0402_50V8J
PCIE_MTX_C_GRX_P6 PEX_RX5_N GPIO11 2 2 2 2
AE18 PEX_RX6 GPIO12 J3
PCIE_MTX_C_GRX_N6 AF18 J1
PCIE_MTX_C_GRX_P7 PEX_RX6_N GPIO13
AG18 PEX_RX7 GPIO14 K1
PCIE_MTX_C_GRX_N7 AG19 F3
PCIE_MTX_C_GRX_P8 PEX_RX7_N GPIO15 PM@ PM@PM@PM@
AF19 PEX_RX8 GPIO16 G3
PCIE_MTX_C_GRX_N8 AE19 G2 PAD
PEX_RX8_N GPIO17 T29
PCIE_MTX_C_GRX_P9 AE21 F1
PCIE_MTX_C_GRX_N9 PEX_RX9 GPIO18
AF21 PEX_RX9_N GPIO19 F2
PCIE_MTX_C_GRX_P10 AG21
PCIE_MTX_C_GRX_N10 PEX_RX10 VGA_HSYNC
AG22 PEX_RX10_N DACA_HSYNC AD2 VGA_HSYNC <25>
PCIE_MTX_C_GRX_P11 AF22 AD1 VGA_VSYNC VGA_VSYNC <25>
PEX_RX11 DACA_VSYNC

DACA
PCIE_MTX_C_GRX_N11 AE22
PCIE_MTX_C_GRX_P12 PEX_RX11_N VGA_CRT_R
AE24 PEX_RX12 DACA_RED AE2 VGA_CRT_R <25>
PCIE_MTX_C_GRX_N12 AF24 AD3 VGA_CRT_B
PCIE_MTX_C_GRX_P13 AG24
PEX_RX12_N DACA_BLUE
AE3 VGA_CRT_G
VGA_CRT_B <25>
VGA_CRT_G <25>
CRT OUT
PCIE_MTX_C_GRX_N13 PEX_RX13 DACA_GREEN VGA_CRT_R R164 PM@ 2 150_0402_1%
AF25 PEX_RX13_N 1
PCIE_MTX_C_GRX_P14 AG25 AF1 DACA_VREF 2 1 PM@ VGA_CRT_G R168 1 PM@ 2 150_0402_1%
PCIE_MTX_C_GRX_N14 PEX_RX14 DACA_VREF DACA_RSET C648 0.1U_0402_16V4Z VGA_CRT_B R180 PM@ 2 150_0402_1%
AG26 PEX_RX14_N DACA_RSET AE1 1
PCIE_MTX_C_GRX_P15 AF27
PCIE_MTX_C_GRX_N15 PEX_RX15 R503 PM@ 124_0402_1%
AE27 PEX_RX15_N DACB_CSYNC D6

PCIE_GTX_C_MRX_P0 C261 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P0

DACB
1 2 AD10 PEX_TX0 DACB_RED F7
PCIE_GTX_C_MRX_N0 C260 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N0 AD11 E6
PCIE_GTX_C_MRX_P1 C294 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P1 PEX_TX0_N DACB_BLUE +3VS
1 2 AD12 PEX_TX1 DACB_GREEN E7
PCIE_GTX_C_MRX_N1 C293 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N1 AC12
PCIE_GTX_C_MRX_P2 C259 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P2 PEX_TX1_N
1 2 AB11 PEX_TX2
PCIE_GTX_C_MRX_N2 C258 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N2 AB12 G6
PCIE_GTX_C_MRX_P3 C292 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P3 PEX_TX2_N DACB_VREF HDMI_PM@
1 2 AD13 PEX_TX3 DACB_RSET F8
PCIE_GTX_C_MRX_N3 C291 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N3 AD14 C79
PEX_TX3_N

1
PCIE_GTX_C_MRX_P4 C257 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P4 AD15 U6 1 2 0.1U_0402_16V4Z
C PCIE_GTX_C_MRX_N4 C256 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N4 PEX_TX4 DACC_HSYNC R75 R69 R65 C
1 2 AC15 PEX_TX4_N DACC_VSYNC U4
PCIE_GTX_C_MRX_P5 C290 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P5 AB14 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5%
PCIE_GTX_C_MRX_N5 C289 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N5 PEX_TX5 HDMI_PM@ HDMI_PM@ @ U4

DACC
1 2 AB15 PEX_TX5_N DACC_RED T5
PCIE_GTX_C_MRX_P6 C255 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P6 AC16 R4 8 1

PCI EXPRESS

2
PCIE_GTX_C_MRX_N6 C254 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N6 PEX_TX6 DACC_BLUE VCC A0
1 2 AD16 PEX_TX6_N DACC_GREEN T4 7 WP A1 2
PCIE_GTX_C_MRX_P7 C287 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P7 AD17 HDCP_SMB_CK1 6 3
PCIE_GTX_C_MRX_N7 C288 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N7 PEX_TX7 HDCP_SMB_DAI SCL A2
1 2 AD18 PEX_TX7_N DACC_VREF R6 5 SDA GND 4
PCIE_GTX_C_MRX_P8 C253 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P8 AC18 V6
PCIE_GTX_C_MRX_N8 C252 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N8 PEX_TX8 DACC_RSET AT24C16AN-10SU-2.7_SO8
1 2 AB18 PEX_TX8_N
PCIE_GTX_C_MRX_P9 C285 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P9 AB19 HDMI_PM@
PEX_TX9

1
PCIE_GTX_C_MRX_N9 C286 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N9 AB20 PEX_TX9_N

1
PCIE_GTX_C_MRX_P10 C251 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P10 AD19 R1 VGA_DDCCLK_C +3VS R71 R66
PCIE_GTX_C_MRX_N10 C250 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N10 PEX_TX10 I2CA_SCL VGA_DDCDATA_C 10K_0402_5% 10K_0402_5% R70
1 2 AD20 PEX_TX10_N I2CA_SDA T3
PCIE_GTX_C_MRX_P11 C284 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P11 AD21 R2 R116 1 2 2.2K_0402_5% PM@ @ @ 100K_0402_1% HDMI_PM@
PCIE_GTX_C_MRX_N11 C283 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N11 PEX_TX11 I2CB_SCL R119 1 2.2K_0402_5% PM@
1 2 AC21 R3 2

2
PCIE_GTX_C_MRX_P12 C249 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P12 PEX_TX11_N I2CB_SDA VGA_LVDS_SCL_C
1 2 AB21 A2

2
PCIE_GTX_C_MRX_N12 C248 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N12 PEX_TX12 I2CC_SCL VGA_LVDS_SDA_C
1 2 AB22 PEX_TX12_N I2CC_SDA B1
PCIE_GTX_C_MRX_P13 C282 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P13 AC22 I2C N2 R196 1 2 2.2K_0402_5% PM@
PCIE_GTX_C_MRX_N13 C281 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N13 PEX_TX13 I2CD_SCL R193 1 2.2K_0402_5% PM@
1 2 AD22 PEX_TX13_N I2CD_SDA N3 2
PCIE_GTX_C_MRX_P14 C267 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P14 AD23 Y6 VGA_HDMI_SCL VGA_HDMI_SCL <23>
PCIE_GTX_C_MRX_N14 C266 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N14 PEX_TX14 I2CE_SCL VGA_HDMI_SDA PM@
1 2 AD24 PEX_TX14_N I2CE_SDA W6 VGA_HDMI_SDA <23>
PCIE_GTX_C_MRX_P15 C280 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P15 AE25 A3 HDCP_SMB_CK1 JTAG_TRST_N 1 R645 2
PCIE_GTX_C_MRX_N15 C279 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N15 PEX_TX15 I2CH_SCL HDCP_SMB_DAI 10K_0402_5%
1 2 AE26 PEX_TX15_N I2CH_SDA A4
T1 EC_SMB_CK2 TESTMODE 1 R646 2
I2CS_SCL EC_SMB_CK2 <5,35,41>
<22> CLK_PCIE_VGA CLK_PCIE_VGA AB10 T2 EC_SMB_DA2 10K_0402_5%
PEX_REFCLK I2CS_SDA EC_SMB_DA2 <5,35,41>
<22> CLK_PCIE_VGA# CLK_PCIE_VGA# AC10 PM@
PEX_REFCLK_N
AF10 PEX_TSTCLK_OUT
1 2 AE10 AF3 JTAG_TCK PAD
PEX_TSTCLK_OUT_N JTAG_TCK T60
R183 200_0402_5% @ AG4
TEST

JTAG_TDI JTAG_TDO
2 1 AG10 PEX_TERMP JTAG_TDO AE4 PAD T59
R504 2.4K_0402_1% PM@ AF4 +3VS
B PLT_RST# JTAG_TMS JTAG_TRST_N B
<8,26,32,33,36,40> PLT_RST# AD9 PEX_RST_N JTAG_TRST_N AG3 PAD T92
AD25 TESTMODE PAD VGA_HDMI_SDA R492 1 @ 2 2.2K_0402_5%
TESTMODE T57
1 2 10K_0402_5% VGA_HDMI_SCL R490 1 @ 2 2.2K_0402_5%
@ R173 VGA_DDCCLK R489 1 @ 2 2.2K_0402_5%
OSC_SPREAD D11 F9 SPDIF_IN PAD VGA_DDCDATA R491 1 @ 2 2.2K_0402_5%
XTAL_SSIN SPDIF T28
E9 W15 +VGASENSE +VGASENSE
XTAL_OUTBUFF VDD_SENSE
XTALOUT
HDA
CLK

E10 XTAL_OUT
1

XTALIN D10 C6 HDA_RST_CODEC#_R R650 1 PM@

2 22_0402_5% HDA_RST_CODEC# <8,27,30>
R99 R100 XTAL_IN HDA_RST_N HDA_SDIN1_R R86 PM@ 10_0402_5%
HDA_SDI A6 1 2 HDA_SDIN1 <27>
10K_0402_5% 10K_0402_5% B6 HDA_SDOUT_CODEC_R R651 1 PM@
2 22_0402_5%
HDA_SDO HDA_SDOUT_CODEC <8,27,30>
PM@ PM@ B7 HDA_SYNC_CODEC_R R652 1 PM@
2 22_0402_5%
HDA_SYNC HDA_SYNC_CODEC <8,27,30>
A7 HDA_BITCLK_CODEC_R R653 1 PM@
2 22_0402_5%
HDA_BITCLK_CODEC <8,27,30>
2

PM@ HDA_BCLK
1

NB9M-GS_BGA533
If External Spread Spectrum not stuff than stuff resistor R647
10K_0402_5%
External Spread Spectrum @
2

Y3 U3
3 OUT GND 4 1 REFOUT VSS 6
@
2 GND IN 1 2 XOUT MODOUT 5 1 2 OSC_SPREAD
R55 22_0402_5%
27MHZ_16PF_X7S027000BG1H-U 3 4 +3VS
PM@ XIN/CLKIN VDD
1 1
C612 C614 2
A ASM3P2872AF-06OR_TSOT-23-6 A
18P_0402_50V8J 18P_0402_50V8J @ C66
PM@ 2 PM@ 2 0.1U_0402_16V4Z
1
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB9M-GS PCIE,LVDS,GPIO,CLK
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008
1
Sheet 16 of 53
 5 4 3 2 1

FBAD[0..63]
FBAD[0..63] <20,21>

FBAA[0..12]
FBAA[0..12] <20,21>
FBAODT0

1
FBBA[2..5]
FBBA[2..5] <21>
R129
10K_0402_5%
FBADQS[0..7]
FBADQS[0..7] <20,21>
PM@

2
D FBADQS#[0..7] D
FBADQS#[0..7] <20,21>

FBADQM#[0..7]
FBADQM#[0..7] <20,21>

U27C
U27B
FBAD0 D21 F26 FBAA3 VGA_LVDS_ACLK AC4 Part 3 of 5 C15
FBA_D0 Part 2 of 5 FBA_CMD0 <24> VGA_LVDS_ACLK IFPA_TXC NC
FBAD1 C22 J24 FBAA0 VGA_LVDS_ACLK# AD4 D15
FBA_D1 FBA_CMD1 <24> VGA_LVDS_ACLK# IFPA_TXC_N NC
FBAD2 B22 F25 FBAA2 VGA_LVDS_A0 V5 E15
FBA_D2 FBA_CMD2 <24> VGA_LVDS_A0 IFPA_TXD0 NC
FBAD3 A22 M23 FBAA1 VGA_LVDS_A0# V4 F6
FBA_D3 FBA_CMD3 <24> VGA_LVDS_A0# IFPA_TXD0_N NC
FBAD4 C24 N27 FBBA3 VGA_LVDS_A1 AA5 J5
FBA_D4 FBA_CMD4 <24> VGA_LVDS_A1 IFPA_TXD1 NC
FBAD5 B25 M27 FBBA4 VGA_LVDS_A1# AA4 J22
<24> VGA_LVDS_A1#

NC
FBAD6 FBA_D5 FBA_CMD5 FBBA5 VGA_LVDS_A2 IFPA_TXD1_N NC
A25 FBA_D6 FBA_CMD6 K26 <24> VGA_LVDS_A2 W4 IFPA_TXD2 NC L22
FBAD7 A26 J25 FBACS1# PAD T33 VGA_LVDS_A2# Y4 T6
FBA_D7 FBA_CMD7 <24> VGA_LVDS_A2# IFPA_TXD2_N NC
FBAD8 D22 J27 FBACS0# AB4 AA6
FBA_D8 FBA_CMD8 FBACS0# <20,21> IFPA_TXD3 NC
FBAD9 E22 G23 FBAWE# AB5 AC19
FBA_D9 FBA_CMD9 FBAWE# <20,21> <20,21> FBA_CKE IFPA_TXD3_N NC
FBAD10 E24 G26 FBA_BA0 AE9
FBA_D10 FBA_CMD10 FBA_BA0 <20,21> NC
FBAD11 D24 J23 FBA_CKE AB3 AG9
FBAD12 FBA_D11 FBA_CMD11 AODT0 R494 1 IFPB_TXC NC
D26 FBA_D12 FBA_CMD12 M25 2 FBAODT0 FBAODT0 <20,21> AB2 IFPB_TXC_N

1
FBAD13 D27 K27 FBBA2 PM@ 0_0402_5% W1
FBAD14 FBA_D13 FBA_CMD13 FBAA12 R118 IFPB_TXD4 STRAP0
C27 G25 V1 C7

STRAP
FBA_D14 FBA_CMD14 IFPB_TXD4_N STRAP0 STRAP0 <19>
FBAD15 B27 L24 FBARAS# 10K_0402_5% W3 B9 STRAP1
FBA_D15 FBA_CMD15 FBARAS# <20,21> IFPB_TXD5 STRAP1 STRAP1 <19>

1
FBAD16 D16 K23 FBAA11 PM@ W2 A9 STRAP2
FBA_D16 FBA_CMD16 IFPB_TXD5_N STRAP2 STRAP2 <19>
FBAD17 E16 K24 FBAA10 R499 AA2

2
FBAD18 FBA_D17 FBA_CMD17 FBA_BA1 IFPB_TXD6
D17 FBA_D18 FBA_CMD18 G22 FBA_BA1 <20,21> 10K_0402_5% AA3 IFPB_TXD6_N
FBAD19 F18 K25 FBAA8 @ AB1 F10
FBAD20 FBA_D19 FBA_CMD19 FBAA9 IFPB_TXD7 STARP_REF_MIOB
D20 H22 AA1 F11

2
FBA_D20 FBA_CMD20 IFPB_TXD7_N STARP_REF_3V3

1
FBAD21 F20 M26 FBAA6
C FBAD22 FBA_D21 FBA_CMD21 FBAA5 R88 R91 C
E21 FBA_D22 FBA_CMD22 H24
FBAD23 F21 F27 FBAA7 <23> VGA_HDMI_TX2+ VGA_HDMI_TX2+ P4 40.2K_0402_1% 40.2K_0402_1%
FBAD24 FBA_D23 FBA_CMD23 FBAA4 VGA_HDMI_TX2- IFPC_L0 PM@ PM@
C16 FBA_D24 FBA_CMD24 J26 <23> VGA_HDMI_TX2- N4 IFPC_L0_N BUFRST_N N5 PAD T36

GENERAL
MEMORY INTERFACE

FBAD25 B18 G24 FBACAS# <23> VGA_HDMI_TX1+ VGA_HDMI_TX1+ M5

FBACAS# <20,21>

2
FBAD26 FBA_D25 FBA_CMD25 VGA_HDMI_TX1- IFPC_L1

LVDS/TMDS
C18 FBA_D26 FBA_CMD26 G27 <23> VGA_HDMI_TX1- M4 IFPC_L1_N THERMDN D8 PAD T24
FBAD27 D18 M24 FBABA2 <23> VGA_HDMI_TX0+ VGA_HDMI_TX0+ L4
FBA_D27 FBA_CMD27 FBABA2 <20,21> IFPC_L2
FBAD28 C19 K22 <23> VGA_HDMI_TX0- VGA_HDMI_TX0- K4 D9 PAD
FBA_D28 FBA_CMD28 IFPC_L2_N THERMDP T85
FBAD29 C21 <23> VGA_HDMI_CLK+ VGA_HDMI_CLK+ H4
FBAD30 FBA_D29 FBADQM#0 VGA_HDMI_CLK- IFPC_L3
B21 FBA_D30 FBA_DQM0 D23 <23> VGA_HDMI_CLK- J4 IFPC_L3_N
FBAD31 A21 C26 FBADQM#1
FBAD32 FBA_D31 FBA_DQM1 FBADQM#2
P22 D19 F5 B10
FBAD33 P24
FBA_D32
FBA_D33
FBA_DQM2
FBA_DQM3 B19 FBADQM#3 C269~C276 NEAR CONNECT F4
IFPE_L0
IFPE_L0_N
ROM_CS_N
FBAD34 FBADQM#4 ROM_SCLK

SERIAL
FBAD35
R23
R24
FBA_D34 FBA_DQM4 T24
T26 FBADQM#5
R186~R195 NEAR CONNECT PULL DOWN E4
D5
IFPE_L1 ROM_SCLK C9 ROM_SCLK <19>
FBAD36 FBA_D35 FBA_DQM5 FBADQM#6 IFPE_L1_N ROM_SI
FBAD37
T23
U24
FBA_D36 FBA_DQM6 AA23
AB27 FBADQM#7 TMDS pull down (500ohm) resistors G9x only C3
C4
IFPE_L2 ROM_SI A10 ROM_SI <19>
FBAD38 FBA_D37 FBA_DQM7 IFPE_L2_N ROM_SO
V23 FBA_D38 B3 IFPE_L3 ROM_SO C10 ROM_SO <19>
FBAD39 V24 B24 FBADQS#0 B4
FBAD40 FBA_D39 FBA_DQS_RN0 FBADQS#1 IFPE_L3_N
N25 FBA_D40 FBA_DQS_RN1 D25
FBAD41 N26 E18 FBADQS#2 D4
FBAD42 FBA_D41 FBA_DQS_RN2 FBADQS#3 R182 1 IFPE_AUX_N
R25 FBA_D42 FBA_DQS_RN3 A18 2 @ 1K_0402_5% AB6 IFPAB_RSET IFPE_AUX D3
FBAD43 R26 R22 FBADQS#4 R98 1 2 @ 1K_0402_5% M6 G5
FBAD44 FBA_D43 FBA_DQS_RN4 FBADQS#5 R102 1 1K_0402_5% IFPE_RSET IFPC_AUX_N
T25 FBA_D44 FBA_DQS_RN5 R27 2 R5 IFPC_RSET IFPC_AUX G4
FBAD45 V26 Y24 FBADQS#6
FBAD46 FBA_D45 FBA_DQS_RN6 FBADQS#7
V25 FBA_D46 FBA_DQS_RN7 AA27 PM@
FBAD47 V27 NB9M-GS_BGA533
FBAD48 FBA_D47 FBADQS0 PM@
V22 FBA_D48 FBA_DQS_WP0 A24
FBAD49 W22 C25 FBADQS1 +1.8VS
FBAD50 FBA_D49 FBA_DQS_WP1 FBADQS2
W23 FBA_D50 FBA_DQS_WP2 E19
FBAD51 W24 A19 FBADQS3
FBA_D51 FBA_DQS_WP3

1
FBAD52 AA22 T22 FBADQS4
FBAD53 FBA_D52 FBA_DQS_WP4 FBADQS5 R87
AB23 FBA_D53 FBA_DQS_WP5 T27
B FBAD54 FBADQS6 1K_0402_1% B
AB24 FBA_D54 FBA_DQS_WP6 AA24
FBAD55 AC24 AA26 FBADQS7 @
FBAD56 FBA_D55 FBA_DQS_WP7
W25 15mil
2
FBAD57 FBA_D56 FB_VREF1
W26 FBA_D57 FB_VREF A16
FBAD58 W27 FBA_D58
FBAD59 AA25 FBA_D59 FBA_CLK0 F24 FBACLK0 <20> 1 1
FBAD60 AB25 F23 C90 R90
FBA_D60 FBA_CLK0_N FBACLK0# <20>
FBAD61 AB26 @ 1K_0402_1%
FBAD62 FBA_D61 0.1U_0402_16V4Z
AD26 FBA_D62 FBA_CLK1 N24 FBACLK1 <21> @
FBAD63 2
AD27 N23 FBACLK1# <21>
2

FBA_D63 FBA_CLK1_N +1.8VS

M22 FBA_DEBUG 1 2
FBA_DEBUG R113 10K_0402_5%
NB9M-GS_BGA533 PM@
PM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB9M-GS Memory
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008
1
Sheet 17 of 53
 5 4 3 2 1

PLACE NEAR BGA +1.8VS

+VGA_CORE 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U 6.3V K X5R 0603

11.57A NEAR BALL U27D C128

1
C134
1
C125
1
C124
1 1
C107 C131
1
@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J9 A13 PM@ PM@ PM@ PM@ PM@
VDD FBVDDQ 2 2 2 2 2 2
D 1 J10 VDD FBVDDQ B13 D

220U_D2_4VM
1 1 1 1 1 1 J12 C13 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U 6.3V K X5R 0603
+ C182 C135 C141 C148 C146 C147 VDD FBVDDQ
J13 VDD FBVDDQ D13

C680
PM@ L9 D14
PM@ PM@ PM@ PM@ PM@ PM@ VDD FBVDDQ
M9 VDD FBVDDQ E13
2 2 2 2 2 2 2 Part 4 of 5
M11 F13
M17
VDD
VDD
FBVDDQ
FBVDDQ F14 PLACE BELOW GPU FBAVDDQ=1.72A +1.8VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z N9 F15
VDD FBVDDQ 4700P_0402_25V7K 4700P_0402_25V7K 1U_0603_10V4Z
N11 VDD FBVDDQ F16
N12 VDD FBVDDQ F17 1 1 1 1 1 1
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K N13 F19 C111 C108 C127 C109 C142 C118
VDD FBVDDQ
N14 VDD FBVDDQ F22
1 1 1 1 1 1 N15 H23 PM@ PM@ PM@ PM@ PM@ PM@
VDD FBVDDQ 2 2 2 2 2 2
N16 VDD FBVDDQ H26
C144 C153 C160 C166 C165 C186 N17 J15 4700P_0402_25V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z
PM@ PM@ PM@ PM@ PM@ PM@ VDD FBVDDQ +1.8VS
N19 VDD FBVDDQ J16
2 2 2 2 2 2 4700P_0402_25V7K 0.022U_0402_16V7K 1U_0603_10V4Z
P11 VDD FBVDDQ J18
0.47U_0402_6.3V6K P12 J19 1 1 1 1 1
VDD FBVDDQ C140 C139 C119 C106 C97
P13 VDD FBVDDQ L19
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K P14 L23
VDD FBVDDQ PM@ PM@ PM@ PM@ PM@
P15 VDD FBVDDQ L26
2 2 2 2 2
P16 VDD FBVDDQ M19
4700P_0402_25V7K 0.1U_0402_16V4Z

POWER
P17 VDD FBVDDQ N22
4.7U 6.3V K X5R 0603 R9 U22
VDD FBVDDQ
R11 VDD FBVDDQ Y22
1 1 R12 VDD
C169 C133 R13 AG6
PM@ PM@ NEAR BGA R14
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ AF6 0.1U_0402_16V4Z 0.47U_0402_6.3V6K
+1.1VS
R15 VDD PEX_IOVDDQ AE6 1 1 1 1
2 2
R16 AD6
R17
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ AC13 C212 C203 C202 C201 PEX_IOVDDQ=1.6A
4.7U 6.3V K X5R 0603 T9 AC7 PM@ PM@ PM@ PM@
C
T11
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ AB17
2 2 2 2 PEX_IOVDD=500mA C

T17 AB16 0.1U_0402_16V4Z 0.47U_0402_6.3V6K

U9
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ AB13 PEX_PLLVDD=100mA
U19 VDD PEX_IOVDDQ AB9
+3VS W9 AB8 1U_0402_6.3V4Z 10U_0805_10V4Z
VDD PEX_IOVDDQ
W10 AB7
NEAR BGA NEAR BALL W12
VDD
VDD
PEX_IOVDDQ
PEX_IOVDD AG7
1
NEAR BALL 1 1 1
0.1U_0402_16V4Z W13 AF7 C200 C262 C295 C270
VDD PEX_IOVDD PM@ PM@ PM@ PM@
W18 AE7
110mA 2 1 1
W19
VDD
VDD
PEX_IOVDD
PEX_IOVDD AD8
2 2 2 2
C93 C105 C120 AD7 4.7U 6.3V K X5R 0603 10U_0805_10V4Z
PM@ PM@ PM@ PEX_IOVDD
A12 VDD33 PEX_IOVDD AC9
1 2 2
B12 VDD33
1U_0603_10V4Z 0.1U_0402_16V4Z C12 VDD33 +PEX_PLLVDD MBK1608121YZF_0603 +1.1VS
D12 VDD33 PEX_PLLVDD AF9
E12 K6 0.1U_0402_16V4Z 1U_0402_6.3V6K 2 1
VDD33 VID_PLLVDD L10 PM@
F12 VDD33 SP_PLLVDD L6
K5
12~16mil 1 1 1 1 1
PLLVDD=65mA
+1.8VS NEAR BALL +IFPAB_IOVDD V3 IFPA_IOVDO
PLLVDD C132 C123 C138 C145 C122 NEAR BALL SP_PLLVDD=25mA
L32 V2 R19 +FB_PLLAVDD PM@ PM@ PM@ PM@ PM@
MBK1608121YZF_0603 4700P_0402_25V7K 470P_0402_50V8J +IFPC_IOVDD IFPB_IOVDD FB_PLLAVDD 2 2 2 2 2
J6
1 2 4700P_0402_25V7K 470P_0402_50V8J 10K_0402_5% R109 IFPC_IOVDD
FB_DLLAVDD T19 +FB_DLLAVDD 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K VID_PLLVDD=50mA
PM@ 1 PM@
NEAR BGA 1 1 1 1 1 12~16mil 2 H6 IFPE_IOVDD
AG2 +DACA_VDD
C634 C633 C776 C632 C777 +IFPAB_PLLVDD DACA_VDD +DACB_VDD
AD5 D7 1 PM@ 2
110mA 2
PM@
2
PM@
2
PM@
2
PM@
2
PM@ +IFPC_PLLVDD P6
IFPAB_PLLVDD
IFPC_PLLVDD
DACB_VDD
DACC_VDD W5 +DACC_VDD R1011 2 10K_0402_5%
2 1 PM@ N6 IFPE_PLLVDD
R130 PM@ 10K_0402_5%
4.7U 6.3V K X5R 0603 10K_0402_5% R181 PM@ +1.1VS
FB_CAL_PD_VDDQ B15 1 2 R93 +1.8VS
30_0402_1% L11
+FB_PLLAVDD 0.1U_0402_16V4Z 1 2
B NB9M-GS_BGA533 MBK1608121YZF_0603 B
L15 PM@ 1 1 1 PM@
+1.8VS MBK1608121YZF_0603 +1.1VS
470P_0402_50V8J C154 C172 C174
1 2 4700P_0402_25V7K +IFPAB_PLLVDD L38 PM@ PM@ PM@
+PEX_PLLVDD 0.1U_0402_16V4Z 10U_0603_6.3V6M 2 2 2
1 2
NEAR BGA 1 1 1
NEAR BALL 1 1 1 MBK1608121YZF_0603
C309 C302 C778 PM@ 0.01U_0402_16V7K 4.7U 6.3V K X5R 0603
260mA 2
PM@
2
PM@
2
PM@ C657 C660 C788 C671
PM@ PM@ PM@ PM@ PM@ L14
4.7U 6.3V K X5R 0603 2 2 2 +FB_DLLAVDD 0.1U_0402_16V4Z 1 2
0.01U_0402_16V7K 4.7U 6.3V K X5R 0603 MBK1608121YZF_0603
1 1 1 PM@

+1.8VS
NEAR BALL NEAR BGA C189 C190 C205
L13 PM@ PM@ PM@
MBK1608121YZF_0603 2 2 2
1 2 4700P_0402_25V7K 470P_0402_50V8J +IFPC_PLLVDD
PM@ 0.01U_0402_16V7K 4.7U 6.3V K X5R 0603
1 1 1
C231 C173
PM@ PM@ C779
PM@
2 2 2 L37
MBK1608121YZF_0603 +3VS
+1.1VS 4.7U 6.3V K X5R 0603 PM@
L9 +DACA_VDD 4700P_0402_25V7K 4.7U 6.3V K X5R 0603 2 1
MBK1608121YZF_0603
PM@
1 2 4700P_0402_25V7K +IFPC_IOVDD 150mA 1
C652
1
C651
1
C664
PM@ PM@ PM@
A 1 1 1 2 2 2
A
C115 C112 C117
NEAR BGA PM@ PM@ PM@
470P_0402_50V7K
2 2 2
NEAR BALL
4.7U 6.3V K X5R 0603 470P_0402_50V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB9M-GS Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom JIWA3/A4_LA4212P 1.0
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 18 of 53
gratuito - free of charge. 5 4 3 2 1
 5 4 3 2 1

A total of 8 signals are required for GB1 strapping this includes

2 reference signals
6 physical strapping pins
4 logical strapping bits
U27E A total of 24 logical strapping bits are available
B2 GND GND U2
B5 Part 5 of 5 U5
GND GND
B8 GND GND U11
B11 GND GND U12
B14 GND GND U13
B17 U14 +3VS
D GND GND D
B20 GND GND U15
B23 GND GND U16
B26 GND GND U17
E2 GND GND U23

1
E5 GND GND U26
E8 V9 R62 R60 R485 R61 R54 R53
GND GND

10K_0402_1%

10K_0402_5%

45.3K_0402_1%~D
E11 V19 X76@ @ PM@ @ @ PM@
GND GND

4.99K_0402_1%
E14 GND GND W11

10K_0402_5%

2K_0402_5%
E17 W14

2
GND GND
E20 GND GND W17
E23 Y2 STRAP2
GND GND <17> STRAP2
E26 Y5 STRAP1
GND GND <17> STRAP1
H2 Y23 STRAP0
GND GND <17> STRAP0
H5 Y26 ROM_SCLK
GND GND <17> ROM_SCLK
J11 AC2 ROM_SI
GND GND <17> ROM_SI
J14 AC5 ROM_SO
GND GND <17> ROM_SO
J17 GND GND AC6
K9 GND GND AC8

1
K19 GND GND AC11
L2 AC14 R59 R57 R481 R58 R51 R50
GND GND @ PM@ @ PM@ X76@ @
L5 GND GND AC17

10K_0402_5%

10K_0402_1%

10K_0402_5%

15K_0402_1%

20K_0402_1%

2K_0402_5%
GND
L11 GND GND AC20
L12 AC23

2
GND GND
L13 GND GND AC26
L14 GND GND AF2
L15 GND GND AF5
L16 GND GND AF8
L17 GND GND AF11
M12 GND GND AF14
M13 GND GND AF17
M14 GND GND AF20
M15 GND GND AF23
C C
M16 GND GND AF26
P2 T16
P5
GND
GND
GND
GND T15 GB1 Family GPU Strap Qptions
P9 GND GND T14
P19 GND
P23 GND GND_SENSE W16 1 R700 2 GPU FB Memory ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
P26 PM@ 0_0402_5%
GND R97 PM@ 2 30_0402_1%
T12 GND FB_CAL_PU_GND A15 1
T13 GND 32Mx16(5) PU 5K PD 15K PD 30K PU 10K PD 10K PU 45K
B16 R96 1 2 40.2_0402_1% Samsung
FB_CAL_TERM_GND @
64Mx16 PU 5K PD 15K PD 5K PU 10K PD 10K PU 45K
NB9M-GS_BGA533
PM@
NB9M-GS 32Mx16(7) PU 5K PD 15K PD 45K PU 10K PD 10K PU 45K
(0x06E9) Hynix
64Mx16 PU 5K PD 15K PD 10K PU 10K PD 10K PU 45K

32Mx16(6) PU 5K PD 15K PD 35K PU 10K PD 10K PU 45K

Qimonda

B B

Component Manufacturer Compal PN

Hynix SA00000FF30
DDR2 VRAM
(32M*16) Qimonda SA00000S820
Samsung SA00001VX10

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB9M-GE GND & STRAP
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008
1
Sheet 19 of 53
 5 4 3 2 1

U6 U28
FBA_BA0 L2 B9 FBAD7 FBA_BA0 L2 B9 FBAD25
FBA_BA1 BA0 DQ15 FBAD3 FBA_BA1 BA0 DQ15 FBAD29
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD4 D9 FBAD24
FBAA12 DQ13 FBAD0 FBAA12 DQ13 FBAD31
R2 A12 DQ12 D1 R2 A12 DQ12 D1
FBAA11 P7 D3 FBAD1 FBAA11 P7 D3 FBAD28
FBAA10 A11 DQ11 FBAD6 FBAA10 A11 DQ11 FBAD27
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBAA9 P3 C2 FBAD2 FBAA9 P3 C2 FBAD30
FBAA8 A9 DQ9 FBAD5 FBAA8 A9 DQ9 FBAD26
P8 A8 DQ8 C8 P8 A8 DQ8 C8
FBAA7 P2 F9 FBAD10 FBAA7 P2 F9 FBAD18
FBAA6 A7 DQ7 FBAD15 FBAA6 A7 DQ7 FBAD23
N7 A6 DQ6 F1 N7 A6 DQ6 F1
FBAA5 N3 H9 FBAD8 FBAA5 N3 H9 FBAD17
FBAA4 A5 DQ5 FBAD13 FBAA4 A5 DQ5 FBAD21
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBAA3 N2 H3 FBAD12 FBAA3 N2 H3 FBAD19
FBAA2 A3 DQ3 FBAD9 FBAA2 A3 DQ3 FBAD16
M7 A2 DQ2 H7 M7 A2 DQ2 H7
D FBAA1 M3 G2 FBAD14 FBAA1 M3 G2 FBAD22 FBBA[2..5] D
A1 DQ1 A1 DQ1 <17,21> FBBA[2..5]
FBAA0 M8 G8 FBAD11 FBAA0 M8 G8 FBAD20
A0 DQ0 A0 DQ0
FBAD[0..63]
<17,21> FBAD[0..63]
FBACLK0# K8 A9 FBACLK0# K8 A9
FBACLK0 CK VDDQ1 FBACLK0 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C3 C3 FBAA[0..12]
VDDQ3 VDDQ3 <17,21> FBAA[0..12]
FBA_CKE K2 C7 FBA_CKE K2 C7
CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9
E9 E9 FBADQS[0..7]
VDDQ6 +1.8VS VDDQ6 +1.8VS <17,21> FBADQS[0..7]
VDDQ7 G1 VDDQ7 G1
FBACS0# L8 G3 FBACS0# L8 G3
CS VDDQ8 CS VDDQ8 FBADQS#[0..7]
VDDQ9 G7 VDDQ9 G7 <17,21> FBADQS#[0..7]
FBAWE# K3 G9 1 FBAWE# K3 G9
WE VDDQ10 WE VDDQ10
FBARAS# K7 A1 C184 + PM@ FBARAS# K7 A1 FBADQM#[0..7]
RAS VDD1 RAS VDD1 <17,21> FBADQM#[0..7]
E1 220U_D2_4VM_R15 E1
FBACAS# VDD2 FBACAS# VDD2
L7 CAS VDD3 J9 L7 CAS VDD3 J9
2 FBA_BA0
VDD4 M9 VDD4 M9 <17,21> FBA_BA0
FBADQM#1 F3 R1 FBADQM#2 F3 R1
FBADQM#0 LDM VDD5 FBADQM#3 LDM VDD5 FBA_BA1
B3 UDM B3 UDM <17,21> FBA_BA1
VDDL J1 VDDL J1
J7 1 1 J7 1 1 FBAODT0
VSSDL VSSDL <17,21> FBAODT0
FBAODT0 K9 C630 C617 FBAODT0 K9 C92 C98
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBA_CKE
<17,21> FBA_CKE
PM@ PM@ PM@ PM@
+1.8VS FBADQS1 2 2 FBADQS2 2 2 FBARAS#
F7 LDQS F7 LDQS <17,21> FBARAS#
FBADQS#1 E8 A7 FBADQS#2 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBACAS#
VSSQ2 B2 VSSQ2 B2 <17,21> FBACAS#
VSSQ3 B8 VSSQ3 B8
1

D2 D2 FBAWE#
VSSQ4 VSSQ4 <17,21> FBAWE#
R480 FBADQS0 B7 D8 FBADQS3 B7 D8
C +VRAM_VREFA 1K_0402_1% FBADQS#0 UDQS VSSQ5 +VRAM_VREFA FBADQS#3 UDQS VSSQ5 FBACS0# C
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 <17,21> FBACS0#
PM@ F2 F2
VSSQ7 VSSQ7
F8 F8
2

VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
(SSTL-1.8) VREF = .5*VDDQ H8 (SSTL-1.8) VREF = .5*VDDQ H8
VSSQ10 VSSQ10
1

1 A2 NC#A2 1 A2 NC#A2
R479 C613 E2 A3 C91 E2 A3
1K_0402_1% 0.047U_0402_16V4Z NC#E2 VSS1 0.047U_0402_16V4Z NC#E2 VSS1
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
PM@ PM@ R3 J3 PM@ R3 J3
2 NC#R3 VSS3 2 NC#R3 VSS3
R7 N1 R7 N1 Close to U5
2

NC#R7 VSS4 NC#R7 VSS4 FBACLK0

Close to U6 R8 NC#R8 VSS5 P9 Close to U4 R8 NC#R8 VSS5 P9 <17> FBACLK0

X76@ HY5PS561621F-25 X76@ HY5PS561621F-25

1
FBABA2 FBABA2 R104
<17,21> FBABA2 <17,21> FBABA2
475_0402_1%

DDR2 BGA MEMORY DDR2 BGA MEMORY PM@

2
+1.8VS FBACLK0#
+1.8VS <17> FBACLK0#
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 C110 C113 C130 C137 C143 C103 C100 C158
C621 C622 C624 C626 C625 C619 C620 C615 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRA
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 20 of 53
 5 4 3 2 1

U29 U7
FBA_BA0 L2 B9 FBAD40 FBA_BA0 L2 B9 FBAD39
FBA_BA1 BA0 DQ15 FBAD45 FBA_BA1 BA0 DQ15 FBAD34
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD41 D9 FBAD38
FBAA12 DQ13 FBAD46 FBAA12 DQ13 FBAD35
R2 A12 DQ12 D1 R2 A12 DQ12 D1
FBAA11 P7 D3 FBAD47 FBAA11 P7 D3 FBAD32
FBAA10 A11 DQ11 FBAD43 FBAA10 A11 DQ11 FBAD36
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBAA9 P3 C2 FBAD44 FBAA9 P3 C2 FBAD33
FBAA8 A9 DQ9 FBAD42 FBAA8 A9 DQ9 FBAD37
P8 A8 DQ8 C8 P8 A8 DQ8 C8
FBAA7 P2 F9 FBAD61 FBAA7 P2 F9 FBAD55
FBAA6 A7 DQ7 FBAD62 FBAA6 A7 DQ7 FBAD51
N7 A6 DQ6 F1 N7 A6 DQ6 F1
FBBA5 N3 H9 FBAD58 FBBA5 N3 H9 FBAD52 FBAD[0..63]
A5 DQ5 A5 DQ5 <17,20> FBAD[0..63]
FBBA4 N8 H1 FBAD56 FBBA4 N8 H1 FBAD50
FBBA3 A4 DQ4 FBAD59 FBBA3 A4 DQ4 FBAD49
N2 A3 DQ3 H3 N2 A3 DQ3 H3
FBBA2 M7 H7 FBAD57 FBBA2 M7 H7 FBAD54 FBAA[0..12]
D A2 DQ2 A2 DQ2 <17,20> FBAA[0..12] D
FBAA1 M3 G2 FBAD63 FBAA1 M3 G2 FBAD48
FBAA0 A1 DQ1 FBAD60 FBAA0 A1 DQ1 FBAD53
M8 A0 DQ0 G8 M8 A0 DQ0 G8
FBBA[2..5]
<17> FBBA[2..5]
FBACLK1# K8 A9 FBACLK1# K8 A9
FBACLK1 CK VDDQ1 FBACLK1 CK VDDQ1 FBADQS[0..7]
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 <17,20> FBADQS[0..7]
VDDQ3 C3 VDDQ3 C3
FBA_CKE K2 C7 FBA_CKE K2 C7
CKE VDDQ4 CKE VDDQ4 FBADQS#[0..7]
VDDQ5 C9 VDDQ5 C9 <17,20> FBADQS#[0..7]
VDDQ6 E9 VDDQ6 E9
G1 +1.8VS G1 +1.8VS
FBACS0# VDDQ7 FBACS0# VDDQ7 FBADQM#[0..7]
L8 CS VDDQ8 G3 L8 CS VDDQ8 G3 <17,20> FBADQM#[0..7]
VDDQ9 G7 VDDQ9 G7
FBAWE# K3 G9 FBAWE# K3 G9
WE VDDQ10 WE VDDQ10 FBA_BA0
<17,20> FBA_BA0
FBARAS# K7 A1 FBARAS# K7 A1
RAS VDD1 RAS VDD1 FBA_BA1
VDD2 E1 VDD2 E1 <17,20> FBA_BA1
FBACAS# L7 J9 FBACAS# L7 J9
CAS VDD3 CAS VDD3 FBAODT0
VDD4 M9 VDD4 M9 <17,20> FBAODT0
FBADQM#7 F3 R1 FBADQM#6 F3 R1
FBADQM#5 LDM VDD5 FBADQM#4 LDM VDD5 FBA_CKE
B3 UDM B3 UDM <17,20> FBA_CKE
VDDL J1 VDDL J1
J7 1 1 J7 1 1 FBARAS#
VSSDL VSSDL <17,20> FBARAS#
FBAODT0 K9 C305 C224 FBAODT0 K9 C654 C655
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBACAS#
<17,20> FBACAS#
PM@ PM@ PM@ PM@
FBADQS7 2 2 FBADQS6 2 2 FBAWE#
F7 LDQS F7 LDQS <17,20> FBAWE#
+1.8VS FBADQS#7 E8 A7 FBADQS#6 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBACS0#
VSSQ2 B2 VSSQ2 B2 <17,20> FBACS0#
VSSQ3 B8 VSSQ3 B8
1

VSSQ4 D2 VSSQ4 D2
R184 FBADQS5 B7 D8 FBADQS4 B7 D8
C +VRAM_VREFB 1K_0402_1% FBADQS#5 UDQS VSSQ5 +VRAM_VREFB FBADQS#4 UDQS VSSQ5 C
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
PM@ F2 F2
VSSQ7 VSSQ7
F8 F8
2

VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
(SSTL-1.8) VREF = .5*VDDQ H8 H8
VSSQ10 VSSQ10
1

1 A2 1 (SSTL-1.8) VREF = .5*VDDQ A2

R190 C319 NC#A2 C672 NC#A2
E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3
1K_0402_1% 0.047U_0402_16V4Z L1 E3 0.047U_0402_16V4Z L1 E3
PM@ PM@ NC#L1 VSS2 PM@ NC#L1 VSS2
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
2 2
R7 N1 R7 N1
2

NC#R7 VSS4 NC#R7 VSS4

Close to U3 R8 NC#R8 VSS5 P9 Close to U7 R8 NC#R8 VSS5 P9

X76@ HY5PS561621F-25 X76@ HY5PS561621F-25

FBABA2 FBABA2
<17,20> FBABA2 <17,20> FBABA2

DDR2 BGA MEMORY

DDR2 BGA MEMORY

+1.8VS FBACLK1
+1.8VS <17> FBACLK1
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 C668 C666 C665 C659 C656 C647 C642 C667

1
C272 C234 C225 C304 C269 C263 C239 C233 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ R154
2 2 2 2 2 2 2 2 475_0402_1%
2 2 2 2 2 2 2 2 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K PM@
B 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K B

2
FBACLK1#
<17> FBACLK1#
Close to U7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRB
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 21 of 53
 5 4 3 2 1

+3VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB +3VS

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1
R364
2
0_0805_5% 1 1 1 1 1 1 1
C419 C422 C420 C438 C457 C474 C473 R278 R263
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 2 2 2 2N7002DW-T/R7_SOT363-6
0 0 1 133 100 33.3 14.318 96.0 48.0 @ Q27A
+1.5VS 1 2 +1.5VM_CK505
R306 0_0805_5% <28,32,40> ICH_SMBDATA 6 1 CLK_SMBDATA
0 1 0 200 100 33.3 14.318 96.0 48.0
+VCCP 1 2
R389 0_0805_5% 1 1 1 1 1 1 1

2
0 1 1 166 100 33.3 14.318 96.0 48.0 C421 C423 C472 C425 C463 C471 C444 +3VS
D D

5
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
1 0 0 333 100 33.3 14.318 96.0 48.0
<28,32,40> ICH_SMBCLK 3 4 CLK_SMBCLK

1 0 1 100 100 33.3 14.318 96.0 48.0 Q27B

2N7002DW-T/R7_SOT363-6
1 1 0 400 100 33.3 14.318 96.0 48.0

1 1 1 Reserved SA000020K00 (Silego : SLG8SP556VTR )

SA000020H00 (ICS : ICS9LPRS387AKLFT)

+3VM_CK505 U14
9 CLK_SMBDATA
SDA CLK_SMBDATA <14,15>
55 VDD_SRC
SCL 10 CLK_SMBCLK
CLK_SMBCLK <14,15>
SRC PORT LIST
6 VDD_REF
12 71 CLK_CPU_BCLK
VDD_PCI CPU_0 CLK_CPU_BCLK <5>
72 70 CLK_CPU_BCLK#
PORT DEVICE
VDD_CPU CPU_0# CLK_CPU_BCLK# <5>
19 VDD_48 CPU_1 68 CLK_MCH_BCLK
CLK_MCH_BCLK <8> SRC0 MCH_DREFCLK
CLK_MCH_BCLK#
27 VDD_PLL3 CPU_1# 67 CLK_MCH_BCLK# <8> SRC2 MCH_3GPLL
+VCCP
+1.5VM_CK505 66 24 R_CLK_DOT R251
1 2 GM@ 0_0402_5%
CLK_MCH_DREFCLK <8>
SRC3 PCIE_EXP#
C VDD_CPU_IO SRC_0/DOT_96 R255 PM@ 0_0402_5% C
1 2 CLK_PCIE_VGA <16> SRC4
2

31 25 R_CLK_DOT# R250
1 2 GM@ 0_0402_5%
VDD_PLL3_IO SRC_0#/DOT_96# CLK_MCH_DREFCLK# <8>
R261 R254 PM@ 0_0402_5%
62
1 2 CLK_PCIE_VGA# <16> SRC6 PCIE_WLAN
R267 56_0402_5% VDD_SRC_IO
2.2K_0402_5% @ 52
LCDCLK/27M 28 MCH_SSCDREFCLK <8> SRC7 PCIE_WLAN1
1

FSA 2 VDD_SRC_IO
1 1 2 MCH_CLKSEL0 <8>
23
LCDCLK#/27M_SS 29 MCH_SSCDREFCLK# <8> SRC8
R262 VDD_IO
<6> CPU_BSEL0 1
R257
2
1K_0402_5% 38 32 CLK_MCH_3GPLL
CLK_MCH_3GPLL <8>
SRC9 PCIE_LAN
0_0402_5% VDD_SRC_IO SRC_2
SRC10 PCIE_ICH
1

33 CLK_MCH_3GPLL#
SRC_2# CLK_MCH_3GPLL# <8>
R268
33_0402_5% 1 2 R270 FSA 20
SRC11 PCIE_SATA
1K_0402_5% <28> CLK_48M_ICH USB_0/FS_A CLK_PCIE_EXP
SRC_3 35 CLK_PCIE_EXP <40>
@ FSB 2
2

FS_B/TEST_MODE CLK_PCIE_EXP#
SRC_3# 36 CLK_PCIE_EXP# <40>
33_0402_5% 1 2 R316 FSC 7
<28> CLK_14M_ICH <BOM Structure> REF_0/FS_C/TEST_
+VCCP 33_0402_5% 1 2 R310 8 39 CLK_PCIE_CARD
<37> CLK_14M_SIO REF_1 SRC_4 CLK_PCIE_CARD <36>
@
40 CLK_PCIE_CARD#
SRC_4# CLK_PCIE_CARD# <36>
2

CK_PWRGD 1
R376 <28> CK_PWRGD CKPWRGD/PD#
11 57 CLK_PCIE_WLAN
NC SRC_6 CLK_PCIE_WLAN <32>
1K_0402_5%
@ 56 CLK_PCIE_WLAN#
CLK_PCIE_WLAN# <32>
1

FSB SRC_6#
1 2 MCH_CLKSEL1 <8>
PM_STP_CPU# 53
R366 <28> H_STP_CPU# CPU_STOP#
<6> CPU_BSEL1 1 2 SRC_7 61
R367 1K_0402_5% PM_STP_PCI# 54
0_0402_5% <28> H_STP_PCI# PCI_STOP#
SRC_7# 60
1

R375 CLK_XTAL_IN 5 XTAL_IN +3VS

B
SRC_8/CPU_ITP 64 B
0_0402_5% CLK_XTAL_OUT 4
@ XTAL_OUT
63
2

SRC_8#/CPU_ITP#

13 44 CLK_PCIE_LAN SATA_CLKREQ#_R R315 2 1 10K_0402_5%

PCI_1 SRC_9 CLK_PCIE_LAN <33>
EXP_CLKREQ# R295 2 1 10K_0402_5%
+VCCP 33_0402_5% 1 @ 2 R290 PCI2_TME 14 45 CLK_PCIE_LAN# MCH_CLKREQ#_R R256 2 1 10K_0402_5%
<37> CLK_PCI_DB PCI_2 SRC_9# CLK_PCIE_LAN# <33>
CLKREQ_LAN# R304 2 1 10K_0402_5%
15 WLAN_CLKREQ# R372 2 1 10K_0402_5%
PCI_3
2

50 CLK_PCIE_ICH
SRC_10 CLK_PCIE_ICH <28>
R312 33_0402_5% 1 2 R289 PCI4_SEL 16
<35> CLK_PCI_LPC PCI_4/SEL_LCDCL
51 CLK_PCIE_ICH#
SRC_10# CLK_PCIE_ICH# <28>
R311 1K_0402_5% 33_0402_5% 1 2 R288 ITP_EN 17
<26> CLK_PCI_ICH PCIF_5/ITP_EN
10K_0402_5% @
1

FSC CLK_PCIE_SATA
2 1 1 2 MCH_CLKSEL2 <8> SRC_11 48 CLK_PCIE_SATA <27>
REQ PORT LIST
1 2 R303 18 47 CLK_PCIE_SATA#
<6> CPU_BSEL2 VSS_PCI SRC_11# CLK_PCIE_SATA# <27>
R296 1K_0402_5% For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
0_0402_5% 3 VSS_REF PORT DEVICE
1

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

R302 22 37 EXP_CLKREQ#
Pin28/29 : LCDCLK / LCDCLK# VSS_48 CLKREQ_3# EXP_CLKREQ# <40>
0_0402_5% 1 = Pin24/25 : SRC_0 / SRC_0# 26 41
REQ_3# PCIE_EXP#
@ VSS_IO CLKREQ_4#
REQ_4#
2

Pin28/29 : 27M/27M_SS 69 58 WLAN_CLKREQ#

VSS_CPU CLKREQ_6# WLAN_CLKREQ# <32>
30 65
REQ_6# PCIE_WLAN
VSS_PLL3 CLKREQ_7#
+3VS +3VS +3VS 34 43 CLKREQ_LAN#
CLKREQ_LAN# <33>
REQ_7# PCIE_WLAN1
VSS_SRC CLKREQ_9#
59 49
REQ_9# PCIE_LAN
VSS_SRC SLKREQ_10#
2

R285 R287 R286 42 46 SATA_CLKREQ#_R R307 1 2 0_0402_5% SATA_CLKREQ# <28>

REQ_10#
VSS_SRC CLKREQ_11#
A
10K_0402_5% 10K_0402_5% 10K_0402_5% 73 21 MCH_CLKREQ#_R R260 1 2 0_0402_5% MCH_CLKREQ# <8>
REQ_11# PCIE_SATA A
CLK_XTAL_IN @ PM@ VSS USB_1/CLKREQ_A#
REQ_A# MCH_3GPLL
1

C464 22P_0402_50V8J
1

ITP_EN PCI4_SEL PCI2_TME SLG8SP556VTR_QFN72_10X10

Y2
14.31818MHZ_16PF_DSX840GA
2

2
2

CLK_XTAL_OUT R275 R277 R276

C476 22P_0402_50V8J
10K_0402_5% 10K_0402_5%
GM@
10K_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
1

hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
JIWA3/A4_LA4212P 1.0
gratuito - free of charge. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 22 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS
09/13 change pull low enable

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
4.7K_0402_5%1 2 R212 C357 C318 C374 C335

0_0402_5% 1 2 R211 U8 HDMI_GM@HDMI_GM@HDMI_GM@ HDMI_GM@

@ 2 2 2 2

25 OE#
09/13 change pull high enable VCC 2
HDMICLK 28 11
+3VS +3VS SCL_SINK VCC
D VCC 15 D
HDMIDAT 29 21 +3VS +3VS
SDA_SINK VCC
VCC 26
HDMI_GM@ 33
4.7K_0402_5%1 R209 HDMI_DETECT VCC
2 30 HPD_SINK VCC 40

2
VCC 46
0_0402_5% 1 2 R210 32 R187 R188
@ DDC_EN
2.2K_0402_5% 2.2K_0402_5%
default : pull low
@ 4.7K_0402_5% 2 1 R697 34 4 HDMI_GM@
4.7K_0402_5% 2 1 R695 HDMI_GM@ HDMI_GM@ 9/13 Add inverting lavel shift

1
@ 4.7K_0402_5% 2 CFG0 PC1
1 R696 35 CFG1 PC0 3 @ 4.7K_0402_5% 2 1 R664 circuit base on Design Guide P.277
9/14 Change from 4.7K to 2.2K
default : pull low
6 R189 1 HDMI_GM@
2 499_0402_1%
base on Design Guide P.274
REXT
7 HDP 1 HDMI_GM@
2 TMDS_B_HPD# <10>
HPD# R665 0_0402_5%
SDA 8 HDMIDAT_NB <8>

SCL 9 HDMICLK_NB <8>

RT_EN# 10

<10> TMDS_B_DATA2 48 13 HDMI_TX2+

IN_D4+ OUT_D4+ HDMI_TX2-
<10> TMDS_B_DATA2# 47 IN_D4- OUT_D4- 14

45 16 HDMI_TX1+
<10> TMDS_B_DATA1 IN_D3+ OUT_D3+
44 17 HDMI_TX1-
<10> TMDS_B_DATA1# IN_D3- OUT_D3-
42 19 HDMI_TX0+
<10> TMDS_B_DATA0 IN_D2+ OUT_D2+
41 20 HDMI_TX0-
<10> TMDS_B_DATA0# IN_D2- OUT_D2-
39 22 HDMI_CLK+
<10> TMDS_B_CLK IN_D1+ OUT_D1+
38 23 HDMI_CLK-
<10> TMDS_B_CLK# IN_D1- OUT_D1-

C C

GND 1
TMDS pull down (500ohm) resistors G9x only GND 5
12
GND
GND 18
HDMI_CLK+_CONN R155 1 HDMI_PM@
2 499_0402_1% 24 C369 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_CLK-
GND <17> VGA_HDMI_CLK-
27 C362 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_CLK+
GND <17> VGA_HDMI_CLK+
HDMI_CLK-_CONN R156 1 HDMI_PM@
2 499_0402_1% 31 C350 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX0-
GND <17> VGA_HDMI_TX0-
36 C341 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX0+
GND <17> VGA_HDMI_TX0+
HDMI_TX0+_CONN R150 1 HDMI_PM@
2 499_0402_1% 37 C324 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX1-
GND <17> VGA_HDMI_TX1-
43 C321 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX1+
GND <17> VGA_HDMI_TX1+
HDMI_TX0-_CONN R153 1 HDMI_PM@
2 499_0402_1% 49 C313 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX2-
PAD <17> VGA_HDMI_TX2-
C308 1 2 HDMI_PM@
0.1U_0402_10V7K HDMI_TX2+
<17> VGA_HDMI_TX2+
HDMI_TX1+_CONN R145 1 HDMI_PM@
2 499_0402_1% PS8101TQFN48G_QFN48_7X7
HDMI_GM@
HDMI_TX1-_CONN R149 1 HDMI_PM@
2 499_0402_1%

HDMI_TX2+_CONN R141 1 HDMI_PM@

2 499_0402_1%
<16> VGA_HDMI_SDA R228 2 1 HDMI_PM@ 0_0402_5% HDMIDAT
HDMI_TX2-_CONN R144 1 HDMI_PM@
2 499_0402_1% <16> VGA_HDMI_SCL R227 2 1 HDMI_PM@ 0_0402_5% HDMICLK

NEAR CONNECT
1

+3VS 2 Q4
G 2N7002_SOT23
S
3

HDMI_PM@

+5VS

1800P_0402_50V7K
B B
HDMI_DETECT 1 R216 2 HDMI_GM@ +5VS

1
0_0402_5%

C792
R725 HDMI@
9/14 Reserve for VGA 0_0805_5%

2
3

2
0_0402_5% 1 @ 2 R687
L36 used;check pin name @

2
HDMI_CLK+ 1 1 2 HDMI_CLK+_CONN D4 HDMI_GM@
2

2
R200 L16 HDMI_PM@
HDMI@ <16> HDMI_DETECT_VGA HDMI_DETECT_VGA 1 2 1 2 1 R215 2 HDMI_PM@ BAT54S-7-F_SOT23-3 D2 HDMI@
HDMI_CLK- 4 4 3 HDMI_CLK-_CONN 1K_0402_1% FBML10160808121LMT_0603 RB411DT146_SOT23-3

1
3 0_0402_5%
1
WCM-2012-900T_4P HDMI_PM@

1
0_0402_5% 1 @ 2 R688 C338 +5VS_HDMI
1

D3 330P_0402_50V7K 2
1 1
RB751V_SOD323 R199
0_0402_5% 1 @ 2 R689 @ 10K_0402_1% C806 C276HDMI@

2
L35 HDMI_PM@ HDMI@ HDMI@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2

HDMI_TX0+ HDMI_TX0+_CONN R198 R194 2 2

1 1 2 2
2.2K_0402_5% 2.2K_0402_5%
HDMI@ HDMI_PM@ @
HDMI_TX0- 4 4 3 HDMI_TX0-_CONN JHDMI1

1
3
19 HP_DET
WCM-2012-900T_4P 18
0_0402_5% 1 @ +5V
2 R690 L43 HDMI_PM@ MBK1608121YZF_0603 17 DDC/CEC_GND
HDMIDAT 1 2 16
HDMICLK SDA
1 2 15 SCL
0_0402_5% 1 @ 2 R691 L44 HDMI_PM@ MBK1608121YZF_0603 14
L34 +5VS +5VS Reserved
1 1 13 CEC
HDMI_TX1+ 1 1 2 HDMI_TX1+_CONN C774 C775 HDMI_CLK-_CONN 12 20
2 CK- GND
11 CK_shield GND 21
HDMI@ HDMI_PM@ HDMI_PM@ HDMI_CLK+_CONN 10 22
D25 D26 CK+ GND
HDMI_TX1- 4 4 3 HDMI_TX1-_CONN L43 L44 12P_0402_50V8J 2 2
12P_0402_50V8J HDMI_TX0-_CONN 9 23
3 D0- GND
3 3 8 D0_shield
WCM-2012-900T_4P HDMI_TX0+_CONN 7
0_0402_5% 1 @ HDMIDAT HDMICLK HDMI_TX1-_CONN D0+
2 R692 1 1 6 D1-
A 5 D1_shield
A
2 2 HDMI_TX1+_CONN 4
HDMI_TX2-_CONN D1+
0_0603_5% 0_0603_5% 3 D2-
HDMI_GM@ HDMI_GM@ 2
0_0402_5% BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 HDMI_TX2+_CONN D2_shield
1 @ 2 R693 1 D2+
L33 @ @
HDMI_TX2+ 1 1 2 HDMI_TX2+_CONN TYCO_16-004-6131
2
HDMI@ ME@
HDMI_TX2- 4 4 3 HDMI_TX2-_CONN
3
WCM-2012-900T_4P
0_0402_5% 1 @
Security Classification Compal Secret Data Compal Electronics, Inc.
2 R694 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
Level shiftter-CH7318
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
JIWA3/A4_LA-4212P
Rev
1.0

gratuito - free of charge. 5 4 3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
Date: Thursday, May 22, 2008
1
Sheet 23 of 53
 5 4 3 2 1

INVERTER Conn.
INVT_PWM

LCD POWER CIRCUIT DAC_BRIG

JP2 DISPOFF#
1 1
2 2
+LCDVDD +5VALW
<35> INVT_PWM 3 3 1 1 1
B+ DISPOFF# 4 C21 C23 C22
D +3VS 4 D
<35> DAC_BRIG 5 5
W=60mils L2 2 1 +INVPWR_B+ 6 470P_0402_50V7K
6 G8 8

1
FBMA-L11-201209-221LMA30T_0805 2 2 2
7 7 G9 9

1
R4 R5 470P_0402_50V7K 470P_0402_50V7K
150_0603_1% 100K_0402_5% 1 1 1 ACES_87213-0700G
C4 C18 ME@
C789

1 2
4.7U_0805_10V4Z 0.1U_0603_25V7K 470P_0603_50V8J

3
D R6 220K_0402_5%
S
2 2 2
G For EMI
2 1 2 2
Q2 G
2N7002_SOT23 S SI2301BDS-T1-E3_SOT23-3

C2
DTC124EK 1
Q3 D

OUT

1
0.47U_0402_6.3V6K
GM@
R2 2 +LCDVDD
<10> GM_ENVDD 1 2 0_0402_5% 2 IN Q1 W=60mils

GND
DTC124EKAT146_SC59-3 +3VS

1
R3 1 2 0_0402_5% 1 1
<16> VGA_ENVDD

1
R1 C1 C3
PM@ 10K_0402_5% R377
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2

2 2 4.7K_0402_5%
D13

2
BKOFF# 1 2 DISPOFF#
<35> BKOFF#
CH751H-40PT_SOD323-2
<10> GMCH_ENBKL 2 1 ENBKL
ENBKL <35>
R358 GM@ 0_0402_5%

2
<16> VGA_ENBKL 2 1
C R351 PM@ 0_0402_5% R368 C

10K_0402_5%

1
LCD/PANEL BD. Conn. LCD/PANEL BD. Conn.
+3VS
+3VS
JLVDS2 JLVDS1
R18 R17
GND 22 +LCDVDD_CONN L1 2.2K_0402_5% 2.2K_0402_5% GND 22
+LCDVDD_CONN R22 R21
GND 21 GND 21
20 20 2 1 +LCDVDD GM@ GM@
20 20 2.2K_0402_5% 2.2K_0402_5%
PM@ PM@
19 19 FBMA-L11-201209-221LMA30T_0805 19 19
18 18 (60 MIL) 18 18 (60 MIL)
17 17 +3VS 17 17 +3VS
16 16 16 16
VGA_LVDS_SDA
15 15 LVDS_SDA <10> 15 15
VGA_LVDS_SCL
VGA_LVDS_SDA <16>
14 14 LVDS_ACLK
LVDS_SCL <10> 14 14
VGA_LVDS_ACLK
VGA_LVDS_SCL <16>
13 13 LVDS_ACLK#
LVDS_ACLK <10> 13 13
VGA_LVDS_ACLK#
VGA_LVDS_ACLK <17>
12 12 LVDS_ACLK# <10> 12 12 VGA_LVDS_ACLK# <17>
11 11 LVDS_A1 11 11
VGA_LVDS_A1
B 10 10 LVDS_A1#
LVDS_A1 <10> 10 10
VGA_LVDS_A1#
VGA_LVDS_A1 <17> B
9 9 LVDS_A1# <10> 9 9 VGA_LVDS_A1# <17>
8 8 LVDS_A0 8 8
VGA_LVDS_A0
7 7 LVDS_A0#
LVDS_A0 <10> 7 7
VGA_LVDS_A0#
VGA_LVDS_A0 <17>
6 6 LVDS_A0# <10> 6 6 VGA_LVDS_A0# <17>
5 5 LVDS_A2 5 5
VGA_LVDS_A2
4 4 LVDS_A2#
LVDS_A2 <10> 4 4
VGA_LVDS_A2#
VGA_LVDS_A2 <17>
3 3 LVDS_A2# <10> 3 3 VGA_LVDS_A2# <17>
2 2 2 2
1 1 1 1

ME@ ME@
ACES_87212-2000L ACES_87212-2000L

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008
1
Sheet 24 of 53
 A B C D E

CRT Connector
Place closed to chipset +CRT_VCC
+5VS 0.1U_0402_16V4Z
C679
1 2 CRT_R_1 1 2 RED D18 W=40mils
<16> VGA_CRT_R
R229 1 2 PM@ 0_0402_5% L20 FCM1608C-121T_0603 2 1 1 2
<10> GMCH_CRT_R
1 R231 GM@ 0_0402_5% <BOM Structure> 1
1 2 CRT_G_1 1 2 GREEN RB491D_SC59-3 JCRT1
<16> VGA_CRT_G
R221 1 2 PM@ 0_0402_5% L19 FCM1608C-121T_0603 6
<10> GMCH_CRT_G
R224 GM@ 0_0402_5% 11
1 2 CRT_B_1 1 2 BLUE RED 1
<16> VGA_CRT_B
R214 1 2 PM@ 0_0402_5% L18 FCM1608C-121T_0603 7
<10> GMCH_CRT_B

1
R218 GM@ 0_0402_5% CRT_DDC_DAT 12

1
R230 R223 1 1 1 GREEN 2
R219 C406 C391 C385 1 1 1 8
JVGA_HS 13
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J C405 C390 C384 BLUE 3

2
2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 9

2
150_0402_1% 2 2 2 JVGA_VS 14 16
150_0402_1% 4 17
10
CRT_DDC_CLK 15
+CRT_VCC JVGA_HS
1 2 5
L22 FCM1608C-121T_0603
1 2 2 1 <BOM Structure> ALLTO_C10534-91507
C413 0.1U_0402_16V4Z R239 1K_0402_5% 1 2 JVGA_VS
<BOM Structure> L21 FCM1608C-121T_0603 ME@

1
U11
1 1

OE#
1 2 2 4 CRT_HSYNC_1
<16> VGA_HSYNC A Y
R241 PM@ 0_0402_5% @ C412 @ C408

G
1 2 10P_0402_50V8J 10P_0402_50V8J
<10> GMCH_CRT_HSYNC 2 2
R240 GM@ 0_0402_5% SN74AHCT1G125DCKR_SC70-5

3
2 2
+CRT_VCC
Place closed to chipset
1 2
C410 0.1U_0402_16V4Z

1
U10
PIN ASSIGMENT

OE#
1 2 2 4 CRT_VSYNC_1
<16> VGA_VSYNC A Y
R233 PM@ 0_0402_5%

G
1 2
<10> GMCH_CRT_VSYNC
R235 GM@ 0_0402_5% SN74AHCT1G125DCKR_SC70-5 D-SUB FUNCTION

3
9 +CRT_VCC
+5VS +5VS +5VS 1 RED
+3VS 6 GND
D27 D28 D29

2.2K
+CRT_VCC
2.2K
3 3 3 2 GREEN
1

1 BLUE 1 GREEN 1 RED

R247 2.2K_0402_5%
2 2 2
7, 5 GND
2.2K_0402_5% R269 +3VS
3
3 BLUE 3
1

1
2

R266 R253 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

@ @ @
<16> VGA_DDCDATA
0_0402_5%
2
PM@
1
R252
2.2K_0402_5% 2.2K_0402_5% 8 GND
2

2
5

2 1 4 3 CRT_DDC_DAT
14 VSYNC
<10> GMCH_CRT_DATA 0_0402_5% GM@ R643
Q23B 10 GND
2

2N7002DW-T/R7_SOT363-6

<10> GMCH_CRT_CLK 0_0402_5%

2
GM@
1
R644
1 6 CRT_DDC_CLK 13 HSYNC
<16> VGA_DDCCLK 2 1
Q23A
2N7002DW-T/R7_SOT363-6
11 SENSE
0_0402_5% PM@ R264 1 1
C414
@
C417
@
12 SM_DAT
100P_0402_50V8J
2 2
68P_0402_50V8K
15 SM_CLK
4 PIN4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JIWA3/A4_LA4212P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 25 of 53
A B C D E

hexainf@hotmail.com
gratuito - free of charge.
 5 4 3 2 1

+3VS

D D

1 2 PCI_DEVSEL#
R425 8.2K_0402_5%
1 2 PCI_STOP#
R420 8.2K_0402_5%
1 2 PCI_TRDY# PCI_AD[0..31] U34B
R430 8.2K_0402_5% PCI_AD0 D11 F1 PCI_REQ0#
AD0 REQ0# PCI_REQ0#
1 2 PCI_FRAME# PCI_AD1 C8 G4 PCI_GNT0#
AD1 GNT0# PCI_GNT0#
R415 8.2K_0402_5% PCI_AD2 PCI_REQ1#
1 2 PCI_PLOCK# PCI_AD3
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT1#
R464 8.2K_0402_5% PCI_AD4 AD3 GNT1#/GPIO51 PCI_REQ2#
E9 AD4 REQ2#/GPIO52 F13
1 2 PCI_IRDY# PCI_AD5 C9 F12 PCI_GNT2#
R453 8.2K_0402_5% PCI_AD6 AD5 GNT2#/GPIO53 PCI_REQ3#
E10 AD6 REQ3#/GPIO54 E6
1 2 PCI_SERR# PCI_AD7 B7 F6 PCI_GNT3#
R449 8.2K_0402_5% PCI_AD8 AD7 GNT3#/GPIO55
C7 AD8
1 2 PCI_PERR# PCI_AD9 C5 D8 PCI_CBE#0
AD9 C/BE0# PCI_CBE#0
R438 8.2K_0402_5% PCI_AD10 G11 B4 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1
PCI_AD11 F8 D6 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2
PCI_AD12 F11 A5 PCI_CBE#3
+3VS AD12 C/BE3# PCI_CBE#3 <33>
PCI_AD13 E7
PCI_AD14 AD13 PCI_IRDY#
A3 AD14 IRDY# D3 PCI_IRDY#
PCI_AD15 D2 E3 PCI_PAR
AD15 PAR PCI_PAR
1 2 PCI_PIRQA# PCI_AD16 F10 R1 PCI_RST#
R428 8.2K_0402_5% PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6 PCI_DEVSEL#
1 2 PCI_PIRQB# PCI_AD18 D10 E4 PCI_PERR# Place closely pin D4
R580 8.2K_0402_5% PCI_AD19 AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
1 2 PCI_PIRQC# PCI_AD20 F7 J4 PCI_SERR#
R402 8.2K_0402_5% PCI_AD21 AD20 SERR# PCI_STOP# CLK_PCI_ICH
C3 AD21 STOP# A4 PCI_STOP#
1 2 PCI_PIRQD# PCI_AD22 F3 F5 PCI_TRDY#
AD22 TRDY# PCI_TRDY#

2
R563 8.2K_0402_5% PCI_AD23 F4 D7 PCI_FRAME#
AD23 FRAME# PCI_FRAME#
1 2 PCI_PIRQE# PCI_AD24 C1 R444
C R448 8.2K_0402_5% PCI_AD25 AD24 PLT_RST# C
G7 AD25 PLTRST# C14
1 2 PCI_PIRQF# PCI_AD26 H7 D4 CLK_PCI_ICH @ 10_0402_5%
AD26 PCICLK CLK_PCI_ICH <22>
R427 8.2K_0402_5% PCI_AD27 D1 R2 PCI_PME#
PCI_PME# <35>

1
PCI_PIRQG# PCI_AD28 AD27 PME#
1 2 G5 AD28
R457 8.2K_0402_5% PCI_AD29 H6 1
PCI_PIRQH# PCI_AD30 AD29 C567
1 2 G1 AD30 1 2 +3VALW
R456 8.2K_0402_5% PCI_AD31 H3
PCI_REQ0# AD31 R575 @ 10K_0402_5% @ 8.2P_0402_50V
1 2
R463 8.2K_0402_5% 2
PCI_REQ1#
1
R419
2
8.2K_0402_5% PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_REQ2# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
1 2 E1 PIRQB# PIRQF#/GPIO3 K6
R396 8.2K_0402_5% PCI_PIRQC# J6 F2 PCI_PIRQG#
PIRQC# PIRQG#/GPIO4 PCI_PIRQG#
1 2 PCI_REQ3# PCI_PIRQD# C4 G2 PCI_PIRQH#
R426 8.2K_0402_5% PIRQD# PIRQH#/GPIO5
ICH9-M ES_FCBGA676

PCI_GNT0# SB_SPI_CS#1
<28> SB_SPI_CS#1
Pull high?
1

1
R326
R433 R434 @ 1K_0402_5%
1 2 PCI_GNT3# @ 1K_0402_5%
2

2
@ 1K_0402_5%

B B

Boot BIOS Strap PCI_RST#

PCI_RST# <35,37>

1
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction R576
A16 Swap Override Strap 100K_0402_5%
Low= A16 swap override Enable 0 1 SPI
PCI_GNT#3

2
High= Default*
1 0 PCI
PLT_RST#
1 1 LPC* PLT_RST# <8,16,32,33,36,40>

1
R390
100K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

5 4 3 2
Date: Wednesday, May 14, 2008
1
Sheet 26 of 53
 5 4 3 2 1

+3VS

R407
GATEA20 2 1
+RTCVCC 10K_0402_5%

R520 330K_0402_1% 1 2 C707 ICH_RTCX1 R462

1 2 LAN100_SLP 12P_0402_50V8J KB_RST# 2 1

1
R513 1M_0402_5% Y4 10K_0402_5%
1 2 SM_INTRUDER# 2 NC IN 1 R515
32.768KHZ_12.5P_1TJS125BJ2A251 10M_0402_5% +VCCP
R517 330K_0402_1% 3 4
D NC OUT D
1 2 ICH_INTVRMEN LPC_AD[0..3] <35,37>
R510 @

2
U34A H_DPRSTP# 2 1
C23 K5 LPC_AD0
RTCX1 FWH0/LAD0
1 2 C706 ICH_RTCX2 C24 RTCX2 FWH1/LAD1 K4 LPC_AD1 56_0402_5%
12P_0402_50V8J L6 LPC_AD2 R514 @
ICH_RTCRST# FWH2/LAD2 LPC_AD3 H_DPSLP#
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2 2 1
+RTCVCC R324 20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME# 56_0402_5%
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <35,37>

RTC

LPC
CLRP1
ICH_INTVRMEN B22 J3 LPC_DRQ0#
+RTCBATT INTVRMEN LDRQ0# LPC_DRQ0# <37>
R322 2 1 LAN100_SLP A22 J1
LAN100_SLP LDRQ1#/GPIO23
1 2
E25 N7 GATEA20
2MM GLAN_CLK A20GATE GATEA20 <35>
2 100_0402_1% AJ27 H_A20M# R509 +VCCP
A20M# H_A20M# <5>
C451 C13 2 1
C470 LAN_RSTSYNC
DPRSTP# AJ25 H_DPRSTP_R# R511 2 1 0_0402_5% H_DPRSTP#
H_DPRSTP# <6,8,51>
0.1U_0402_16V4Z 1 2 F14 AE23 H_DPSLP# H_DPSLP# 56_0402_5%
1 LAN_RXD0 DPSLP# H_DPSLP# <6>
G13 LAN_RXD1
D14 AJ26 H_FERR#_S 56_0402_5% 2 1 R20
1U_0603_10V4Z LAN_RXD2 FERR# H_FERR# <5>

LAN / GLAN
close to RAM door D13 AD22 H_PWRGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD <6>
D12 LAN_TXD_1
E13 AF25 H_IGNNE#
+1.5VS LAN_TXD_2 IGNNE# H_IGNNE# <5>
B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# <5>
24.9_0402_1% AG25 H_INTR

CPU
INTR H_INTR <5>
R305 1 2 GLAN_COMP B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# <35>
B27 GLAN_COMPO
<8,16,30> HDA_BITCLK_CODEC 1 R554 2 HDA_BITCLK_R
NMI AF23 H_NMI
H_NMI <5>
33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# <5>
1 R559 2 HDA_SYNC_R AH4
<8,16,30> HDA_SYNC_CODEC HDA_SYNC
0_0402_5% AH27 H_STPCLK#
C STPCLK# H_STPCLK# <5> C
1 R550 2 HDA_RST_R# AE7
<8,16,30> HDA_RST_CODEC# HDA_RST#
0_0402_5% AG26 THRMTRIP_ICH# R112 1 2 54.9_0402_1% H_THERMTRIP#
THRMTRIP# H_THERMTRIP# <5,8>
<8> HDA_SDIN0 AF4 HDA_SDIN0
<16> HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 2 1 +VCCP
AH3 R114 56_0402_5%
<30> HDA_SDIN2 HDA_SDIN2
AE5

IHDA
HDA_SDIN3 R541 2 @
SATA4RXN AH11 1 1K_0402_5% R329 need to place within 2" of ICH9M
<8,16,30> HDA_SDOUT_CODEC 1 R557 2 HDA_SDOUT_R AG5
HDA_SDOUT SATA4RXP AJ11 R540 2 @ 1 1K_0402_5%
0_0402_5% AG12 R328 must be place within 2" of R258 w/o stub.
10K_0402_5% SATA4TXN
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
+3VS 2 1 R549 AE8 HDA_DOCK_RST#/GPIO34
SATA_LED# AG8
<39> SATA_LED# SATALED#
AH9 R544 2 @ 1 1K_0402_5%
SATA_DTX_C_IRX_N0 SATA5RXN R547 2 @
<39> SATA_DTX_C_IRX_N0 AJ16 SATA0RXN SATA5RXP AJ9 1 1K_0402_5%
<39> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 AH16 AE10
SATA_ITX_DRX_N0 SATA_ITX_C_DRX_N0 SATA0RXP SATA5TXN
<39> SATA_ITX_DRX_N0 1 2 AF17 SATA0TXN SATA5TXP AF10
<39> SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 C721 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AG17
C719 0.01U_0402_16V7K SATA0TXP CLK_PCIE_SATA#
SATA_CLKN AH18 CLK_PCIE_SATA# <22>

SATA
<39> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
SATA1RXN SATA_CLKP CLK_PCIE_SATA <22>
<39> SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 AJ13 AJ7
SATA_ITX_DRX_N1 SATA_ITX_C_DRX_N1 SATA1RXP SATARBIAS# SATARBIAS R5532
<39> SATA_ITX_DRX_N1 1 2 AG14 SATA1TXN SATARBIAS AH7 1
<39> SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 C677 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1 AF14 10mils width less than 500mils
C678 0.01U_0402_16V7K SATA1TXP
24.9_0402_1%
ICH9-M ES_FCBGA676

B B

Need check

+3VS
XOR Chain Entrance Strap
2

R556
ICH_TP3 HDA_SDOUT Description
1K_0402_5% 0 0 RSVD
@
0 1 Enter XOR Chain
1

HDA_SDOUT_R
1 0 Normal Operation
1 1 Set PCIE port config bit 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008
1
Sheet 27 of 53
 5 4 3 2 1

+3VALW +3VS
+3VALW
+3VALW Place closely pin B2 Place closely pin AC1
+3VS 1 2 SERIRQ

2
R406 10K_0402_5% R378 R543

1
R344 CLK_48M_ICH CLK_14M_ICH

2
1 2 PCI_CLKRUN# R361 R371 2.2K_0402_5% 2.2K_0402_5% 8.2K_0402_5%
R461 8.2K_0402_5% 10K_0402_5% 10K_0402_5% U34C

1
<22,32,40> ICH_SMBCLK G16 AH23

1
SMBCLK SATA0GP/GPIO21

2
GPIO38 R566 R460
1 2 <22,32,40> ICH_SMBDATA A13 SMB AF19

2
R352 10K_0402_5% LINKALERT# SMBDATA SATA1GP/GPIO19 R551 10_0402_5%

SATA
GPIO
E17 AE21 33_0402_5%

1
ME__EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
C17 SMLINK0 SATA5GP/GPIO37 AD20 10K_0402_5%
@ 1 2 EC_THERM# V ME__EC_DATA1 B18

2
R519 8.2K_0402_5% SMLINK1 CLK_14M_ICH
H1 CLK_14M_ICH <22>

1
ICH_RI# CLK14 CLK_48M_ICH
1 2 SATA_CLKREQ#
F19 RI# clocks CLK48 AF3 CLK_48M_ICH <22> 1
C733
1
D
+3VS D
R579 10K_0402_5% R4 P1 ICH_SUSCLK T101 @ 10P_0402_50V8J C576
XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK 22P_0402_50V8J
<5> XDP_DBRESET# G19 SYS_RESET#

2
2 2
1 2 OCP# SLP_S3# C16 SLP_S3#
SLP_S3# <35>
R355 10K_0402_5% @ R332 @R538
@ R538 PM_BMBUSY# M6 E16 SLP_S4#
<8> PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# <35>
10K_0402_5% 10K_0402_5% G17 SLP_S5#

SYS / GPIO
SLP_S5# SLP_S5# <35>
2 @ 1PM_BMBUSY# <35> EC_LID_OUT# 1 2LID_OUT# A17 SMBALERT#/GPIO11
R410 8.2K_0402_5% R532 0_0402_5% C10 S4_STATE# @
R170 100_0402_5%

1
H_STP_PCI# S4_STATE#/GPIO26 M_PWROK
<22> H_STP_PCI# A14 STP_PCI# 1 2
1 2 GPIO39 <22> H_STP_CPU# 2 1 R_STP_CPU# E19 STP_CPU# PWROK G20 ICH_POK
ICH_POK <8,35>
R336 10K_0402_5% R348 0_0402_5% 1 2 R362
PCI_CLKRUN# L4 M2 1 2 R574 DPRSLPVR @ 10K_0402_5%

Power MGT
PCI_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR <8,51>
1 2 GPIO48 499_0402_1%
R345 10K_0402_5% ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
<32,33,40> ICH_PCIE_WAKE# WAKE# BATLOW#
SERIRQ M5
<35,37> SERIRQ SERIRQ
EC_THERM# AJ23 R3 PBTN_OUT#
<35> EC_THERM# THRM# PWRBTN# PBTN_OUT# <35>
+3VALW 1 2 LINKALERT#
R370 10K_0402_5% 1 2 VRMPWRGD D21 D20
<8,51> VGATE VRMPWRGD LAN_RST#
R334 0_0402_5%
1 @ 2 CL_RST# T98 SST_CTL A20 TP11 RSMRST# D22 EC_RSMRST#R EC_RSMRST#R 1 2
R338 10K_0402_5% R335 10K_0402_5%
OCP# AG19 R5 CK_PWRGD_R 1 2 CK_PWRGD R320 3.24K_0402_1%
OCP# GPIO1 CK_PWRGD CK_PWRGD <22>
1 2 XDP_DBRESET# <40> CPUSB# AH21 GPIO6
R423 0_0402_5% 1 2 +3VS
R374 10K_0402_5% GPIO7 AG21 R6 M_PWROK
GPIO7 CLPWROK M_PWROK <8>

1
EC_SMI# A21 1
<35> EC_SMI# GPIO8
1 2 ICH_RI# <35> EC_SCI#
EC_SCI# C12 GPIO12 SLP_M# B16 T78 1 2 VGATE C441 R301
R360 10K_0402_5% GPIO13 C21 R707 100_0402_5% 0.1U_0402_16V4Z 453_0402_1%
GPIO17 GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 <8> 2
1 2 ICH_PCIE_WAKE# GPIO18 K1 B19 T2

GPIO
Controller Link

2
R350 1K_0402_5% GPIO20 GPIO18 CL_CLK1
AF8 GPIO20
GPIO22 AJ22 F22
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>
2 1 ICH_LOW_BAT# GPIO27 A9 GPIO27 CL_DATA1 C19 T3
R546 8.2K_0402_5% T76 D19
C SATA_CLKREQ# GPIO28 CL_VREF0_ICH R383 3.24K_0402_1% C
<22> SATA_CLKREQ# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25
1 2 LID_OUT# GPIO38 AE19 A19 CL_VREF1_ICH 1 2 +3VALW
R539 10K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39

1
GPIO48 AF21 F21 CL_RST# 1
SDATAOUT1/GPIO48 CL_RST0# CL_RST# <8>
1 2 WOL_EN GPIO49 AH24 GPIO49 CL_RST1# D18 T4 C717 R528
R524 100K_0402_5% GPIO57 A8 0.1U_0402_16V4Z 453_0402_1%
GPIO57/CLGPIO5 GPIO24 D14 RB751V_SOD323
MEM_LED/GPIO24 A16
12/14 changed from +3VS to +3VALW SB_SPKR 2
<30> SB_SPKR M7 C18 2 1 ACIN ACIN <35,44>

2
MCH_ICH_SYNC# SPKR GPIO10/SUS_PWR_ACK GPIO14
AJ24 C11

MISC
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
+3VS 1 2 GPIO7 ICH_RSVD B21 C20 +3VALW 2 1 2 1
R349 10K_0402_5% GPIO13 T96 TP3 WOL_EN/GPIO9 R356 R357 0_0402_5%
1 2 AH20 TP8
R365 1 2 10K_0402_5% GPIO17 T97 AJ20 WOL_EN 100K_0402_5% @
@ R363 10K_0402_5% GPIO18 T95 TP9
1 2 low-->default AJ21 TP10
@ R578 1 2 10K_0402_5% GPIO20
R548 1 2 10K_0402_5% GPIO22 High -->No boot ICH9-M ES_FCBGA676
R521 10K_0402_5% U34D
<36> PCIE_RXN1
PCIE_RXN1 N29 PERN1 DMI0RXN V27 DMI_RXN0 DMI_RXN0 <8>
RSMRST circuit
1 2 GPIO57 <36> PCIE_RXP1
PCIE_RXP1 N28 PERP1 DMI0RXP V26 DMI_RXP0 DMI_RXP0 <8> R271
R411 @ 100K_0402_5% TV TUNER <36> PCIE_TXN1 0.1U_0402_10V7K C435 PCIE_C_TXN1 P27 U29 DMI_TXN0 DMI_TXN0 <8> @
PETN1 DMI0TXN
1 2 DPRSLPVR <36> PCIE_TXP1 0.1U_0402_10V7K C436 PCIE_C_TXP1 P26 U28 DMI_TXP0 0_0402_5%

Direct Media Interface

PETP1 DMI0TXP DMI_TXP0 <8>
R573 @ 100K_0402_5% 1 2
L29 Y27 DMI_RXN1 DMI_RXN1 <8> R714
PERN2 DMI1RXN
2 1 ICH_RSVD L28 PERP2 DMI1RXP Y26 DMI_RXP1 DMI_RXP1 <8> Q26 0_0402_5%
R522 @ 1K_0402_5% DMI_TXN1 EC_RSMRST#R1

C
M27 PETN2 DMI1TXN W29 DMI_TXN1 <8> <35> EC_RSMRST# 3 1 2 POK <45,47>
DMI_TXP1

E
M26 PETP2 DMI1TXP W28 DMI_TXP1 <8>
2 @ 1 GPIO49 BAV99DW-7_SOT363 MMBT3906_SOT23-3

PCI - Express
R512 1K_0402_5% PCIE_RXN3 DMI_RXN2

B
<32> PCIE_RXN3 J29 AB27 DMI_RXN2 <8> 1 2 +3VALW

1 2
PCIE_RXP3 PERN3 DMI2RXN DMI_RXP2 R279 4.7K_0402_5%
<32> PCIE_RXP3 J28 PERP3 DMI2RXP AB26 DMI_RXP2 <8>

2
WLAN <32> PCIE_TXN3 0.1U_0402_10V7K C454 PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 <8>
SB_SPKR 0.1U_0402_10V7K C453 PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2 R272 D8B
+3VS 1 2 <32> PCIE_TXP3 K26 PETP3 DMI2TXP AA28 DMI_TXP2 <8>
R408 @ 10K_0402_5% @ 2.2K_0402_5%
PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 <8> D8A
B <40> PCIE_RXN4 PERN4 DMI3RXN B
PCIE_RXP4 G28 AD26 DMI_RXP3 DMI_RXP3 <8> BAV99DW-7_SOT363
<40> PCIE_RXP4

1
0.1U_0402_10V7K C439 PCIE_C_TXN4 PERP4 DMI3RXP DMI_TXN3
NEW CARD <40> PCIE_TXN4 H27 AC29 DMI_TXN3 <8> R274

6
0.1U_0402_10V7K C440 PCIE_C_TXP4 PETN4 DMI3TXN DMI_TXP3
<40> PCIE_TXP4 H26 PETP4 DMI3TXP AC28 DMI_TXP3 <8> 1 2
+3VS
E29 T26 CLK_PCIE_ICH# 2.2K_0402_5%
PERN5 DMI_CLKN CLK_PCIE_ICH# <22>
E28 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH <22>
2

F27 PETN5
F26 AF29 R297 24.9_0402_1% Within 500 mils
R319 PETP5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP AF28 1 2 +1.5VS
@ 330_0402_5% LAN PCIE_RXN6 C29
<33> PCIE_RXN6 PERN6/GLAN_RXN
PCIE_RXP6 C28 AC5 USB20_N0
<33> PCIE_RXP6 USB20_N0 <43>
1

PERP6/GLAN_RXP USBP0N
1 R328 2 VRMPWRGD 0.1U_0402_10V7K C449 PCIE_C_TXN6 D27 AC4 USB20_P0
@ 0_0402_5%
<33> PCIE_TXN6
<33> PCIE_TXP6 0.1U_0402_10V7K C450 PCIE_C_TXP6 D26
PETN6/GLAN_TXN USBP0P
AD3 USB20_N1
USB20_P0 <43> LEFT USB USB PORT LIST
PETP6/GLAN_TXP USBP1N USB20_N1 <43>
1

D USB20_P1
AD2
2 Q29 D23
USBP1P
AC1 USB20_N2
USB20_P1 <43> LEFT USB
<51> CLK_ENABLE# <38> SPI_CLK_SB SPI_CLK USBP2N USB20_N2 <40>
G @ RHU002N06_SOT323 USB20_P2
S <26> SB_SPI_CS#1
<38> FSEL#SPICS#_SB
SB_SPI_CS#1
D24
F23
SPI_CS0# USBP2P AC2
AA5 USB20_N3
USB20_P2 <40> PORT DEVICE
3

SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_P3

USBP3P AA4
SPI not used, Left NC USB20_N4
<38> FWR#SPI_SI_SB D25 SPI_MOSI SPI USBP4N AB2
USB20_P4
USB20_N4 <43> 0 LEFT SIDE
RP15
<38> FRD#SPI_SO_SB E23 SPI_MISO USBP4P AB3
USB20_N5
USB20_P4 <43> RIGHT USB
+3VALW 5 4 USB_OC#6
<43> USB_OC#0
USB_OC#0 N4
USBP5N AA1
AA2 USB20_P5 2 CMOS
USB_OC#1 USB_OC#1 OC0#/GPIO59 USBP5P USB20_N6
6
7
3
2 USB_OC#2
<43> USB_OC#1
USB_OC#2
N5
N6
OC1#/GPIO40
USB
USBP6N W5
W4 USB20_P6
USB20_N6 <32> 3 3G
USB_OC#4 USB_OC#3 OC2#/GPIO41 USBP6P USB20_N7
USB20_P6 <32> BT
8 1
USB_OC#4
P6
M1
OC3#/GPIO42 USBP7N Y3
Y2 USB20_P7 4 RIGHT SIDE
10K_1206_8P4R_5% USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8
USB_OC#6
N2 OC5#/GPIO29 USBP8N W1
USB20_P8
USB20_N8 <32> 6 BT
RP14 USB_OC#7
M4 OC6#/GPIO30 USBP8P W2
USB20_N9
USB20_P8 <32> WLAN
5 4 USB_OC#5 USB_OC#8
M3
N3
OC7#/GPIO31 USBP9N V2
V3 USB20_P9 8 WIRELESS
USB_OC#7 USB_OC#9 OC8#/GPIO44 USBP9P USB20_N10
6
7
3
2 USB_OC#9 USB_OC#10
N1
P5
OC9#/GPIO45 USBP10N U5
U4 USB20_P10
USB20_N10 <40> 10 NEW CARD
A USB_OC#0 USB_OC#11 OC10#/GPIO46 USBP10P USB20_N11
USB20_P10 <40> New Card A
8 1 <43> USB_OC#11 P3 OC11#/GPIO47 USBP11N U1
U2 USB20_P11
USB20_N11 <43> 11 RIGHT SIDE
10K_1206_8P4R_5% 2 1 USBRBIAS AG2
USBP11P USB20_P11 <43> RIGHT USB
22.6_0402_1% R447 USBRBIAS
AG1 USBRBIAS#
RP13
5 4 USB_OC#8 Within 500 mils ICH9-M ES_FCBGA676
6 3 USB_OC#3
7 2 USB_OC#10
8 1 USB_OC#11
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
10K_1206_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008
1
Sheet 28 of 53
 5 4 3 2 1

+VCCP
20 mils U34F U34E
+RTCVCC A23 VCCRTC VCC1_05[01] A15 AA26 VSS[001] VSS[107] H5
VCC1_05[02] B15 AA27 VSS[002] VSS[108] J23
1 1 ICH_V5REF_RUN A6 C15 AA3 J26
C459 C460 V5REF VCC1_05[03] VSS[003] VSS[109]
VCC1_05[04] D15 AA6 VSS[004] VSS[110] J27
0.1U_0402_16V4Z 0.1U_0402_16V4Z E15 1 1 AB1 AC22
ICH_V5REF_SUS VCC1_05[05] C521 C515 0.1U_0402_16V4Z VSS[005] VSS[111]
AE1 V5REF_SUS VCC1_05[06] F15 AA23 VSS[006] VSS[112] K28
2 2
VCC1_05[07] L11 AB28 VSS[007] VSS[113] K29
AA24 L12 0.1U_0402_16V4Z AB29 L13
VCC1_5_B[01] VCC1_05[08] 2 2 VSS[008] VSS[114]
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB4 VSS[009] VSS[115] L15
AB24 VCC1_5_B[03] VCC1_05[10] L16 AB5 VSS[010] VSS[116] L2
AB25 VCC1_5_B[04] VCC1_05[11] L17 AC17 VSS[011] VSS[117] L26
+5VS +3VS AC24 L18 AC26 L27
VCC1_5_B[05] VCC1_05[12] VSS[012] VSS[118]
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC27 VSS[013] VSS[119] L5
D R280 D
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC3 VSS[014] VSS[120] L7
1

2 0.01U_0402_16V7K

CORE
AD25 VCC1_5_B[08] VCC1_05[15] P11 1 2 +1.5VS AD1 VSS[015] VSS[121] M12
R558 D21 AE25 P18 CHB1608U301_0603 AD10 M13
VCC1_5_B[09] VCC1_05[16] VSS[016] VSS[122]
CH751H-40PT_SOD323-2 AE26 VCC1_5_B[10] VCC1_05[17] T11 1 1 AD12 VSS[017] VSS[123] M14
100_0402_5% AE27 T18 C426 C429 10U_0805_6.3V6M AD13 M15
VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[124]
AE28 U11 AD14 M16
2

VCC1_5_B[12] VCC1_05[19] VSS[019] VSS[125]

AE29 VCC1_5_B[13] VCC1_05[20] U18 AD17 VSS[020] VSS[126] M17
ICH_V5REF_RUN 2 2
F25 VCC1_5_B[14] VCC1_05[21] V11 AD18 VSS[021] VSS[127] M23
1 20 mils G25 VCC1_5_B[15] VCC1_05[22] V12 AD21 VSS[022] VSS[128] M28
H24 VCC1_5_B[16] VCC1_05[23] V14 AD28 VSS[023] VSS[129] M29
C728 H25 V16 +VCCP AD29 N11
VCC1_5_B[17] VCC1_05[24] VSS[024] VSS[130]
1U_0603_10V4Z J24 VCC1_5_B[18] VCC1_05[25] V17 AD4 VSS[025] VSS[131] N12
2

VCCA3GP
J25 VCC1_5_B[19] VCC1_05[26] V18 AD5 VSS[026] VSS[132] N13
K24 VCC1_5_B[20] 1 AD6 VSS[027] VSS[133] N14
K25 C504 10U_0805_10V4Z AD7 N15
VCC1_5_B[21] VSS[028] VSS[134]
L23 VCC1_5_B[22] AD9 VSS[029] VSS[135] N16
L24 VCC1_5_B[23] VCCDMIPLL R29 AE12 VSS[030] VSS[136] N17
+5VALW +3VALW 2
L25 VCC1_5_B[24] AE13 VSS[031] VSS[137] N18
M24 VCC1_5_B[25] VCC_DMI[1] W23 AE14 VSS[032] VSS[138] N26
M25 Y23 +VCCP AE16 N27
VCC1_5_B[26] VCC_DMI[2] VSS[033] VSS[139]
1

N23 VCC1_5_B[27] AE17 VSS[034] VSS[140] P12

R582 D22 N24 AB23 AE2 P13
VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[141]
CH751H-40PT_SOD323-2 N25 VCC1_5_B[29] V_CPU_IO[2] AC23 AE20 VSS[036] VSS[142] P14

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
100_0402_5% P24 AE24 P15
VCC1_5_B[30] VSS[037] VSS[143]
P25 AG29 +3VS 1 1 1 AE3 P16
2

VCC1_5_B[31] VCC3_3[01] VSS[038] VSS[144]

C502

C484

C466
ICH_V5REF_SUS R24 AJ6 +3VS 1 (DMI) AE4 P17
VCC1_5_B[32] VCC3_3[02] +3VS (SATA) VSS[039] VSS[145]
20 mils R25 VCC1_5_B[33] VCC3_3[07] AC10 1 AE6 VSS[040] VSS[146] P2
1 R26 C433 AE9 P23
VCC1_5_B[34] C549 0.1U_0402_16V4Z 2 2 2 VSS[041] VSS[147]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AF13 VSS[042] VSS[148] P28
2

VCCP_CORE
C738 T24 AF20 1 0.1U_0402_16V4Z AF16 P29
VCC1_5_B[36] VCC3_3[04] 2 VSS[043] VSS[149]
1U_0603_10V4Z T27 VCC1_5_B[37] VCC3_3[05] AG24 AF18 VSS[044] VSS[150] P4
2 C486
T28 VCC1_5_B[38] VCC3_3[06] AC20 AF22 VSS[045] VSS[151] P7
C 0.1U_0402_16V4Z C
T29 VCC1_5_B[39] AH26 VSS[046] VSS[152] R11
2 +3VS
U24 VCC1_5_B[40] AF26 VSS[047] VSS[153] R12
R309 40 mils U25 B9 AF27 R13
10U_0805_10V4Z VCC1_5_B[41] VCC3_3[08] VSS[048] VSS[154]
+1.5VS 1 2 V24 VCC1_5_B[42] VCC3_3[09] F9 AF5 VSS[049] VSS[155] R14
V25 G3 +3VS +1.5VS AF7 R15
1 VCC1_5_B[43] VCC3_3[10] 1 1 1 VSS[050] VSS[156]
0_0805_5% 1 1 1 U23 G6 AF9 R16
VCC1_5_B[44] VCC3_3[11] VSS[051] VSS[157]

PCI
+ C445 C446 C447 W24 J2 C545 C532 C519 AG13 R17
VCC1_5_B[45] VCC3_3[12] VSS[052] VSS[158]

2
C455 W25 J7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AG16 R18
220U_D2_4VM VCC1_5_B[46] VCC3_3[13] 2 2 2 R612 VSS[053] VSS[159]
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[054] VSS[160] R28
2 2 2 2 R613
Y24 VCC1_5_B[48] 0_0402_5% AG20 VSS[055] VSS[161] T12
Y25 PM@ GM@ AG23 T13
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[49] VSS[056] VSS[162]
AJ4 AG3 T14

1
VCCHDA VSS[057] VSS[163]
R518 AG6 VSS[058] VSS[164] T15
AJ3 1 0_0402_5% AG9 T16
VCCSUSHDA 0.1U_0402_16V4Z VSS[059] VSS[165]
+1.5VS 1 2 AJ19 VCCSATAPLL AH12 VSS[060] VSS[166] T17
1U_0603_10V4Z

C534 AH14 T23

1
check HDMI VSS[061] VSS[167]
10U_0805_10V4Z

CHB1608U301_0603 AC8 T82 0.1U_0402_16V4Z AH17 B26

VCCSUS1_05[1] T79 C552 2 VSS[062] VSS[168]
1 1 +1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 AH19 VSS[063] VSS[169] U12
C712

C710

1 AD15 VCC1_5_A[02] AH2 VSS[064] VSS[170] U13

C542 2 +3VALW
AD16 VCC1_5_A[03] AH22 VSS[065] VSS[171] U14
AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 VCCSUS1_5_ICH_1 R615 AH25 VSS[066] VSS[172] U15
2 2
ARX

1U_0603_10V4Z AF15 AH28 U16

VCC1_5_A[05] VSS[067] VSS[173]

2
2 VCCSUS1_5_ICH_2
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 AH5 VSS[068] VSS[174] U17
AH15 R615 AH8 AD23
VCC1_5_A[07] VSS[069] VSS[175]
AJ15 VCC1_5_A[08] 549_0402_1% AJ12 VSS[070] VSS[176] U26
A18 GM@ R715 @ AJ14 U27
VCCSUS3_3[01] VSS[071] VSS[177]
+1.5VS AC11 D16 1 2 0_0402_5% AJ17 U3
VCCPSUS

1
VCC1_5_A[09] VCCSUS3_3[02] PM@ VSS[072] VSS[178]
1 AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ8 VSS[073] VSS[179] V1
C492 AE11 E22 0_0402_5% B11 V13
VCC1_5_A[11] VCCSUS3_3[04] R614 VSS[074] VSS[180]
AF11 VCC1_5_A[12] B14 VSS[075] VSS[181] V15
ATX

1U_0603_10V4Z AG10 453_0402_1% B17 V23

2 VCC1_5_A[13] +3VALW @ VSS[076] VSS[182]
AG11 VCC1_5_A[14] B2 VSS[077] VSS[183] V28
B B
AH10 VCC1_5_A[15] B20 VSS[078] VSS[184] V29
AJ10 AF1 0.1U_0402_16V4Z B23 V4
VCC1_5_A[16] VCCSUS3_3[05] VSS[079] VSS[185]
1 1 B5 VSS[080] VSS[186] V5
+1.5VS AC9 VCC1_5_A[17] B8 VSS[081] VSS[187] W26
1 C551 C546 C26 W27
C528 0.1U_0402_16V4Z VSS[082] VSS[188]
AC18 VCC1_5_A[18] C27 VSS[083] VSS[189] W3
2 2
AC19 VCC1_5_A[19] E11 VSS[084] VSS[190] Y1
1U_0603_10V4Z T1 E14 Y28
2 VCCSUS3_3[06] VSS[085] VSS[191]
AC21 VCC1_5_A[20] VCCSUS3_3[07] T2 E18 VSS[086] VSS[192] Y29
VCCSUS3_3[08] T3 E2 VSS[087] VSS[193] Y4
G10 VCC1_5_A[21] VCCSUS3_3[09] T4 E21 VSS[088] VSS[194] Y5
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E24 VSS[089] VSS[195] AG28
VCCSUS3_3[11] T6 E5 VSS[090] VSS[196] AH6
AC12 +3VALW
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] U6 E8 VSS[091] VSS[197] AF2

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 F16 VSS[092] VSS[198] B25
AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F28 VSS[093]
VCCSUS3_3[15] V7 1 F29 VSS[094]
+1.5VS AJ5 W6 C560 G12
VCCUSBPLL VCCSUS3_3[16] 4.7U_0603_6.3V6K VSS[095]
+1.5VS VCCSUS3_3[17] W7 G14 VSS[096] VSS_NCTF[01] A1
USB CORE

1 1 AA7 VCC1_5_A[26] VCCSUS3_3[18] Y6 G18 VSS[097] VSS_NCTF[02] A2

C510 C493 2
AB6 VCC1_5_A[27] VCCSUS3_3[19] Y7 G21 VSS[098] VSS_NCTF[03] A28
0.1U_0402_16V4Z 0.1U_0402_16V4Z AB7 T7 G24 A29
VCC1_5_A[28] VCCSUS3_3[20] VSS[099] VSS_NCTF[04]
AC6 VCC1_5_A[29] G26 VSS[100] VSS_NCTF[05] AH1
2 2
AC7 VCC1_5_A[30] G27 VSS[101] VSS_NCTF[06] AH29
G8 VSS[102] VSS_NCTF[07] AJ1
T100 VCC_LAN1_05_INT_ICH_1 A10 H2 AJ2
+3VS VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VSS[103] VSS_NCTF[08]
T99 A11 VCCLAN1_05[2] VCCCL1_05 G22 VCCCL1_05_ICH T75 H23 VSS[104] VSS_NCTF[09] AJ28
close to AC7 VCCCL1_5 G23 H28 VSS[105] VSS_NCTF[10] AJ29
A12 VCCLAN3_3[1] 1 H29 VSS[106] VSS_NCTF[11] B1
1 B12 C498 B29
C529 VCCLAN3_3[2] @ 1U_0603_10V4Z VSS_NCTF[12]
VCCCL3_3[1] A24 +3VS
0.1U_0402_16V4Z CHB1608U301_0603 2.2U_0603_6.3V4Z B24
VCCCL3_3[2] 2
GLAN POWER

A ICH9-M ES_FCBGA676 A
1 2 A27 VCCGLANPLL
2 R282
+1.5VS 1 1
D28 VCCGLAN1_5[1]
C431 C434 D29 VCCGLAN1_5[2]
(10UF*1, 2.2UF*1) 2 2
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4]
10U_0805_10V4Z
R281 4.7U_0805_10V4Z A26
+1.5VS 1 2
CHB1608U301_0603
+3VS
VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
1 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

C430
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
Size Document Number Rev
hexainf@hotmail.com 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Wednesday, May 14, 2008
1
Sheet 29 of 53
 A B C D E

0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p
AUDIO CODEC CODEC POWER (3.33V)
For Layout: 250mW
In order for the modem wake on ring feature to function, Place decoupling caps near the power pins of R395
the CODEC must be powered by a rail that is not @ +5VALW +VDDA_CODEC
SmartAMC device. 2 1 +3VS W=40Mil U21
removed when the system is in standby. MBV2012301YZF_0805
1 2 1 2 1 VIN OUT 5
+3VDD_CODEC +3VAMP_CODEC C524 4.7U_0805_10V4Z C571 0.1U_0402_16V4Z 1 1
R333 R424 2.2kohm for MICL + MICR 2 C555 C562
GND
+3VS 1 2 2 1 +VDDA_CODEC 4.7kohm for MICL or MICR

680P_0402_50V7K

680P_0402_50V7K

1U_0603_10V4Z
1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
MBV2012301YZF_0805 MBV2012301YZF_0805 <35,40,41,42,46,48,49,50> SUSP# 3 4 0.1U_0402_16V4Z 4.7U_0805_10V4Z
SHDN# BP 2 2

680P_0402_50V7K

1U_0603_10V4Z
R722 1 1 1 1 1 1 1 1 @ 1 @ @
+3VALW 1 2 APE8805A-33Y5P_SOT23-5
MBV2012301YZF_0805 @ C558
@ +3VAMP_CODEC 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

C478

C475

C497

C491

@ C479

C512

C537

C540
@

1K_0402_5%

R656
R611
+3VDD_CODEC

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
MIC_C_BIAS

C477

C481

C536

C541

1
1

R611
2 2 2 2
4.7K_0603_5% 0_0603_5%

R380

R588

R405
PM@

44

26
40
36
@

9
4
3

R385
U15
2

2
AVEE
VDD_IO
DVDD_1-8
DVDD_3-3
DVDD_44

AVDD_26
AVDD_40

10U_0805_10V4Z
1

@
+1.5VS 1 2 1

4.7K_0402_5%

C783
R723 R610 GM@ 0_0402_5% 34 @
PORTA_L HP_L <41>

2.2K_0402_5%

2.2K_0402_5%

4.7K_0402_5%
3.9K_0603_1% R666 1 2 33_0402_5%11 35
<8,16,27> HDA_RST_CODEC# HP_R <41>

1
RESET# PORTA_R
@ 2
R659 1 2 33_0402_5% 6 19
<8,16,27> HDA_BITCLK_CODEC
2

R667 33_0402_5%10 BIT_CLK MICBIASB

<8,16,27> HDA_SYNC_CODEC 1 2 SYNC PORTB_L 14
R323 1 2 33_0402_5% 8 15
<27> HDA_SDIN2 SDATA_IN PORTB_R
R668 1 2 33_0402_5% 5
<8,16,27> HDA_SDOUT_CODEC SDATA_OUT
MICBIASC 18 MIC_C_BIAS
16 MIC_EXTL C496 1 2 2.2U_0603_16V6K 2 1 EXT_MIC_L <41>

2
CX20548 DIBP_HS
DIBN_HS
R387
R394
1
1
2 0_0402_5% DIBP_C
2 0_0402_5% DIBN_C
43
42
DIB_P
DIB_N
PORTC_L
PORTC_R 17 MIC_EXTR C505 1

@
2 2.2U_0603_16V6K R701 2
R702
@
100_0402_5%
1
100_0402_5%
EXT_MIC_R <41>external MIC
2

AMOM DAA PC_BEEP 12 PC_BEEP

PORTD_L
PORTD_R
27
28

48 20 MIC_INL C516 1 2 2.2U_0603_16V6K

S/PDIF MIC_L INT_MICL <31>
PC_BEEP dB control 21 MIC_INR C525 1 2 2.2U_0603_16V6K Internal MIC / Array MIC
MIC_R INT_MICR

MONO 29 @ Internal WOOFER

1 2 45 GPIO2 STEREO_L 30 LINE_OUTL <31>
R369 1 2 10K_0402_5% 46 31 Internal SPKR.
GPIO1 STEREO_R LINE_OUTR <31>
R359 10K_0402_5% 47
<35> EAPD EAPD/GPIO0
+3VAMP_CODEC
13 SENSE 1 2
HDA_BITCLK_CODEC SENSEA For Vista R392 5.1K_0402_1%
1 24 VC_REFA
DMIC_CLOCK VREF
2 DMIC_1/2 1 2 JACK_PLUG_HP <41> Port A
1

10U_0805_10V4Z
0.1U_0402_16V4Z
39 VREF_HI R391 5.1K_0402_1%
R327 FLY_P VREF_LO
FLY_N 37 1 2 1 1

C535

C548
47_0402_5% C533 1U_0603_10V4Z 1 2 JACK_PLUG_MIC <41> Port C
22 R386 20K_0402_5%
DVSS_41

AVSS_25
AVSS_38

VREF_LO
DVSS_7

23
2

VREF_HI 2 2
1 RESERVED_32 32 port A : 5.11K ohm

1U_0603_10V4Z

1U_0603_10V4Z
RESERVED_33 33 port B : 10.0K ohm
C458 1 1
33P_0402_50V8K CX20561-12Z_LQFP48_7X7
port C : 20.0K ohm
7
41

25
38

2 port D : 39.2K ohm

2 2

C526

C517
3 0216_Change value. 3

+3VS
DIGITAL ANALOG
1

R347
C553 10K_0402_1%
1 2
2

0.1U_0402_16V4Z 2 1C465
1

C565 1U_0603_10V4Z
1 2
0.1U_0402_16V4Z R346
10K_0402_1%
CX20548 RING_1
TIP_1
1
2
JRJ11
1
C490 C485 1U_0603_10V4Z 2

AMOM DAA
2

1 2 1 2PC_BEEP1 2 1 PC_BEEP 3 GND1

0.1U_0402_16V4Z R354 20K_0402_5% 4 GND2
C480 FOX_JM74613-P2002-7F
1

1 2 C456 R318 C
2

0.1U_0402_16V4Z <35> BEEP# 2 1 1 2 2 Q28 ME@

1 B 2SC2411KT146_SOT23-3 R353

330P 3KV J NPO 1808 X2Y3

330P 3KV J NPO 1808 X2Y3

R443 C452 560_0402_5% E 20K_0402_5% RING_1
3

1 2 1U_0603_10V4Z TIP_1
0_0402_5% @ 0.1U_0402_16V4Z
1

2
R446 1 1

C797

C798
1 2 @
0_0402_5%

4 C443 2 2 4
R454 R317
1 2 <28> SB_SPKR 2 1 1 2
0_0402_5%
1

560_0402_5%
1U_0603_10V4Z R313 D10 @
GND GNDA 10K_0402_5%
RB751V_SOD323

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

Place these C and R around AGND and DGND, CX20561-AMOM Codec
then choose the one which is close to Codec THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
hexainf@hotmail.com
to populate
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. A B C D

Date: Monday, May 12, 2008
E
Sheet 30 of 53
 A B C D E

+5VAMP +5VS

L27
1 2

1 2 FBMA-L11-160808-700LMT_0603

C689 C686
0.1U_0402_16V4Z 10U_0805_10V4Z
Speaker Amplifier 2 1
1 1

1nd = APA2031 (SA00001RZ00) +5VAMP +5VAMP JP10

GAIN0 GAIN1 SPKL+O R413 1 2 0_0402_5% SPK_L1+ 4
2nd = G1431F2U (SA000012Y00) 0 0 6dB
SPKL-O
SPKR+O
R412
R435
1 2 0_0402_5%
0_0402_5%
SPK_L1-
SPK_R1+
3
4
3
1 2 2 2

2
SPKR-O R436 0_0402_5% SPK_R1-
@ R397 R401
0 1 10dB 1 2 1 1
100K_0402_1% 100K_0402_1% 1 0 15.6dB 20mil ACES_85204-0400N
1 1 21.6dB Speaker Conn.
ME@

2 1

2 1

@C544
@

@C543
@

@C556
@

@C557
@
GAIN0 GAIN1

C544 22P_0402_50V8J

C543 22P_0402_50V8J

C556 22P_0402_50V8J

C557 22P_0402_50V8J
1 1 1 1
R400 R398
100K_0402_1% 100K_0402_1%
@
2 2 2 2

1
+5VAMP +3VALW

W=40mil

1
2
R414

1 1
R439
10K_0402_5%
INT MIC 0_0402_5%
@
@

2
C527 C569 U18

1
0.1U_0402_16V4Z 4.7U_0805_10V4Z 16 12
2 2 2 VDD NC AMP_OFF# 2
6 PVDD SHUTDOWN# 19 R441 1 2 EC_MUTE# EC_MUTE# <35>
15 0_0402_5% JMIC2
PVDD SPKL-O INT_MICL
LOUT- 8 1 1 INT_MICL <30>
GAIN0 2 2 GNDA
GAIN0 SPKR-O 2
ROUT- 14 1
GAIN1 3 3
GAIN1 SPKL+O GND C742
LOUT+ 4 GND 4
R409 0_0402_5% 0.1U_0603_25V7K 20mil 47P_0402_50V8J
C550 LIN SPKR+O MOLEX_53780-0270 2
<30> LINE_OUTL 1 2 1 2 5 LIN- ROUT+ 18
0.1U_0603_25V7K GNDA
R455 1 2 C570 1 2 RIN 17 1 ME@
<30> LINE_OUTR RIN- GND
0_0402_5% 11
GND
9 LIN+ GND 13
1

R417 R451 2 20
GND
0.1U_0603_25V7K

7 RIN+ GND 21
10K_0402_5%

10K_0402_5%

C506

BYPASS 10 1
@ @ 2
1 D30
0.1U_0603_25V7K

APA2031RI-TRL_TSSOP20 C523
2

C507

4.7U_0805_10V4Z INT_MICL 2
2
1
1
3

PJMBZ6V8_SOT23-3

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

AMP/VR/Audio Jack/MIC
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom JIWA3/A4_LA4212P
Rev
1.0

gratuito - free of charge. A B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Date: Monday, May 12, 2008
E
Sheet 31 of 53
 A B C D E

Mini-Express Card for 3G Or TV Tuner +5VS

1
Mini-Express Card for WLAN R246
10K_0402_1%
+3VS +1.5VS BT@

1 2
+3VALW

1 1 1 1 1

OUT
C734 C704 C729 C709 1
C732 C725 WLAN@

1 2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<35> BT_OFF# 2 IN
BT MODULE CONN 1
0.1U_0402_16V4Z Q17

GND
2 DTC124EKAT146_SC59-3 Q18
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ +3VS SI2301BDS-T1-E3_SOT23-3 +3VS_BT

D
3 1 2 1
C409
BT@ 0.1U_0402_16V4Z
BT@ BT@

G
<38> BT_LED#

2
Mini-Express Card(Slot 1-WLAN) JP7

1
1 1
1 @ 2 2

OUT
0_0402_5% +3VALW 2
JP22 R708 <28> USB20_N6 USB20_N6 3
ICH_PCIE_WAKE# USB20_P6 3
<28,33,40> ICH_PCIE_WAKE# 1 1 2 2 1 2 +3VS <28> USB20_P6 4 4
BT_ACTIVE @ R569 1 2 0_0402_5% 3 4 R709 WLAN@ 0_0402_5% 2 BTON_LED 5
WLAN_ACTIVE @ R565 1 0_0402_5% 3 4 Q16 IN BT_ACTIVE 5
2 5 6 2 1 6

GND
5 6 +1.5VS 6
WLAN_CLKREQ# 7 8 J3 JOPEN 2Watt DTC124EKAT146_SC59-3 WLAN_ACTIVE 7
<22> WLAN_CLKREQ# 7 8 7

1
9 10 BT@ 8
9 10 8
CR#_G <22> CLK_PCIE_WLAN# 11 12 R596 1 @ 2 0_0402_5%
3G_OFF# 9

3
11 12 GND1
SRC9 <22> CLK_PCIE_WLAN 13
15
13
15
14
16
14
16
R245
10K_0402_5%
10 GND2
17 18 WLAN@ 0_0402_5% @ MOLEX_53780-0870

2
17 18 R592 1 WL_OFF# ME@
19 19 20 20 2 WL_OFF# <35>
21 21 22 22 PLT_RST# <8,16,26,33,36,40>
<28> PCIE_RXN3 23 23 24 24 1 2 @ +3VALW
<28> PCIE_RXP3 25 25 26 26 R552 1 2 0_0402_5% +3VS
27 28 R555 @ 0_0402_5%
27 28 R537 1 @ 0_0402_5%
29 29 30 30 2 ICH_SMBCLK <22,28,40>
31 32 R534 1 @ 2 0_0402_5% ICH_SMBDATA <22,28,40>
<28> PCIE_TXN3 31 32
<28> PCIE_TXP3 33 33 34 34
2 35 36 2
35 36 USB20_N8 <28>
WLAN@ 1 2 37 38
37 38 USB20_P8 <28>
+3VS 1 2 R710 0_0402_5% 39 40
R711 0_0402_5% @ 2 WLAN@ 39 40
+3VALW 1 41 41 42 42
R712 0_0402_5% 1 2 43 44 (WWAN_LED#) 1 2
43 44 WLAN_LED# <38>
R713 0_0402_5% 45 46 R525 0_0402_5%
WLAN@ 45 46
47 47 48 48 WLAN@
49 49 50 50
51 51 52 52

53 54 @ R523
GND1 GND2
1 2 +5VS
FOX_AS0B226-S56N-7F 100K_0402_5%
ME@

2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1
Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 1000mA

3 3

4 4

Security Classification
2007/10/15
Compal Secret Data
2008/10/15 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/3G/FeliCa/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JIWA3/A4_LA4212P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 20, 2008 Sheet 32 of 53
A B C D E

hexainf@hotmail.com
gratuito - free of charge.
 5 4 3 2 1

Layout Notice : Filter place as close L3 @ Layout Notice : Place as close

FBM-L11-321611-260-LMT_1206 Layout Notice : 1.2V filter. Place as close
chip as possible. chip as possible.
1 2 chip as possible.
+2.5V_LAN +3V_LAN
L4 +3VALW +1.2V_LAN
3 Q7

S
2 1 +XTALVDD 1
FBM-L11-160808-601LMT_06032 +5VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AO3414_SOT23-3

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C56 2 2 2 1

G
2
1

C32

4.7U_0805_10V4Z
0.1U_0402_16V4Z 2 2 2 2 2 2 2
1

C62

C55
R25 C81

C77

C67

C49

C46

C58

C65

C45
21.5 33K_0402_5% 1U_0603_10V4Z
L7 1 1 1 2
D 1 1 1 1 1 1 1 D
2 1 +LAN_AVDD

2
FBM-L11-160808-601LMT_06032 2 1
C68 C76 C74 2

1
0.047U_0402_16V4Z 0.01U_0402_16V7K D C34
1
0.047U_0402_16V4Z 1 2 EN_WOL 2
<35> EN_WOL
Q8 G 0.1U_0402_16V4Z
2N7002_SOT23 S 1

3
L8
2 1 +LAN_BIASVDD
FBM-L11-160808-601LMT_0603 1 U1
C71
41 LAN_TX0-
TRD0_N LAN_TX0- <34>
0.1U_0402_16V4Z 28 40 LAN_TX0+
2 <22> CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_TX0+ <34>
42 LAN_RX1-
TRD1_N LAN_RX1- <34>
29 43 LAN_RX1+
<22> CLK_PCIE_LAN PCIE_REFCLK_P TRD1_P LAN_RX1+ <34>
TRD2_N 48 T20
<22> CLKREQ_LAN# 11 CLKREQ TRD2_P 47 T18
TRD3_N 49 T21
TRD3_P 50 T19
+1.2V_LAN
1 2 3 +3V_LAN
+3VS LOW PWR
2 1 +AVDDL (CLKREQ#) and (ENERGY_DET) are R35 @ 0_0402_5%
L30 FBM-L11-160808-601LMT_0603
1 2 +3VS 1 2 53 2 R36 1 2 0_0402_5% LINKLED# <34> C53 1 2 0.1U_0402_16V4Z
only supported in BCM5787M R52 1K_0402_5% VMAIN_PRSNT LINKLED
1 R37 1 2 0_0402_5%
C73 C75 SPD100LED
+3V_LAN 1 2 54 VAUX_PRSNT SPD1000LED 67 R38 1 2 @ 0_0402_5%
1U_0603_10V4Z 0.1U_0402_16V4Z R49 1K_0402_5% 66 ACTIVITY# <34>
TRAFFICLED

3
2 1
MMJT9435T1G_SOT223
R40 1 2 59 65 LAN_CLK CTL12 1
<26> PCI_CBE#3 ENERGY_DET SCLK(EECLK)
2 1 +GPHY_PLLVDD @ 0_0402_5% 63 SI
L6 FBM-L11-160808-601LMT_0603 SI LAN_DATA +1.2V_LAN
2 2 +GPHY_PLLVDD 35 GPHY_PLLVDD SO(EEDATA) 64
C
62 CS# Q6 C

2
4
C72 C70 CS
<28> PCIE_TXN6 32 PCIE_RXD_N
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1
1 1 C61
<28> PCIE_TXP6 31 PCIE_RXD_P
14 CTL12
0.1U_0402_16V7K PCIE_MRX_C_LTX_N6 REGCTL12 CTL25 10U_0805_10V4Z
<28> PCIE_RXN6 25 PCIE_TXD_N REGCTL25 18
C57 2
2 1 +PCIE_PLLVDD RDAC 37 1 2
L31 FBM-L11-160808-601LMT_0603
2 2 <28> PCIE_RXP6 0.1U_0402_16V7K PCIE_MRX_C_LTX_P6 26 R56 1K_0402_5%
C59 PCIE_TXD_P
C64 C63
4.7U_0805_10V4Z 0.1U_0402_16V4Z 23 +XTALVDD
1 1 XTALVDD
<8,16,26,32,36,40> PLT_RST# 10 PERST VDDIO 6 +3V_LAN
VDDIO 15
<28,32,40> ICH_PCIE_WAKE# @ 1 2 12 19
R31 0_0402_5% WAKE VDDIO
2 1 +PCIE_VDD <35> LAN_WAKE# VDDIO 56
L5 FBM-L11-160808-601LMT_0603
1 2 61
VDDIO +3V_LAN
C69 C60 +3V_LAN 1 2 58 17
SMB_CLK VDDP +2.5V_LAN
1U_0603_10V4Z 0.1U_0402_16V4Z R42 @ 47K_0402_5% 68
2 1 VDDP
+3V_LAN 1 2 57 SMB_DATA
R44 @ 47K_0402_5% 5 +1.2V_LAN
VDDC

4
13 Q9
VDDC MBT35200MT1G_TSOP6
VDDC 20
1 2 4 GPIO_0(SERIAL_DO) VDDC 34
R34 0_0402_5% 55 CTL25 3
LAN_WP VDDC
1 2 7 GPIO_1(SERIAL_DI) VDDC 60
R33 @ 4.7K_0402_5%
1 2 GPIO2 8 36 +LAN_BIASVDD

1
2
5
6
R32 @ 4.7K_0402_5% GPIO_2 BIASVDD
Layout Notice : Place as close PCIE_PLLVDD 30 +PCIE_PLLVDD
chip as possible. +3V_LAN 1 2 9 UART_MODE PCIE_VDD 27 +PCIE_VDD
R41 @ 0_0402_5% 33
PCIE_VDD
B +2.5V_LAN 38 B
AVDD +LAN_AVDD
XTALI 21 45
XTALI AVDD
R39 AVDD 52
200_0402_1% XTALO 22 XTALO
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 1 XTALO 39
AVDDL +AVDDL +2.5V_LAN
10U_0805_10V4Z

2 2 2 AVDDL 44
C52

C44
C54

XTALI 16 46
Y1 REG_GND AVDDL
51 Notice : 4.7u 6.3V capactor Thickness 1.25mm

GND
AVDDL
27P_0402_50V8J

27P_0402_50V8J

1 2 24 PCIE_GND
1 1 1
2 2 Layout Notice : Filter place as close

69
C42

C43

25MHZ_20P
chip as possible.
1 1
+3V_LAN

1 2

1
C38
0.1U_0402_16V4Z
R28 R27
4.7K_0402_5% 4.7K_0402_5%

2
U2
8 VCC A0 1
LAN_WP 7 2
LAN_CLK WP A1
6 SCL NC 3
LAN_DATA 5 4
SDA GND
AT24C02_SO8

A LAN_CLK A
1 2
R30 4.7K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BCM5787MKML
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 33 of 53
 5 4 3 2 1

+2.5V_LAN
RJ45 CONN
EMI request

R67
C602 1 2 0.1U_0402_16V4Z 330_0402_5% JRJ45
<33> ACTIVITY# 2 1 12 Amber LED-

1
R476 +3V_LAN 11 16
D 0_0402_5% U25 Amber LED+ SHLD4 D

2 8 PR4- SHLD3 15
LAN_RX1+ 1 16 MDO1+ 220P_0402_25V8J
<33> LAN_RX1+

2
LAN_RX1- RD+ RX+ MDO1- C80
<33> LAN_RX1- 2 RD- RX- 15 7 PR4+
C607 1 2 0.1U_0402_16V4Z TCT 3 14 MCT0 R72 2 1 75_0402_5%
CT CT RJ45_PR 1 MDO1-
4 NC NC 13 6 PR2-
5 NC NC 12
C601 1 2 0.1U_0402_16V4Z TCT 6 11 MCT1 R76 2 1 75_0402_5% 5
LAN_TX0+ CT CT MDO0+ PR3-
<33> LAN_TX0+ 7 TD+ TX+ 10
@ LAN_TX0- 8 9 MDO0- 4
<33> LAN_TX0- TD- TX- PR3+
MDO1+ 3
350uH_NS0013LF PR2+
MDO0- 2 PR1-
SHLD2 14
MDO0+ 1
R92 PR1+
330_0402_5%
<33> LINKLED# 2 1 10 13
Green LED- SHLD1
+3V_LAN 9 Green LED+
Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF 1
FOX_JM36113-P2221-7F
C88
220P_0402_25V8J ME@
2

LAN_RX1- 2 1 C600
R475 49.9_0402_1% 1 2 0.1U_0402_16V4Z
LAN_RX1+ 2 1
R472 49.9_0402_1% RJ45_PR 1 2
C85
1000P_1206_2KV7K

2
C C
R669
0_0402_5%
LAN_TX0- 2 1 C610
R478 49.9_0402_1% 1 2 0.1U_0402_16V4Z

1
LAN_TX0+ 2 1
R477 49.9_0402_1%

near LAN controller

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONTROLLER
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge.5 4 3 2

Date: Monday, May 12, 2008
1
Sheet 34 of 53
 +3VALW +3VALW +3VALW
+EC_AVCC
1 1 1 1 1 1

1
0.1U_0402_16V4Z
C513

0.1U_0402_16V4Z
C531

0.1U_0402_16V4Z
C530

0.1U_0402_16V4Z
C520

1000P_0402_50V7K
C448

1000P_0402_50V7K
C487
L23 1 2 C418
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603
2 1 1 2 0.1U_0402_16V4Z R265
100K_0402_1%
C432 2 2 2 2 2 2
0.1U_0402_16V4Z C437 @

111
125
1000P_0402_50V7K U12 @

22
33
96

67

2
U17

9
1 ECAGND 2
1 2 8 VCC A0 1
L24 FBM-11-160808-601-T_0603 7 2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
EC_SMB_CK1 WP A1
6 SCL A2 3
EC_SMB_DA1 5 4
SDA GND
D23
1 21 INVT_PWM AT24C16AN-10SU-2.7_SO8
<27> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <24>
2 1 KB_RST#_EC 2 23 BEEP#
<27> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <30>
3 26 BATT_OVP C744 1 2 100P_0402_50V8J @
<28,37> SERIRQ SERIRQ# FANPWM1/GPIO12 NOVO# <41>

1
4 27 ACOFF
<27,37> LPC_FRAME#
RB751V_SOD323 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <44,46>
LPC_AD3 5 BATT_TEMP
C745 1 2 100P_0402_50V8J R273
<27,37> LPC_AD3 LAD3
LPC_AD2 7 PWM Output 100K_0402_1%
<27,37> LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP ACIN C746 1 2 100P_0402_50V8J
<27,37> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <45>
LPC_AD0 BATT_OVP @
<27,37> LPC_AD0 10 LAD0 LPC & MISC 64 BATT_OVP <46>

2
BATT_OVP/AD1/GPIO39
2 1 2 1 ADP_I/AD2/GPIO3A 65 ADP_I <46>
@C538
@ C538 22P_0402_50V8J @R40310_0402_5%
@ R40310_0402_5% 12 AD Input 66 BRD_ID
<22> CLK_PCI_LPC PCICLK AD3/GPIO3B
13 75 TSATN#_EC@ 1 2
<26,37> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 TSATN# <8>
1 2 EC_RST# 37 76 R382 0_0603_5%
+3VALW
R388 47K_0402_5%
<28> EC_SCI#
EC_SCI# 20
ECRST#
SCI#/GPIO0E
SELIO2#/AD5/GPIO43 for G sensor
2 PWR_LED_SC# 38 CLKRUN#/GPIO1D
68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <24>
C509 70 EN_FAN1 +3VALW
EN_DFAN1/DA1/GPIO3D EN_FAN1 <5>
0.1U_0402_16V4Z DA Output 71 IREF
1 IREF/DA2/GPIO3E IREF <46>
KSI0 55 72
<37> KSI0 KSI0/GPIO30 DA3/GPIO3F BT_OFF# <32>
KSI1 56
KSI2 KSI1/GPIO31 EC_MUTE# 1 +5VS
57 KSI2/GPIO32 2
+3VS KSI3 58 83 R300 @ 10K_0402_5%
<37> KSI3 KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <31>
KSI4 59 84 USB_ON USB_ON 2 1 TP_CLK 1 2
<37> KSI4 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON <43>
KSI5 60 85 10K_0402_5% R291 R299 4.7K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C TP_DATA
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 TP_LED# <38> 1 2
2

KSO[0..15] KSI7 62 87 TP_CLK R298 4.7K_0402_5%

<37> KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <37>
R716 R717 KSO0 39 88 TP_DATA
KSI[0..7] KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <37>
100_0402_5% 100_0402_5% KSO1 40
ENE@ ENE@ <37> KSI[0..7] KSO2 KSO1/GPIO21 @
41 KSO2/GPIO22 KB925 SPI STRAP PIN
EC_SMB_CK1 KSO3 42 97 R325 1 2 4.7K_0402_5%
1

KSO4 43
KSO3/GPIO23 SDICS#/GPXOA00
98 unpoped for C0 version
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL <33>
ESB_CK EC_SMB_DA1 KSO5 UMA_DIS
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 11/16
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 CMOS_OFF# <40>
2

ESB_DA KSO7 46 SPI Device Interface

R718 R719 KSO8 KSO7/GPIO27 +3VALW +3VS
47 KSO8/GPIO28 Analog Board ID definition,
4.7K_0402_5% 4.7K_0402_5% KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <38> Please see page 3.
@ @ KSO10 49 120 FWR#SPI_SI
KSO10/GPIO2A SPIDO/WR# FWR#SPI_SI <38>
2

2
KSO11 50 SPI Flash ROM 126 SPI_CLK
SPI_CLK <38>
1

R609 R608 KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# R583 R616

51 KSO12/GPIO2C SPICS# 128 FSEL#SPICS# <38>
4.7K_0402_5% 4.7K_0402_5% 2 2 KSO13 52 10K_0402_5% 10K_0402_5%
@ @ KSO14 KSO13/GPIO2D +3VALW +3VALW +3VALW
<37> KSO14 53 KSO14/GPIO2E
C793 C794 KSO15 54 73
<37> KSO15
1

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z KSO16 KSO15/GPIO2F CIR_RX/GPIO40 I2C_INTE I2C_INTE
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 I2C_INT <41>

2
@ 1 1 @ KSO17 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG <46>
2 2 L47 MBC1608121YZF_0603 90 CHARGE_LED0# @ R342 GM@ R330 R308
BATT_CHGI_LED#/GPIO52 CHARGE_LED0# <38>
L48 MBC1608121YZF_0603 91 CAPS_LED# 10K_0402_1% 10K_0402_1% 100K_0402_1%
CAPS_LED#/GPIO53 CAPS_LED# <38>
C790 C791 EC_SMB_CK1 1 2 77 GPIO 92 CHARGE_LED1#
<45> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CHARGE_LED1# <38>
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW EC_SMB_DA1 1 2 78 93
<45> EC_SMB_DA1 PWR_LED# <38>

1
@ 1 1 @ EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON
<5,16,41> EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON <40,42,48>
EC_SMB_DA2 80 121 Vab MODULE_ID Vab UMA_DIS BRD_ID
<5,16,41> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <51>
2

127 ACIN
AC_IN/GPIO59 ACIN <28,44>

2
R404 1
10K_0402_5% R341 PM@ R329 R321 C442
6 100 0_0402_5% 0_0402_5% @ 100K_0402_1%
<28> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <28>

0.1U_0402_16V4Z
14 101 EC_LID_OUT#
<28> SLP_S5# EC_LID_OUT# <28>
1

EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON 2

1 2 <28> EC_SMI# 15 102 EC_ON <41,46>

1
<33> LAN_WAKE# R421 0_0402_5% LID_SW# EC_SMI#/GPIO08 EC_ON/GPXO05 MODULE_ID D12 RB751V_SOD323
<41> LID_SW# 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103
ESB_CK 17 104 ICH_POK_EC 1 2 ICH_POK
<41> ESB_CK SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK <8,28>
ESB_DA 18 GPO 105 BKOFF#
<41> ESB_DA PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <24>
1 2 EC_PME# 19 GPIO 106 1 2 1 2 +3VS
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <32>
@R422
@ R422 0_0402_5% 25 107 R340 0_0402_5% R339 10K_0402_5%
<43> KILL_SW# FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 @
<5> FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 SCROLL_LED# <38>
S

<26> PCI_PME# 3 1 29 FANFB2/GPIO15

EC_TX_P80_DATA 30
<14,15,37> EC_TX_P80_DATA EC_TX/GPIO16
@ Q31 EC_RX_P80_CLK 31 110 SLP_S4# <28> UMA_DIS Vab
<14,15,37> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1
G

2N7002_SOT23 <41> ON/OFF# 32 112 ENBKL <24>

2

+3VALW ON_OFF/GPIO18 ENBKL/GPXID2

34 PWR_LED#/GPIO19 GPXID3 114 EAPD <30> H UMA
36 GPI 115 EC_THERM#
<38> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <28>
116 SUSP# L VGA
GPXID5 SUSP# <30,40,41,42,46,48,49,50>
117 PBTN_OUT#
GPXID6 PBTN_OUT# <28>
GPXID7 118
+3VALW XCLKI 122
XCLKO XCLK1 no used at B-test
123 XCLK0 V18R 124
AGND

1 2 FRD#SPI_SO
GND
GND
GND
GND
GND

@ R379 100K_0402_1% 1
1 2 FSEL#SPICS#
@ R399 100K_0402_1% KB926QFA1_LQFP128 C511
11
24
35
94
113

69

4.7U_0805_10V4Z
KSO17 2
1 2
ECAGND

@ R292 10K_0402_5% ENE

suggesttion Module ID
+5VALW
at C0 ID BRD ID
XCLKO 1 R393 revision 1 0 R54/42(Rb) Vab
2 XCLKI
EC_SMB_CK1 @ 20M_0603_5% J J 0 R01 (EVT)
1
R294
2
6.8K_0402_5% I I
0 0V
EC_SMB_DA1 T W 1 R02 (DVT)
1
R293
2
6.8K_0402_5% R A
8.2K 0.25V
1 1 2 R03 (PVT) 18K 0.50V
R A
2 2 3 R10A (MP) 33K 0.82V
2 2 J 4 R01 (EVT) 56K 1.19V
I
1

C514 C501 W 5 R02 (DVT)

15P_0402_50V8J 15P_0402_50V8J A
100K 1.65V
IN

OUT

1 1
3 6 R03 (PVT) 200K 2.20V
A
+3VS 4 7 R10A (MP) NC 3.30V
NC

NC

EC_SMB_CK2
1
R258
2
4.7K_0402_5%
R537/541(Ra)=100K Ohm
2

1 2 EC_SMB_DA2
R259 4.7K_0402_5% 1 1
C416 C415

@ 100P_0402_50V8J @ 100P_0402_50V8J
X1 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
32.768KHZ_12.5P_1TJS125BJ2A251
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom JIWA3/A4_LA4212P 1.0
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 20, 2008 Sheet 35 of 53
gratuito - free of charge.
 5 4 3 2 1

+3VS CARD@ +3VS_CARD +1.8VS +1.8VS_CARD

R642
1 R670 2 2 1
0_0603_5%
0_0805_5% @ +CR1_POWER

+3VS_CARD +3VS_CARD +CR1_POWER 1 R626 2 0_0402_5%

D @ D
JREAD1
1

33 XD-VCC SD-VCC 23
1K_0402_1%
R627
Need check CLK GEN & MDIO0 @1 R671 2 0_0402_5% 8 24 MDIO5
XD-D0 SD-CLK
@ SB select pin & page MDIO1 @1 R672 2 0_0402_5% 9 XD-D1 4 IN 1 CONN SD-DAT0 25 MDIO0
MDIO2 @1 R673 2 0_0402_5% 26 29 MDIO1
2

XD-D2 SD-DAT1

3
S
U39 MDIO3 @1 R675 2 0_0402_5% 27 10 MDIO2
G
Q34 MDIO8 @1 R676 0_0402_5% XD-D3 SD-DAT2 MDIO3
2 2 28 XD-D4 SD-DAT3 11
CR1_PCTLN AO3413_SOT23-3 CLK_PCIE_CARD# 3 5 +1.8VS_CARD MDIO9 @1 R677 2 0_0402_5% 30
<22> CLK_PCIE_CARD# APCLKN APVDD XD-D5
D
@ CLK_PCIE_CARD 4 10 MDIO10 @1 R678 2 0_0402_5% 31
<22> CLK_PCIE_CARD
1
APCLKP APV18 MDIO11 @1 R674 0_0402_5% XD-D6
1 TAV33 30 +3VS_CARD 2 32 XD-D7
PCIE_TXN1 9
<28> PCIE_TXN1 APRXN
C755 PCIE_TXP1 8 19 +3VS_CARD MDIO4 @1 R679 2 0_0402_5% 6 12 MDIO4
<28> PCIE_TXP1 APRXP DV33 XD-WE SD-CMD
@ CARD@ 20 MDIO6 @1 R680 2 0_0402_5% 7 36 CR1_CD0N
2 0.1U_0402_16V4Z PCIE_RXN1C756 DV33 XD-WP SD-CD-SW
<28> PCIE_RXN1 2 1 0.1U_0402_10V7K PCIE_C_RXN1 11 APTXN DV33 44 MDIO14 @1 R681 2 0_0402_5% 5 XD-ALE SD-WP-SW 35 MDIO6
<28> PCIE_RXP1 PCIE_RXP1C757 2 1 0.1U_0402_10V7K PCIE_C_RXP1 12 18 +1.8VS_CARD XDCD# @1 R682 2 0_0402_5% 34
CARD@ APTXP DV18 MDIO13 @1 R683 0_0402_5% XD-CD-SW
DV18 37 2 1 XD-R/B MS-VCC 14
1 R628 2 PREXT 7 MDIO12 @1 R684 2 0_0402_5% 2 15 MDIO5
+3VS_CARD CARD@ 8.2K_0402_5% APREXT MDIO0 MDIO5 @1 R685 0_0402_5% XD-RE MS-SCLK MDIO0
MDIO0 48 2 3 XD-CE MS-DATA0 19
MDIO1 MDIO7 @1 R686 0_0402_5% MDIO1
Reserve circuit for new version MDIO1 47 2 4 XD-CLE MS-DATA1 20

1
1 R633 2 1K_0402_5% 38 PCIES_EN MDIO2 46 MDIO2
MS-DATA2 18 MDIO2
not ready & debugging CARD@ 1 T102 39 PCIES JMB385 MDIO3 45 MDIO3
MS-DATA3 16 MDIO3 1K_0402_1%1K_0402_1%
43 MDIO4 17 CR1_CD1N R654 R655
C762 MDIO4 MDIO5_C 1 R705 MS-INS
MDIO5 42 2 22_0402_5% MDIO5
MS-BS 21 MDIO4 @ @
@ 41 MDIO6 CARD@

2
+3VS_CARD 2 0.1U_0402_16V4Z MDIO6 MDIO7
MDIO7 40
29 MDIO8 13 37
CARD@ <8,16,26,32,33,40> PLT_RST# PLT_RST# MDIO8 MDIO9 4IN1-GND GROUND
1 XRSTN MDIO9 28 GROUND 38
1 R629 2 4.7K_0402_5% CR1_CD0N GND 2 XTEST MDIO10 27 MDIO10 22 4IN1-GND
CARD@ 26 MDIO11 1 1
MDIO11
1 R630 2 4.7K_0402_5% CR1_CD1N
MDIO12 25 MDIO12
C T103 13 23 MDIO13 T-SOL_144-3000000900_NR C780 C781 C
T104 SEEDAT MDIO13 MDIO14 ME@ @ @
14 SEECLK MDIO14 22 D24 2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
CR1_CD1N 2
JMB385 Operation Modes CR1_CD1N 15
NC 34
35 1 XDCD#
close to close to
CR1_CD1N NC
Normal CR1_CD0N 16 CR1_CD0N NC 36 CR1_CD0N 3 JREAD1.24 JREAD1.15
1
XTEST 0 6 GND C758
CR1_PCTLN APGND DAN202UT106_SC70-3
17 CR1_PCTLN
CR1_CD0N X 24 @ @ 270P_0402_50V7K
GND 2
GND 31
CR1_CD1N X T105 21 32
CR1_LEDN GND
GND 33

JMB385-LGEZ0A_LQFP48_7X7
SD,MMC,MS,XD muti-function pin define
+CR1_POWER MDIO
CARD@ SD Card MMC Card MS Card XD Card
CARD@ PIN Name PIN Name PIN Name PIN Name PIN Name
1 R631 2 10K_0402_5% MDIO6 MDIO00 SD_DAT0 MMC_DAT0 MS_DAT0 XD_DAT0
CARD@
1 R632 2 10K_0402_5% MDIO13 MDIO01 SD_DAT1 MMC_DAT1 MS_DAT1 XD_DAT1
MDIO02 SD_DAT2 MMC_DAT2 MS_DAT2 XD_DAT2
MDIO03 SD_DAT3 MMC_DAT3 MS_DAT3 XD_DAT3
MDIO04 SD_CMD MMC_CMD MS_BS XD_WE#
+1.8VS_CARD
B
MDIO05 SDCLK1 MMCCLK MSCCLK XD_CE# B
MDIO06 SD_WP# MMC_WP# XD_WP#
+3VS_CARD
MDIO07 XD_CLE
1 1 CARD@ Close to PIN5
CARD@ C759 0.1U_0402_16V4Z MDIO08 MMC_DAT4 MS_DAT4 XD_DAT4
1 R634 2 10K_0402_1% MDIO7 CARD@ 1 C760 1
CARD@ 10U_0805_10V4Z CARD@ CARD@ MDIO09 MMC_DAT5 MS_DAT5 XD_DAT5
MDIO12 2 2
1 R635 2 200K_0402_1% C763 C761
CARD@ 0.1U_0402_16V4Z 1000P_0402_50V7K MDIO10 MMC_DAT6 MS_DAT6 XD_DAT6
2 2
1 R636 2 200K_0402_1% MDIO14
MDIO11 MMC_DAT7 MS_DAT7 XD_DAT7
MDIO12 XD_RE#
MDIO13 XD_R/B#
MDIO14 XD_ALE
CARD@ +CR1_POWER
CR1_PCTLN 1 R637 2 CR1_POWER +1.8VS_CARD +3VS_CARD

0_0805_5%
1 1
CARD@ CARD@
C764 C765 Cardreader contactor not support MMC & MS
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 C766
1 1
C767 C768
1 1
C769
1
C782
Bit 4~7
CARD@ CARD@ CARD@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2
0.1U_0402_16V4Z
A @ @ A

Use 0805 type and over

20 mils trace width on
both side

Card Reader power circuit

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4 in 1 Card
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JIWA3/A4_LA4212P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 36 of 53
5 4 3 2 1

hexainf@hotmail.com
gratuito - free of charge.
 5 4 3 2 1

INT_KBD Conn. To TP/B Conn. EC DEBUG PORT

KSI[0..7]
KSI[0..7] <35>
D D
KSO[0..15]
KSO[0..15] <35>
JP4
+5VS +3VALW 1 1
JP5 EC_TX_P80_DATA 2
<14,15,35> EC_TX_P80_DATA 2
1 EC_RX_P80_CLK 3
1 <14,15,35> EC_RX_P80_CLK 3
TP_CLK 2 4
<35> TP_CLK 2 4
TP_DATA 3
<35> TP_DATA 3
JP6 SW/L 4 ACES_85205-0400
KSO2 C396 1 4
2 @ 100P_0402_50V8J KSO1 C401 1 2 @ 100P_0402_50V8J KSI1 1 1
SW/R 5 5 ME@
KSI7 2 6
KSO15 C334 1 2 6
2 @ 100P_0402_50V8J KSO7 C398 1 2 @ 100P_0402_50V8J KSI6 3 3 7 GND
KSO9 4 8
KSO6 C400 1 4 GND
2 @ 100P_0402_50V8J KSI2 C392 1 2 @ 100P_0402_50V8J KSI4 5 5
KSI5 6 ACES_85201-06051
KSO8 C399 1 6
2 @ 100P_0402_50V8J KSO5 C394 1 2 @ 100P_0402_50V8J KSO0 7 7
KSI2 8 ME@
KSO13 C330 1 8
2 @ 100P_0402_50V8J KSI3 C393 1 2 @ 100P_0402_50V8J KSI3 9 9
KSO5 10 +5VS TP_DATA C327 1 2 @ 100P_0402_50V8J
KSO12 C329 1 10
2 @ 100P_0402_50V8J KSO14C331 1 2 @ 100P_0402_50V8J KSO1 11 11
KSI0 12 TP_CLK C326 1 2 @ 100P_0402_50V8J
KSO11 C332 1 12
2 @ 100P_0402_50V8J KSI7 C377 1 2 @ 100P_0402_50V8J KSO2 13 13
C245
KSO4 14
KSO10 C333 1 14
2 @ 100P_0402_50V8J KSI6 C378 1 2 @ 100P_0402_50V8J KSO7 15 15
0.1U_0402_16V4Z
KSO8 16
KSO3 C328 1 16
2 @ 100P_0402_50V8J KSI5 C381 1 2 @ 100P_0402_50V8J KSO6 17 17
KSO3 18
KSO4 C397 1 18
2 @ 100P_0402_50V8J KSI4 C380 1 2 @ 100P_0402_50V8J KSO12 19 19
KSO13 20 TP_CLK TP_DATA
KSI0 C395 1 20
C 2 @ 100P_0402_50V8J KSO9 C379 1 2 @ 100P_0402_50V8J KSO14 21 21
C
KSO11 22
KSO0 C382 1 22
2 @ 100P_0402_50V8J KSI1 C376 1 2 @ 100P_0402_50V8J KSO10 23 23

2
KSO15 24 24 D31
ACES_85202-2405 PJDLC05_SOT23-3

1
6
5
2 4
SW/L
1 3

SW3
FOR LPC SIO DEBUG PORT EVQPLHA15_4P
B B
JP11

6
5
1 1 +5VS
2 2 2 4
3 +3VS SW/R
3
4 4 1 3
5 5
6 6 CLK_14M_SIO <22> SW4
7 LPC_AD0
7 LPC_AD0 <27,35> EVQPLHA15_4P
8 LPC_AD1
8 LPC_AD1 <27,35>
9 LPC_AD2
9 LPC_AD2 <27,35>
10 LPC_AD3
10 LPC_AD3 <27,35>
11 LPC_FRAME#
11 LPC_FRAME# <27,35>
12 LPC_DRQ0#
12 LPC_DRQ0# <27>
13 PCI_RST#
13 PCI_RST# <26,35>
14 14 2 1
15 CLK_PCI_DB CLK_PCI_DB <22> R458 10K_0402_5%
15 SERIRQ
16 16 SERIRQ <28,35> @
17 17
18 18
19 19
20 20

ACES_85201-2005
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge. 5 4 3 2

Date: Monday, May 12, 2008 Sheet
1
37 of 53
 FOR EC 8M SPI ROM
+3VALW

+3VS
1
C566 20mils
0.1U_0402_16V4Z 1
2
C743 @
0.1U_0402_16V4Z
2

U22
FSEL#SPICS#
R437 2 15_0402_5%
1 SPI_CS# 1 8 R603 @ 15_0402_5% U35
<35> FSEL#SPICS# CS# VCC
FRD#SPI_SO 1 2 SPI_SO 2 7 33_0402_5% R465 2 @ 1 SPI_CS#_SB 1 8
<35> FRD#SPI_SO SO HOLD# <28> FSEL#SPICS#_SB CS# VCC
15_0402_5% R431 3 6 SPI_CLK_R1 2 SPI_CLK 1 2 SPI_SO_SB 2 7
WP# SCLK SPI_CLK <35> <28> FRD#SPI_SO_SB SO HOLD#
4 5 SPI_SI 1 2 FWR#SPI_SI 15_0402_5% R605 3 6 SPI_CLK_SB
GND SI FWR#SPI_SI <35> WP# SCLK SPI_CLK_SB <28>
4 5 SPI_SI_SB 1 @ 2
GND SI FWR#SPI_SI_SB <28>
MX25L1605AM2C-12G SO8 ROM 33_0402_5% R467 15_0402_5% R606
MX25L512AMC-12G_SO8
@

SPI_CLK_R
JP12

1
SPI_CS# 1 2 +3VALW R106
SPI_SO 1 2 FD6 FD4 FD5 FD2 FD3 FD1
3 3 4 4 33_0402_5%
+3VALW 5 5 6 6 2 R466 1 SPI_CLK 1 1 1 1 1 1
7 8 SPI_SI 15_0402_5%

2
7 8
@
E&T_2941-G08N-00E~D 1
ME@
C573
22P_0402_50V8J
2
H1 H3 H21 H22
HOLEA HOLEA HOLEA HOLEA

1
LED
H23 H24 H20 H7 H10 H18 H16 H19
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

+5VS 1 2 2 1 LED1 TP_LED# <35>

R585 1.27K_0402_1%

1
19-215SUBC/S280/TR8 0603 BLUE

H14 H13 H12 H8 H5 H9 H27 H28

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
JP24 H2 H4 H6 H26 H25
+5VALW 1 HOLEA HOLEA HOLEA HOLEA HOLEA
BT_LED# 1
<32> BT_LED# 2 2
WLAN_LED# 3
<32> WLAN_LED# 3
4

1
CHARGE_LED1# 4
<35> CHARGE_LED1# 5 5
CHARGE_LED0# 6
<35> CHARGE_LED0# 6
PWR_LED# 7
<35> PWR_LED# 7
+5VS 8 8
9 GND
10 GND
ACES_85201-08051~N

JP25
+5VS 1 1
SCROLL_LED# 2
<35> SCROLL_LED# 2
CAPS_LED# 3
<35> CAPS_LED# 3
NUM_LED# 4
<35> NUM_LED# 4
DRIVE_LED# 5
<39> DRIVE_LED# 5
6 6
7 GND
8 GND
ACES_85201-06051

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B JIWA3/A4_LA4212P 1.0
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 14, 2008 Sheet 38 of 53
gratuito - free of charge.
 A B C D E F G H

+5VS +3VS

1 1 1 1 1 1
C316
1 C274 C462 C298 C461 C469 0.1U_0402_16V4Z 1
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2 2 @

SATA HDD Conn. SATA ODD Conn.

JP15
JP18
1 GND 1 GND
<27> SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 2 <27> SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 2
SATA_ITX_DRX_N0 A+ SATA_ITX_DRX_N1 A+
<27> SATA_ITX_DRX_N0 3 A- <27> SATA_ITX_DRX_N1 3 A-
4 GND 4 GND
2 SATA_DTX_C_IRX_N0 SATA_DTX_IRX_N0 SATA_DTX_C_IRX_N1 SATA_DTX_IRX_N1 2
<27> SATA_DTX_C_IRX_N0 1 2 5 B- <27> SATA_DTX_C_IRX_N1 1 2 5 B-
C684 0.01U_0402_16V7K 6 C676 0.01U_0402_16V7K 6
SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 B+ SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1 B+
<27> SATA_DTX_C_IRX_P0 1 2 7 GND <27> SATA_DTX_C_IRX_P1 1 2 7 GND
C685 0.01U_0402_16V7K C675 0.01U_0402_16V7K

8 VCC3.3 8 DP
+3VS 9 VCC3.3 +5VS 9 +5V
10 VCC3.3 10 +5V
11 GND 11 MD
12 GND 12 GND
13 GND 13 GND
14 VCC5
15 OCTEK_SLS-13SB1G
+5VS VCC5
16 VCC5
17 GND
18 ME@
RESERVED
19 GND
20 VCC12
21 VCC12
22 VCC12
23 G1
24 G2
OCTEK_SAT-22SB1G_RV

ME@

3 3

D20 RB751V_SOD323
1 2 DRIVE_LED#
<27> SATA_LED# DRIVE_LED# <38>

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge.

A B C D E F
Date:
G
Monday, May 12, 2008 Sheet 39
H
of 53
 A B C D E

+1.5VS_CARD1
Imax = 0.75A
New Card Socket (Left/TOP)
1 1
Express Card Power Switch C467 C489 JEXP1
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
+1.5VS U16 1 GND
+1.5VS_CARD1 40mil <28> USB20_N10 2 USB_D-
2 1 12 1.5Vin 1.5Vout 11 <28> USB20_P10 3 USB_D+
1 C482 0.1U_0402_16V4Z CPUSB# 1
14 1.5Vin 1.5Vout 13 4 CPUSB#
+3VS 5 RSV
+3VS_CARD1 60mils +3VS_CARD1
6 RSV
2 1 2 3.3Vin 3.3Vout 3 <22,28,32> ICH_SMBCLK 7 SMB_CLK
C483 0.1U_0402_16V4Z 4 5 Imax = 1.35A <22,28,32> ICH_SMBDATA 8
3.3Vin 3.3Vout SMB_DATA
+3VALW +3VALW_CARD1 40mil +1.5VS_CARD1 9 +1.5V
2 1 17 AUX_IN AUX_OUT 15 10 +1.5V
C500 0.1U_0402_16V4Z 1 1 <28,32,33> ICH_PCIE_WAKE# 11
PLT_RST# WAKE#
<8,16,26,32,33,36> PLT_RST# 6 SYSRST# OC# 19 +3VALW_CARD1 12 +3.3VAUX
C468 C488 PERST# 13
SYSON PERST# 10U_0805_10V4Z 0.1U_0402_16V4Z PERST#
<35,42,48> SYSON 20 SHDN# PERST# 8 +3VS_CARD1 14 +3.3V
2 2
15 +3.3V
SUSP# 1 16 16
<30,35,41,42,46,48,49,50> SUSP# STBY# NC <22> EXP_CLKREQ# CLKREQ#
CPUSB# 17 CPPE#
+3VALW 2 R337 1 @ 100K_0402_5% 10 CPPE# GND 7 <22> CLK_PCIE_EXP# 18 REFCLK-
<22> CLK_PCIE_EXP 19 REFCLK+
CPUSB# 9 20
<28> CPUSB# CPUSB# GND
<28> PCIE_RXN4 21 PERn0
18 +3VALW_CARD1 22
RCLKEN <28> PCIE_RXP4 PERp0
Imax = 0.275A 23 GND
R5538_QFN20 <28> PCIE_TXN4 24 PETn0
<28> PCIE_TXP4 25 PETp0
1 1 26 GND
C495 C499 27
10U_0805_10V4Z 0.1U_0402_16V4Z GND
28 GND
@ 2 2
FOX_1CH4110C_LT
ME@

(NEW)
2 2

CMOS Camera Conn

+5VS
C784

S
0.1U_0402_16V4Z

D
3 1
3 3
1
SI2301BDS-T1-E3_SOT23-3
Q35

G
2
1

2
R660
10K_0402_5% R661
0_0603_5%
1 2

CMOS1

1
JP1
1
OUT

USB20_N2 1
<28> USB20_N2 2 2
<28> USB20_P2 USB20_P2 3 3
<35> CMOS_OFF# 2 IN 4 4
Q36 1 5
GND

DTC124EKAT146_SC59-3 5
6 GND1
C785 7
10U_0805_10V4Z GND2
3

2 ACES_88266-05001

ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & CMOS Connector
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B JIWA3/A4_LA4212P 1.0

gratuito - free of charge. A B C D

Date: Monday, May 12, 2008
E
Sheet 40 of 53
 +3VS

Switch Board Conn.

1
R724
Power Button CY@
0_0603_5%

SW1 @ JP3

2
ON/OFFBTN# 1
NOVO_BTN# 1
1 3 2 2
FB1 3
FB2 3
2 4 4 4
+3VALW EC_SMB_CK2_C 5
SMT1-05_4P EC_SMB_DA2_C 5
6

6
5
I2C_INT_C 6
7
ON/OFF switch TOP Side 8
7
8

2
2 1 9 GND
J1 @ JOPEN R720 R721 10
R242 4.7K_0402_5% GND
2 1 4.7K_0402_5%
J2 @ JOPEN 100K_0402_5% @ @ ACES_85201-08051
Bottom Side D5
ME@

2
3 ON/OFF# ON/OFFBTN# R662 R663
ON/OFF# <35>
ON/OFFBTN# 1 NOVO_BTN# 2 2 0_0603_5% 0_0603_5%
2 51_ON# I2C_INT_C
51_ON# <44> GNDS
C795 C796

1
+3VALW 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2

1
DAN202UT106_SC70-3 @ 1 1 @
2
D6 C809 C810 C811
1

C411 RLZ20A_LL34 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
R243 1000P_0402_50V7K @ 1 1 @ 1 @
4.7K_0402_5% Q24 1

OUT

2
DTC124EKAT146_SC59-3
2

EC_ON 1 2 2
<35,46> EC_ON
R244 33K_0402_5% IN L45 CY@ 1 2 MBC1608121YZF_0603 1 2

GND
<5,16,35> EC_SMB_CK2
R620 CY@ 0_0402_5% EC_SMB_CK2_C
<35,37> KSI4
<35> ESB_CK 1ENE@ 2
L46 CY@ 1 2 MBC1608121YZF_0603 R638 1 2 0_0402_5%
<5,16,35> EC_SMB_DA2

3
R622 CY@ 0_0402_5% EC_SMB_DA2_C
<35,37> KSO14
<35> ESB_DA 1ENE@ 2
1

D R639 1
<35> I2C_INT 2 0_0402_5%
2 R624 0_0402_5% I2C_INT_C
<35,37> KSO15
G
<35,37> KSI0
S Q19 +3V FB1
3

2N7002_SOT23-3
<35,37> KSI3
+3V FB2

EXT_MIC_L 1 2 EXT_MIC_L-2
<30> EXT_MIC_L
L25
FBM-11-160808-700T_0603
1 1
C503 C494
47P_0402_50V8J 220P_0402_50V8J
Lid Switch 2 2
Audio Jack
GNDA GNDA

EXT_MIC_R 1 2 EXT_MIC_R-2
<30> EXT_MIC_R
L26
+VCC_LID R429 1 2 100K_0402_5% FBM-11-160808-700T_0603
+3VALW 1
R432
2
0_0402_5% 1 @ 1
MIC IN
2

A3212ELHLT-T_SOT23W-3 C508 @ C518 JMIC1

@ 47P_0402_50V8J 220P_0402_50V8J 1
VDD

2 2
2
1 6
3 GNDA GNDA 3
OUTPUT LID_SW# <35>
C561
0.1U_0402_16V4Z 2 JACK_PLUG_MIC 4
GND

2 <30> JACK_PLUG_MIC
C547 1 GNDA5
U19 10P_0402_50V8J
1

1 C522 SINGA_2SJ-S351-012
ME@
2
GNDA

220P_0402_50V8J

+3VALW 220P_0402_50V8J 220P_0402_50V8J

1 1
C568 Headphone
2

1
C564
R314 2 2
@ R445 @ R452
100K_0402_5% 1K_0402_5% 1K_0402_5%
D9
1

2
GNDA
NOVO# 2
<35> NOVO#
1 NOVO_BTN# JHP1
51_ON# 3 1
<44> 51_ON#
<30> HP_L L28 1 2 PL-OUT 2
FBM-11-160808-700T_0603 6
DAN202UT106_SC70-3 L29 1 PR-OUT
<30> HP_R 2 3
FBM-11-160808-700T_0603
<30> JACK_PLUG_HP 4

SINGA_2SJ-S351-013

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Jack & SW connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B JIWA3/A4_LA4212P 1.0
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 41 of 53
gratuito - free of charge.
 A B C D E

1 1

+5VALW TO +5VS
+3VALW TO +3VS +1.8V to +1.8VS
+5VALW +5VS
+3VALW +3VS +1.8V +1.8VS
U23
8 1 U20 U9 PM@
D S
7 D S 2 8 D S 1 8 D S 1

2
10U_0805_10V4Z

1U_0603_10V4Z
6 D S 3 1 1 7 D S 2 7 D S 2 1 1

2
1 1 5 4 C580 C578 R468 6 3 1 1 6 3 C345 C360
D G D S D S

10U_0805_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
C575 C577 1 1 5 4 C563 C554 R418 1 1 5 4 PM@ PM@ R207
D G D G

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
SI4800BDY-T1-E3_SO8 470_0603_5% C539 C559 C365 C383 PM@
10U_0805_10V4Z 10U_0805_10V4Z 2 2 SI4800BDY-T1-E3_SO8 470_0603_5% PM@ PM@ SI4800BDY-T1-E3_SO8 2 2 470_0603_5%

1
2 2 2 2

1 1

1
2 2 2 2

1
D D

1
D
2 SUSP 2 SUSP
G G 2 SUSP
+VSB 5VS_GATE S Q33 S Q30 G

3
R226 2N7002_SOT23 2N7002_SOT23 S Q13 PM@

3
20K_0402_5% 1 2N7002_SOT23
1

D C581
SUSP 2 R416 @ R222
Q14G 0.1U_0603_50V4Z 47K_0402_5% 100K_0402_5%
2N7002_SOT23 2 5VS_GATE 1.8VS_GATE 5VS_GATE
S +VSB 1 2 1 2 +VSB
3

R450 R220 PM@ @

2 47K_0402_5% 1 100K_0402_5% 1 1 2

1
D C572 C389 C386

1
SUSP D @ PM@ 0.1U_0603_50V4Z
2
Q32 G 0.1U_0603_50V4Z SUSP 2
2N7002_SOT23 S 2 G 2 2

3
Q15 PM@ S 0.1U_0603_50V4Z

3
2N7002_SOT23

RTCVREF +5VALW +5VALW

2
+1.5VS +VCCP +0.9VS +1.8V
R234 R238 R237
10K_0402_5% 100K_0402_5% 100K_0402_5%
2

2
@
R283 R68 R165 R236

1
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% SUSP
<50> SUSP
SYSON#
SYSON#
1

1
D D
2 Q22 SYSON 2 Q21
<30,35,40,41,46,48,49,50> SUSP# <35,40,48> SYSON
1

1
D D D D G 2N7002_SOT23 G 2N7002_SOT23
3 3
2 SUSP 2 SUSP 2 SUSP 2 SYSON# S S

3
1

1
G G G G
S Q25 S Q10 S Q12 S Q20 R249 R248
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 100K_0402_5% 100K_0402_5%

2
+5VALW +5VS

1 1 1 1 1 1
C799 C800 C801 C802 C804 C805

0.01U_0402_16V7K 0.01U_0402_16V7K 470P_0402_50V7K 470P_0402_50V7K 0.01U_0402_16V7K 470P_0402_50V7K

2 2 2 2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JIWA3/A4_LA4212P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 42 of 53
A B C D E

hexainf@hotmail.com
gratuito - free of charge.
 A B C D E

+5VALW
LIFT USB CONN. 1 LIFT USB CONN. 2
+USB_VCCA
C803 470P_0402_50V7K
2 1 +USB_VCCA
+USB_VCCA
U13 +USB_VCCA
W=80mils W=80mils
1 GND OUT 8 1
1 C694 0.1U_0402_16V4Z 2 7 1 1 1
IN OUT + C691 C688 C754
2 1 3 IN OUT 6
<35> USB_ON USB_ON 4 5
EN# OC# USB_OC#0 <28>
150U_D2_6.3VM 470P_0402_50V7K 470P_0402_50V7K
G545A1P1U_SO8 2 2 2
USB_OC#1 <28>
JUSB1 JUSB2
1 1 VCC 1 VCC
C428 USB20_N0 2 USB20_N1 2
<28> USB20_N0 D- <28> USB20_N1 D-
@ 1000P_0402_50V7K USB20_P0 3 USB20_P1 3
<28> USB20_P0 D+ <28> USB20_P1 D+
4 GND 4 GND
2
5 GND1 5 GND1
6 GND2 6 GND2
7 GND3 7 GND3
8 GND4 8 GND4
SUYIN_020173MR004G579ZR SUYIN_020173MR004G579ZR
ME@ ME@

+3VALW

Kill Switch

2
R706
2 100K_0402_5% 2
+3VS
R581@ SW2

1
2 1 3 3
100K_0402_5%
<35> KILL_SW# 2 2
KILL_SW#
1 1

1BS003-1211L_3P

+5VALW +USB_VCCC
U31
1 GND OUT 8
2 7
3
1
3
4
IN
IN
OUT
OUT 6
5 RIGHT USB CONN. 3 RIGHT USB CONN.4 3
EN# OC# USB_OC#11 <28> +USB_VCCC
C693
G545A1P1U_SO8 +USB_VCCC
1 USB_OC#4 <28>
4.7U_0805_10V4Z C690
2
0.1U_0402_16V4Z
W=80mils
@ 2 @ W=80mils
<35> USB_ON 1
1 C786
C726
470P_0402_50V7K
470P_0402_50V7K 2
2 JUSB4
+USB_VCCC JUSB3 1
+USB_VCCC USB20_N4 1
1 1 <28> USB20_N4 2 2
+USB_VCCC USB20_N11 2 USB20_P4 3
<28> USB20_N11 2 <28> USB20_P4 3
1 USB20_P11 3 4
<28> USB20_P11 3 4
1 +USB_VCCC 4 5
+ 4 GND
1 5 GND 6 GND
C711 C716 @ 6 7
150U_D2_6.3VM 470P_0402_50V7K C697 GND GND
7 GND 8 GND
2 2 470P_0402_50V7K 8 GND
2 SUYIN_020173MR004S558ZL
SUYIN_020173MR004S558ZL
ME@
ME@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JIWA3/A4_LA4212P 1.0

gratuito - free of charge. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 14, 2008 Sheet 43 of 53
A B C D E
 A B C D

VIN
PF1 PL6 ACIN BATT ONLY
JDCIN @ 7A_24VDC_429007.WRML SMB3025500YA_2P
@ 4602-Q04C-09R 4P P2.5 1 2 1 2
Precharge detector Precharge detector
PJ9
Min. typ. Max. Min. typ. Max.
4 4 2 2 1 1
H-->L 13.843V 14.247V 14.636V H-->L 6.138V 6.214V 6.359V

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
0.01U_0402_50V7K

0.01U_0402_50V7K
@ JUMP_43X118
3 3
L-->H 14.936V 15.381V 15.814V L-->H 7.196V 7.349V 7.505V

1
1 1

2 2

2
PC53

PC167

PC54

PC50

PC168

PC52
1 1

PR69
1K_1206_5%
DC030006J00 1 2

PR70
1K_1206_5% PQ16
VIN 2 1 1 2 3 TP0610K-T1-E3_SOT23-3
1

PD3 PR71
RLS4148_LL34-2 1K_1206_5%
Vin Detector 1 2

100K_0402_5%

100K_0402_5%
VS 2 1

1
PR72

PR76

PR77
PD4 1K_1206_5%

2
High 18.135 17.566 17.011 @ RLS4148_LL34-2 1 2

Low 14.866 14.355 14.063

100K_0402_5%
1
PR79
1
PQ14
PR85 PC60 DTC115EUA_SC70-3

1 2
2
@ 10K_0402_1% @ 0.01U_0402_25V7K 2

1 2 1 2 2
VIN <33,40> ACOFF
PR83
VIN 1M_0402_1%
1 2 2
B+

3
10K_0805_5%
1
82.5K_0402_1%
1

VS
PR88
PQ13
PR84

PR87 DTC115EUA_SC70-3

3
10K_0402_5%
1 2
2

PR86 ACIN <21,33>

2

215K_0402_1% PU8A
1 2 3 PR159
P

+ VL
0.068U_0603_25V7M

1 PACIN 2.2M_0402_5%
O PACIN <40>
24.9K_0402_1%

2 - 2 1
1

10K_0402_1%
0.1U_0402_16V7K

RLZ4.3B_LL34
1

1
PR82

LM393DG_SO8
4
PC59

PC113

PR80

499K_0402_1%
PD5
2

1
VS
2

PR157
0.01U_0402_25V7K
PR160
2

100K_0402_1%
10K_0402_1%

1
2 1 RTCVREF
3.3V

1
PR161

PC109

2
VIN

2
PD15

8
RB715F_SOT323-3
2

<41,46> MAINPWON 2 5

P
+
3 1 7 O 3

205K_0402_1%

499K_0402_1%

0.01U_0402_25V7K
PD2 <40> ACON 3 6
-

1
G
RLS4148_LL34-2 PU8B

1
1000P_0402_50V7K

PR156

PR158

PC111
PR154 LM393DG_SO8
1

1
200K_0402_1%

PC108
0.1U_0603_25V7K
2 1 <40> PRECHG 2 1

2
BATT+
1

PRG++ 2

2
1

PC107
PD1 PR67 PR63
RLS4148_LL34-2 PQ6 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3

2
PR65
2

200_0603_5% PQ10
CHGRTCP 1 2 N1 3 1 VS PR153 SSM3K7002F_SC59-3 PR81

1
10K_0402_5% D 47K_0402_5%
2 1 2 2 1
RTCVREF PACIN <40>
1

G
1

1
PC48 S

3
66.5K_0402_1%
PR75 PC57 0.1U_0603_25V7K

1
100K_0402_1% 0.22U_0603_25V7K
2

2
2

PR155
2 +5VALWP
<32> 51_ON# 1 2
PR74
RTC Battery

2
22K_0402_1%
@ PQ17
- +

3
JRTC PR114 DTC115EUA_SC70-3
0_0603_5%
RTCVREF 2 1 2 1 +RTCBATT
1

PR66
PU7 200_0603_5% PD6
PR113 PR112 G920AT24U_SOT89-3 @ MAXEL_ML1220T10 1 2
4
560_0603_5% 560_0603_5% 3.3V +CHGRTC 4
2

1 2 1 2 3 2 N2 RB751V-40TE17_SOD323-2
+CHGRTC OUT IN

SP093MX0000
1

GND
PC106
10U_0805_10V4Z 1 PC47
2

1U_0805_25V4Z Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/06/22 Deciphered Date 2008/06/22 Title
DCIN & DETECTOR
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
gratuito - free of charge. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 44 of 53
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

VL VL
1 1
VL

2
PR162

1
47K_0402_1%
PH2 PC114
MAINPWON <4,36,39>
PF2 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K

1
@ 12A_65V_451012MRL 1 2

1
1 2 VMB

2
PL3 PR166 PR163 PQ39

8
JBATT PJ7 SMB3025500YA_2P 13.7K_0402_1% 47K_0402_1% DTC115EUA_SC70-3
1 BATT_S1 2 1 1 2 1 2 3

P
1 2 1 BATT+ +
2 2 O 1 2
3 EC_SMCA @ JUMP_43X118 TM_REF1 2
3 -

G
4 EC_SMDA
4 TS PU9A
5

4
5

1
6 LM393DG_SO8

3
6

0.22U_0603_16V7K
7 PC101 PC26
7

1000P_0402_50V7K
15.4K_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND

1
9 PR147 PR148
GND

1
PC116

PR167
100_0402_1% 100_0402_1% 2 1 VL

PC115
@ TYCO_1775768-1
PR164

1
100K_0402_1%

2
PR165
100K_0402_1%
EC_SMB_CK1 <29,34>

8
2
5

P
EC_SMB_DA1 <29,34> +
O 7
2 2
6 -

G
1 2 +3VALWP PU9B
PR149 LM393DG_SO8

4
6.49K_0402_1%
1

PR146
10K_0402_1%
2

A/D
BATT_TEMPA <29,34>

PJ19
2 2 1 1
PJ14 PJ12
@ JUMP_43X39 +3VALWP 2 1 +3VALW +1.8VP 2 1 +1.8V
2 1 2 1
PQ26 @ JUMP_43X118 @ JUMP_43X118
@ TP0610K-T1-E3_SOT23-3 (5A,200mils ,Via NO.= 10) (8A,320mils ,Via NO.=16)

B+ 3 1 +VSBP PJ15 PJ3

+5VALWP 2 2 1 1 +5VALW +0.9VSP 2 2 1 1 +0.9VS
100K_0402_1%

0.22U_1206_25V7K

0.1U_0603_25V7K
1

@ JUMP_43X118 @ JUMP_43X39
1

3 3
PR120

PC88

PC89

(5A,200mils ,Via NO.= 10) (2A,80mils ,Via NO.= 4)

PJ10
2

PR119 PJ13
2

@ 22K_0402_1% @ +1.5VSP 2 1 +1.5VS 1 2

VL 2 1 1 2
1 2
@ @ @ JUMP_43X118
JUMP_43X79
(6.0A,240mils ,Via NO.=12)
2

PR115
PJ11
@ 100K_0402_1% PJ6
+VSBP 2 2 1 1 +VSB +VGA_COREP 1 1 2 2 +VGA_CORE
PR116
1

@ 0_0402_5% D @ JUMP_43X39
PQ25 JUMP_43X79
<39> POK 1 2 2 (120mA,40mils ,Via NO.= 2) (15A,600mils ,Via NO.=30)
G @ SSM3K7002F_SC59-3
0.1U_0402_16V7K

S
3
1

PC87

PJ17 PJ18

+VCCPP 1 2 +VCCP +VGA_CORE 1 2 +VCCP

2

1 2 1 2

JUMP_43X79 JUMP_43X79
(3000mA,120mils ,Via NO.= 6)
@
PJ21

+1.1VSP 1 1 2 2 +1.1VS

JUMP_43X79
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title
BATTERY CONN / OTP
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
gratuito - free of charge. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 45 of 53
A B C D
 A B C D E

CP mode Fosc=14100/Rt=14100/47=300KHz PJ8

@ JUMP_43X118
Charger
65W: 2.8A 2 2 1 1
P2 P3 90W: 4.0A B+ PQ32 PQ34
PQ37 PQ38 AO4407_SO8 @ AO4407_SO8
FDS4435BZ_SO8 FDS4435BZ_SO8 1 8 8 1
8 D S 1 1 S D 8 4 1 2 7 7 2
VIN 7
6
D S 2 2 S D 7 PL12 CHG_B+ 3 6 6 3
D S 3 3 S D 6 3 2 5 5

1800P_0402_50V7K
0.01U_0603_50V7K

5 D G 4 4 G D 5 1 2

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K

0.01U_0402_25V7K
1 PR152 FBMA-L11-321611-121LMA30T_1206 1

4
1

200K_0402_1%

BATT+
0.1U_0603_25V7K
0.015_1206_1%

1
PR121

1
PC160

PC162

PC56

PR73

PC39

PC38

PC37

PC36
47K_0402_1% 1 2
2

10K_0402_1%
PC150
1 2
VIN
1

1
47K_0402_5%

2 1 PR139
<31,33> ADP_I

10K_0402_1%
PR68

PR138
@ 100K_0402_1%

2
PR122 PD8
A/D

PR125
PC92 10K_0402_5% 1SS355TE-17_SOD323-2

0_0402_5%
0.22U_0603_16V7K 1 2
2

3 2
ACOFF
3

BATT+
PR17
PU1 @
MB39A126PFV-ER_SSOP24

1
1 -INC2 +INC2 24 PQ30
2 PR126 PC90 PR123 PR124 @DTA144EUA_SC70-3

2
10K_0402_1% 4700P_0402_25V7K 100K_0402_1% 200K_0402_1% 2

1
MB39A126 1 2 1 2 2 1 2 23 1 2
OUTC2 GND VIN

4
3
2
1

1
PQ27
PQ9 DTC115EUA_SC70-3

S
S
S
G

FDS4435BZ_SO8
DTA144EUA_SC70-3 3 22 CS 1 2 PD9
1

+INE2 CS
1

31.6K_0402_1%
PC1 2 1 21SS355TE-17_SOD323-2

1
0.22U_0603_16V7K 2

D
D
D
D
10K_0402_1%
0.01U_0402_25V7K
4 -INE2 VCC 21 1 2 PRECHG <39>

1
D

PR1
PC8

5
6
7
8
1

1
PQ5
PC6

PR12
2 65W: PR1=49.9K 0.1U_0603_25V7K 2 PACIN

3
5 20 PC91 G PQ29
90W: PR1=31.6K

3
ACOK OUT PC13 0.1U_0603_25V7K PQ28 @ DTC115EUA_SC70-3
S
2

3
0.1U_0603_25V7K SSM3K7002F_SC59-3
2

PQ8

LXCHRG
6 19 1 2
3

VREF VH
1

150K_0402_1%

0.22U_0603_16V7K
DTC115EUA_SC70-3
PR78
1

1
D PC9 PL5
7 ACIN XACOK 18
2 PR14 PC14 PR19 ACON 10U_LF919AS-100M-P3_4.5A_20%
2 G 1K_0402_1% 2200P_0402_50V7K 47K_0402_1% ACON 1 2 4 1 2
2

S MB39A1261 2 1 2 8 17 1 2 <39>
3

-INE1 RT

1
B340A_SMA2

B340A_SMA2
PQ7 3 2

2
SSM3K7002F_SC59-3

10U_1206_25V6M

10U_1206_25V6M
9 16 PR135
+INE1 -INE3

PD14

PD13
PR27 PR18 PC17 @ 0_0402_5% PR150

1
PC103

PC102
<33> IREF 100K_0402_1% 10K_0402_1% 1500P_0402_50V7K 0.02_1206_1%

2
1 2 2 1 10 15 MB39A126
1 2 1 2

1
OUTC1 FB123
1

D PR28

2
100K_0402_1%

0.01U_0402_25V7K

2 33K_0402_1%
1

G 11 14
SEL CTL
1
PR22

S PQ11 IREF=0.4~2.88V
3

SSM3K7002F_SC59-3 PD11 RB751V-40TE17_SOD323-2

12 13 1 2 1 2
2

-INC1 +INC1

2
FSTCHG <32>

0_0402_5%
PC16

PC21
2

100K_0402_5%
PR33
10P_0402_50V8J
PD10 RB751V-40TE17_SOD323-2
PR132 1 2
SUSP#

PR137
3K_0402_1%

1
<39> PACIN 1 2
PD12 @ RB751V-40TE17_SOD323-2
1 2
EC_ON

+3VALWP
<39> ACON
47K_0402_5%

CS
1
1

PR2

PC22
1

47P_0402_50V8J
1 2 VMB
2

3 3
<39> ACOFF 2
2
LI-3S :13.5V----BATT-OVP=1.5V
1

CC=3.6A
PQ15 PQ1
BATT-OVP=0.1112*BATT+
3

DTC115EUA_SC70-3 DTC115EUA_SC70-3 (100K/(100K+100K))*2.88V=1.44V

3

<33> FSTCHG
2
VMB
1.44/(20*0.02)=3.6A

499K_0402_1% 340K_0402_1%
PQ2

1
DTC115EUA_SC70-3 VS
3

PR34
Charge voltage

1800P_0402_50V7K

0.01U_0402_25V7K

2
3S CC-CV MODE : 12.6V

1
SEL is L

PC5
PC161

PR29
2

2
8
PR23
10K_0402_1% 3 Adapter 65W CP Point=2.8A
P
+
VS <33> BATT_OVP 2 1 1 0
G - 2 5V*(10K/(49.9K+10K))=0.835V

105K_0402_1%
A/D

0.01U_0402_25V7K
PU3A 0.835V/(20*0.015)=2.78A
4

1
PR35
LM358DR_SO8
8

PC20
Adapter 90W CP Point=4A
5
P

2
4 + 4
7 5V*(10K/(31.6K+10K))=1.202V

2
0
- 6
G

1.202V/(20*0.015)=4.006A
PU3B
4

LM358DR_SO8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B 1.0

gratuito - free of charge. A B C D

Date: Monday, May 12, 2008
E
Sheet 46 of 53
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PR168
PL13 0_0805_5%
1 2 1 2
FBMA-L11-321611-121LMA30T_1206

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
D D

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC128

PC130

PC132

8
7
6
5

1
PC134
VL

PC131

PC129
2

1U_0402_6.3V6K

2
2
PQ42 PC120

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0603_6.3V6K
4

1
PC121
4

PC122
1
PQ43 +5VALWP

2
AO4466_SO8

3
2
1
1
2
3
PL10

7
PL11 PC127 2 1
1 2 1U_0402_6.3V6K 4.7UH_PCMC063T-4R7MN_5.5A_20%

LDO
VIN

VCC
+3VALWP

470P_0402_50V7K
6.8_1206_5%

0.01U_0402_25V7K
4.7UH_PCMC063T-4R7MN_5.5A_20% 33 19 1 2
TP PVCC

5
6
7
8

1
8
7
6
5

1
6.8_1206_5%
DH3 26 15 DH5
UGATE2 UGATE1

PR195
0_0402_5%

PR196

PC166

PC165
PQ41 2 1 BST3A 24 17 BST5A2 1

2
BOOT2 BOOT1
2

680P_0402_50V7K
1 AO4712_SO8 PR183 PR184

2
2

2
PR171

61.9K_0402_1%
0_0603_5% 0_0603_5% 4
PC133 + 4 PC126

1 2

2
680P_0402_50V7K

PC157
220U_6.3V_M 0.1U_0603_25V7K

1
PC156

PR174
OS-CON LX3 25 16 LX5 PQ40 1
1

2 PHASE2 PHASE1 PC124 AO4712_SO8

3
2
1

2
0.1U_0603_25V7K + PC135

1
2
3
C DL3 23 18 DL5 220U_6.3V_M C

1
LGATE2 LGATE1
2
OS-CON
10K_0402_1%
2

PGND 22

2
PR173

FB3 30 OUT2

10K_0402_1%
PR172
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC119
0.22U_0603_10V7K
BYP 9
8 LDOREFIN

SKIP 29 2 1 VL
PD16 PR175
RB751V-40TE17_SOD323-2 @ 0_0402_5%
1 2 1 2
20 28 PR177
PD7 PR118 NC POK2 0_0402_5%
VS RLZ5.1B_LL34 100K_0402_1%
POK <38>
1 2 1 2 4 EN_LDO POK1 13
2
200K_0402_5%

2
PR117

PC86 14 12 ILM1 2 1
B 0.22U_0603_25V7K EN1 ILIM1 PR176 B
301K_0402_1%
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2

PD17 PR170
2

@ RB751V-40TE17_SOD323-2 @ PR180 PU10 301K_0402_1%

21
1 2 VL 0_0402_5% ISL6237IRZ-T_QFN32_5X5
806K_0603_1%
2

PR178
1

1
PR181

0_0402_5%
2VREF_ISL6237 1

PR182
@ 47K_0402_5% 2 PR169
PR179 PC149 0_0402_5%
1

2 1 1 2 1U_0402_6.3V6K
1

<42,44> MAINPWON 2VREF_ISL6237 2

0_0402_5%
1

PC123
0.047U_0402_16V7K PC125
2

@ 0.047U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/06/22 Deciphered Date 2008/06/22 Title
+5V/+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom 1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008
1
Sheet 47 of 53
 A B C D

1
PC78 PC77

2
1U_0402_6.3V6K 1U_0402_6.3V6K

+5VALW 2 1 1 2 +5VALW
PR102 PR101
1
2.2_0603_1% 2.2_0603_1% 1

1
PC80
0.1U_0603_25V7K PC67
PL14 0.1U_0603_25V7K

2
B+ 1 2 ISL6228_B+
FBMA-L11-321611-121LMA30T_1206 ISL6228_B+ 2 1 2 1 ISL6228_B+
PR103 PR97
10_0603_1% 10_0603_1%

2
1

1
PC81 PC70

2
1000P_0402_50V7K PR108 1000P_0402_50V7K PR95
PR105 22K_0402_1% 18.2K_0402_1%

2
PC85 PR111 16.5K_0402_1% +5VALW 2 1

1
1000P_0402_50V7K 3.3K_0402_5% PR185
2 1 1 2 @ 0_0402_5%

1
1 2
PR109 29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
34.8K_0402_1% GND_T

2
1 2 8 28 2 1 +5VALW PR96 PR92 PC66
PR107 FB1 PGOOD2 PR186 16.5K_0402_1% 3.3K_0402_5% 1000P_0402_50V7K
2
10.5K_0402_1% @ 0_0402_5% 2 1 1 2 2

1
ISL6228_B+

9 VO1 FB2 27 2 1
PR93
4.7U_1206_25V6K

4.7U_1206_25V6K

26.1K_0402_1%
1

1
PC73

PC72

PC84
8
7
6
5

0.022U_0402_25V7K
10 26 1 2
2

PQ21 OCSET1 VO2 PR98

1 2
AO4466_SO8 10.5K_0402_1%
2

PR110 4
10.5K_0402_1% 1.8V_EN 11 25
EN1 PU6 OCSET2
ISL6228_B+
ISL6228HRTZ-T_QFN28_4X4 PR100
1

1
2
3

PL8 47K_0402_5%
1 2 LX_1.8V 12 24 1 2 SUSP# PC68
+1.8VP PHASE1 EN2

4.7U_1206_25V6K

4.7U_1206_25V6K
<42,44> 0.033U_0402_16V7K

5
6
7
8

1
PC75

PC74
1.8UH_SIL104R-1R8PF_9.5A_30% PC71
1

8
7
6
5
6.8_1206_5%

1 0.1U_0402_16V7K 1 2

2
1

PR197

+ PC118 PQ23 UG_1.8V 13 23

UGATE1 PHASE2

2
10U_0805_6.3V6M
PC159

220U_6.3V_M AO4712_SO8
OS-CON 4 PR94
2

1 2

2
680P_0402_50V7K

4 10.5K_0402_1%
PQ22
PC158

2 1 2 1BST_1.8V14 22 UG_1.5V AO4466_SO8

1
BOOT1 UGATE2
2

3
2
1
LGATE1

LGATE2
PC82 PR104 LX_1.5V 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.5VSP
1
2
3

1
0.1U_0402_16V7K 0_0603_5% PL9

5
6
7
8
3 3

1.8UH_SIL104R-1R8PF_9.5A_30%
PR193 1
6.8_1206_5%
15

16

17

18

19

20

21
+ PC117

1 2
220U_6.3V_M
4
2
OS-CON
+5VALW +5VALW BST_1.5V
1 2 1 2
PR99 PC69 PC154

2
2

2
0_0603_5% 0.1U_0402_16V7K 680P_0402_50V7K
PQ24

3
2
1
PC76 PC79 AO4712_SO8
1

1U_0402_6.3V6K 1 1U_0402_6.3V6K

LG_1.8V LG_1.5V

PR106
0_0402_5%
SYSON 2 1 1.8V_EN
<42,44>
1

PC83
@ 0.01U_0402_25V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/06/22 Deciphered Date 2008/06/22 Title
1.8V / 1.5V
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
gratuito - free of charge. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 48 of 53
A B C D
 5 4 3 2 1

PL15
1 2 6268_B+
B+ FBMA-L11-321611-121LMA30T_1206

1800P_0402_50V7K

10U_1206_25V6M

10U_1206_25V6M
470P_0603_50V8J
1

1
D
PHASE_1.05V D
PC151

PC164

PC163

PC55

PC58
1000P_0402_50V7K 6268_1.05V UG_1.05V
2

2
PR54

1
1 2 1 2
PR62 PR60
0_0603_5% 10K_0402_1% 1_0603_5% PC43 0.1U_0603_25V7K
+5VS

1
BOOT_1.05V
PR49

5
6
7
8
0_0603_5%

16

15
8

1
PC51

SI4686DY-T1-E3_SO8
@ 0.1U_0402_16V7K 1 2 6268_1.05V

BOOT
GND

PGOOD

PHASE

UG
2
PR50
4.7_0603_5% 4
3 VIN PVCC 14 1 2
PC33
2.2U_0603_6.3V6K

3
2
1
PQ19
6268_1.05V LG_1.05V PL7
4 VCC LG 13
1UH_PCMB103E-1R0MS_20A_20%
+VGA_CORE

1
1 2 +VGA_COREP

1
PC46
2.2U_0603_6.3V6K 12 PR194
2
PGND 6.8_1206_5% 1
PR64

D 5
D 6
D 7
D 8

D 5
D 6
D 7
D 8

1
0_0402_5% +

FDS8672S 1N SO8

FDS8672S 1N SO8

1 2
1 2 5 11 ISEN_1.05V
1 2 PR57 PC112 PC148
<19,27,29,30,35,40,42> SUSP# EN ISEN 10U_0805_6.3V6M
PR52 @ 0_0402_5% 220U_6.3V_M

2
COMP
3.9K_0402_1% PC155 2

FSET
OS-CON
1

C 680P_0402_50V7K C

VO
FB

1
4 G

4 G
3 S
2 S
1 S

3 S
2 S
1 S
PC44
@ 0.1U_0402_16V7K PU4
2

10

PQ18

PQ12
ISL6268CAZ-T_SSOP16

2 1 +VGASENSE
PR55
0_0402_5%

1 2 1 +VCCP
22P_0402_50V8J

PR53
1

PR61 @ 0_0402_5%

1
6800P_0402_25V7K
PC45

49.9K_0402_1%

2
2

PC34 PR58
PR51 0.01U_0402_25V7K 2.8K_0402_1%

2
1
PC49

37.4K_0402_1%

1
2

1
PR59
3K_0402_1%

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1.0

gratuito - free of charge. Date: Monday, May 12, 2008 Sheet 49 of 53

5 4 3 2 1
 5 4 3 2 1

+VGA_CORE +5VS

D D

1
PC141 PC136
10U_0805_6.3V6M 1U_0402_6.3V6K

2
PU11
6 VCNTL
5 VIN VOUT 3 +VCCPP
PR187 9 4
VIN VOUT

1
100K_0402_5%

1
<19,27,29,30,35,40,42> SUSP# 1 2 8 EN
7 2 PR188 PC142

GND
POK FB 1.27K_0402_1% PC139 10U_0805_6.3V6M

2
1
0.01U_0402_25V7K

2
PC110 APL5912-KAC-TRL_SO8

1
0.47U_0402_6.3V6K

1
PR189
3.65K_0402_1%

2
C C
+1.8V

1
PJ4

1
@ JUMP_43X39

2
PU5

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
PC64

1
4.7U_0603_6.3V6K 3 7 PC65
PR91 VREF NC 1U_0402_6.3V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
TP
APL5331KAC-TRL_SO8

1
PR89 +0.9VSP

1
0_0402_5% D PR90
1 2 2 1K_0402_1% PC63
<35> SUSP

1
G 0.1U_0402_16V7K

2
1
S PQ20 PC62

2
PC61 SSM3K7002F_SC59-3 10U_0805_6.3V6M

2
@ 0.1U_0402_16V7K

2
+1.8VS
B B
1

PJ20
1

JUMP_43X79
2

PU12
2

1 VIN VCNTL 6 +5VS

2 GND NC 5
1

PC144
1

4.7U_0603_6.3V6K 3 7 PC145
PR190 VREF NC 1U_0402_6.3V6K
2

1.91K_0402_1% 4 8
VOUT NC
9
2

TP
APL5331KAC-TRL_SO8
1

PR191 +1.1VSP
1

0_0402_5% D PR192
1 2 2 3.16K_0402_1%~D PC143
<35> SUSP
1

G 0.1U_0402_16V7K
2
1

S PQ44 PC147
3

PC146 SSM3K7002F_SC59-3 22U_0805_6.3V6M

2

@ 0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCP/0.9V/1.1V
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1.0

gratuito - free of charge. Date: Monday, May 12, 2008 Sheet 50 of 53

5 4 3 2 1
 5 4 3 2 1

+5VS

<30>

CPU_VID6 <5>

CPU_VID5 <5>

<5>

<5>
CPU_VID2 <5>

CPU_VID1 <5>

CPU_VID0 <5>

2
CPU_VID4

CPU_VID3
PR142
+CPU_B+ PL1

VR_ON
1_0603_5%
HCB4532KF-800T90_1812
1 2 B+

1
D D

470P_0402_50V7K

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
<8,21> DPRSLPVR 1 2 1

680P_0402_50V7K

3300P_0402_50V7K
220U_25V_M
PR20

1
PC153

PC32

PC35

PC152

PC42

PC40
+

0.022U_0402_16V7K
0_0402_5%

1
PC99

PC105
2.2U_0603_6.3V6K
<5,8,20> H_DPRSTP# 1 2 PC41

PC100
PR16 0.01U_0402_25V7K

2
0_0402_5% 2

2
<21> CLK_ENABLE# 1 2

5
PR15
0_0402_5%

1
1

PR32 0_0402_5%

PR36 0_0402_5%

PR37 0_0402_5%

PR39 0_0402_5%
PR21 0_0402_5%

PR25 0_0402_5%

PR26 0_0402_5%

PR31 0_0402_5%
+3VS 1 2 UGATE_CPU1-2 4 PQ4
PR9 FDMS8692 1N POWER56-8
+3VS

1U_0402_6.3V6K
0_0402_5%

2
2
1.91K_0402_1%
1_0603_5% 0.22U_0603_10V7K

1
PC10
PR42 PC28 0.36UH_MPC1040LR36_24A_20%

3
2
1
1
BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

PR8

PR13

1
10K_0402_1%
3.65K_0402_1%
PL4

PR48

PR45
499_0402_1% PR151 PR44

FDS8672S 1N SO8

FDS8672S 1N SO8
49

48

47

46

45

44

43

42

41

40

39

38

37

5
6
7
8

5
6
7
8
6.8_1206_5% 1_0402_5%
2

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON

D
D
D
D

D
D
D
D
1

PR40

1 2

2
1 36 @ 0_0603_5%
<21,30> VGATE PGOOD BOOT1
1 2

G
S
S
S

S
S
S
<5> H_PSI# 2 35 UGATE_CPU1-1 PC104 VSUM
PSI# UGATE1

PQ35

PQ36
680P_0402_50V7K 1 2

4
3
2
1

4
3
2
1

2
PGD_IN 1 2 3 34 PHASE_CPU1 VCC_PRM
PR7 PMON PHASE1 ISEN1 PC27
1 2 @ 0_0402_5% 4 33 0.22U_0603_10V7K
C PR6 RBIAS PGND1 C
VR_TT# 147K_0402_1% 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M
1 2 1 2 6 NTC PVCC 31

1
PR127 PH3

PC31

PC30
@ 4.22K_0402_1% @ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2
SOFT LGATE2
1 2

2
PC4 8 PU2 29
@ 0.015U_0402_16V7K OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
PC3 VW PHASE2 PQ3
0.022U_0402_16V7K 10 27 UGATE_CPU2-1 UGATE_CPU2-2 FDMS8692 1N POWER56-8 0.36UH_MPC1040LR36_24A_20%
PR5 1 COMP UGATE2
2

3
2
1
13K_0402_1% 11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR43 PL2
1 2

1
PC2 1_0603_5% PC29
DROOP

12 FB2 NC 25

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
VSEN

1000P_0402_50V7K 0.22U_0603_10V7K
GND

VDD
RTN

DFB

5
6
7
8

D 5
D 6
D 7
D 8

1
VIN

PR143
3.65K_0402_1%
PR133 1 PR145
VO

FDS8672S 1N SO8

FDS8672S 1N SO8
2
6.81K_0402_1% 6.8_1206_5%

D
D
D
D
1 2 PR144
13

14

15

16

17

18

19

20

21

22

23

24

1 2
PC95 1_0402_5%

2
PR46
1000P_0402_50V7K PR140

2
G

4 G
S
S
S

3 S
2 S
1 S
ISEN1 @ 0_0603_5%
ISEN2 PC98 1 2

4
3
2
1

2
2

PQ33

PQ31
1 2 +5VS 680P_0402_50V7K
1

1 2 2 1 PR10 PR141 VSUM

1

PR134 PC94 @ 0_0402_5% 1_0603_5% 1 2

97.6K_0402_1% 470P_0402_50V7K PR3 PC24
1 2 1U_0402_6.3V6K PC97
1

PC93 1K_0402_1% 0.22U_0603_10V7K

2

220P_0402_50V7K VCC_PRM
B ISEN2 B

1 2 1 2PC7 1 2 +CPU_B+
PR11 1000P_0402_50V7K PR136
1

255_0402_1%
1 2 10_0603_1%
PR4 PC96
1K_0402_1% 0.1U_0603_25V7K
2

<5> VCCSENSE 1 2 1 2
PR128 PC12 VSUM
1

0_0402_5% 0.018U_0603_50V7J
1

PC11 PC15
+CPU_CORE 1 2 0.018U_0603_50V7J 0.018U_0603_50V7J
2

PR129 PR41
2

20_0402_5% 1 2 2.61K_0402_1%
<5> VSSSENSE PR130
2
1

0_0402_5%
11K_0402_1%

1 2PC19
2

PR131 180P_0402_50V8J
20_0402_5% 1 2 1 2 PH1
PR38

PR30 PR24 10KB_0603_5%_ERTJ1VR103J

2

1K_0402_1% 4.42K_0402_1%
1

VCC_PRM 1 2
PC23
0.1U_0402_16V7K
PC18 2 1 2 1
0.22U_0603_10V7K PC25
0.22U_0402_6.3V6K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title
+CPU_CORE
hexainf@hotmail.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom
Rev
1.0
gratuito - free of charge. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2008 Sheet 51 of 53
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
10/12 P48 Add PR185, PR186 Reserve for debug use.

10/12 P49 Delete PC110 Because HW reserve enough CAP.

10/17 P49 Add PU11, PC136, PC141, PC142, PC139, PC110, Because need separate +VCCP and +VGA_CORE
PR187, PR188, PR189

10/17 P49 Change PR58 from 2.7k_0402_1% to 2.8k_0402_1% HW request change VGA_CORE from 1.1V to 1.16V
PR59 from 3.24k_0402_1% to 3k_0402_1%.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
Size Document Number Rev
hexainf@hotmail.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JIWA3/A4_LA4212P 1.0

Date: Monday, May 12, 2008 Sheet 51 of 51

gratuito - free of charge.
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------
1 12/10 P29 C615 change to R615 and BOM Structure change to PM@ Fix DIS Audio issue

2 12/10 P20、P21 R104 & R154 BOM Structure change to PM@ Reduce cost

3 12/10 P16 R86、R645、R646、R650、R651、R652 & R653 BOM Reduce cost

Structure change to PM@

4 12/10 P29 R614 change from 10K to 45.3ohm Fix UMA Audio issue
R615 change from 12K to 54.9ohm

5 12/10 P08 R79 change from 33 to 10ohm Fix UMA Audio issue
D R80、R81、R82 & R85 change from 0 to 22 ohm D

6 12/10 P30 The C783 links to GND Fix Internal MIC issue

7 12/10 P41 Add L45 & L46 MBC1608121YZF Bead Fix F/B issue

8 01/02 P11 Change C126 package

9 01/02 P28 Add R707 to connect VGATE to M_PWROK Modify power sequence

10 01/02 P16 Add R699 to connect +VGASENSE

11 01/02 P16 Remove U3.P1

12 01/02 P19 Add R700 to connect GND

13 01/02 P11 Add C707 for +VCC_DMI

14 01/02 P16 Add C788 for nvidia request for +PEX_PLLVDD

15 02/27 P08 change R147 from 511 ohm 1% to 499 ohm 1%

16 02/27 P23 change D4 location

17 02/27 P23 Add D25 , D26 for ESD

C C
18 02/27 P25 Add D27 , D28 & D29 for ESD

19 02/27 P29 Add R713 connect to 1.5V

20 02/27 P31 change C550 , C570 , C506 & C507 to 0.1uF 0603 Fix pop noise issue

21 05/08 P05 Add R726 1k ohm & C808 0.1uF to fix issue.

22 05/08 P16 Remove R48 for EMI request.

23 05/08 P27 Change R554 from 0 ohm to 33 ohm for EMI request.

24 05/08 P28 Add R566 10 ohm & C733 10pF for EMI request.

25 05/08 P30 Add R327 47 ohm & C458 33pF for EMI request.

26 05/08 P35 Change C501 & C514 from 15pF to 12pF

27 05/08 P37 Add D31 (PJDLC05_SOT23-3) for ESD request.

28 05/08 P41 Add C494、C522、C564 & C568 220pF for EMI request

B B

A A

Title
<Title>

hexainf@hotmail.com Size Document Number

CustomJIWA3/A4_LA4212P
Rev
1.0

gratuito - free of charge.

5 4 3 2
Date: Monday, May 12, 2008 Sheet
1
53 of 53