algorithms

Article
Fast Tuning of the PID Controller in An HVAC
System Using the Big Bang–Big Crunch Algorithm
and FPGA Technology
Abdoalnasir Almabrok 1, * , Mihalis Psarakis 1 and Anastasios Dounis 2
1 Department of Informatics, University of Piraeus, 18534 Piraeus, Greece; mpsarak@unipi.gr
2 Department of Industrial Design and Production Engineering, University of West Attica,
12244 Piraeus, Greece; aidounis@uniwa.gr
* Correspondence: Nassnaan@webmail.unipi.gr; Tel.: +30-210-414-2122




Received: 1 September 2018; Accepted: 26 September 2018; Published: 28 September 2018


Abstract: This article presents a novel technique for the fast tuning of the parameters of the
proportional–integral–derivative (PID) controller of a second-order heat, ventilation, and air
conditioning (HVAC) system. The HVAC systems vary greatly in size, control functions and
the amount of consumed energy. The optimal design and power efficiency of an HVAC system
depend on how fast the integrated controller, e.g., PID controller, is adapted in the changes of the
environmental conditions. In this paper, to achieve high tuning speed, we rely on a fast convergence
evolution algorithm, called Big Bang–Big Crunch (BB–BC). The BB–BC algorithm is implemented,
along with the PID controller, in an FPGA device, in order to further accelerate of the optimization
process. The FPGA-in-the-loop (FIL) technique is used to connect the FPGA board (i.e., the PID
and BB–BC subsystems) with the plant (i.e., MATLAB/Simulink models of HVAC) in order to
emulate and evaluate the entire system. The experimental results demonstrate the efficiency of the
proposed technique in terms of optimization accuracy and convergence speed compared with other
optimization approaches for the tuning of the PID parameters: sw implementation of the BB–BC,
genetic algorithm (GA), and particle swarm optimization (PSO).

Keywords: Big Bang–Big Crunch optimization algorithm; FPGA based acceleration; digital PID
controller; FPGA-in-the-loop; heat ventilation air condition

1. Introduction
Although novel and effective theories and design methodologies are being continually developed
in the digital control field, proportional–integral–derivative (PID) controllers are still the most widely
adopted solution for control problems in both academic and industry sectors. The tuning of the
parameters of the PID controllers has been proved a hard task and several approaches have been
investigated in the past [1,2] using analytical methods, heuristic methods, such as Ziegler–Nichols
(Z–N) rule, frequency response methods, artificial intelligence such as fuzzy logic [3], and iterative
learning approaches [4]. Evolutionary algorithms (EA), such as genetic algorithms (GA) [5] and particle
swarm optimization (PSO) [6], used in intelligent control applications, have been also proposed as an
efficient solution for tuning the PID parameters. The simplicity and speed convenience of evolutionary
algorithms force the controller quickly seek out the optimal output value.
In this paper, we study the use of an evolutionary algorithm, named Big Bang–Big Crunch
(BB–BC) [7], to optimize PID controller gains. BB–BC optimization algorithm is used to minimize
performance control measures, integral absolute error (IAE), integral time absolute error (ITAE),
integral square error (ISE), and integral time square error (ITSE) while minimizing the system overshoot.

Algorithms 2018, 11, 146; doi:10.3390/a11100146 www.mdpi.com/journal/algorithms

Algorithms 2018, 11, 146 2 of 19

The key idea of using BB–BC here can be explained as the transformation of a convergent solution to a
chaotic state and then back to a single tentative solution point. BB–BC algorithm has been implemented
in various engineering applications, especially where the computational time and convergence time
are important factors [8]. Some representative optimization problems, where the efficiency of BB–BC
has been demonstrated, are the following: optimal design of truss structures [9], Schwedler and ribbed
domes [10], concrete retaining walls [11], fuzzy inverse controllers [12], and fuzzy PID controllers [13].
Moreover, BB–BC algorithm has been adopted in real-time applications where the optimization task is
adaptive or must be solved in relatively small sampling intervals. Besides its low computational time
and high global convergence speed, another advantage of BB–BC, especially important for auto-tuning
processes, is that it does not need gradient information and therefore can operate to minimize naturally
defined cost functions without complex mathematical operations.
We evaluate the efficiency of BB–BC to tune the parameters of a PID controller used in a
second-order heat, ventilation, and air conditioning (HVAC) system. In the HVAC system, the supply
air pressure is regulated by the speed of a supply air fan. Increasing the fan speed will increase supply
air pressure, and vice versa. The dynamics from the fan variable speed drive to the supply air pressure
can be modeled as a second order plus dead time. This process is well established by Bi and Cai [14].
In real applications, however, where both fans and dampers exhibit non-linear properties for different
working points, even a well-tuned PID controller may not be able to achieve a desired performance for
all set points and process variations. Thus, we investigate how fast and accurate the BB–BC algorithm
can tune the PID controller parameters in this HVAC system.
To further reduce the optimization latency of the control system, the BB–BC algorithm along with
the PID controller, are accelerated using FPGA technology. Up to now, embedded computers, built
around programmable microcontrollers, were the dominant computing platform for implementing PID
controllers in industrial environments. The last decades, the field programmable hardware technology,
also known as field programmable gate arrays (FPGAs), has emerged as an alternative solution
for controlling industrial applications. The main advantages of the FPGA technology are reduced
engineering cost, reduced time-to-market, high performance due to the exploitation of fine-grained
hardware parallelism, and adaptation to control system requirements. Especially for control systems
that use demanding computational intelligence techniques, the advanced performance of FPGAs
combined with their low-cost and high adaptability render them an attractive computing platform.
Taking also into consideration the real-time requirements of our HVAC system, we propose the
FPGA-based acceleration of the BB–BC optimization algorithm and the PID controller to speed up the
parameters tuning process, and consequently, improve system performance.
The BB–BC, PID controller and register transfer level (RTL) models have been described using
the VHDL language and implemented in the Xilinx Zybo (Zynq) development board from Xilinx
Corporation (San Jose, CA, USA). Built around the Xilinx Zynq XC7Z010 FPGA device. Moreover,
the FPGA-in-the-loop (FIL) technique has been used to enable the emulation of the plant (HVAC)
in MATLAB/Simulink environment in conjunction with the execution of the PID controller and the
optimization process in the real hardware; this way, the FIL technique facilitates the evaluation of the
entire system in higher abstraction layers [15].
In order to demonstrate the efficiency of the proposed approach, we run various experiments
in a second order system with two sec time delay and compared it with GA and PSO optimization
algorithms in terms of PID tuning speed and convergence speed. The experimental results showed
that the FPGA–BB–BC algorithm tunes the PID controller parameters ~430X faster than the software
version of GA algorithm, ~539X faster than the software version of PSO algorithm, and ~270X faster
than the software version of BB–BC algorithm. Furthermore, the proposed approach was tested under
various fitness functions (error) for different number of iterations, and the integral time absolute error
(ITAE) was chosen.
The organization of this paper is given as follows. Section 2 shortly describes the basics of PID
controllers and BB–BC optimization algorithm. Section 3 presents the HVAC optimization problem
Algorithms 2018, 11, x FOR PEER REVIEW 3 of 19

Algorithms 2018, 11, 146 3 of 19

The organization of this paper is given as follows. Section 2 shortly describes the basics of PID
controllers and BB–BC optimization algorithm. Section 3 presents the HVAC optimization problem
and the proposed BB–BC-based tuning process of the PID parameters. Section 4 describes the FPGA
implementation of the PID and BB–BC
BB–BC subsystems
subsystems and the
the FIL
FIL approach.
approach. Section 5 presents the
experimental results and demonstrates the efficiency of the proposed approach, while Section 6
paper.
concludes the paper.

2. Background

2.1. PID Controller

2.1. PID Controller
The
The PID
PID controller
controller has
has been
been widely
widely used
used since
since its
its invention
invention in
in 1910
1910 in
in both
both academia
academia and
and
industry
industry [16]. There are many PID control configurations, but the most common implementation is
[16]. There are many PID control configurations, but the most common implementation is
shown
shown in
in Figure
Figure 1.
1.

Error P kp e(t)

Setpoint Control Output

I ki ʃe(t).dt

D kd de(t)/dt
Plant Output

Figure
Figure 1.
1. Block
Block diagram
diagram of
of typical
typical PID
PID control structure.
control structure.

In general, the synthesis of the PID controller

controller can
can be
be mathematically
mathematically described
described by
by

Zt 𝑑
𝑢(𝑡) = 𝑘 𝑒(𝑡) + 𝑘 𝑒(𝑡)𝑑𝑡 + 𝑘 d 𝑒(𝑡) (1)
u(t) = k p e(t) + k i e(t)dt + k d 𝑑𝑡e(t) (1)
dt
0
where 𝑘 is the proportional gain, 𝑘 is the derivative gain, 𝑘 is the integral gain, and the error
𝑒(𝑡) is kthe
where p isdifference
the proportional
betweengain, k d is the and
the set-point derivative gain,
the plant k i is y(t).
output the integral gain,Equation
In addition, and the (1) cane(be
error t)
is the difference
rewritten between
in Laplace the set-point and the plant output y(t). In addition, Equation (1) can be
form as
rewritten in Laplace form as
𝑢(𝑠) k𝑘 + 𝑘 𝑠]
u(s)==𝑒(𝑠)[𝑘
e(s)[k p +
+ 𝑠i + k d s] (2)
(2)
s
Finally, under
Finally, under the
the above
above scheme
scheme the the transfer
transfer function
function of of the
the PID
PID controller
controller or
or the
the control
control law
law isis
specified by
specified by
u(s) k𝑘i
𝐶(𝑠) ) =𝑢(𝑠) == 𝑘k p +
C ( s= + +k s (3)
e(s)
𝑒(𝑠) s𝑠 + d𝑘 𝑠 (3)
For digital PID controllers, Equation (3) can be transformed via the z-domain into a difference
For digital PID controllers, Equation (3) can be transformed via the z-domain into a difference
equation for a recursive digital filter with an infinite impulse response (IIR) [16]
equation for a recursive digital filter with an infinite impulse response (IIR) [16]
𝑈(𝑧)
U (z) k𝑘T𝑇
s z𝑧 K𝐾N𝑁(𝑧
(z −−1)1)
= 𝑘k p + i ++ d (4)
(4)
E𝐸(𝑧)
(z) z𝑧−−11 (1(1++NT
𝑁𝑇 )𝑧−−11
s )z

where T𝑇s isissampling

where samplingperiod,
period,NNisisthe
thefilter
filtervalue.
value.
To be
To be implemented
implemented onon an
an FPGA
FPGA platform,
platform, aa digital
digital PID
PID controller
controller must
must be
be transformed
transformed to
to aa
difference equation, as shown below
difference equation, as shown below
𝑈(𝑧) 𝑏 +𝑏 𝑧 +𝑏 𝑧
U ( z ) = b + b z −1 + b z −2 (5)
𝐸(𝑧) =𝑎 0 + 𝑎1 𝑧−1 + 2𝑎−𝑧2 (5)
E(z) a0 + a1 z + a2 z
Algorithms 2018, 11, 146 4 of 19

A differential equation can be derived from Equation (5) as follows

u [ n ] = k 1 u [ n − 1] + k 2 u [ n − 2] − k 3 e [ n ] − k 4 e [ n − 1] − k 5 e [ n − 2] (6)

Therefore, the relationship between the PID gains and its implementation in a digital system is
shown in Table 1.

Table 1. Equivalence of parameters for PID controllers

C(z) k1 k2 k3 k4 k5
C(z) − aa10 − aa20 − ba00 − ba10 − ba20

where the differential equation variables equal

a0 = (1 + N ∗ Ts )
a1 = −(2 + N ∗ Ts ); a2 = 1
b0 = k p ∗ (1 + N ∗ Ts ) + k i ∗ Ts ∗ (1 + N ∗ Ts ) + k d ∗ N (7)
b1 = −(k p ∗ (2 + N ∗ Ts ) + k i ∗ Ts + 2 ∗ k d ∗ N )
b2 = k p + kd ∗ N

2.2. Big Bang–Big Crunch Algorithm

Big Bang–Big Crunch (BB–BC) algorithm was introduced by Erol and Eksin in [7]. Its key concept
has been inspired by the creation theory of the universe. It is mainly consisted of two stages: the Big
Bang phase and the Big Crunch phase. In the Big Bang phase, the population is randomly generated
and the fitness function values of the individuals are calculated. Then, the Big Crunch phase follows.
This phase implements a convergence operator, called the center of mass, that has many inputs but
only one output, which is extracted by calculating the center of mass. Here, the term ‘mass’ refers to
→c
the inverse of the fitness function value. The point representing the center of mass is denoted by x
and calculated according to
i
1→
→c ∑iN=1 fi
x
x = (8)
∑iN=1 f1i

→i
where x is an individual (point) within an L-dimensional search space, f i is the fitness function value
of this individual, and N is the size of the population generated in the Big Bang phase. After the Big
Crunch phase, the algorithm creates new members to be used as the Big Bang of the next iteration
according to the following formula
x new = x c + r ∗ l/k (9)

where r is a random number with normal distribution, k is the number of Big Bang iterations, and
l is a problem-dependent constant, l = a ∗ ( xmax − xmin ); parameter α limits the search space, while
xmax and xmin are the upper and lower values of the optimization function variables. After the second
explosion, the center of mass is recalculated. These successive explosion and contraction steps are
carried out repeatedly until a stopping criterion has been met. Since normally distributed numbers can
exceed ±1, it is necessary to keep the candidate values within the predefined search space bounds [6].
The steps of the BB–BC algorithm implementation as follows:

1. Form an initial generation of N candidates in a random manner.

2. Calculate the fitness function values of all the candidate solutions. This step depends on the
target optimization problem.
3. Find the center of mass according to Equation (8). Best fitness individual of each generation can
be also chosen as the center of mass instead of using Equation (8) reducing the computation time.
Algorithms 2018, 11, x FOR PEER REVIEW 5 of 19
Algorithms 2018, 11, 146 5 of 19
3. Find the center of mass according to Equation (8). Best fitness individual of each generation can
be also chosen as the center of mass instead of using Equation (8) reducing the computation time.
4. Calculate new candidates around the center of mass using Equation (9). Notice that the random
4. Calculate new candidates around the center of mass using Equation (9). Notice that the random
value added or subtracted to the center of mass decreases as the iterations elapse.
value added or subtracted to the center of mass decreases as the iterations elapse.
5. 5.Return
Return to Step
to Step 2 until
2 until stopping
stopping criteria
criteria havehave
beenbeen
met.met.
Figure
Figure 2 below
2 below shows
shows thethe flow
flow chart
chart of BB–BC
of BB–BC algorithm.
algorithm.

An initial generation of
N candidates

Calculate the fitness

function values

Find the center of mass

Calculate new candidates

around the center of mass

No Stopping Yes
Solution
criteria

Figure 2. BB–BC
Figure optimization
2. BB–BC algorithm
optimization flowflow
algorithm chart.
chart.

3. Proposed
3. Proposed Approach
Approach

3.1.3.1.
HVACHVAC System
System andand
PIDPID Controller
Controller
TheThe HVAC
HVAC systems
systems areare automatic
automatic systems
systems thatthat control
control andand provide
provide a comfortable
a comfortable environment
environment
in terms of temperature, humidity, ventilation, and other parameters (power
in terms of temperature, humidity, ventilation, and other parameters (power consumption, pressure, consumption, pressure,
time control). HVAC systems are equipped with various sensors to monitor
time control). HVAC systems are equipped with various sensors to monitor these parameters (e.g., these parameters (e.g.,
temperature
temperature andand humidity
humidity sensors,
sensors, anemometers
anemometers for for measuring
measuring the the
flowflow speed,
speed, etc.)etc.)
andand optimize
optimize
system performance and power consumption. In an HVAC system, the
system performance and power consumption. In an HVAC system, the PID controller can be used PID controller can be used
in in
the the control
control looploop of the
of the supply
supply air air pressure
pressure [17].
[17]. Figure
Figure 3 shows
3 shows thethe block
block diagram
diagram of aofconventional
a conventional
single-zone HVAC system. The control inputs of the HVAC system are
single-zone HVAC system. The control inputs of the HVAC system are the air flow rate, which the air flow rate, which can
can be
adjusted through a variable-speed fan, and the water flow rate from the
be adjusted through a variable-speed fan, and the water flow rate from the chiller to the heat chiller to the heat exchanger.
The PIDThe
exchanger. controller calculations
PID controller adjust motor
calculations speed
adjust motor as speed
necessary to maintain
as necessary a set pointa compared
to maintain set point to
the system output signal.
compared to the system output signal.
ForFor
the the
HVACHVAC system—such
system—such as valve
as valve andand damper
damper operation,
operation, ambient
ambient temperature,
temperature, andand
flowflow
rate—the
rate—the motor
motor speed
speed should
should be adjusted
be adjusted to maintain
to maintain a set
a set point
point difference.
difference. TheThe BBBC-PID
BBBC-PID system
system
performance depends on its ability to maintain a set point
performance depends on its ability to maintain a set point and speedup action.and speedup action.
The tuning process in large HVAC systems is a hard and time consuming task [18,19] due to
their non-linearity and time-variance characteristics. Consequently, tuning the PID controller of an
HVAC system in order to achieve the optimum tracking control performance is a hard problem. Here,
we propose the use of BB–BC algorithm and FPGA technology to tune the PID parameters, and thus
speed up the re-tuning process of the HVAC system when needed.
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19

Heat Exchanger Control Unit

Fan
Filter
BBBC Algorithm
Damper

Heating Coil
Cooling Coil

PID Controller

Kp, Ki, Kd
Sensor

HVAC
Chiller

Thermal Zone
HVAC

Figure
Figure3.3.Block
Blockdiagram
diagramofofconventional
conventionalHVAC
HVACsystem
systemand
andcontrol
controlunit
unitstructure.
structure.

3.2. Tuning of theprocess

The tuning PID Parameters
in largeUsing
HVAC BB–BC
systems is a hard and time consuming task [18,19] due to
their non-linearity
Evolutionary algorithms can be applied for theConsequently,
and time-variance characteristics. tuning of PID tuning the gains/parameters
controller PID controller of an
to
HVAC system in order to achieve the optimum tracking control performance
ensure optimal control performance at stable operating conditions. In this paper, the BB–BC is a hard problem. Here,
algorithm
we propose the
is employed foruse
theofoffline
BB–BCtuning
algorithm and
of the PIDFPGA technology
parameters (kp , to
ki ,tune thethe
kd ) in PID parameters,
HVAC model. and thus3
Figure
speed up the re-tuning process of the HVAC system when needed.
above shows how the control unit consisting of the BB–BC unit and the PID controller is connected
in the HVAC system. First, the BB–BC unit produces initial candidates for the PID parameters in the
3.2. Tuning
target of space.
search the PIDNext,
Parameters
based Using
on the BB–BC
calculation of the objective function, it produces new candidate
solutions around the
Evolutionary center of can
algorithms mass beuntil the stop
applied criteria
for the is satisfied.
tuning of PID controller gains/parameters to
In the design methodology of a PID controller, one
ensure optimal control performance at stable operating conditions. of the most important
In thisperformance
paper, the criterion
BB–BC
is the difference
algorithm (error)for
is employed between the plant
the offline output
tuning of theand
PID theparameters
set point signal.
(kp, ki, Using thisHVAC
kd) in the error criterion
model.
as the fitness
Figure 3 abovefunction of thethe
shows how optimization
control unit algorithm
consisting results
of theinBB–BC
a smallunit
overshoot
and the with
PIDa controller
long settling
is
time. In general, fitness functions are based on error equations. The following
connected in the HVAC system. First, the BB–BC unit produces initial candidates for the PID four equations, integral
time absolute
parameters in error (ITAE),search
the target integral time Next,
space. squarebased
error (ITSE),
on the integral absolute
calculation of theerror (IAE), and
objective integral
function, it
square error (ISE) indicate the most commonly used fitness functions:
produces new candidate solutions around the center of mass until the stop criteria is satisfied.
In the design methodology of a PID controller, Z one of the most important performance criterion
2
is the difference (error) between the plant ISE = and
output e(t)the.dtset point signal. Using this error criterion
(10)
as the fitness function of the optimization algorithmZ
results in a small overshoot with a long settling
time. In general, fitness functions are basedI on
AE = |e(t)|.dt The following four equations, integral
error equations. (11)
time absolute error (ITAE), integral time square error (ITSE), integral absolute error (IAE), and
Z
integral square error (ISE) indicate the most
ITAEcommonly
= t.|e(usedt)|dt fitness functions: (12)
𝐼𝑆𝐸 = Z 𝑒(𝑡) . 𝑑𝑡 (10)
ITSE = t.[e(t)2 ].dt (13)

𝐼𝐴𝐸 =to the|𝑒(𝑡)|.

Fitness functions are not actually limited above𝑑𝑡equations. Engineers can provide custom (11)
fitness functions depending on the target design and control system. The overall performance
(convergence speed and optimization accuracy) |𝑒(𝑡)|𝑑𝑡
𝐼𝑇𝐴𝐸 = of𝑡.evolutionary algorithms depends on the fitness (12)
function adopted to monitor the optimization search.
𝐼𝑇𝑆𝐸 =
To choose the optimal fitness function, 𝑡. [𝑒(𝑡)
i.e., the ]. 𝑑𝑡 function of the BB–BC algorithm,
objective we
(13)
performed a set of experiments for the four typical error equations. We executed the four formulas
Fitness
of the errorsfunctions are not
(ITAE, ITSE, actually
IAE, limited
and ISE) to the above
for different equations.
number Engineers
of iterations, can provide
specifically custom
for 100, 200,
fitness
500, andfunctions depending
1000 cycles, in order on the target
to evaluate thedesign and control
performance system. The
of the objective overallInperformance
functions. the objective
(convergence
function used,speed and optimization
the added term of controlaccuracy) u T (where u T algorithms
output uof×evolutionary depends
is the transpose on the
of u) seeks to fitness
reduce
function adopted to monitor the optimization search.
 To choose the optimal fitness function, i.e., the objective function of the BB–BC algorithm, we
performed a set of experiments for the four typical error equations. We executed the four formulas
of the errors (ITAE, ITSE, IAE, and ISE) for different number of iterations, specifically for 100, 200,
500, and 2018,
Algorithms 100011,
cycles,
146 in order to evaluate the performance of the objective functions. In the objective
7 of 19
function used, the added term of control output 𝑢 × 𝑢 (where 𝑢 is the transpose of u) seeks to
reduce the magnitude of the control signal. When the objective function includes the control signal
the magnitude of the control signal. When the objective function includes the control signal term (u),
term (u), the algorithm seeks to minimize it. Therefore, the Tterm 𝑢 × 𝑢 is equivalent to squaring
the algorithm seeks to minimize it. Therefore, the term u × u is equivalent to squaring every element
every element in u. The objective function that achieved the best performance is the integral time
in u. The objective function that achieved the best performance is the integral time absolute error
absolute error (ITAE) with control signal (u) as reported below in the equation (17). The results of
(ITAE) with control signal (u) as reported below in the equation (17). The results of these experiments
these experiments are shown in Table 2.
are shown in Table 2.
Table 2. Comparison of different errors, ITAE, ITSE, IAE, ISE as performance index (fitness function).
Table 2. Comparison of different errors, ITAE, ITSE, IAE, ISE as performance index (fitness function).
Iteration No. ITAE ITSE IAE ISE
Iteration No. ITAE ITSE IAE ISE
100 5.33 × 10 2 2.47 × 1033 3.10 × 10 22 2.25 × 10 3 3
100 5.33 × 102 2 2.47 × 10 3.10 × 10 2.25 × 10
200 4.85 × 10 2.58 × 1033 2.99 × 10 22 2.24 × 10 3 3
200 4.85 × 102 2.58 × 10 2.99 × 10 2.24 × 10
500500 4.40××1010
2 2 2.62 × 10 3.46
3.46××101022 2.342.34
× 10
3 3
4.40 2.62 × 103 × 103
1000
1000 3.96××1010
3.96 2 2 2.20 × 10
2.20 × 10 3
3 2.86
2.86××101022 2.452.45
× 10
× 3103

Figure 4 presents the convergence and time response of the PID controller using the four
Figure 4 presents the convergence and time response of the PID controller using the four objective
objective functions (ITAE, ITSE, IAE, ISE) for parameters tuning for different number of iterations
functions (ITAE, ITSE, IAE, ISE) for parameters tuning for different number of iterations (100, 200,
(100, 200, 500, and 1000). The curves show how the fitness function response (error) changes during
500, and 1000). The curves show how the fitness function response (error) changes during the
the optimization process of the PID controller using BB–BC algorithm. Among the four traditional
optimization process of the PID controller using BB–BC algorithm. Among the four traditional
objective functions, the integral time absolute error (ITAE) provides the minimum settling time, peak
objective functions, the integral time absolute error (ITAE) provides the minimum settling time, peak
overshoot, and rise time.
overshoot, and rise time.
As mentioned above, any objective function can be adopted to tune the PID parameters.
As mentioned above, any objective function can be adopted to tune the PID parameters. However,
However, it is hard to reduce the rise time without increasing overshoot. By reducing the rise time,
it is hard to reduce the rise time without increasing overshoot. By reducing the rise time, the system
the system will try to follow the set-point faster, which will produce a greater inertia, thus raising the
will try to follow the set-point faster, which will produce a greater inertia, thus raising the chance of an
chance of an increased overshoot. As can be seen in Figure 4, although the response signal of ITAE
increased overshoot. As can be seen in Figure 4, although the response signal of ITAE declines faster,
declines faster, the convergence velocity of ITAE is obviously the best one compared with the other
the convergence velocity of ITAE is obviously the best one compared with the other methods. Note
methods. Note that the integral absolute error (IAE) provides the best convergence, but its time
that the integral absolute error (IAE) provides the best convergence, but its time response (overshoot,
response (overshoot, rise time, and settling time) is not optimal. Thus, in all cases (number of
rise time, and settling time) is not optimal. Thus, in all cases (number of iterations), the integral time
iterations), the integral time absolute error (ITAE) provides the best solution.
absolute error (ITAE) provides the best solution.
(a)
(a)

Figure 4. Cont.
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19

(b)
(b)

(c)
(c)

(d)
(d)

Figure 4. Convergence and time response of the widely used objective function in controller tuning
via optimization (ITAE, ITSE, IAE, ISE) for different number of iterations (a) 100, (b) 200, (c) 500 and
(d) 1000 iterations.

4. FPGA Implementation
4. FPGA Implementation of
of PID
PID Controller
Controller and
and BB–BC
BB–BC
The
The FPGA
FPGA technology
technology provides
provides anan effective
effective solution
solution inin several
several industrial
industrial control
control applications
applications
due
due to its low development cost, high flexibility, and limited power consumption, while it hasitbeen
to its low development cost, high flexibility, and limited power consumption, while has
been proved an ideal processing platform for industrial applications with real-time
proved an ideal processing platform for industrial applications with real-time constraints due to theconstraints due
to the acceleration
acceleration achieved achieved
by the by the hardware
hardware parallelism.
parallelism. In this In this we
paper, paper, we propose
propose the usethe
of use
FPGA of
FPGA technology
technology to implement
to implement the BB–BC
the BB–BC algorithm
algorithm thatthat calculates
calculates andandoptimizes
optimizesthethePID
PID control
control
parameters, (k , k , k ) in order to accelerate the control system process, which can be very effective for
parameters, (kpp, kii, kdd) in order to accelerate the control system process, which can be very effective for
latency-sensitive
latency-sensitive applications.
applications.
Algorithms 2018, 11, 146 9 of 19
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4.1.
4.1. PID
PID Controller
Controller in
in FPGA
FPGA
In
In the
the past,
past, several
several approaches
approaches have
have proposed
proposed the the use
use of FPGA technology
technology to implement
implement PIDPID
controllers
controllers [20,21] and/or
and/oroptimize
optimizethe
thePID
PIDcontroller
controllerparameters
parametersin inreal-time
real-timeindustrial
industrialapplications,
applications,
such
such as
as DC
DC motor
motor speed
speed control
control system
system [22]. In
In [23],
[23], a fuzzy logic controller has been implemented
implemented
on
on an
anFPGA
FPGAplatform
platformand validated
and on aon
validated real-time application,
a real-time namely
application, a truckabacker-upper
namely control
truck backer-upper
system.
control In [24], the
system. Inauthors
[24], thepresented
authors apresented
runtime reconfigurable PID controller
a runtime reconfigurable PIDthat can dynamically
controller that can
switch between
dynamically the different
switch betweencontroller variants,
the different e.g., variants,
controller PI, PD, PI-PD, etc.,
e.g., PI, as PI-PD,
PD, the control
etc., requirements
as the control
change.
requirements change.
Figure
Figure 55 shows
shows the
the block
block diagram
diagram of
of aa typical
typical PID
PID controller
controller FPGA
FPGA architecture
architecture based
based on
on the
the
differential
differential Equation (6) and the parameters of Table 1.

e(n) e(n-1) e(n-2)

REG_1

REG_2

u(n)

ADD
x

k5
clk
REG_3
k4 x
u(n-1)
x

k3 x
k1
REG_4

k2 x
u(n-2)

Figure 5.
Figure Blockdiagram
5. Block diagram of
of aa typical
typical PID
PID controller
controller FPGA
FPGA architecture.
architecture.

The PID
The PIDcontroller
controllerarchitecture
architectureconsists
consistsof five registers
of five blocks,
registers for storing
blocks, the current
for storing the and previous
current and
i.e., e(n), e(n − 1), e(n − 2), u(n − 1), and u(n −
previous error values, i.e., e(n), e(n − 1), e(n − 2), u(n − 1), and u(n − 2). Notice that the PID controllera
error values, 2). Notice that the PID controller has
five-stage
has pipeline
a five-stage structure
pipeline in order
structure to increase
in order clockclock
to increase frequency. Five arithmetic
frequency. multipliers
Five arithmetic are used
multipliers are
to multiply
used the proportional
to multiply part, derivative
the proportional part integral
part, derivative partintegral
part with thepart
corresponding parameters (k3 ,
with the corresponding
k4 , and k5 , respectively)
parameters (𝑘 , 𝑘 , andand 𝑘 ,the output signal
respectively) andwith 1 and ksignal
the(koutput 2 ) as described
with (𝑘 inand Table
𝑘 1, while
) as the adder
described in
finally sums all factors. Embedded DSP slices of the FPGA device are used for
Table 1, while the adder finally sums all factors. Embedded DSP slices of the FPGA device are used the implementation of
arithmetic
for multipliers and
the implementation adders in order
of arithmetic to improve
multipliers the design
and adders areatoand
in order speed.the design area and
improve
speed.
4.2. BB–BC Algorithm in FPGA
4.2. BB–BC
SeveralAlgorithm in FPGA
FPGA-based implementations of evolutionary algorithms have been presented in the
literature to accelerate the optimization process. Most of these approaches focus on the optimal
Several FPGA-based implementations of evolutionary algorithms have been presented in the
design of hardware accelerators to achieve high performance and flexibility [25,26] and satisfy other
literature to accelerate the optimization process. Most of these approaches focus on the optimal
genetic algorithm features, such as multi-objective optimization [27]. In our approach, we adopted the
design of hardware accelerators to achieve high performance and flexibility [25,26] and satisfy other
BB–BC optimization algorithm due to its low computational time and high global convergence speed.
genetic algorithm features, such as multi-objective optimization [27]. In our approach, we adopted
These features of the BB–BC algorithm mainly motivated our work, since an FPGA-based BB–BC
the BB–BC optimization algorithm due to its low computational time and high global convergence
accelerator can greatly reduce the computational time providing an ideal platform for large-scale
speed. These features of the BB–BC algorithm mainly motivated our work, since an FPGA-based BB–
adaptive or latency-sensitive optimization problems [28].
BC accelerator can greatly reduce the computational time providing an ideal platform for large-scale
In this subsection, we describe the FPGA design architecture of the BB–BC algorithm. Figure 6
adaptive or latency-sensitive optimization problems [28].
depicts the top-level design diagram of the FPGA BB–BC architecture consisting of the following blocks:
In this subsection, we describe the FPGA design architecture of the BB–BC algorithm. Figure 6
depicts the top-level design diagram of the FPGA BB–BC architecture consisting of the following
blocks:
 Algorithms2018,
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• Random Number Generation: It generates the random numbers (𝑥⃗𝑖), →i either to form an initial
• Random Number Generation: It generates
population (iteration 0) or to form new candidates around the CoM the random numbers ( x ),(iteration
either to>form 0). Aantypical
initial
population (iteration 0) or to form new candidates around
linear feedback shift register (LFSR) is used to generate random numbers based on the CoM (iteration > 0). A typical linear
a
feedback shiftseed.
configurable register
Note (LFSR)
that theis used to generate
boundaries random
of the randomnumbers
numbersbasedare ondetermined
a configurable by seed.
the
Note that
upper andthe lower boundaries
values of of the
the optimization
random numbers are determined
function variables. Inby each
the upper and lower
iteration, values
the module
of the optimization function variables. In each iteration, the module
generates N candidates sequentially, where N is the population size, with each one consisting of generates N candidates
Lsequentially,
random numbers, wherewhereN is theL ispopulation
the numbersize, with each
of features one candidate.
of each consisting The of Lgenerated
random numbers,
random
numbers of each iteration are stored in a RAM in order to be processed later fornumbers
where L is the number of features of each candidate. The generated random of each
the calculation
iteration are
of center of mass. stored in a RAM in order to be processed later for the calculation of center of mass.
•• ObjectiveFunction:
Objective Function:After Afterthetherandom
randomnumber numbergeneration,
generation,this thismodule
modulecalculates
calculatesthe theobjective
objective
→ i
function
function(𝑓 ( f )i )for
foreach
eachcandidate
candidate(𝑥 (⃗x) )using
usingthe theITAE
ITAEequation,
equation,whichwhichisisalsoalsostored
storedininthetheRAM.
RAM.
Both the random number generation and objective function
Both the random number generation and objective function modules have been implemented modules have been implemented
following
following aa simple,
simple, serial
serialprocessing
processingmodel, model,wherewhere a single
a single element
element is processed
is processed in each
in each clockclock
cycle,
cycle, providing a low-cost FPGA circuit. Note that both modules
providing a low-cost FPGA circuit. Note that both modules can be parallelized (i.e., to generate can be parallelized (i.e., to
generate
the random the numbers
random numbers
and calculate and thecalculate
objectivethe functions
objective concurrently
functions concurrently
using many using many
processing
processing elements
elements working working and
in parallel) in parallel)
pipelinedand pipelined
in order in order
to improve to improveasperformance,
performance, proposed in [28]. as
• proposed in [28].
Calculate Center of Mass: It reads the candidates and their objective function values from the
• Calculate
RAM andCenter calculates of Mass: It reads
the center the candidates
of mass and their objective
which is forwarded function
in the random valuesgeneration
number from the
RAM and calculates the center of mass which
module to generate the population in the next iteration cycle. is forwarded in the random number generation
• module
EvaluatetoFunction:
generate It the population
reads in thefunction
the objective next iteration
valuescycle.
of the candidates from the RAM in order
• Evaluate
to select the best fitness candidate which is store in RAM the
Function: It reads the objective function values of too,candidates from thesignal
and from output RAMwhen in orderthe
to select the best fitness
FPGA-BBBC control the HVAC model. candidate which is store in RAM too, and from output signal when the
FPGA-BBBC control the HVAC model.
• Control Unit: It orchestrates the operation of the other modules and repeats the BB–BC steps until
• Control Unit: It orchestrates the operation of the other modules and repeats the BB–BC steps
the stopping criteria are met.
until the stopping criteria are met.
• Solution: It includes a register that stores the outcome of the BB–BC algorithm.
• Solution: It includes a register that stores the outcome of the BB–BC algorithm.

Random
Number
Generation
FPGA Environment

Objective X(i)
function
Control unit

Calculate
Center of Mass
Optimal
solution
Evaluate
function RAM

Solution

Figure
Figure6.6.Top-level
Top-leveldiagram
diagramof
ofthe
theBB–BC
BB–BCFPGA
FPGAarchitecture.
architecture.
 Algorithms 2018, 11, 146 11 of 19
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Note
Note that a high-performance
that a high-performance FPGA
FPGA architecture of of
architecture BB–BC
BB–BC algorithm
algorithmhas been
has beenpresented
presentedin in
[28]
[28]
which
whichincorporates
incorporates parallel pipelined
parallel pipelinedengines to accelerate
engines the execution
to accelerate of BB–BC.
the execution This FPGA
of BB–BC. BB–
This FPGA
BCBB–BC
architecture has been
architecture optimized
has been in terms
optimized of execution
in terms latency
of execution andand
latency is very suitable
is very forfor
suitable control
control
applications with strict real-time requirements. However, this performance
applications with strict real-time requirements. However, this performance optimization has optimization has been
been
achieved
achievedat at
thethe
expense
expense of of
extra hardware
extra hardware area and
area andpower
power consumption.
consumption. Thus,
Thus,thethe
optimized
optimizedFPGA
FPGA
architecture
architecture ofof
[28] is is
[28] suggested
suggested only
onlyforfor
time
timesensitive
sensitivecontrol
controlapplications.
applications.
Table
Table 3 presents
3 presents the device
the utilization
device utilization summary
summary onon
a Xilinx
a XilinxZynq
ZynqXC7Z010
XC7Z010FPGAFPGAdevice.
device.

Table 3. Device
Table utilization
3. Device summary
utilization of of
summary thethe
PID controller
PID onon
controller a Xilinx Zynq
a Xilinx FPGA
Zynq device
FPGA device

Logic Utilization
Logic Utilization Used
Used Available
AvailableUtilization
Utilization
Number of SliceRegisters
Number of Slice Registers 306
306 54576
54,576 0% 0%
Number of Slice
Number of SliceLUTs
LUTs 16998
16,998 27288
27,288 62%62%
Number of
Number of Block
BlockRAM/FIFO
RAM/FIFO 22 116 116 1% 1%
Number of
Number of DSP48A1s
DSP48A1s 5454 58 58 93%93%

4.3.
4.3. FPGA-In-The-Loop
FPGA-In-The-Loop (FIL)
(FIL)
MATLAB/Simulink
MATLAB/Simulink is aishigh-level
a high-level language
language andand interactive
interactive environment
environment highly
highly popular
popular among
among
system
system and
and algorithm
algorithm designers
designers for for
many many different
different real-world
real-world applications
applications and research
and research topics.topics.
To
To accommodate developers to interface with real hardware (e.g.,
accommodate developers to interface with real hardware (e.g., components implemented in FPGAcomponents implemented in FPGA
devices), MathWorks ® presented the FPGA-in-the-loop (FIL) concept. Based on this idea, data can be
devices), MathWorks ® presented the FPGA-in-the-loop (FIL) concept. Based on this idea, data can be
exchanged
exchanged between
between thethe MATLAB/Simulink
MATLAB/Simulink modules
modules and andthethe FPGA
FPGA device.
device. FILFIL scheme
scheme cancan
bebe used
used
for multiple tasks while designing, evaluating, and verifying designs. For example, it can be used to to
for multiple tasks while designing, evaluating, and verifying designs. For example, it can be used
configureand
configure andtune
tune FPGA
FPGA design designparameters
parameters at runtime,
at runtime, suchsuch
as tuning data pipe
as tuning datagains
pipeand modifying
gains and
modifying filter parameters [29], or to monitor hardware components by reading specific status at
filter parameters [29], or to monitor hardware components by reading specific status registers
runtime.
registers Another Another
at runtime. powerfulpowerfulcapability of the FIL
capability of approach is that allows
the FIL approach is that the generation
allows of complex
the generation of
stimulus
complex datasetsdatasets
stimulus on the host PC host
on the and rapid
PC and download to the FPGA
rapid download target
to the FPGA in real timein[29].
target realBytimeusing
[29].the
ByFIL approach
using the FILand connecting
approach the hardware
and connecting thetarget via some
hardware targetcommon
via some protocol
common interface
protocol(e.g., Ethernet
interface
or JTAG),
(e.g., Ethernetoneorcan obtain
JTAG), onesignificant
can obtain improvements in simulation runtime
significant improvements compared
in simulation to cycle-accurate
runtime compared
to host simulation.host simulation.
cycle-accurate
AsAs shown
shown in in Section
Section 5, 5,
thethe proposed
proposed approach
approach in in conjunction
conjunction with
with thethe
FIL FIL technique
technique achieves
achieves a a
speedupofofaround
speedup around253X 253X compared
compared to tothe
theMATLAB
MATLAB 2015b
2015b software
software simulation.
simulation. Moreover,
Moreover,whenwhendesign
complexity increases, the advantages of the FIL methodology over software
design complexity increases, the advantages of the FIL methodology over software simulation at simulation at runtime will
be more
runtime evident.
will be more Figure
evident.7 presents
Figure 7the structure
presents theof the FIL acceleration
structure scheme used
of the FIL acceleration in our
scheme system,
used in
where
our MATLAB/Simulink
system, where MATLAB/Simulink provides the user with
provides a working
the user with aenvironment.
working environment.

Comparison module in
Matlab

Matlab Environment Scope JTAG

Results Viewer

Script Simulink
file model

JTAG FPGA

Figure 7. FPGA-in-the-loop (FIL) acceleration scheme.

Figure 7. FPGA-in-the-loop (FIL) acceleration scheme.
Algorithms 2018, 11, 146 12 of 19

4.4. System Architecture

Algorithms 2018, 11, x FOR PEER REVIEW 12 of 19
The FPGA design consisting of the PID controller and the BB–BC algorithm is written in VHDL
4.4. System
hardware Architecture
description language and implemented in a Xilinx development platform, Zybo–7010 board,
using the Xilinx ISEdesign
The FPGA Design Suite 14.7
consisting and
of the Vivado
PID Design
controller Suite.
and the BB–BCFigure 8 depicts
algorithm thein
is written entire
VHDL system
architecture
hardwareincluding the FPGA
description device
language and and the HVAC
implemented in model
a Xilinximplemented
development in MATLAB
platform, environment.
Zybo–7010
board, using
The processing the of
steps Xilinx
the ISE Design architecture
proposed Suite 14.7 andare
Vivado Design
shortly Suite. Figure
described below.8 depicts the entire
system architecture including the FPGA device and the HVAC model implemented in MATLAB
(1) The FPGA BB–BC
environment. module generates
The processing steps of thea proposed
set of random PID parameters
architecture (kp , ki , kd ),below.
are shortly described either to form the
initial candidate or the new candidate around the center of mass in the next iteration cycles.
(1) The FPGA BB–BC module generates a set of random PID parameters (kp, ki, kd), either to form the
(2) The FPGA PID controller
initial candidate or the newmodule
candidate receives
around thethecenter
values of the
of mass parameters
in the next iteration and controls the
cycles.
HVAC
(2) The plant.
FPGA PID controller module receives the values of the parameters and controls the HVAC
(3) The FPGA
plant. BB–BC module calculates the fitness functions for this candidate (i.e., PID parameters)
(3)
usingThe theFPGA ITAEBB–BC module
equation andcalculates the fitness
then calculates functions
the for this
new center ofcandidate
mass. (i.e., PID parameters)
(4) using the ITAE equation
The HVAC model runs for a short period. and then calculates the new center of mass.
(4) The HVAC model runs for a short period.
(5) The evaluate function checks the system output and decides whether the BB–BC module must
(5) The evaluate function checks the system output and decides whether the BB–BC module must
re-run to improve
re-run to improve system
systemperformance,
performance, i.e., whenthe
i.e., when thesystem
system hashas
been been affected
affected by external
by external
disturbances
disturbances thatthat
cause thethe
cause output
outputto toexceed somepredefined
exceed some predefined thresholds.
thresholds. NoteNotethat we thatuse
wetheuse the
HVAC HVAC plantplant as aaspart of the
a part FPGA
of the FPGABBBC BBBC module
module to toproduce
produce thethe first
first optimization
optimization parameters
parameters
(kp , ki(k
, kp,dk)i,of
kd)the
of the
PIDPID controllerfor
controller for the
the HVAC
HVACmodel modelininthe first
the run.run.
first

FPGA Platform Matlab

PID Controller & HVAC Plant HVAC System output

kp ki kd Model

BB-BC Engine - Data

Sum
Conversion
+
Set-Point
Evaluate
function

Figure8.8.Proposed
Figure Proposed system
systemarchitecture.
architecture.

GivenGiven thatevolutionary
that the the evolutionary algorithmsconsume
algorithms consume enough
enoughtime
time to to
reach the the
reach optimal solution,
optimal even even
solution,
when the number of iterations is small, they are not suitable for latency-sensitive applications in real
when the number of iterations is small, they are not suitable for latency-sensitive applications in real
time. However, accelerating the evolutionary algorithm using an FPGA-based platform, as in the case
time. However, accelerating the evolutionary algorithm using an FPGA-based platform, as in the case
of FPGA-in-the-loop (FIL) paradigm, can reduce the execution time and achieve the convergence into
of FPGA-in-the-loop (FIL)
the optimal solution paradigm,
under specific can reduce
timing the execution
constraints. time
Therefore, and achieveBB–BC
the FPGA-based the convergence
algorithm into
the optimal
can be executed much faster, fact that improves confidence that the target optimization algorithmalgorithm
solution under specific timing constraints. Therefore, the FPGA-based BB–BC can
can befinally
executed much
satisfy faster, fact
the real-time that improves
requirements confidence
of an industrial that the target optimization algorithm can
application.
The the
finally satisfy totalreal-time
executionrequirements
time of the MATLAB/Simulink model (𝑇 ) incorporates the MATLAB
of an industrial application.
processing time, the FPGA execution time and
The total execution time of the MATLAB/Simulink model the time required for(Tthe data exchange between the
MS ) incorporates the MATLAB
host PC and the FPGA board and is given by the equation
processing time, the FPGA execution time and the time required for the data exchange between the
host PC and the FPGA board and𝑇is given = 𝑇 by + the
𝑇 equation
+ (𝑇 )+ 𝑇 (14)
where 𝑇 is total executionTtime = of the
TMPMATLAB/Simulink
+ TM2F + ( TFPGAmodel, 𝑇
) + TF2M is the MATLAB processing (14)
MS
time, 𝑇 is the time required for transferring data from MATLAB to FPGA platform, 𝑇 is the
whereFPGA
TMS isprocessing time, and
total execution 𝑇 of is
time thetheMATLAB/Simulink
time required for copying dataTfrom
model, MP isFPGA platform to
the MATLAB the
processing
MATLAB/Simulink
time, T environment.
is the time required for transferring data from MATLAB to FPGA platform, T is the
M2F FPGA
FPGA processing time, and TF2M is the time required for copying data from FPGA platform to the
MATLAB/Simulink environment.
Algorithms 2018, 11, 146 13 of 19

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Assuming population size N and number of iterations M, the total execution time (TFPGA ) of the
Assuming
proposed FPGA population sizeisNgiven
BB–BC circuit and number
by the of iterations M, the total execution time (𝑇
equation ) of the
proposed FPGA BB–BC circuit is given by the equation
TFPGA = M × N × ( TCG + TFC + TCOM + TPID+ Plant ) (15)
𝑇 = 𝑀 × 𝑁 × (𝑇 + 𝑇 + 𝑇 +𝑇 ) (15)
whereTCG
where 𝑇 , ,T
𝑇FC,,𝑇TCOMare arethe
thelatencies
latenciesofof the
the FPGA
FPGA BB–BC
BB–BC stages,
stages, i.e.,i.e., candidate
candidate generation,
generation, fitnessfitness
function calculation, and center of mass calculation, respectively
function calculation, and center of mass calculation, respectively and PID and T 𝑇 + Plant is the latency ofFPGA
is the latency of
PID controller and the plant.
FPGA PID controller and the plant.
Figure
Figure9 shows
9 shows thethe
top-level
top-level diagram
diagram of of
our MATLAB/Simulink
our MATLAB/Simulinkmodel, model,which
whichincludes
includesthetheFPGA
BB–BC/PID modulemodule
FPGA BB–BC/PID (using(using
the FIL concept),
the the HVAC
FIL concept), module,
the HVAC an analog-to-digital
module, converter
an analog-to-digital converterto feed
to feed the digital error value into the FPGA BB–BC module, an digital-to-analog converter
the digital error value into the FPGA BB–BC module, an digital-to-analog converter to provide the PID to provide
the PID controller
controller output tooutput
the HVACto themodel,
HVAC an model,
adder anto
adder to calculate
calculate the and
the error errorthe
andset
thepoint.
set point.

FPGA-In-the-Loop

+
10 A/D BBBC-PID Controller D/A HVAC
-
Sum Scope
Set-point

Data type convertor

Figure 9.
Figure 9. Block
Blockdiagram
diagramofofour
ourMATLAB/Simulink
MATLAB/Simulinkmodel.
model.

5. 5.Experiments
Experimentson
onthe
the HVAC
HVAC system
system
Theefficiency
The efficiency of
of the
the proposed
proposed approach
approachwaswasdemonstrated
demonstrated by by
a set of experimental
a set tests tests
of experimental
performed over a second order system with two seconds
performed over a second order system with two seconds delay. delay.
InInour
ourcase
case study
study (HVAC)
(HVAC)simulation experiments,
simulation we observed
experiments, that, when
we observed that, BB–BC runs andruns
when BB–BC the and
error value is calculated in the beginning, the plant output becomes equals to set point, while when
the error value is calculated in the beginning, the plant output becomes equals to set point, while
the optimal values for 𝑘 , 𝑘 , and 𝑘 are used to calculate the current plant output, the plant output
when the optimal values for k P , k i , and k d are used to calculate the current plant output, the plant
equals the set point when error reaches near to zero, hence plant starts running at the set point. The
output equals the set point when error reaches near to zero, hence plant starts running at the set point.
final outputs of the proposed design are the optimized PID controller parameters (𝑘 , 𝑘 , 𝑘 ) used
The final outputs of the proposed design are the optimized PID controller parameters (k P , k i , kthe
in the HVAC control system. The experiments showed that our approach considerably reduces d ) used
inovershoot
the HVAC control
value system.
without The experiments
compromising showed
the latency that our
sensitivity approach
compared considerably
to the reduces the
genetic and particle
overshoot value without compromising the latency sensitivity compared to the genetic and
swarm optimization algorithms where the desired overshoot is not considered, even when the error particle
swarm optimization
and response time isalgorithms where the desired overshoot is not considered, even when the error
reduced [30].
and response time is reduced [30].
5.1. Experimental Setup
5.1. Experimental Setup
In the HVAC systems, the air pressure supplier is regulated by the speed of the air fan.
In the HVAC
Increasing the fansystems,
speed wethe air pressure
manage supplier
to increase is regulated
the supply by the
air pressure, speed
and of the The
vice versa. air fan. Increasing
dynamics
system
the from the
fan speed wecontrol
manage signal output u(t)
to increase thethat providing
supply to the fanand
air pressure, variable speed drive
vice versa. to the supply
The dynamics system
air pressure
from can signal
the control be modeled
output asu(t)
a second-order added
that providing time-delay
to the system.
fan variable The process
speed drive toresponse is air
the supply
shown in Figure 3. For our experiments, we have adopted the HVAC model proposed
pressure can be modeled as a second-order added time-delay system. The process response is shown in in [14]. In [14],
the authors
Figure derived
3. For our this HVAC
experiments, wemodel after various
have adopted experimental
the HVAC model tests on supply
proposed airInpressure
in [14]. [14], theand
authors
room pressure in an HVAC pilot. Thus, our target system is an HVAC model using
derived this HVAC model after various experimental tests on supply air pressure and room pressure the transfer
function
in an HVAC pilot. Thus, our target system is an HVAC model using the transfer function
𝑒
𝐺( ) = e−2s + 1.24 (16)
G(s) 0.12𝑠
= + 1.33𝑠 (16)
0.12s2 + 1.33s + 1.24
The system response performance criterion used as objective function in our optimization
The system
algorithm response
is the integral performance
time absolute errorcriterion used
(ITAE) plus theas objective
control signalfunction
(u) given in
by our optimization
the formula
algorithm is the integral time absolute error (ITAE) plus the control signal (u) given by the formula
𝐼𝑇𝐴𝐸 = Z𝑡. |𝑒(𝑡)|𝑑𝑡 + 𝑢 ∗ 𝑢 (17)
ITAE = t.|e(t)|dt + u T ∗ u (17)
Algorithms 2018, 11, x FOR PEER REVIEW 14 of 19

Note2018,
Algorithms that11,integral
146 time absolute error (ITAE) is widely used in control processing since14 itof is
19
simple to implement and natural to define energy of a signal, which possesses symmetry and
differentiability.
Note that integral time absolute error (ITAE) is widely used in control processing since it is simple
to implement and natural
5.2. System Performance andtoConvergence
define energy of a signal, which possesses symmetry and differentiability.

5.2. System Performance

In order and the
to evaluate Convergence
robustness of the proposed approach against other optimization
methods we simulated our HVAC model running: (i) BB–BC algorithm in MATLAB sw, (ii) BB–BC
In order to evaluate the robustness of the proposed approach against other optimization methods
in FPGA (our approach), (iii) PSO method in MATLAB sw and (iv) GA in MATLAB sw. The
we simulated our HVAC model running: (i) BB–BC algorithm in MATLAB sw, (ii) BB–BC in FPGA (our
simulation is performed for different number of iterations (M = 100, 200, 500, 1000) and the results
approach), (iii) PSO method in MATLAB sw and (iv) GA in MATLAB sw. The simulation is performed
are illustrated in Figure 10.
for different number of iterations (M = 100, 200, 500, 1000) and the results are illustrated in Figure 10.

(a) (b)

(c) (d)

Figure
Figure 10.
10. Time
Time responses
responses ofof four
four optimization
optimization methods
methods (BBBC,
(BBBC, BBBC-FPGA,
BBBC-FPGA, PSO,
PSO, GA)
GA) for
for different
different
number
number of
of iterations
iterations (a,
(a, b,
b, c,
c, and
and d for 100, 200, 500, and 1000 iterations, respectively).

The BB–BC,
The BB–BC,PSO, PSO,andandGAGAmodels
models run
run in in a Core
a Core i7-3612QM@
i7-3612QM@ 2.10 2.10
GHzGHz (64-bit)
(64-bit) processor.
processor. The
The transient
transient performance
performance measured
measured in seconds
in seconds is presented
is presented in Table 4,inwhile
TableFigure
4, while Figurethe
11 shows 11control
shows
the control
system system
action, action, output,
i.e., system i.e., system output,
control signal,control
error, signal, error, and
and objective objective
function function
for all for all
optimization
optimization
methods, methods,
assuming assuming
population population
size (N = 10) andsizenumber
(N = 10)ofand number
iterations (Mof=iterations
100). As it(M
can= be
100). As it
clearly,
canBBBC-FPGA
the be clearly, theapproach
BBBC-FPGA approach
is more robust is more robust
compared compared
to both PSO and to both PSO and GA approaches.
GA approaches.

Table 4.
Table Transient performance comparison.
4. Transient

PID Parameters
PID Parameters
Method
Method Os%
Os % Ts
Ts Tr
Tr
kpk p kki i kdd
k
BBBC
BBBC 0.205 0.063
0.205 0.063 0.046
0.046 0.505
0.505 8.632
8.632 7.708
7.708
BBBC-FPGA
BBBC-FPGA 0.236
0.236 0.076
0.076 0.020
0.020 0.505
0.505 9.498
9.498 7.959
7.959
GA 0.341 0.154 0.014 0.493 23.196 14.014
GA 0.341 0.154 0.014 0.493 23.196 14.014
PSO 0.479 0.217 0.006 0.499 15.430 9.364
Algorithms 2018, 11, x FOR PEER REVIEW 15 of 19
Algorithms 2018, 11, x FOR PEER REVIEW 15 of 19

Algorithms 2018, 11, 146

PSO 0.479 0.217 0.006 0.499 15.430 9.364 15 of 19
PSO 0.479 0.217 0.006 0.499 15.430 9.364

(a) (b)
(a) (b)

(c) (d)
(c) (d)

Figure 11. The (a) system output, (b) control signal, (c) error signal, and (d) objective function for all
Figure 11. The
Figure 11. The (a)
(a) system
system output,
output, (b)
(b) control
control signal,
signal, (c)
(c) error
error signal,
signal, and
and (d)
(d)objective
objective function
function for
for all
all
four
four optimization methods.
four optimization
optimizationmethods.
methods.
Figure
Figure 12
12 shows
shows the
the best
best values
values of
of objective
objective function
function per
per iteration
iteration for
for all
all four
four optimization
optimization
Figure 12 shows the best values of objective function per iteration for all four optimization
algorithms
algorithms for
for different
different number
number ofof iterations.
iterations. In
In all
all cases,
cases, BBBC
BBBC and
and BBBC-FPGA
BBBC-FPGA converge
converge faster
faster
algorithms for different number of iterations. In all cases, BBBC and BBBC-FPGA converge faster
(locally minima) than GA and PSO, mostly expected from the BB–BC algorithm
(locally minima) than GA and PSO, mostly expected from the BB–BC algorithm literature. literature.
(locally minima) than GA and PSO, mostly expected from the BB–BC algorithm literature.

(a) (b)
(a) (b)

Figure 12. Cont.

 Algorithms2018,
Algorithms 11,x146
2018,11, FOR PEER REVIEW 16ofof19
16 19
Algorithms 2018, 11, x FOR PEER REVIEW 16 of 19

(c) (d)
(c) (d)

Figure
Figure12.
Figure 12.Objective
12. Objectivefunction
Objective functionconvergence
function convergencefor
convergence forall
for allfour
all fouroptimization
four optimizationmethods
optimization methodsand
methods andfor
and fordifferent
for differentnumber
different number
number
of iterations
of iterations
of (a,
iterations (a, b,
(a, b, c,
b, c, and d for
and dd for
c, and 100,
for 100, 200,
100, 200, 500,
200, 500, and
500, and 1000
and 1000 iterations,
1000 iterations, respectively).
iterations, respectively).
respectively).

With aa new
With With newa run
run of
new run
of all
allofoptimization methods,
all optimization
optimization Table
methods,
methods, 55 and
Table
Table Figure
5 and
and 13
Figure
Figure provide
1313 provide
provide more
moredetails
more detailsabout
details aboutthe
about the
the
objective
objectivefunction
objective functionconvergence
function convergencepresented
convergence presentedon
presented onFigure
on Figure12
Figure 12including
12 includingthe
including thenumber
the numberof
number ofiterations,
of iterations,the
iterations, thesteady
the steady
steady
state
state time (SST) and the running time assuming population size (N) equals 10 and number of
state time (SST)
(SST) and
and thethe running
running time
time assuming
assuming population
population size size
(N) (N)
equals equals
10 and 10 and
number number
of iterations
of
iterations
(M) equals(M) equals
100.
iterations (M) equals 100.100.

Objective functionconvergence
Table 5. Objective
Table convergence details(iterations
(iterations andexecution
execution time) for
for all four
four
Table 5.
5. Objective function
function convergence details
details (iterations and
and execution time)
time) for all
all four
optimizationmethods
optimization methods
optimization methods
Tuning
Tuning Method
Tuning Method Convergence
Method Convergence Iteration
Convergence Iteration Steady
Iteration State
Steady
Steady StateTime
State Time(s)
Time (s) Running
(s) RunningTime
Running Time (s)
Time (s)
(s)
BBBC
BBBC
BBBC 22 2 10.642
10.642
10.642 4.061
4.061
4.061
BBBC-FPGA
BBBC-FPGA
BBBC-FPGA 22 2 11.456
11.456
11.456 0.016
0.016
0.016
GA GA 73 73 25.116
25.116 6.887
6.887
GAPSO 73 2 25.116
19.440 6.887
8.634
PSO
PSO 22 19.440
19.440 8.634
8.634

Figure 13. Objective function convergence for all four optimization methods.
Figure
Figure 13.
13. Objective
Objective function
function convergence
convergence for
for all
all four
four optimization
optimization methods.
methods.
5.3. Computation Time
5.3.
5.3. Computation
Computation Time
Time the computation time of the proposed approach (BBBC-FPGA) with GA and
Table 6 compares
BB–BC implemented
Table
Table comparesin
66 compares thesoftware
the (MATLAB
computation
computation time model).
time of
of the The proposed
the proposed
proposed approach
approach
approach achieveswith
(BBBC-FPGA)
(BBBC-FPGA) a speedup
with GA
GA andof
and
more
BB–BC than 428X
implementedcompared
in to
softwarethe GA (in
(MATLAB sw) approach
model). Theand more
proposed than 253X
approach compared
achieves
BB–BC implemented in software (MATLAB model). The proposed approach achieves a speedup of a to the
speedupBBBC
of
(in sw)
more
more approach.
than
than 428X
428X compared
compared to to the
the GA
GA (in
(in sw)
sw) approach
approach andand more
more than
than 253X
253X compared
compared toto the
the BBBC
BBBC
(in
(in sw)
sw) approach.
approach.
Algorithms 2018, 11, 146 17 of 19

Table 6. Computation time in (s) for GA, BBBC (in sw), and BBBC-FPGA (proposed approach)

BBBC-FPGA
M GA Mat sw BBBC Mat sw
Exec. Time Speedup vs. GA Speedup vs. BBBC
100 6.887 4.061 0.016 430 253
200 12.008 7.990 0.028 428 258
500 28.728 18.023 0.065 441 277
1000 59.205 40.302 0.140 422 287

6. Conclusions
In this paper, we presented a novel technique for the fast tuning of the parameters of the PID
controller of a second-order heat, ventilation, and air conditioning (HVAC) system using a low-cost,
fast-convergent optimization algorithm, called Big Bang–Big Crunch (BB–BC). To further accelerate
the optimization process, we proposed the implementation of both the BB–BC algorithm and the PID
controller using FPGA technology. In order to emulate and evaluate the entire system we adopted
the FPGA-in-the-loop (FIL) technique, according to which, the plant (i.e., MATLAB/Simulink model
of HVAC) is connected to the FPGA board (i.e., the PID and BB–BC modules). To demonstrate the
efficiency of the proposed approach, we run an extensive set of experiments in a second-order HVAC
model using different optimization methods (BB–BC in FPGA, BB–BC in sw, GA, and PSO in sw). The
experimental results proved the benefits of the proposed approach against the other methods in terms
of convergence speed and computation time.

Author Contributions: The contributions of all authors are equals. All authors have worked together to develop
and approved the manuscript. A.D., M.P. are the research advisors, who helped in proofreading and improving
the quality of the final version of the manuscript.
Acknowledgments: The gratefully acknowledges the helpful comments and suggestions of both reviewers, which
have improved the manuscript. As well
Conflicts of Interest: The authors declare no conflict of interest.

Abbreviations
ADD Adder
BB-BC Big Bang-Big Crunch
Clk Clock
CoM Center of Mass
DE Deferential Equation
FIL Field programmable gate array in the Loop
FPGA Field Programmable Gate Array
GA Genetic Algorithm
HVAC Heat Ventilation Air Condition
IAE Integrated Absolute Error
ISE Integrated Square Error
ITAE Integrated Time Absolute Error
ITSE Integrated Time-weighted Square Error
PID Proportional Integrating Derivative
PSO Particle Swarm Optimization
RandGen Random Generator
REG Register
RT Running Time
RTL Register Transfer Level
SST Steady State Time
VHDL Very High Speed Integrated Circuit Hardware Description Language
Algorithms 2018, 11, 146 18 of 19

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