52f2c Foxconn 945P01 PC Mainboard Schematics

5 4 3 2 1
Page Title of Schematic :

945P01 Rev : 0B D
Page
Title Intel (R) Lakeport-G + ICH7 Chipset
Index Page 1 Intel LGA775 Processor
Topology 2
Reset Map 3
Form Factor Pico BTX
Clock Distribution 4
Power Delivery Map 5 CPU Intel LGA775
Power Sequence 6
System Chipset Intel Lakeport-G (North Bridge)
GPIO / IRQ / IDSEL Map 7 Intel ICH7 (South Bridge)
LGA775 -1 8
On Board Chipset BIOS -- FWH EEPROM
LGA775 -2 9 Codec -- ALC880
LPC Super I/O -- ITE8712F/IX
ICS954128 Clock Gen 10
Remark LAN --Marvell 88E8052
C ACPI Voltage Regulator 11 CLOCK --ICS954128 C
1394--TI TSB43AB22
Lakeport -GMCH -1 12 "Dummy" -> No Stuff
Lakeport -GMCH -2 13 Main Memory 2 DIMM,Dual-Channel DDR2
Lakeport -GMCH -3 14
Expansion Slots PCI Slot * 1
DDR2 Channel A DIMM1 15 Fab A: (Connector) PCI-E X16 Slot * 1
IDE Slot * 1
DDR2 Channel B DIMM2 16 945G SATA Connector * 2 (Two Master)
PCI & PCI-E x16 Slot 17 ICH7 USB Connector * 8 (4 ports on board and 4 ports on Rear I/O)
1394 Connector (1 port on board and 1 port on Rear I/O)
ICH7 -1_DIM,PCI-E,USB,MISC 18
Front Panel, Front Audio, SPDIF-Out, TPM, CD_IN, IrDA, Recovery,
ICH7 -2_IDE,SATA,CPU,FWH 19 Case-Open, WOL, AUX_IN,
FAN Connector (CPUFAN1, CPUFAN2)
ICH7 -3_PCI,Power/ Gnd,FWH 20
MARVELL 88E8052 LAN 21 PWM For CPU VCORE Controller--ISL6561+ISL6614A+ISL6612
ALC880 Azalia Audio-1 22 For 1D5V_CORE Controller--RT9214PS
ALC880 Azalia Audio-2 23
B
Front I/O connector---3 USB ports B
Power / MISC Connectors 24 1 headphone out
SMSC 47M182 SIO KB/MS/FAN 25 1 microphone in
SKU1(8EKS) Rear I/O connectors--1 PS/2 keyboard port, 1 PS/2 mouse port
VGA & Serial / Parallel Con 26
1 VGA, 1 Parallel port, 1 Serial port
TI TSB43AB22 1394 27 2 USB ports + RJ45 port
1394 & Rear-LANUSB Conn 28 6 audio jacks (7.1 HD audio jack)
IEEE 1394 port
VRD10.1 Intersil ISL6561 29
Front I/O connector---4 USB ports
Modify List 30 1 headphone out
SKU1(8KS) 1 microphone in
Rear I/O connectors--1 PS/2 keyboard port, 1 PS/2 mouse port
1 VGA, 1 Parallel port, 1 Serial port
2 USB ports + RJ45 port
6 audio jacks (7.1 HD audio jack)
4 USB ports
A A
FOXCONN PCEG
Title
Index Page
Size Document Number Rev
C 945P01 A
Date: Wednesday, July 20, 2005 Sheet 1 of 30

5 4 3 2 1
5 4 3 2 1
Prescott, Smithfield &

Cedar Mill
VRD 10.1 LGA775 Processor
4 Phase PWM
D Socket T D
For Intel 2005A & Intel 2004B

1066/800/533 FSB
CK-410 Clock
PCI Express x 16 Channel A DDR2

PCI Express x16 Port DDR2 533/667
External Graphics
DIMM1
Card
DIMM2
GMCH DDR2 533/667 Channel B DDR2

VGA Connector
Lakeport DIMM2
C C
Back Panel
USB2.0 Port 1 PCI Express x1 Interface LAN
4 Lanes
USB2.0 Port 2 MARVELL 88E8052
Direct Media Interface (DMI)
USB2.0 Port 3
USB2.0 Port 4
PCI Slot 1
ICH7RW
TI TSB43AB22 1394
Front Panel
USB2.0 Port 5
B
USB2.0 Port 6 B
Header Serial ATA
LPC I/F
SATA Connector 1
USB2.0 Port 7 AHCI, RAID0,1,5,10
ATA100
USB2.0 Port 8 IDE CONN 1 SATA Connector 2
LPC I/F Intel HD Audio

Super I/O Realtek ALC880
IT8712F 8 Channels W/ SPDIF-Out
Firmware HUB
4Mb or 8Mb
PS2 Parallel TPM HEADER
Keyboard / Mouse Serial
A A
FOXCONN PCEG
Title
Topology
C 945P01 A
Date: Monday, June 13, 2005 Sheet 2 of 30

5 4 3 2 1
5 4 3 2 1
CPU (Tejas / Prescott)
CPU_PWRGD
CPURST#
D
LGA775 processor D
ATX
Power
PWRGD_3V
PWRGD_PS SIO PWROK CPURST#
PS_ON# Translation
Circuitry GMCH PCI Slost
Lakeport
C
RSTIN# C
TI 1394
ICH7RW
ICH_PWRGD
Marvell LAN
PCIRST#
PLTRST# PCI Express x16

SIO
Front Panel Buffer
PWROK
ATA100
IDE CONN 1
FR_RST SYS_RESET#
B B
SW_ON PWRBTN# AC_RST#
RSMRST#
RST# Audio
RCIN# RST#
SLP_S3# FWH
RST#
TPM
RST#
Power on/off KBRST
circuit RSMRST#
Super IO
SLP_S3#
PSIN
A A
PSOUT#
FOXCONN PCEG
Title
Reset Map
C 945P01 A

5 4 3 2 1
5 4 3 2 1
14.318MHz
CPU XDP
D
CPU 133/200/266 MHz Diff Pair D
XDP 133/200 MHz Diff Pair

MCH 133/200 MHz Diff Pair
DDR2 2 Slots 12 Diff CLKs

PCI Express 100 MHz Diff Pair
PCI Express x16 Gfx Channel A DDR2
GMCH DIMM1
DOT 96 MHz Diff Pair Lakeport DIMM2
Channel B DDR2
DIMM2
PCI Express/DMI 100 MHz Diff Pair
C C
CK-410
PCI Express/DMI 100 MHz Diff Pair
USB/SIO 48 MHz
ICH 33 MHz
REF 14 MHz
FWH 33 MHz FWH

ICH7RW
PCI 33 MHz PCI Slot 1 Azalia Bit Clock
B
PCI 33 MHz IEEE 1394 B
32.768KHz
PCI Express 100 Mhz Diff Pair MARVELL
88E8052 LAN
HD Audio
SIO 14 MHz Super I/O
SATA 100 MHz Diff Pair
A A
TPM 33 MHz TPM
FOXCONN PCEG
Title
CLOCK Distribution
C 945P01 A

5 4 3 2 1
5 4 3 2 1
Voltage Distribution
12V : 12V_SYS 3.3VSB : 3D3V_SB Super I/O
5V : 5V_SYS 1.8VSB : VCC1_8SB
3.3V 3.3V
3.3V : 3D3V_SYS 1.8V for DDR-II : 1_8VSTR
Icc(Max)=50mA
5VSB : 5V_SB_SYS 0.9VTT for DDR-II : VTT_DDR Proceessor
-12V : -12V_SYS 1.5V for ICH and GMCH core : 1D5V_CORE Vccp (CPU Vcore) 3.3SBV
VRD 10.1
for CPU : VCCP 5V_DUAL : 5V_DUAL Voltage=0.8375~1.6V Icc(Max)=50mA(S0)
Switching
2.5V for MCH : 2D5V_MCH Icc(Max)=125A
Four Phase 3.3SBV
D
4-Phases Swithing D
Icc(Max)=38mA(S3)
1.2V FSB
Vtt-5.3A
ATX P/S USB 8 Ports
+5V DUAL=4A(S0, S1)
12V +5V DUAL=20mA(S3)
Lakeport GMCH
5VSB
FSB_Vtt PS2
Linear 1.5V
3.3V 1.2V FSB Vtt +5V DUAL=345mA(S0, S1)
to 1.2V
CK410 6.2A
Icc(Max)=0.9A +5V DUAL=2mA(S3)
5V
Vdd (Core)
3.3V -12V 3.3V FWH
Ivdd(Max)=560mA 1.8V DDR2 I/O=4A(S0,S1)
3.3V=107mA(S0, S1)
1.8V DDR2 I/O= tbd mA(S3)
PCI Express
X16 slot (1)
Vcore (Core Logic)
+12V=5.5A
1.5V
5VDUAL Icc(Max)=13.8A(Integrated) 3.3VSB
C Icc(Max)= Icc(Max)=8.9A(Discrete) Icc(Max)=0.375A(wake) C
DDR2 Channel A/B 4.345A(S0,S1) *1.5V PCIe & DMI 1.5A Icc(Max)=0.02A(no wake)
22mA(S3)
3.3V
+3.3V=3A
Vdd (Core)=1.8V
Ivdd(S0,S1Max)=9.4A(4 2.5V DAC PCI Express
channel) *2.5V DAC=0.07A
Single Phase Switch regulator
2.5V HV=25mA
X1 slot (1)
Ivdd(S3)=400mA(4 5V to 1.8V V_2p5_DAC
channel)
+12V=0.5A
Ivdd(Max)=14A 100mA
Ivdd(Max)=425mA(S3) 3.3VSB
LDO Icc(Max)=0.375A(wake)
Vtt (Core) 1.8V to 0.9V Icc(Max)=0.02A(no wake)
0.9V Ivterm(Max)=1.2A
Ivterm(Max)=200mA 3.3V
+3.3V=3A
(per channel)
ICH7RW
Vin=12V
V_1p5_core 1.2V VCC_CPU-14mA
1.5V PCI Per Slot (2)
Switching=17A -12V
B 1.05V Core=1.31A Icc(Max)=0.1A B
1.5V_A-0.97A
1.5V_B-0.74A 5V
HDA Codec Icc(Max)=5A
Vcc LDO 1.5V- 1.05V -12V
5V 12V LDO 3.3V 3.3V
Icc(Max)=tbdA 3.3V
to 5V Icc(Max)=7.6A
3.3V=0.58A
Vcc 12V
3.3V VccSus
3.3V Icc(Max)=0.5A
Icc(Max)=0.7A
Icc(Max)=tbdA
3.3VSB
5VRef=6mA Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
5VrefSus=10mA
1.0V
LDO Lan Core Tekoa GbE Lan
5V_dual to 3.3SB RTC=tbduA V_1p2_ctrl BJT
Icc(Max)=1.5A +1.2V=tbdA
1.8V +2.5V=tbdA BJT

Lan Phy
A V_2p5_ctrl A
RTC
Battery
*Power derived through filter FOXCONN PCEG

Title
Power Delivery Map
C 945P01 A

5 4 3 2 1
5 4 3 2 1
S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL
+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C
S0->S3 S3->S0
+12V_SYS +12V_SYS
+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS
+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

B B
+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ
A A
FOXCONN PCEG
Title
Power Sequence
C 945P01 A

5 4 3 2 1
5 4 3 2 1
ICH7 GPIO Summary FWH GPIO Summary

Name Power Well Type Description Name Power Plane Type Description
GPIO0 Vcc3_3 I/O Pull-up through 10K resistor(Unused) FGPI0 Vcc3_3 I IDE1 Cable Detection(33 or 66/100)
GPIO1 V5REF I/O PREQ5J FGPI1 Vcc3_3 I Pull-up through 10K resistor(Unused)
GPIO2 V5REF I/OD INTEJ FGPI2 VccSus3_3 I Pull-up through 10K resistor(Unused)
D D
GPIO3 V5REF I/OD INTFJ FGPI3 VccSus3_3 I Pull-up through 10K resistor(Unused)
GPIO4 V5REF I/OD INTGJ FGPI4 Vcc3_3 I Pull-up through 10K resistor(Unused)
GPIO5 V5REF I/OD INTHJ
GPIO6 Vcc3_3 I/O Pull-up through 10K resistor(Unused)
GPIO7
GPIO8
GPIO9
Vcc3_3
VccSus3_3
VccSus3_3
I/O
I/O
I/O
FWH_WPJ
LPC PME#
S1_LED
PCI Routing Summary
GPIO10 VccSus3_3 I/O S3_LED PCI1 1394
GPIO11 VccSus3_3 I/O RECOVERY INTAJ B F
GPIO12 VccSus3_3 I/O TPM_RSV0 Pull-up through 10K resistor(Unused) INTBJ C
GPIO13 VccSus3_3 I/O TPM_RSV1 Pull-up through 10K resistor(Unused) INTCJ D
GPIO14 VccSus3_3 I/O TPM_RSV2 Pull-up through 10K resistor(Unused) INTDJ A
GPIO15 VccSus3_3 I/O EXTSMI_L (Chassis Intruder) INTEJ
GPIO16 Vcc3_3 I/O (Unused) INTFJ
GPIO17 Vcc3_3 I/O (Unused) INTGJ
GPIO18 Vcc3_3 I/O (Unused) INTHJ
GPIO19 Vcc3_3 I/O Pull-up through 10K resistor(Unused) REG#/GNT# 1 0
GPIO20 Vcc3_3 I/O GPIO_LAN_DISABLEJ IDSEL 17 19
C
GPIO21 Vcc3_3 I/O Pull-up through 10K resistor(Unused) C
GPIO22 Vcc3_3 I/O PREQ4J
GPIO23 Vcc3_3 I/O Pull-up through 10K resistor(Unused)_Dummy
GPIO24 VccSus3_3 I/O (Unused) DDR2 DIMM Config.
GPIO25 VccSus3_3 I/O (Unused) DEVICE ADDRESS CLOCK
GPIO26 VccSus3_3 I/O (Unused) CK_M_200M_P_DDR0_A
DIMM 1 A0H
GPIO29 VccSus3_3 I/O USB_OCJ_FRONT CK_M_200M_P_DDR0_B
DIMM 2 A4H
GPIO32 Vcc3_3 I/O TURBOJ
GPIO33 Vcc3_3 I/O (Unused)
Jumper Setting Summary
GPIO36 Vcc3_3 I/O Pull-up through 10K resistor(Unused)
GPIO37 Vcc3_3 I/O Pull-up through 10K resistor(Unused) Lock JBLOCK1(1-2) Default
GPIO38 Vcc3_3 I/O FWH_TBLJ FWH TBL#
GPIO39 Vcc3_3 I/O Pull-up through 10K resistor(Unused) Unlock JBLOCK1(2-3)
B GPIO40 N/A N/A Not Implemented B
GPIO41 N/A N/A Not Implemented Normal JCMOS1(1-2) Default

GPIO42 N/A N/A Not Implemented CLR_CMOS
GPIO43 N/A N/A Not Implemented Clear JCMOS1(2-3)
GPIO44 N/A N/A Not Implemented
GPIO49 V_CPU_IO I/O CPU_PWRGD
Super I/O GPIO Summary

Name Power Plane Type Description
GPIO23 VccSus3_3 I/O DDCA_CLK
GPIO22 VccSus3_3 I/O DDCA_DATA
GPIO21 VccSus3_3 I/O DDCSCL_5V
A GPIO20 VccSus3_3 I/O DDCSDA_5V A
FOXCONN PCEG
Title
GPIO / IRQ / IDSEL Map
C 945P01 A

5 4 3 2 1
5 4 3 2 1
HAJ[31..3]
12 HAJ[31..3]
HDJ[63..0]
HDJ[63..0] 12 U10A
HAJ3 L5 D2 3 OF 7
HAJ4 A03# ADS# HADSJ 12 U10C
P6 A04# BNR# C2 HBNRJ 12
2 OF 7 HAJ5 M5 D4 P2 F26 TESTHI_0
U10B A05# HIT# HITJ 12 19 SMIJ SMI# TESTHI00
HAJ6 L4 H4 K3 W3 TESTHI_1
A06# RSP# 19 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 TESTHI_11
A07# BPRI# HBPRIJ 12 19 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 12 19 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 12 19 NMI LINT1 TESTHI02
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 12 19 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 19 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 19 TESTHI05
D
B6 D05# D37# F17 U4 A13# LOCK# C3 HLOCKJ 12 9 HVCCA A23 VCCA TESTHI06 G24 D
HDJ6 B7 F18 HDJ38 HAJ14 V5 E3 B23 F24 TESTHI_2_7
D06# D38# A14# TRDY# HTRDYJ 12 9 HVSSA VSSA TESTHI07
HDJ7 A7 E18 HDJ39 HAJ15 V4 AD3 TP3 1 TP_VCCPLL D23 AK6
HDJ8 D07# D39# HDJ40 HAJ16 A15# BINIT# RSVD5 FORCEPH RSVD_G6
A10 D08# D40# E19 W5 A16# DEFER# G7 HDEFERJ 12 9 HVCCIOPLL C23 VCCIOPLL RSVD11 G6
HDJ9 A11 F20 HDJ41 N4 F2
HDJ10 D09# D41# HDJ42 RSVD1 EDRDY# TESTHI_13
B10 D10# D42# E21 12 HREQJ[4..0] P5 RSVD2 MCERR# AB3 TESTHI13 L2
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2
D11# D43# REQ0# 29 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 VID1 AL5 N1
D12# D44# REQ1# AP0# 29 VID1 VID1 PWRGOOD CPU_PWRG 18
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# 29 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 29 VID3 VID3 THERMTRIP# THERMTRIPJ 19
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[31..3] REQ4# BR0# HBR0J 12 29 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 R6 G3 TESTHI_8 VID5 AL4
12 HDBIJ0 DBI0# DBI2# HDBIJ2 12 12 HAJ[31..3] 12 HADSTBJ0 ADSTB0# TESTHI08 29 VID5 VID5
C8 G20 G5 G4 TESTHI_9 TP24 1 TP_VID6 AM5 A13 HCOMP0
12 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 12 PCREQ# TESTHI09 FC11 COMP0
B9 G19 H5 TESTHI_10 AM7 T1 HCOMP1
12 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 12 TESTHI10 FC12 COMP1
HAJ17 AB6 R286 62R0603 +/-5% VID_SELECT AN7 G2 HCOMP2
HDJ16 HDJ48 HAJ18 A17# TP_DPJ0 TP11 FC16 COMP2 HCOMP3
G9 D16# D48# D20 W6 A18# DP0# J16 1 10 CK_200M_P_CPU F28 BCLK0 COMP3 R1
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 1 TP12 G28 J2 HCOMP4
D17# D49# A19# DP1# 10 CK_200M_N_CPU BCLK1 COMP4
HDJ18 F9 A14 HDJ50 HAJ20 Y4 H16 TP_DPJ2 1 TP8 T2 HCOMP5
HDJ19 D18# D50# HDJ51 HAJ21 A20# DP2# TP_DPJ3 TP9 COMP5
E9 D19# D51# C15 AA4 A21# DP3# J17 1 25 SKTOCC_L AE8 SKTOCC#
HDJ20 D7 C14 HDJ52 HAJ22 AD6 N5
D20# D52# A22# 25 THERMDA RSVD13
HDJ21 E10 B15 HDJ53 HAJ23 AA5 H2 HGTLREF_1 AE6
D21# D53# A23# GTLREF1 25 THERMDC RSVD14
HDJ22 D10 C18 HDJ54 HAJ24 AB5 H1 HGTLREF_0 AL1 C9
HDJ23 D22# D54# HDJ55 HAJ25 A24# GTLREF0 CPU_MCH_GTLREF THERMDA RSVD15
F11 D23# D55# B16 AC5 A25# CS_GTLREF E24 MCH_GTLREF_CPU 12 AK1 THERMDC RSVD16 G10
HDJ24 F12 A17 HDJ56 HAJ26 AB4 D16
HDJ25 D24# D56# HDJ57 HAJ27 A26# AN3 RSVD17
D13 D25# D57# B18 AF5 A27# AN3 VCCSENSE RSVD18 A20
HDJ26 E13 C21 HDJ58 HAJ28 AF4 G23 AN4 AN4 E23
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 12 VSSSENSE RSVD19
G13 D27# D59# B21 AG6 A29# 29 VCC_SENSE AN5 VCC_MB_REG RSVD21 F23
HDJ28 F14 B19 HDJ60 HAJ30 AG4 B3 AN6 J3
D28# D60# A30# RS0# HRSJ0 12 29 VSS_SENSE VSS_MB_REG RSVD24
HDJ29 G14 A19 HDJ61 HAJ31 AG5 F5
HDJ30 D29# D61# HDJ62 A31# RS1# HRSJ1 12
F15 D30# D62# A22 TP22 1TP_LAG775_PIN_AH4 AH4 A32# RS2# A3 HRSJ2 12
Changed pin name
MSID1 V1 MS_ID1
HDJ31 G15 D31# D63# B22 HDJ63 TP23 1TP_LAG775_PIN_AH5 AH5 A33# F29 from RSV
RSVD9 MSID0 W1 MS_ID0
HDBIJ1 G11 C20 HDBIJ3 TP21 1TP_LAG775_PIN_AJ5 AJ5
12 HDBIJ1 DBI1# DBI3# HDBIJ3 12 A34#
12 HDSTBNJ1 G12 DSTBN1# DSTBN3# A16 HDSTBNJ3 12
TP20 1TP_LAG775_PIN_AJ6 AJ6 A35#
12 HDSTBPJ1 E12 DSTBP1# DSTBP3# C17 HDSTBPJ3 12 AC4 RSVD3 BOOTSELECT Y1
AE4 RSVD4
THERMDA/THERMDC LL_ID0 V2
AD5 1. width=10 mils, spacing=10 mils. AA2 LL_ID1
CPU_Prescott_Rev1.0_LGA775 12 HADSTBJ1 ADSTB1# LL_ID1
2. route the lines in parallel
cpu_lga775h600_945u02 CPU_Prescott_Rev1.0_LGA775
C cpu_lga775h600_945u02 1 OF 7 C
CPU_Prescott_Rev1.0_LGA775
cpu_lga775h600_945u02 LL_ID1
R297
0
FSB routing guidelines: If under 5" OK (pin to pin) R0603
+/-5%
Dummy
C267 AN3
1
* 4.7uF
10V, Y5V, +80%/-20% Loadline ID for Cedar Mill support
C0805 AN4
2
VTT_OUT_LEFT VTT_OUT_LEFT GTLREF voltage should be 0.63*VTT Dummy
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin FSB_VTT
Place at CPU end of route R300
R238 62 R0603 +/-5% HBR0J VTT_OUT_RIGHT 124 0.22nF caps should be placed near CPU pin U10D 4 OF 7
+/-1% place series resistor as close to divider HTCK AE1 A29
R292 62 R0603 +/-5% HIERRJ R0603 HTDI TCK VTT1
Place at CPU end of route AD1 TDI VTT2 B25
R272 100 R0603 +/-5% Dummy CPU_PWRG HTDO AF1 B29
R260 TDO VTT3
HTMS AC1 B30
VTT_OUT_RIGHT HGTLREF_1 HTRSTJ TMS VTT4
AG1 TRST# VTT5 C29
VTT6 A26
R239 62 R0603 +/-5% TESTHI_8 R148 62 R0603 +/-5% HCPURSTJ B27
R303 10 C255 HBPM0J VTT7
AJ2 BPM0# VTT8 C28
1
TESTHI_9 R0603 HBPM1J
R249 62 R0603 +/-5% Place at CPU end of route 210 C281
* 220pF AJ1 BPM1# VTT9 A25
1
R244 62 R0603 +/-5% TESTHI_10 R279 130 R0603 +/-5% PROCHOTJ
+/-1%
R0603 * 1uF +/-5%
10V, Y5V, +80%/-20%
50V, X7R, +/-10%
C0603
HBPM2J
HBPM3J
AD2
AG2
BPM2# VTT10 A28
A27
2
C0603 Dummy HBPM4J BPM3# VTT11
AF2 C30
2
R273 62 R0603 +/-5% TESTHI_11 C284 HBPM5J BPM4# VTT12
AG3 BPM5# VTT13 A30
1
R293 62 R0603 +/-5% TESTHI_12 * 0.1uF

16V, Y5V, +80%/-20%
10,18,24 ICH_SYS_RSTJ
ICH_SYS_RSTJ AC2 DBR#
VTT14
VTT15
C25
C26
C0603 C27
2
R270 62 R0603 +/-5% TESTHI_13 VTT16

AK3 ITPCLKOUT0 VTT17 B26
AJ3 ITPCLKOUT1 VTT18 D27
VTT19 D28
R265 60.4 R0603 +/-1% HCOMP4 FSBSEL0 G29 D25
B 10,12 FSBSEL0 FSBSEL1 BSEL0 VTT20 B
10,12 FSBSEL1 H30 BSEL1 VTT21 D26
R277 60.4 R0603 +/-1% HCOMP5 FSBSEL2 G30 B28 VTT_OUT_RIGHT
10,12 FSBSEL2 BSEL2 VTT22 TPEV_VCCFUSEPRG
design guide 1.0 15 mils width VTT23 D29
7 mils spacing VTT_OUT_LEFT D30 TPEV_VIDFUSEPRG VTT_OUT_LEFT
VTT24
max. 1200mils VTTPWRGD AM6 VTTPWRGD 29
VTT_OUT_RIGHT
AA1 VTT_OUT_RIGHT
R241 62 R0603 +/-5% Dummy RSVD_G6 VTT_OUT1 VTT_OUT_LEFT
VTT_OUT2 J1
R240 60.4 R0603 +/-1% HCOMP2 F27
VTT_SEL
R275 60.4 R0603 +/-1% HCOMP3 R288 62 R0603 +/-5% HBPM5J CPU_Prescott_Rev1.0_LGA775
FSB_VTT cpu_lga775h600_945u02
R294 62 R0603 +/-5% HBPM4J VTT_OUT_LEFT
15 mils width 3D3V_SYS
7 mils spacing R291 62 R0603 +/-5% HBPM3J
max. 1200mils R142 62 R0603 +/-5% TESTHI_0
R301 62 R0603 +/-5% HBPM2J R290
Intel reply 60.4 Ohm is corrected 62
R145 62 R0603 +/-5% TESTHI_2_7 R283 62 R0603 +/-5% HBPM1J R139 R0603
1K +/-5%
R295 62 R0603 +/-5% HBPM0J +/-5% Dummy
R188 60.4 R0603 +/-1% HCOMP0 R0603
VTT_OUT_RIGHT Dummy
R281 60.4 R0603 +/-1% HCOMP1 Place BPM termination near CPU MS_ID0 R280 62R0603 +/-5%
15 mils width
7 mils spacing R276 62 R0603 +/-5% TESTHI_1 MS_ID1 R287 62R0603 +/-5%
max. 1200mils
GTLREF voltage should be 0.63*VTT MSID0: VTT = 2005 Mainstream FMB
VTT_OUT_RIGHT 12 mils width, 15 mils spacing Vss = 2005 Performance FMB
VTT_OUT_LEFT
divider should be within 1.5" of the GTLREF pin MSID1: NC = PSC only
0.22nF caps should be placed near CPU pin Vss = Cedar Mill
C283 C268 R269 place series resistor as close to divider
1
R299
62
R306
62
R296
62
R313
62
R302
62 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
124
+/-1%
Intel recommend pull down to VSS
A +/-5% +/-5% +/-5% +/-5% +/-5% C0603 C0603 R0603 A
2
R0603 R0603 R0603 R0603 R0603

Dummy
R266 10 HGTLREF_0
R0603 +/-5%
place TDO termination near XDP connector
HTDO R261 C260
1
210 C256
* 220pF
1
place TCK/TDI/TMS terminations near

CPU within 1.5 inch
+/-1%
R0603 * 1uF
10V, Y5V, +80%/-20%
50V, X7R, +/-10%
C0603
FOXCONN PCEG
2
HTDI C0603 Dummy

2
HTMS Title
HTCK LGA775 -1
HTRSTJ
place TRSTJ termination anywhere on route
C 945P01 A
Date: Saturday, August 20, 2005 Sheet 8 of 30

5 4 3 2 1
5 4 3 2 1
VCCP VCCP VCCP

U10G 7 OF 7
U10E 5 OF 7 U10F 6 OF 7
AG22 VCCP1 VCCP93 AK12 AF9 VCCP185 VSS41 AL23 H22 VSS126 VSS211 D5
K29 VCCP2 VCCP94 AH22 AF22 VCCP186 VSS42 A12 H21 VSS127 VSS212 A9
AM26 VCCP3 VCCP95 T29 AH11 VCCP187 VSS43 L25 H20 VSS128 VSS213 D3
AL8 VCCP4 VCCP96 AM14 AJ14 VCCP188 VSS44 J7 H19 VSS129 VSS214 B1
AE12 VCCP5 VCCP97 AM25 AH19 VCCP189 VSS45 AE28 H18 VSS130 VSS215 B5
AE11 AE9 AH29 AE29 AB7 B8 FSB_VTT
D VCCP6 VCCP98 VCCP190 VSS46 VSS131 VSS216 D
W23 VCCP7 VCCP99 Y29 AH27 VCCP191 VSS47 K5 H17 VSS132 VSS217 AJ4 PLL Supply Filter
W24 VCCP8 VCCP100 AK25 AG28 VCCP192 VSS48 J4 AJ24 VSS133 VSS218 AE26
W25 VCCP9 VCCP101 AK19 AL26 VCCP193 VSS49 AE30 AM17 VSS134 VSS219 AH1
T25 VCCP10 VCCP102 AG15 AM12 VCCP194 VSS50 AN20 AC3 VSS135 VSS220 E29
1
Y28 VCCP11 VCCP103 J22 J24 VCCP195 VSS51 AF10 H14 VSS136 VSS221 V7
AL18 T24 J13 AE24 P28 C13 L6 L7
VCCP12 VCCP104 VCCP196 VSS52 VSS137 VSS222 L0805 10uH L0805 10uH
AC25 VCCP13 VCCP105 AG21 T28 VCCP197 VSS53 AM24 V6 VSS138 VSS223 AK24
W30 AM21 W28 AN23 AK2 AB30
2
VCCP14 VCCP106 VCCP198 VSS54 VSS139 VSS224
Y30 VCCP15 VCCP107 J25 J12 VCCP199 VSS55 H9 P27 VSS140 VSS225 L6 SRF: >=30MHz SRF: >=30MHz
AN14 VCCP16 VCCP108 U30 J27 VCCP200 VSS56 H8 P26 VSS141 VSS226 L7 Rated I: >=120mA Rated I: >=120mA
AD28 VCCP17 VCCP109 AL21 AG19 VCCP201 VSS57 H13 AM28 VSS142 VSS227 AB29 DCR: <=0.36 ohm DCR: <=0.36 ohm
Y26 VCCP18 VCCP110 AG25 AL9 VCCP202 VSS58 AC6 AJ13 VSS143 VSS228 M1
AC29 VCCP19 VCCP111 AJ18 AD30 VCCP203 VSS59 AC7 W4 VSS144 VSS229 AB28
M29 J19 AF21 AH6 P25 E8 HVCCIOPLL
VCCP20 VCCP112 VCCP204 VSS60 VSS145 VSS230 8 HVCCIOPLL
U24 VCCP21 VCCP113 AH30 Y24 VCCP205 VSS61 C16 AJ20 VSS146 VSS231 AG20
J23 VCCP22 VCCP114 J15 AK14 VCCP206 VSS62 AM16 W7 VSS147 VSS232 AN17
AC27 AG12 J9 AE25 P23 AB27 HVCCA
VCCP23 VCCP115 VCCP207 VSS63 VSS148 VSS233 8 HVCCA
AM18 VCCP24 VCCP116 AJ22 M27 VCCP208 VSS64 AE27 AG13 VSS149 VSS234 AB26
AM19 VCCP25 VCCP117 J20 AF14 VCCP209 VSS65 AJ28 AG16 VSS150 VSS235 AN16
AB8 AH18 J30 AJ7 AG17 M7 EC10 ESL <= 9 nH, ESR < 0.3 ohm
AC26
J8
VCCP27 VCCP119 AH26
W27
AG18
AA8
VCCP211 VSS67 F19
AH13
C7
Y2
VSS152 VSS237 AB25
AB24
* 33uF
35V, +/-20%
VCCP28 VCCP120 VCCP212 VSS68 VSS153 VSS238 CE20D50H110
J28 VCCP29 VCCP121 AL25 AG8 VCCP213 VSS69 AD7 L30 VSS154 VSS239 AB23
T30 AN8 AL29 AH16 L29 N3 check component requirements
AM9 VCCP31 VCCP123 AH14 AD29 VCCP215 VSS71 AK17 D15 VSS156 VSS241 AA30
AF15 VCCP32 VCCP124 U27 W8 VCCP216 VSS72 E17 AL27 VSS157 VSS242 F4 Notes:
AC8 T23 AH8 AH17 Y7 AG10 HVSSA 1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
VCCP33 VCCP125 VCCP217 VSS73 VSS158 VSS243 8 HVSSA
AE14 VCCP34 VCCP126 R8 N24 VCCP218 VSS74 AH20 L27 VSS159 VSS244 AE13 2. VCCA route should be parallel and next to VSSA route to minimize loop area
N23 VCCP35 VCCP127 AK22 AN22 VCCP219 VSS75 AE5 AA29 VSS160 VSS245 AF30 3. VCCIOPLL route should be parallel and next to VSSA route to minimize loop area
W29 VCCP36 VCCP128 AN29 J14 VCCP220 VSS76 AH23 N6 VSS161 VSS246 H28
U29 AG11 K26 AE7 N7 F7 3. Min. 12 mils trace from the filter to the processor pins
VCCP37 VCCP129 VCCP221 VSS77 VSS162 VSS247 4. The inductors should be close to the cap.
AC24 VCCP38 VCCP130 AK26 AF19 VCCP222 VSS78 AM13 AA28 VSS163 VSS248 AF29
AC23 VCCP39 VCCP131 J10 N8 VCCP223 VSS79 AH24 AN13 VSS164 VSS249 AF28
Y23 VCCP40 VCCP132 AJ15 AF12 VCCP224 VSS80 AJ30 AA27 VSS165 VSS250 G1
AN26 VCCP41 VCCP133 AG26 M28 VCCP225 VSS81 AJ10 AA26 VSS166 VSS251 AF27
AN25 VCCP42 VCCP134 AN9 AK9 VCCP226 VSS82 AF3 P4 VSS167 VSS252 AF26
AN11 VCCP43 VCCP135 AH15 VSS83 AK5 AA25 VSS168 VSS253 AF25
C AN18 VCCP44 VCCP136 AF18 VSS84 AJ16 AA24 VSS169 VSS254 AN28 C
Y27 VCCP45 VCCP137 AL15 C10 VSS1 VSS85 AF6 P7 VSS170 VSS255 AN27
Y25 VCCP46 VCCP138 J26 D12 VSS2 VSS86 AK29 E26 VSS171 VSS256 AF24
AD24 VCCP47 VCCP139 J18 VSS87 AJ17 V30 VSS172 VSS257 AF23
AE23 VCCP48 VCCP140 J21 C24 VSS4 VSS88 F22 R2 VSS173 VSS258 AG24
AE22 VCCP49 VCCP141 AG27 K2 VSS5 VSS89 AH3 V29 VSS174 VSS259 AF17
AN19 VCCP50 VCCP142 AK15 C22 VSS6 VSS90 AK10 V28 VSS175 VSS260 AN24
V8 VCCP51 VCCP143 AF11 AN1 VSS7 VSS91 AM10 R5 VSS176 VSS261 H3
K8 VCCP52 VCCP144 AD23 B14 VSS8 VSS92 F16 V27 VSS177
AE21 VCCP53 VCCP145 AM15 K7 VSS9 VSS93 AJ23 R7 VSS178 VSS263 P24
AM30 VCCP54 VCCP146 AF8 AE16 VSS10 VSS94 F13 E20 VSS179 VSS264 AE20
AE19 VCCP55 VCCP147 AK21 B11 VSS11 VSS95 AG7 AN10 VSS180 VSS265 AE17
AC30 VCCP56 VCCP148 AG30 AL10 VSS12 VSS96 F10 V25 VSS181 VSS266 E27
AE15 AJ21 AK23 L26 T3 T7 HS1
VCCP57 VCCP149 VSS13 VSS97 VSS182 VSS267 MTG-HOLE-8_0
M30 VCCP58 VCCP150 AM11 H12 VSS14 VSS98 AD4 V24 VSS183 VSS268 R30
K27 AL11 AF7 H11 V23 AJ27 VTT_OUT_RIGHT
VCCP59 VCCP151 VSS15 VSS99 VSS184 VSS269
M24 VCCP60 VCCP152 AJ11 AK7 VSS16 VSS100 L24 T6 VSS185 VSS270 AB1
AN21 VCCP61 VCCP153 K30 H7 VSS17 VSS101 L23 AL7 VSS186 VSS271 AM4
6
5
T8 AL14 E14 AM23 E25 V26 R285 60.4 R0603 +/-1% HCOMP6
AC28 VCCP63 VCCP155 AN30 L28 VSS19 VSS103 A15 U1 VSS188 VSS273 AA23 7 4
N25 AH25 Y5 AH10 R29 AL28 8 3 R298 60.4 R0603 +/-1% HCOMP7
AE18 VCCP65 VCCP157 AL12 E11 VSS21 VSS105 H29 GTLREF_SEL R28 VSS190 VSS275 AF20 9 2
W26 AJ9 AL16 B24 R27 AG23
1
AD25 VCCP67 VCCP159 AK11 AL24 VSS23 VSS107 L3 R26 VSS192
15 mils width
M8 AG14 AK13 H27 R25 LKPT_HS_ATX 7 mils spacing
VCCP68 VCCP160 VSS24 VSS108 VSS193
N30 VCCP69 VCCP161 N29 AL3 VSS25 VSS109 A21 U7 VSS194 max. 1200mils
AD26 VCCP70 VCCP162 AL30 D21 VSS26 VSS110 AE2 R24 VSS195
AJ26 VCCP71 VCCP163 AJ25 AL20 VSS27 VSS111 AJ29 R23 VSS196
AM29 VCCP72 VCCP164 AH9 D18 VSS28 VSS112 A24 P30 VSS197
M25 VCCP73 VCCP165 J29 AN2 VSS29 VSS113 AK27 V3 VSS198
M26 VCCP74 VCCP166 J11 AK16 VSS30 VSS114 AK28 P29 VSS199
L8 VCCP75 VCCP167 K25 AK20 VSS31 VSS115 B20 AF16 VSS200 RSVD26 F6 IMPSEL
U25 VCCP76 VCCP168 P8 AM27 VSS32 VSS116 AM20 AE10 VSS201
Y8 VCCP77 VCCP169 K23 AM1 VSS33 VSS117 H26 AF13 VSS202 RSVD28 Y3 HCOMP6 vccp
AJ12 AL19 AL13 B17 H6 AE3 HCOMP7
VCCP78 VCCP170 VSS34 VSS118 VSS203 RSVD29
AD27 VCCP79 VCCP171 AM8 AL17 VSS35 VSS119 H25 A18 VSS204
U23 VCCP80 VCCP172 T26 C19 VSS36 VSS120 H24 A2 VSS205 RSVD31 E7
B
M23 VCCP81 VCCP173 N28 E28 VSS37 VSS121 AA3 E2 VSS206 RSVD32 B13 B
AG29 AH12 AH7 AA7 D9 D14 TC3 100uF CTD
*
N27 AL22 AK30 H23 C4 E6 2V, +/-20%
AM22 VCCP84 VCCP176 AN15 D24 VSS40 VSS124 AA6 A6 VSS209 RSVD35 D1
U28 VCCP85 VCCP177 AJ8 VSS125 H10 D6 VSS210 RSVD36 E5
K28 VCCP86 VCCP178 U26
U8 AJ19 CPU_Prescott_Rev1.0_LGA775 CPU_Prescott_Rev1.0_LGA775 TC4 100uF CTD
VCCP87 VCCP179
*
AK18 T27 cpu_lga775h600_945u02 cpu_lga775h600_945u02 2V, +/-20%
VCCP88 VCCP180
AD8 VCCP89 VCCP181 AK8
K24 VCCP90 VCCP182 AN12
AH28 VCCP91 VCCP183 AG9 Place caps within socket
AH21 VCCP92 VCCP184 N26 cavity solder side
CPU_Prescott_Rev1.0_LGA775
cpu_lga775h600_945u02
Put under CPU Heat-Sink

VCCP VCCP 0.8V~1.55V/ 119A
C220 C204 C208 C182 C187 C202 C214 C216 C196 C189 C205 C215 C179 C197 C217 C210 C207 C201 C496
EC11 EC23 EC31 EC30 EC22 EC13 EC16 EC26 EC28 EC27
1
22uF
* 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * 22uF * * 560uF * 560uF * 560uF * 560uF * 560uF * 560uF * 560uF * 560uF * 560uF * 560uF
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
CE35D80H200
Dummy
Dummy
Dummy
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2
6.3V, X5R, +/-20% 2

C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
C1206
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
4V, +/-20%
A A
Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy FOXCONN PCEG
Title
LGA775 -2
C 945P01 A
Date: Saturday, July 16, 2005 Sheet 9 of 30

5 4 3 2 1
5 4 3 2 1
3D3V_SYS 3D3V_SYS
3D3V_SYS
Analog/SRC/CPU Power Filter
3D3V_SYS
3D3V_CLK_A_SRC_CPU
C32
*
1
* 0.1uF L2
*
R76 L1 16V, Y5V, +80%/-20% FB L0805 300 Ohm
4.7K FB L0805 300 Ohm C0603 3D3V_CLK_A_SRC_CPU
2
+/-5%
R0603
3D3V_CLK_PCI_REF_USB
TURBOJ
C29 C24 C89 C88
1
D
Real time input pin to change frequency * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% D
to a pre_programmed under or over clock C0603 C0603 C0603 C0603
2
entries located in the ROM table C66 C90 C26 C28 C27 C77
1
* 10uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C1206 C0603 C0603 C0603 C0603 C0603
2
place near pin 5, 56 place near pin 48 Dummy
place near pin 19, 28, 34 place near pin 43 place near pin 37
3D3V_CLK_PCI_REF_USB
3D3V_CLK_A_SRC_CPU
C20 C25
1
R0603 XDP/PCI-E selection * 10uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
+/-5% High=XDP enable C1206 C0603
2
4.7K Dummy
R77 Low=PCI-E enable
place near pin 10
20 CK_33M_ICH
R78 Ce = 2*32pf - 5pf -
4.7K 2.8pf = 56.2p
+/-5% -> 56pf = C182 = C183
R0603 R62 33R0603 +/-5% 33M_1394 U3
Dummy
1 56 3D3V_CLK_PCI_REF_USB X1 XTAL 14.31818MHz
R59 33R0603 +/-5% 33M_PCI2 GND VDDPCI 33M_TPM R18 33R0603 +/-5%
27 CK_33M_1394 2 PCICLK2 PCICLK1 55 CK_33M_TPM 24 1 2
R60 33R0603 +/-5% 3 54 33M_PCI1 R19 33R0603 +/-5%
19 CK_33M_FWH PCICLK3 PCICLK0 CK_33M_PCI1 17
4 53 C70 C67
GND Reset# ICH_SYS_RSTJ 8,18,24
1
TURBOJ 3D3V_CLK_PCI_REF_USB 14M_ICH
C
18 TURBOJ
R61 0 R0603 +/-5% 5
6
VDDPCI
*Turbo#
REF0/FS_C
GND
52
51 ICS_FSBSEL2
R5
R20
15R0603 +/-5%
10R0603 +/-5%
CK_14M_ICH
CK_14M_SIO
18
25
* 56pF
50V, NPO, +/-5% * 56pF
50V, NPO, +/-5% C
ICS_FSBSEL0 7 50 C0603 C0603
2
R63 33R0603 +/-5% 33M_SIO ITP_EN/PCICLK_F0 X1
25 CK_33M_SIO 8 FS_A/PCICLK_F1 X2 49
9 48 3D3V_CLK_PCI_REF_USB
ICS_FSBSEL1 FS_B/PCICLK_F2 VDDREF
10 VDD48 SCLK 47 SMB_CLK_MAIN 15,16,25
11 **SEL24_48#/24_48MHz SDATA 46 SMB_DATA_MAIN 15,16,25
R82 33R0603 +/-5% 48M_ICH 12 45 200M_P_GMCH R22 33R0603 +/-5%
18 CK_48M_ICH USB_48MHz CPUCLKT0 CK_200M_P_GMCH 12
13 44 200M_N_GMCH R23 33R0603 +/-5%
GND CPUCLKC0 CK_200M_N_GMCH 12
R65 33R0603 +/-5% 96M_DOT_P 14 43 3D3V_CLK_A_SRC_CPU
12 CK_96M_P_GMCH DOTT_96MHz VDDCPU
R66 33R0603 +/-5% 96M_DOT_N 15 42 200M_P_CPU R24 33R0603 +/-5%
12 CK_96M_N_GMCH DOTC_96MHz CPUCLKT1 CK_200M_P_CPU 8
CLK_VTT_PWRGDJ 16 41 200M_N_CPU R25 33R0603 +/-5%
Vtt_PwrGd#_PD CPUCLKC1 CK_200M_N_CPU 8
R67 33R0603 +/-5% 17 40
21 CK_PE_100M_P_LAN R68 33R0603 +/-5% PCIEXT0 GND CLK_IREF R11 475 R0603 +/-1%
21 CK_PE_100M_N_LAN 18 PCIEXC0 IREF 39
3D3V_CLK_A_SRC_CPU 19 38
VDDPCIEX GNDA 3D3V_CLK_A_SRC_CPU
20 GND VDDA 37 making the IREF 2.32 mA
R69 33R0603 +/-5% PE_100M_P_16PORT 21 36
17 CK_PE_100M_P_16PORT PCIEXT1 CPUCLK_ITP/PCIEXT5
R70 33R0603 +/-5% PE_100M_N_16PORT 22 35
17 CK_PE_100M_N_16PORT PCIEXC1 CPUCLK_ITP/PCIEXC5
R71 22 R0603 +/-5% PE_100M_P_ICH 23 34 3D3V_CLK_A_SRC_CPU
18 CK_PE_100M_P_ICH PCIEXT2 VDDPCIEX
R72 22 R0603 +/-5% PE_100M_N_ICH 24 33
18 CK_PE_100M_N_ICH PCIEXC2 PCIEXT4
25 GND PCIEXC4 32
R73 27R0603 +/-5% SATA_100M_P_ICH 26 31 PE_100M_P_GMCH R26 33R0603 +/-5%
19 CK_SATA_100M_P_ICH SRCCLKT_SATA PCIEXT3 CK_PE_100M_P_GMCH 12
R74 27R0603 +/-5% SATA_100M_N_ICH 27 30 PE_100M_N_GMCH R27 33R0603 +/-5%
19 CK_SATA_100M_N_ICH SRCCLKC_SATA PCIEXC3 CK_PE_100M_N_GMCH 12
3D3V_CLK_A_SRC_CPU 28 29
VDDSRC GND
R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 ICS954128AFLF R12 R13 R7 R8 R9 R10
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
+/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1% +/-1%
R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603
SMBus Address :1101-0010
100 MHz(PCIEX) 100 MHz(SRC SATA)

FSB_VTT
R79
PCIEX1 X16 connector SRCCLK_SATA ICH7
B FSBSEL0 8,12 B
PCIEX2 ICH7 BSEL TABLE 470

VCCP 3D3V_CLK_A_SRC_CPU R0603
PCIEX3 GMCH FS_C FS_B FS_A FSB Frequency +/-5%
R80
R40 R55 0 0 1 133MHz(533)
220 10K
FSBSEL1 8,12
+/-5% +/-5% 0 1 0 200MHz(800)
R39
R0603 R0603
CLK_VTT_PWRGDJ 470
0 0 0 266MHz(1066) R0603
C
+/-5%
Q10 4.7K
B R6
MMBT3904 R0603
+/-5%
FSBSEL2 8,12
E
470
R0603
+/-5%
1D8V_STR
CK_33M_ICH
CK_33M_FWH C468
1
CK_33M_TPM
* 0.1uF
16V, Y5V, +80%/-20%
C0603
2
Dummy
C91 C87 C14
1
* 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5%
C0603 C0603 C0603 ICS_FSBSEL0 R64 2.2K
FSBSEL0 8,12
2
Dummy Dummy Dummy R0603 +/-5%
3D3V_SYS
A C234 A
1
CK_48M_ICH
* 0.1uF
16V, Y5V, +80%/-20% ICS_FSBSEL1 R81 2.2K
FSBSEL1 8,12
CK_33M_SIO C0603 R0603 +/-5%
2
CK_33M_1394
C93 C92 C86

1
* 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5%
5V_SYS
C0603 C0603 C0603 C74 C248 C124

FOXCONN PCEG
2
Dummy Dummy Dummy

* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
ICS_FSBSEL2 R21
R0603
2.2K
+/-5%
FSBSEL2 8,12
C0603 C0603 C0603 Title
2
ICS954128 ClockGen
C
945P01 A

5 4 3 2 1
5 4 3 2 1
12V_SYS
R155
5V_SYS 10
+/-5%
R165
R0805 D2
Vout=Vref(1+R2/R1)+IadjR2
ANODE CATHODE C130 1 2 0.1uF 15V_PHASE R1 is Up Resistor.
*
C0603 25V, Y5V, +80%/-20%
Iadj=50uA 1D05V_ICH(1.5A)
*
For RT9202 1N4148W
10 15V_3VIN Chock 1.2uH L4 5V_SYS
R170 R0805 R171 C141 Vref=1.25V
1
20K +/-5% 20K
* 4.7uF EC9 EC8 C118
1
+/-5% Dummy +/-5% 16V, Y5V, +80%/-20% * 1500uF * 1500uF
* 4.7uF 5V_DUAL 3D3V_SB 1D5V_CORE
D
5
R0603 R0603 C1206 U9 6.3V, +/-20% 6.3V, +/-20% 10V, Y5V, +80%/-20% Max. output current = 3A
2
Dummy 1 Q18 CE35D80H200 CE35D80H200 C0805 U15 AMS1085
VCC
D
2
BOOT
3 VIN VOUT 2 R125
4
7 2 R138 0 R0805 +/-5%15V_UG1 G PHD45N03LTA 1.5V Power requires 1D5V_CORE U5A Q24
D COMP/OCSET UGATE D
17A maximum current 1D5V_CORE 3 +
ADJ
N-CH / TO-252 R243 1 G PHD45N03LTA
*
S
6 8 R168 0 R0805 +/-5% 15V_PHASE L5 Choke Coil 3.3uH 301 2
FB PHASE 1K -
+/-1% LM324
GND
S
1
4 C266 R0603 EC32 R0603 R136
11
LGATE
1
*
EC14
EC24
EC17
R175
* 1uF 220uF +/-1% R124 1K
D
R167 RT9214PS 2.2 C151 10V, Y5V, +80%/-20% 3D3VADJ 6.3V, +/-20% 2.1K +/-5% 1D05V_ICH
1
140 Dual-Layout Q22 +/-5%
* 0.1uF * * * C0603 CE20D50H110 +/-1% R0603
2
+/-1% with RT9214 R0805 16V, Y5V, +80%/-20% R0603
CE35D80H200
6.3V, +/-20%
1000uF
CE35D80H200
6.3V, +/-20%
1000uF
CE35D80H200
6.3V, +/-20%
1000uF
R0603 R147 0 R0805 +/-5%15V_LG1 G PHD45N03LTA C155 C0603 R242
2
1
VOUT= 0.8V(1+Rt / Rb) Near MOSFET N-CH / TO-252 * 0.1uF
16V, Y5V, +80%/-20%
499
+/-1% *
EC12
100uF
S
C0603 R0603 16V, +/-20%
2
CE20D50H110
R166 124
R0603 +/-1%
1.5V Voltage
R169 60.4 C152 1 2 18nF C0603 50V, Y5V, +80%/-20%
*
R0603 +/-1%
5V_SB_SYS 12V_SYS
5V_SYS 5V_SYS 5V_SYS
R42 R36
VCC25_EN 4.7K 1K
+/-5% +/-5%
See page 261
C
R14 2.5V R0603 R0603
S
3D3V_SB B Q4 Q67 close to IDE
MMBT3904 G G G
2D5V_MCH
C
10K E
1D5V_CORE VDDQ L
R0603 3D3V_SB 0.7V B Q7 R44
C
R34 R35 MMBT3904

+/-5% R33 4.7K Q25 Q23 Q67
D
B Q1 10 0.7V +/-5% AOD412 AOD412 AOD412
E
C22 MMBT3904 R15 +/-5% R0603 Dummy
C
R41
1
R17
* 1uF 100 R0805
E
0 2.2K 10K 10V, Y5V, +80%/-20% +/-5% Q6 5V_DUAL

C B C
C
R0603 R0603 SLP_S3# 24,25 PWRG_ATX MMBT3904 L
+/-5% C0603 R0603
2
+/-5% R0603 +/-5% B Q5
E
Dummy MMBT3904 S5 L 4.7K H
C
R16 VCC3 R0603 C31 C158

E
1
S0 H H
18,24,25 SLP_S3J
C18
B Q2
MMBT3904
1D5V_CORE +/-5%
H * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
G
1
VCC25_EN S3 H
* 1uF C0603 C0603
E
2
3.3K 10V, Y5V, +80%/-20% H
D1
R0603 C0603 1 S D
1D5V_CORE 5V_SB_SYS
2
+/-5% 3 L
2D5V_MCH
2
APM2301A
Q8
BAT54C
3D3V_SB 12V_SYS 1D5V_CORE
VTT_DDR2 Voltage Supplier C448 C156
1
3D3V_SYS
R467
R127
1.05K * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
+/-1% C0603 C0603
D
2
2
1D8V_STR R0603
3
4
Q21
2 Q51 VTT_DDR 5 U5B
10K +
4
U23C HA8050 7 G PHD45N03LTA

R0603 10 R126 6
1
+ -
+/-1% 8 604 LM324
S
9 +/-1%
11
-
1
C449 R496 EC51 EC52 R0603 FSB_VTT

1
* 0.1uF R455 LM324 150 2 Q52 * 1000uF * 1000uF

11
16V, Y5V, +80%/-20% 10K +/-5% HA8550 6.3V, +/-20% 6.3V, +/-20% R172 1K R0603 +/-5%
C0603 +/-1% R0805 CE35D80H200 CE35D80H200
2
B B
R0603
S
EC15
Reserve large copper C116 1 2 0.1uF C0603 16V, Y5V, +80%/-20% G * 1000uF
*
Dummy 6.3V, +/-20%
CE35D80H200
Q20
3D3V_SB 3D3V_SB 5V_SB_SYS VCC1_8SB 1D8V_STR 1.8V Standby Voltage FDT458P
D 4
R493
R500 R479 10K VCC1_8SB
A
S
10K 8.2K +/-5% Q57

+/-5% +/-5% R0603 G 5V_DUAL
B
4
R0603 R0603 3D3V_SYS
VCC1_8SB U25
Vout 4
1.8V Power requires SOT223
V_2P5_MCH(100mA)
C
ADJ
APM2301A 3D3V_SB
Vin
15.2A maximum current
D
S
B Q58 Q49 EC35

MMBT3904 G * 1000uF AME1117 3D3V_SYS
C
1
Q56 6.3V, +/-20% R386
E
B R443 CE35D80H200 1K
0 +/-1%
D
MMBT3904 +/-5% AOD434L R0603
E
4
R0603 R465 Q13
R492 100 2.7V 180 VCC25_EN 10 U5C 2D5V_MCH
18,25 SLP_S4J +
R0603 +/-5% BC7 EC50 +/-1% 2.5V 8 G
24,25 PWRG_ATX
*
EC49
470uF * 0.1uF
16V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20%
* EC38
1000uF Vref=1.25V
R0603
R379
9 -
LM324
2N7002
S
6.3V, +/-20% C0603 CE35D80H200 6.3V, +/-20% 3.16K
11
CE35D80H200 CE35D80H200 EC48 R456 +/-1% R95
Dummy * 100uF 86.6 R0603 1K
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

16V, +/-20% +/-1% +/-5%
12V_SYS CE20D50H110 R0603 R0603 C172 C117 C497
1
VCC1_8SB
C96 1 2 0.1uF
* 0.1uF
* 0.1uF
* 10uF
*
C431 C0603 16V, Y5V, +80%/-20% C0603 C0603 C1206
2
1
A
R472
1K * 0.1uF
16V, Y5V, +80%/-20%
Dummy
A
R0603 C0603
A B C
D
2
+/-5%
C
4
Q50
1.8V 12 U23D
+
14 G
SLP4_L ATXPOK P-MOS N-MOS Power from
S
Q59 13 AOD434L
- S5 L L H Off Off Nothing
4
G LM324 R484
S
1K U5D
S0(Before ATXPOK) H L L On Off Standby 1.8V 12
11
+
R475 +/-5% 14
APM2301A
60.4K
+/-1%
R0603
S0(After ATXPOK) H H H Off ON Vcc3 13 -
LM324
FOXCONN PCEG
D
R0603 C469 1 2 0.1uF Title

S3 H L L On Off Standby 1.8V
11
*
Dummy 16V, Y5V, +80%/-20%

C0603 ACPI Voltage Regulator
close U12 C 945P01 A

5 4 3 2 1
5 4 3 2 1
U14A HDJ[63..0]
8 HAJ[31..3] HDJ[63..0] 8
HAJ3 J39 HA3* 1.0 HD0* P41 HDJ0 U14D Place close to GMCH
HAJ4 K38 HA4* HD1* M39 HDJ1 Within 500 mils
HAJ5
HAJ6
J42 HA5*
HA6*
HD2*
HD3*
P42 HDJ2
HDJ3
U14G FSBSEL0 BSEL0 1.0 HSYNC_P R202 39 R0603 +/-5%
K35 M42 F21 HSYNC D17 HSYNC 26
HAJ7 J37 HA7* HD4* N41 HDJ4 FSBSEL1 H21 BSEL1 VSYNC C17 VSYNC_P R205 39 R0603 +/-5%
HAJ8
HAJ9
M34
N35
HA8*
HA9* FSB HD5*
HD6*
M40
L40
HDJ5
HDJ6 17
17
EXP_RXP0
EXP_RXN0
EXP_RXP0
EXP_RXN0
G12
F12
EXP_RX0
EXP_RX0*
1.0 EXP_TX0
EXP_TX0*
D14
C13
EXP_TXP0
EXP_TXN0
EXP_TXP0
EXP_TXN0
17
17
FSBSEL2
TP_ALLZTEST
L20
K18
BSEL2
ALLZTEST RED F17
VSYNC
RED
26
26
HAJ10 R33 HA10* HD7* M41 HDJ7
17 EXP_RXP1
EXP_RXP1 D11 EXP_RX1 EXP_TX1 A13 EXP_TXP1
EXP_TXP1 17
TP_XORTEST H20 XORTEST GREEN K17 GREEN 26
VGA
HAJ11 N32 HA11* HD8* K42 HDJ8
17 EXP_RXN1
EXP_RXN1 D12 EXP_RX1* EXP_TX1* B12 EXP_TXN1
EXP_TXN1 17
TP_RSV_TP5 L18 RSV_TP5 BLUE H18 BLUE 26
HAJ12 N34 HA12* HD9* G39 HDJ9
17 EXP_RXP2
EXP_RXP2 J13 EXP_RX2 EXP_TX2 A11 EXP_TXP2
EXP_TXP2 17
GMCH_EXP_SLR K21 EXP_SLR RED* G17 REDJ
HAJ13 M38 HA13* HD10* J41 HDJ10
17 EXP_RXN2
EXP_RXN2 H13 EXP_RX2* EXP_TX2* B10 EXP_TXN2
EXP_TXN2 17
TP_RSV_TP4 L21 RSV_TP4 GREEN* J17 GREENJ R248 R254 R258
D
HAJ14 N42 HA14* HD11* G42 HDJ11
17 EXP_RXP3
EXP_RXP3 E10 EXP_RX3 EXP_TX3 C10 EXP_TXP3
EXP_TXP3 17
GMCH_EXP_EN F20 EXP_EN BLUE* J18 BLUEJ 150 150 150
D
HAJ15 N37 HA15* HD12* G40 HDJ12 EXP_RXN3 F10 EXP_RX3* EXP_TX3* C9 EXP_TXN3
EXP_TXN3 17
TP_RSV_TP6 N21 RSV_TP6 +/-1% +/-1% +/-1%
PCIE
17 EXP_RXN3 DDC_DATA
HAJ16 N38 HA16* HD13* G41 HDJ13
17 EXP_RXP4
EXP_RXP4 J9 EXP_RX4 EXP_TX4 A9 EXP_TXP4
EXP_TXP4 17
1D5V_CORE N18 DDCA_DATA DDCA_DATA
R0603
25
R0603 R0603
HAJ17 R32 HA17* HD14* F40 HDJ14
17 EXP_RXN4
EXP_RXN4 H10 EXP_RX4* EXP_TX4* B7 EXP_TXN4
EXP_TXN4 17 DDC_CLK N20 DDCA_CLK DDCA_CLK 25
Place close to
HAJ18 R36 HA18* HD15* F43 HDJ15
17 EXP_RXP5
EXP_RXP5 F7 EXP_RX5 EXP_TX5 D7 EXP_TXP5
EXP_TXP5 17 M17 RESERVED GMCH
HAJ19 HA19* HD16* HDJ16 EXP_RXN5 EXP_RX5* EXP_TXN5 REFSET A20 REFSET Within 500 mils
U37 F37 17 EXP_RXN5 F9 EXP_TX5* D6 EXP_TXN5 17 L17 RESERVED
HAJ20 R35 HA20* HD17* E37 HDJ17
17 EXP_RXP6
EXP_RXP6 C4 EXP_RX6 EXP_TX6 A6 EXP_TXP6
EXP_TXP6 17 DREFCLKP J15 CK_96M_P_GMCH CK_96M_P_GMCH 10
HAJ21 R38 HA21* HD18* J35 HDJ18
17 EXP_RXN6
EXP_RXN6 D3 EXP_RX6* EXP_TX6* B5 EXP_TXN6
EXP_TXN6 17 RESERVED
R27 DREFCLKN H15 CK_96M_N_GMCH CK_96M_N_GMCH 10
2D5V_MCH
HAJ22 V33 HA22* HD19* D39 HDJ19
17 EXP_RXP7
EXP_RXP7 G6 EXP_RX7 EXP_TX7 E2 EXP_TXP7
EXP_TXP7 17 RESERVED
U27
HAJ23 U34 HA23* HD20* C41 HDJ20 EXP_RXN7 J6 EXP_RX7* EXP_TX7* F1 EXP_TXN7
EXP_TXN7 17 RESERVED
M15 EXTTS* J20 EXTTSJ R183 10K R0603 +/-5%
17 EXP_RXN7
HAJ24 U32 HA24* HD21* B39 HDJ21
17 EXP_RXP8
EXP_RXP8 K9 EXP_RX8 EXP_TX8 G2 EXP_TXP8
EXP_TXP8 17 RESERVED
L15 RESERVED M11
HAJ25 V42 HA25* HD22* B40 HDJ22
17 EXP_RXN8
EXP_RXN8 K8 EXP_RX8* EXP_TX8* J1 EXP_TXN8
EXP_TXN8 17 Intel Symbol 1.0 update RESERVED V30
HAJ26 HA26* HDJ23 EXP_RXP9 EXP_TXP9 NC PLTRSTJ
HAJ27
U35
Y36 HA27*
HD23*
HD24*
H34
C37 HDJ24 17
17
EXP_RXP9
EXP_RXN9
EXP_RXN9
F4
G4
EXP_RX9
EXP_RX9*
EXP_TX9
EXP_TX9*
J3
K4 EXP_TXN9
EXP_TXP9
EXP_TXN9
17
17
BB2
BA2 NC MISC RSTIN*
PWROK
AJ12
AJ9 PWRGD_3V
PLTRSTJ
PWRGD_3V
18,19,24,25
18,25,27
HAJ28 Y38 HA28* HD25* J32 HDJ25 EXP_RXP10 M6 EXP_RX10 EXP_TX10 L4 EXP_TXP10
EXP_TXP10 17 AW26 NC ICH_SYNC* M18 ICH_SYNCJ
ICH_SYNCJ 18
17 EXP_RXP10 NC
HAJ29 AA37 HA29* HD26* B35 HDJ26
17 EXP_RXN10
EXP_RXN10 M7 EXP_RX10* EXP_TX10* M4 EXP_TXN10
EXP_TXN10 17 AW2
HAJ30 V32 HA30* HD27* J34 HDJ27
17 EXP_RXP11
EXP_RXP11 K2 EXP_RX11 EXP_TX11 M2 EXP_TXP11
EXP_TXP11 17 AV27 NC RESERVED A43
HAJ31 Y34 HA31* HD28* B34 HDJ28 EXP_RXN11 L1 EXP_RX11* EXP_TX11* N1 EXP_TXN11
EXP_TXN11 17 AV26 NC REDJ R246 0 R0603 +/-5%
17 EXP_RXN11 NC
TP_FSB_AA35 AA35 RSVD HD29* F32 HDJ29
17 EXP_RXP12
EXP_RXP12 U11 EXP_RX12 EXP_TX12 P2 EXP_TXP12
EXP_TXP12 17 E35 NC BC43 GREENJ R252 0 R0603 +/-5%
TP_FSB_AA42 AA42 RSVD HD30* L32 HDJ30 EXP_RXN12 U10 EXP_RX12* EXP_TX12* T1 EXP_TXN12
EXP_TXN12 17 C42 NC NC BC42 BLUEJ R256 0 R0603 +/-5%
17 EXP_RXN12 NC
TP_FSB_AA34 AA34 RSVD HD31* J31 HDJ31
17 EXP_RXP13
EXP_RXP13 R8 EXP_RX13 EXP_TX13 T4 EXP_TXP13
EXP_TXP13 17 B42 NC BC2
TP_FSB_AA38 AA38 RSVD HD32* H31 HDJ32 EXP_RXN13 R7 EXP_RX13* EXP_TX13* U4 EXP_TXN13
EXP_TXN13 17 B41 NC NC BC1
17 EXP_RXN13
HD33* M33 HDJ33
17 EXP_RXP14
EXP_RXP14 P4 EXP_RX14 EXP_TX14 U2 EXP_TXP14
EXP_TXP14 17 NC BB43
HD34* K31 HDJ34 EXP_RXN14 N3 EXP_RX14* EXP_TX14* V1 EXP_TXN14
EXP_TXN14 17 AJ27 RESERVED NC BB1
8 HREQJ[4..0] HREQJ0 HD35* HDJ35 17 EXP_RXN14 EXP_RXP15 EXP_TXP15 RESERVED
E41 HREQ0* M27 17 EXP_RXP15 Y10 EXP_RX15 EXP_TX15 V3 EXP_TXP15 17 AG27 NC C2
HREQJ1 D41 HREQ1* HD36* K29 HDJ36 EXP_RXN15 Y11 EXP_RX15* EXP_TX15* W4 EXP_TXN15
EXP_TXN15 17 AG26 RESERVED NC B43
HD37* 17 EXP_RXN15 RESERVED
HREQJ2 K36 HREQ2* F31 HDJ37 AG25 NC B3
HREQJ3 G37 HREQ3* HD38* H29 HDJ38 DMI_RXP0 Y7 DMI_RX0 AJ24 RESERVED NC B2
18 DMI_RXP0 DMI_TX0
HREQJ4 E42 HREQ4* HD39* F29 HDJ39
18 DMI_RXN0
DMI_RXN0 Y8 DMI_RX0* W2 DMI_TXP0
DMI_TXP0 18 NC A42
HD40* L27 HDJ40 DMI_RXP1 AA9 DMI_RX1 DMI_TX0* Y1 DMI_TXN0
DMI_TXN0 18 AD30 RESERVED
18 DMI_RXP1
8
8
HADSTBJ0
HADSTBJ1
M36
V35
HADSTB0*
HADSTB1*
HD41*
HD42*
M24
J26
HDJ41
HDJ42 18
18
DMI_RXN1
DMI_RXP2
DMI_RXN1
DMI_RXP2
AA10
AA6
DMI_RX1*
DMI_RX2 DMI DMI_TX1
DMI_TX1*
AA2
AB1
DMI_TXP1
DMI_TXN1
DMI_TXP1
DMI_TXN1
18
18
1D5V_PE_GMCH
AC34
Y30
RESERVED
RESERVED
RESERVED
RESERVED
AK21
AJ23
HD43* K26 HDJ43
18 DMI_RXN2
DMI_RXN2 AA7 DMI_RX2* DMI_TX2 Y4 DMI_TXP2
DMI_TXP2 18 Y33 RESERVED RESERVED AJ26 2D5V_DAC
K41 HDSTBP0 HD44* G26 HDJ44 DMI_RXP3 AC9 DMI_RX3 DMI_TX2* AA4 DMI_TXN2
DMI_TXN2 18 AF31 RESERVED RESERVED AL29
8 HDSTBPJ0 18 DMI_RXP3 RESERVED RESERVED
8 HDSTBNJ0 L43 HDSTBN0* HD45* H24 HDJ45
18 DMI_RXN3
DMI_RXN3 AC8 DMI_RX3* DMI_TX3 AB3 DMI_TXP3
DMI_TXP3 18 AD31 AL20
8 HDBIJ0
HDBIJ0 K40 HDINV_0* HD46* K24 HDJ46 DMI_TX3* AC4 DMI_TXN3
DMI_TXN3 18 R237 U30 RESERVED RESERVED AJ21
8 HDSTBPJ1 F35 HDSTBP1 HD47* F24 HDJ47
10 CK_PE_100M_P_GMCH
CK_PE_100M_P_GMCH B14 GCLKP V31 RESERVED RESERVED AL26
G34 HDSTBN1* HD48* E31 HDJ48
10 CK_PE_100M_N_GMCH
CK_PE_100M_N_GMCH B16 GCLKN EXP_COMPO AC12 GMCH_EXP_COMP AA30 RESERVED RESERVED AK27
C
8
8
HDSTBNJ1
HDBIJ1
HDBIJ1 A38 HDINV_1* HD49* A33 HDJ49 Dummy EXP_COMPI AC11 AC30 RESERVED 5 OF 7 RESERVED AJ29 R247 R253 R257 C
J27 HDSTBP2 HD50* E40 HDJ50 R181 0 R0603 +/-5% F15 SDVO_CTRLDATA RESERVED AG29 0 0 0
8 HDSTBPJ2 17 SDVO_CTRLDATA 24.9
8 HDSTBNJ2 M26 HDSTBN2* HD51* D37 HDJ51
17 SDVO_CTRLCLK
R179 0 R0603 +/-5% E15 SDVO_CTRLCLK width 10 mils, spacing 7 mils +/-5% +/-5% +/-5%
HDBIJ2 HDINV_2* HDJ52 Dummy R0603 RED R0603 R0603 R0603
8 HDBIJ2 E29 HD52* C39
8 HDSTBPJ3 E34 HDSTBP3 HD53* D38 HDJ53
2 OF 7 +/-1% GREEN Dummy Dummy Dummy
B37 HDSTBN3* HD54* D33 HDJ54 unstuff when no internal BLUE
8 HDSTBNJ3 HDBIJ3 HDJ55
8 HDBIJ3 B32 HDINV_3* HD55* C35
graphics connection
HD56* D34 HDJ56 FSBSEL0 1D5V_CORE 2D5V_DAC
8,10 FSBSEL0
8 HADSJ W42 HADS* HD57* C34 HDJ57 5V_SYS
8 HTRDYJ W40 HTRDY* HD58* B31 HDJ58
8 HDRDYJ V41 HDRDY* HD59* C31 HDJ59 2D5V_MCH
8,10 FSBSEL1
FSBSEL1
8 HDEFERJ P40 HDEFER* HD60* C32 HDJ60 R267 R177
8 HITMJ W41 HHITM* HD61* D32 HDJ61 2.7K 0 R245 R251 R255
8 HITJ U41 HHIT* HD62* B30 HDJ62 CRB 1.03 pull-up to 2.5V
8,10 FSBSEL2
FSBSEL2 +/-5% +/-5% 0 0 0
8 HLOCKJ U40 HLOCK* HD63* D30 HDJ63 R0603 CK_96M_P_GMCH R0603 +/-5% +/-5% +/-5%
8 HBR0J AA41 HBREQ0* DDCA_CLK CK_96M_N_GMCH Dummy REDJ R0603 R0603 R0603
8 HBNRJ U39 HBNR* HSWING B27 HSWING R182 R180 GREENJ Dummy Dummy Dummy
8 HBPRIJ D42 HBPRI* HSCOMP C27 HSCOMP 4.7K 4.7K R268 R176 BLUEJ
8 HDBSYJ U42 HDBSY* HRCOMP A28 HRCOMP +/-5% +/-5% 3D3V_SYS 2.7K 1D5V_CORE 0
T40 HRS0* R0603 R0603 +/-5% +/-5%
8 HRSJ0
8 HRSJ1 Y43 HRS1* HDVREF D27 MCH_GTLREF Dummy Dummy R0603 R178 R0603
T43 HRS2* HACCVREF D28 0 Dummy HSYNC_P
8 HRSJ2 R164 +/-5% VSYNC_P
8 HCPURSTJ C30 HCPURST*
F38 HPCREQ* HCLKP M31 1K CK_PE_100M_P_GMCH R0603 R204 R203
CK_200M_P_GMCH 10
Y40 HEDRDY* HCLKN M29 +/-5% CK_PE_100M_N_GMCH Dummy 10K 10K 2D5V_DAC
CK_200M_N_GMCH 10
R0603 +/-5% +/-5%
1 OF 7 Dummy 5V_SYS R185 R0603 R0603
0 Dummy Dummy
GMCH_EXP_EN_HDR GMCH_EXP_EN +/-5% R191
17 GMCH_EXP_EN_HDR R262 R0603 0
2.7K Dummy +/-5%
+/-5% R0603
Signal termination (follow Intel reference 0p7) R0603 Dummy
FSB_VTT COMP SIGNAL TERMINATION DDCA_DATA REFSET
FSB_VTT Intel confirm
R263
R192
2.7K stuff when no internal
R198 REFSET +/-5%
B R197 graphics connection B
301 R0603
+/-1% HSCOMP place near GMCH
R0603 255
15 mils width
C200 R0603
R206 60.4 20 mils spacing
1
HSWING R0603 * 2.2pF

50V, NPO, +/-0.25pF
+/-1%
+/-1% C0603
2
Dummy
R199 C183 62
1
R0603
84.5
+/-1% * 10nF
25V, X7R, +/-10% +/-5%
R184
R0603
1K
+/-5%
GMCH_EXP_SLR
R0603 C0603 5 mils width, 5 mils spacing in the breakout

2
5 mils width, 8 mils spacing after the breakout ATX dummy

HSWING voltage should be 0.22*FSB_VTT max. 750 mils BTX pop
12 mils width, 10 mils spacing
max. 3 inches long
caps should be placed near GMCH pin.
FSB_VTT
R213
HRCOMP
R195
16.9 124
R0603 +/-1%
+/-1% R0603
MCH_GTLREF_CPU 8
U14_5 10 mils width, 7 mils spacing R193
max. 500 mils
MCH_GTLREF
R194 C178 10 C177

1
1
R0603
210
+/-1% * 0.1uF
16V, Y5V, +80%/-20% +/-5% * 220pF
50V, X7R, +/-10%
R0603 C0603 C0603
2
U14_1 U14_2 U14_3 U14_4 2 Dummy

A A
Heatsink Clip_2P Clip_2P Clip_2P Clip_2P GTLREF voltage should be 0.63*VTT = 0.75V
Need to apply Heatsink for Lakeport 12 mils width, 15 mils spacing
chipset. For GMCH heatsink hook divider should be within 1.5" of the GTLREF pin
0.22nF caps should be placed near MCH pin
place series resistor as close to divider
FOXCONN PCEG
Title
Lakeport GMCH -1
C 945P01 A

5 4 3 2 1
5 4 3 2 1
U14B U14C
16 M_MAA_B[13..0] M_DQS_B[7..0] 16
15 M_MAA_A[13..0] M_MAA_A0 SMA_A0 1.0 SDQS_A0 M_DQS_A0
M_DQS_A[7..0] 15
M_MAA_B0
M_MAA_B1
BB22 SMA_B0 1.0 SDQS_B0 AM8 M_DQS_B0
M_DQS_BJ0
M_DQS_BJ[7..0] 16
BA32 AU4 M_DQS_AJ[7..0] 15 BB21 SMA_B1 SDQS_B0* AM6 M_DQM_B[7..0] 16
M_MAA_A1 AW32 SMA_A1 SDQS_A0* AR2 M_DQS_AJ0
M_DQM_A[7..0] 15
M_MAA_B2 BA21 SMA_B2 SDM_B0 AL11 M_DQM_B0
M_DATA_B[63..0] 16
M_MAA_A2 BB30 SMA_A2 SDM_A0 AR3 M_DQM_A0
M_DATA_A[63..0] 15
M_MAA_B3 AY21 SMA_B3
M_MAA_A3 BA30 SMA_A3 M_MAA_B4 BC20 SMA_B4 SDQ_B0 AL6 M_DATA_B0
M_MAA_A4 AY30 SMA_A4 SDQ_A0 AP3 M_DATA_A0 M_MAA_B5 AY19 SMA_B5 SDQ_B1 AL8 M_DATA_B1
M_MAA_A5 BA27 SMA_A5 SDQ_A1 AP2 M_DATA_A1 M_MAA_B6 AY20 SMA_B6 SDQ_B2 AP8 M_DATA_B2
M_MAA_A6 BC28 SMA_A6 SDQ_A2 AU3 M_DATA_A2 M_MAA_B7 BA18 SMA_B7 SDQ_B3 AP9 M_DATA_B3
M_MAA_A7 AY27 SMA_A7 SDQ_A3 AV4 M_DATA_A3 M_MAA_B8 BA19 SMA_B8 SDQ_B4 AJ11 M_DATA_B4
M_MAA_A8 AY28 SMA_A8 SDQ_A4 AN1 M_DATA_A4 M_MAA_B9 BB18 SMA_B9 SDQ_B5 AL9 M_DATA_B5
M_MAA_A9 BB27 SMA_A9 SDQ_A5 AP4 M_DATA_A5 M_MAA_B10 BA22 SMA_B10 SDQ_B6 AM10 M_DATA_B6
M_MAA_A10 AY33 SMA_A10 SDQ_A6 AU5 M_DATA_A6 M_MAA_B11 BB17 SMA_B11 SDQ_B7 AP6 M_DATA_B7
D
M_MAA_A11 AW27 SMA_A11 SDQ_A7 AU2 M_DATA_A7 M_MAA_B12 BA17 SMA_B12 M_DQS_B[7..0] 16 D
M_MAA_A12 BB26 SMA_A12 M_DQS_A[7..0] 15
M_MAA_B13 AW42 SMA_B13 SDQS_B1 AV7 M_DQS_B1
M_DQS_BJ[7..0] 16
M_MAA_A13 BC38 SMA_A13 SDQS_A1 BA3 M_DQS_A1
M_DQS_AJ[7..0] 15 SDQS_B1* AR9 M_DQS_BJ1
M_DQM_B[7..0] 16
SDQS_A1* BB4 M_DQS_AJ1 BB23 SWE_B* SDM_B1 AW7 M_DQM_B1
M_DQM_A[7..0] 15 16 M_WE_BJ M_DATA_B[63..0] 16
BB35 SWE_A* SDM_A1 AY2 M_DQM_A1 AY24 SCAS_B*
15 M_WE_AJ M_DATA_A[63..0] 15 16 M_CAS_BJ
BA37 SCAS_A* BA23 SRAS_B* SDQ_B8 AU7 M_DATA_B8
15 M_CAS_AJ 16 M_RAS_BJ M_DATA_B9
15 M_RAS_AJ BA34 SRAS_A* 16 M_BS_B[2..0] SDQ_B9 AV6
SDQ_A8 AW3 M_DATA_A8 M_BS_B0 AW23 SBS_B0 SDQ_B10 AV12 M_DATA_B10
M_BS_A0 BC33 SBS_A0 SDQ_A9 AY3 M_DATA_A9 M_BS_B1 AY23 SBS_B1 SDQ_B11 AM11 M_DATA_B11
M_BS_A1 AY34 SBS_A1 SDQ_A10 BA7 M_DATA_A10 M_BS_B2 AY17 SBS_B2 SDQ_B12 AR5 M_DATA_B12
M_BS_A2 BA26 SBS_A2 SDQ_A11 BB7 M_DATA_A11 SDQ_B13 AR7 M_DATA_B13
15 M_BS_A[2..0]
SDQ_A12 AV1 M_DATA_A12
16 M_SCS_B0J BA40 SCS_B0* SDQ_B14 AR12 M_DATA_B14
BB37 SCSB_A0* SDQ_A13 AW4 M_DATA_A13 AW41 SCS_B1* SDQ_B15 AR10 M_DATA_B15
15 M_SCS_A0J SDQ_A14 M_DATA_A14 16 M_SCS_B1J
15 M_SCS_A1J BA39 SCSB_A1* BC6 BA41 SCS_B2* M_DQS_B[7..0] 16
BA35 SCSB_A2* SDQ_A15 AY7 M_DATA_A15 AW40 SCS_B3* SDQS_B2 AV13 M_DQS_B2
M_DQS_BJ[7..0] 16
AY38 SCSB_A3* M_DQS_A[7..0] 15
SDQS_B2* AT13 M_DQS_BJ2
M_DQM_B[7..0] 16
SDQS_A2 AY11 M_DQS_A2
M_DQS_AJ[7..0] 15
M_SCKE_B0 BA14 SCKE_B0 SDM_B2 AP13 M_DQM_B2
M_DATA_B[63..0] 16
SCKE_A0 16 M_SCKE_B0
15 M_SCKE_A0
M_SCKE_A0 BB25 SDQS_A2* BA10 M_DQS_AJ2
M_DQM_A[7..0] 15 16 M_SCKE_B1
M_SCKE_B1 AY16 SCKE_B1
15 M_SCKE_A1
M_SCKE_A1 AY25 SCKE_A1 SDM_A2 BB10 M_DQM_A2
M_DATA_A[63..0] 15 BA13 SCKE_B2 SDQ_B16 AM15 M_DATA_B16
BC24 SCKE_A2 BB13 SCKE_B3 SDQ_B17 AM13 M_DATA_B17
BA25 SCKE_A3 SDQ_A16 AW12 M_DATA_A16 SDQ_B18 AV15 M_DATA_B18
SDQ_A17 AY10 M_DATA_A17 M_ODT_B0 AY42 SODT_B0 SDQ_B19 AM17 M_DATA_B19
SODT_A0 16 M_ODT_B0 SDQ_B20
15 M_ODT_A0
M_ODT_A0 AW37 SDQ_A18 BA12 M_DATA_A18
16 M_ODT_B1
M_ODT_B1 AV40 SODT_B1 AN12 M_DATA_B20
M_ODT_A1 AY39 SODT_A1 SDQ_A19 BB12 M_DATA_A19 AV43 SODT_B2 SDQ_B21 AR13 M_DATA_B21
15 M_ODT_A1 M_DATA_A20 SDQ_B22 M_DATA_B22
AY37 SODT_A2 SDQ_A20 BA9 AU40 SODT_B3 AP15
BB40 SODT_A3 SDQ_A21 BB9 M_DATA_A21 SDQ_B23 AT15 M_DATA_B23
SDQ_A22 BC11 M_DATA_A22
M_DQS_B[7..0] 16
SDQ_A23 AY12 M_DATA_A23 SDQS_B3 AU23 M_DQS_B3
SCLK_A0 M_DQS_BJ[7..0] 16
BB32 M_DQS_A[7..0] 15 AM29 SCLK_B0 SDQS_B3* AR23 M_DQS_BJ3
M_DQM_B[7..0] 16
15 CK_M_200M_P_DDR0_A SCLK_A0* SDQS_A3 M_DQS_A3 16 CK_M_200M_P_DDR0_B SCLK_B0* M_DQM_B3
15 CK_M_200M_N_DDR0_A AY32 AU18 M_DQS_AJ[7..0] 15 16 CK_M_200M_N_DDR0_B AM27 SDM_B3 AP23 M_DATA_B[63..0] 16
15 CK_M_200M_P_DDR1_A AY5 SCLK_A1 SDQS_A3* AR18 M_DQS_AJ3
M_DQM_A[7..0] 15 16 CK_M_200M_P_DDR1_B AV9 SCLK_B1
15 CK_M_200M_N_DDR1_A BB5 SCLK_A1* SDM_A3 AP18 M_DQM_A3
M_DATA_A[63..0] 15 16 CK_M_200M_N_DDR1_B AW9 SCLK_B1* SDQ_B24 AM24 M_DATA_B24
15 CK_M_200M_P_DDR2_A AK42 SCLK_A2 16 CK_M_200M_P_DDR2_B AL38 SCLK_B2 SDQ_B25 AM23 M_DATA_B25
AK41 SCLK_A2* SDQ_A24 AM20 M_DATA_A24 AL36 SCLK_B2* SDQ_B26 AV24 M_DATA_B26
15 CK_M_200M_N_DDR2_A 16 CK_M_200M_N_DDR2_B
BA31 SCLK_A3 SDQ_A25 AM18 M_DATA_A25 AP26 SCLK_B3 SDQ_B27 AM26 M_DATA_B27
BB31 SCLK_A3* SDQ_A26 AV20 M_DATA_A26 AR26 SCLK_B3* SDQ_B28 AP21 M_DATA_B28
AY6 SCLK_A4 SDQ_A27 AM21 M_DATA_A27 AU10 SCLK_B4 SDQ_B29 AR21 M_DATA_B29
BA5 SCLK_A4* SDQ_A28 AP17 M_DATA_A28 AT10 SCLK_B4* SDQ_B30 AP24 M_DATA_B30
C AH40 SCLK_A5 SDQ_A29 AR17 M_DATA_A29 AJ38 SCLK_B5 SDQ_B31 AT24 M_DATA_B31 C
AH43 SCLK_A5* SDQ_A30 AP20 M_DATA_A30 AJ36 SCLK_B5* M_DQS_B[7..0] 16
SDQ_A31 AT20 M_DATA_A31 SDQS_B4 AT29 M_DQS_B4
M_DQS_BJ[7..0] 16
BC16 RSVD M_DQS_A[7..0] 15 SDQS_B4* AV29 M_DQS_BJ4
M_DQM_B[7..0] 16
AY14 RSVD SDQS_A4 AU35 M_DQS_A4
M_DQS_AJ[7..0] 15 SDM_B4 AR29 M_DQM_B4
M_DATA_B[63..0] 16
AW17 RSVD SDQS_A4* AV35 M_DQS_AJ4
M_DQM_A[7..0] 15
AW18 RSVD SDM_A4 AT34 M_DQM_A4
M_DATA_A[63..0] 15 SDQ_B32 AU27 M_DATA_B32
AL39 RSVD SDQ_B33 AN29 M_DATA_B33
SDQ_A32 AP32 M_DATA_A32 SDQ_B34 AR31 M_DATA_B34
SDQ_A33 AV34 M_DATA_A33 SDQ_B35 AM31 M_DATA_B35
SDQ_A34 AV38 M_DATA_A34 SDQ_B36 AP27 M_DATA_B36
SDQ_A35 AU39 M_DATA_A35 SDQ_B37 AR27 M_DATA_B37
SDQ_A36 AV32 M_DATA_A36 SDQ_B38 AP31 M_DATA_B38
AK40 RSVD SDQ_A37 AT32 M_DATA_A37 DDR_GMCH_VREF_B AM2 SVREF1 SDQ_B39 AU31 M_DATA_B39
SDQ_A38 AR34 M_DATA_A38
M_DQS_B[7..0] 16
SDQ_A39 AU37 M_DATA_A39 SDQS_B5 AP36 M_DQS_B5
M_DQS_BJ[7..0] 16
SDQS_B5* AM35 M_DQS_BJ5
M_DQS_A[7..0] 15 M_DQM_B[7..0] 16
SDQS_A5 M_DQS_A5 M_DQM_B5
DDR_GMCH_VREF_A AM4 SVREF0 SDQS_A5*
SDM_A5
AP42
AP40
AP39
M_DQS_AJ5
M_DQM_A5
M_DQS_AJ[7..0] 15
M_DQM_A[7..0] 15
M_DATA_A[63..0] 15
DDR_B SDM_B5
SDQ_B40
AR38
AP35 M_DATA_B40
M_DATA_B[63..0] 16
SDQ_B41 AP37 M_DATA_B41

SDQ_A40 AR41 M_DATA_A40 TP_RSV_AK18 AK18 RSV_TP3 SDQ_B42 AN32 M_DATA_B42
DDR_A SDQ_A41
SDQ_A42
SDQ_A43
AR42
AN43
AM40
M_DATA_A41
M_DATA_A42
M_DATA_A43
1D8V_STR
WW39 MOW/CRB1.01 update
(must remove pull-down resistor)
Double check in DG1.0
TP_RSV_AK23 AK23 RSV_TP2 SDQ_B43
SDQ_B44
SDQ_B45
AL35
AR35
AU38
M_DATA_B43
M_DATA_B44
M_DATA_B45
SDQ_A44 AU41 M_DATA_A44 SDQ_B46 AM38 M_DATA_B46
SDQ_A45 AU42 M_DATA_A45 TP_SMOCDCOMP1 AM3 SOCOMP1 SDQ_B47 AM34 M_DATA_B47
TP_RSV_AL17 AL17 RSV_TP1 SDQ_A46 AP41 M_DATA_A46
R274
TP_SMOCDCOMP0 AJ8 SOCOMP0 M_DQS_B[7..0] 16
TP_RSV_AK17 AK17 RSV_TP0 SDQ_A47 AN40 M_DATA_A47 SRCOMP1 AJ6 SRCOMP1 SDQS_B6 AG34 M_DQS_B6
M_DQS_BJ[7..0] 16
SRCOMP0 AL5 SRCOMP0 SDQS_B6* AG32 M_DQS_BJ6
M_DQS_A[7..0] 15 M_DQM_B[7..0] 16
SDQS_A6 AG42 M_DQS_A6
M_DQS_AJ[7..0] 15 SDM_B6 AJ39 M_DQM_B6
M_DATA_B[63..0] 16
SDQS_A6* AG41 M_DQS_AJ6
M_DQM_A[7..0] 15 80.6
SDM_A6 AG40 M_DQM_A6
M_DATA_A[63..0] 15
C462 SDQ_B48 AL34 M_DATA_B48
1
R0603 SDQ_B49
SDQ_A48 AL41 M_DATA_A48 * 0.1uF
16V, Y5V, +80%/-20% +/-1%
R271
80.6 SDQ_B50
AJ34
AF32
M_DATA_B49
M_DATA_B50
SDQ_A49 AL42 M_DATA_A49 C0603 +/-1% SDQ_B51 AF34 M_DATA_B51
2
SDQ_A50 AF39 M_DATA_A50 R0603 SDQ_B52 AL31 M_DATA_B52
SDQ_A51 AE40 M_DATA_A51 SDQ_B53 AJ32 M_DATA_B53
B B
SDQ_A52 AM41 M_DATA_A52 SDQ_B54 AG35 M_DATA_B54
SDQ_A53 AM42 M_DATA_A53 SDQ_B55 AD32 M_DATA_B55
SDQ_A54 AF41 M_DATA_A54
M_DQS_B[7..0] 16
SDQ_A55 AF42 M_DATA_A55 SDQS_B7 AD36 M_DQS_B7
M_DQS_BJ[7..0] 16
SDQS_B7* AD38 M_DQS_BJ7
M_DQS_A[7..0] 15 M_DQM_B[7..0] 16
SDQS_A7 AC42 M_DQS_A7
M_DQS_AJ[7..0] 15 SDM_B7 AD39 M_DQM_B7
M_DATA_B[63..0] 16
SDQS_A7* AC41 M_DQS_AJ7 SRCOMP[1:0]
M_DQM_A[7..0] 15
SDM_A7 AC40 M_DQM_A7
M_DATA_A[63..0] 15 10 mils width, 10 mils spacing, max 1.5" length SDQ_B56 AC32 M_DATA_B56
place cap/res within 1" of GMCH package SDQ_B57 AD34 M_DATA_B57
SDQ_A56 AD40 M_DATA_A56 SDQ_B58 Y32 M_DATA_B58
SDQ_A57 AD43 M_DATA_A57 SDQ_B59 AA32 M_DATA_B59
SDQ_A58 AA39 M_DATA_A58 SDQ_B60 AF35 M_DATA_B60
SDQ_A59 AA40 M_DATA_A59 SDQ_B61 AF37 M_DATA_B61
SDQ_A60 AE42 M_DATA_A60 SDQ_B62 AC33 M_DATA_B62
SDQ_A61 M_DATA_A61 SDQ_B63 M_DATA_B63
SDQ_A62
AE41
AB41 M_DATA_A62 4 OF 7 AC35
3 OF 7 SDQ_A63 AB42 M_DATA_A63
1D8V_STR 1D8V_STR
R336 R321
1K 1K
+/-1% +/-1%
R0603 R0603
DDR_GMCH_VREF_A DDR_GMCH_VREF_B
R333 C290 R324 C285

1
A 1K
+/-1% * 0.1uF
16V, Y5V, +80%/-20%
1K
+/-1% * 0.1uF
16V, Y5V, +80%/-20%
A
R0603 C0603 R0603 C0603

2
FOXCONN PCEG
width 12 mils, spacing 12 mils Title
5 mils width/spacing minimum for a max. of 300 mils
in the GMCH break-out area Lakeport GMCH -2
place each cap to Vref pin Size Document Number Rev
C 945P01 A

5 4 3 2 1
5 4 3 2 1
U14E 1D8V_STR
1D5V_CORE
VCCSM BC18
N17 VCC 1.0 VCCSM BC22
P17 VCC VCCSM BC26
AH4 VCC VCCSM BC31 1D5V_CORE 1D5V_CORE
AJ5 VCC VCCSM BC35 U14F U14I
VCC VCCSM U14H
AK4 BC13
AF30 VCC VCCSM BB42 A16 VSS VSS AL2 BB39 VSS VSS M10
AK20 VCC VCCSM BB38 AJ15 VCC 1.0 VCC AC15 A22 VSS VSS AL21 BB41 VSS VSS M13
AK3 VCC VCCSM BB33 AG23 VCC VCC AC17 A26 VSS VSS AL23 BB6 VSS VSS M20
AK2 VCC VCCSM BB28 AG22 VCC VCC AC18 A31 VSS VSS AL24 BC4 VSS VSS M21
AJ14 VCC VCCSM BB24 AG21 VCC VCC AC20 A35 VSS VSS AL27 BC9 VSS VSS M3
AK14 VCC VCCSM BB20 AG20 VCC VCC AC24 A4 VSS VSS AL3 C12 VSS VSS M35
AK15 VCC VCCSM BB16 AG19 VCC VCC AC26 A40 VSS VSS AL32 C14 VSS VSS M37
AJ13 VCC VCCSM AY41 AG18 VCC VCC AC27 AA11 VSS VSS AL33 C22 VSS VSS M5
D
AH2 VCC VCCSM AW21 AG17 VCC VCC AD15 AA12 VSS VSS AL37 C3 VSS VSS M8 D
AH1 VCC VCCSM AW13 AG15 VCC VCC AD17 AA14 VSS VSS AL43 C40 VSS VSS M9
AG14 VCC VCCSM AV31 AB18 VCC VCC AJ17 AA21 VSS VSS AL7 C5 VSS VSS N13
AG13 VCC VCCSM AV21 Y27 VCC VCC AD19 AA23 AM33 C7 N15
VCC VSS VSS VSS VSS
AG12 VCC VCCSM AW35 Y25 VCC AD21 AA25 VSS VSS AM36 D1 VSS VSS N2
AG11 VCC VCCSM AW34 Y19 VCC VCC AD23 AA27 AM37 D10 N24
VSS VSS VSS VSS
AG10 VCC VCCSM AW31 Y18 VCC VCC AD25 AA29 VSS VSS AM39 D16 VSS VSS N26
AG9 VCC VCCSM AW29 W27 VCC VCC AD26 AA3 VSS VSS AM5 D2 VSS VSS N27
AG8 VCC VCCSM AW24 W26 VCC VCC AE17 AA31 AM7 D20 N29
VCC VSS VSS VSS VSS
AG7 VCCSM AW20 W20 VCC VCC AE18 AA33 VSS VSS AM9 D21 VSS VSS N31
AG6 VCC VCCSM AW15 U19 VCC VCC AE20 AA36 VSS VSS AN13 D43 VSS VSS N33
AG5 VCC VCCSM AV42 U18 VCC VCC AE22 AA8 VSS VSS AN15 D5 VSS VSS N36
AG4 VCC VCCSM AV23 U17 VCC VCC AE24 AB2 VSS VSS AN17 E12 VSS VSS N39
AG3 VCC VCCSM AV18 U15 VCC VCC AJ18 AB43 VSS VSS AN18 E13 VSS VSS N43
AG2 VCC R24 VCC VCC AE26 AC10 VSS VSS AN2 E17 VSS VSS N6
AF14 VCC 1D5V_PE_GMCH R23 VCC VCC AE27 AC14 VSS VSS AN20 E18 VSS VSS N8
AF13 VCC R21 VCC VCC AF15 AC19 VSS VSS AN21 E20 VSS VSS P14
AF12 VCC VCC_EXP AD4 R20 VCC VCC AF17 AC2 VSS VSS AN23 E21 VSS VSS P15
VCC VCC_EXP VCC VCC
POWER
AF11 AD5 R18 AF19 AC21 VSS VSS AN24 E3 VSS VSS P24
POWER
AF10 VCC VCC_EXP AD6 AF29 VCC VCC AF21 AC23 VSS VSS AN26 E32 VSS VSS P26
AF9 VCC VCC_EXP AD8 R17 VCC VCC AF23 1D8V_STR AC25 VSS VSS AN27 E4 VSS VSS P27
AF8 VCC VCC_EXP AD10 R15 VCC VCC AJ20 AC29 VSS VSS AN31 E7 VSS VSS P29
AF7 VCC VCC_EXP AD12 U20 VCC AC3 VSS VSS AN4 E9 VSS VSS P3
AF6 VCC VCC_EXP N5 U21 VCC VCCSM BC40 AC31 VSS VSS AN42 F13 VSS VSS P30
AD14 VCC VCC_EXP N7 U22 VCC VCCSM AY43 AC36 VSS VSS AP10 F18 VSS VSS R12
AC22 VCC VCC_EXP N9 U23 VCC AC37 VSS VSS AP12 F2 VSS VSS R14
AB23 VCC VCC_EXP N10 U24 VCC AC38 VSS VSS AP29 F26 VSS VSS R26
AB22 VCC VCC_EXP N12 U25 VCC AC39 AP34 F34 R29
VSS VSS VSS VSS
AB21 VCC VCC_EXP R5 U26 VCC AC7 VSS VSS AP38 F42 VSS VSS R30
AA22 VCC VCC_EXP R10 V15 VCC AD11 VSS VSS AP5 F6 VSS VSS R31
P21 VCC VCC_EXP AE2 V17 VCC AD13 VSS VSS AP7 G10 VSS VSS R34
P20 VCC VCC_EXP R11 V18 VCC AD18 VSS VSS AR1 G13 VSS VSS R37
FSB_VTT P18 VCC VCC_EXP R13 AF25 VCC AD20 VSS VSS AR15 G15 VSS VSS R39
VCC_EXP U6 AF26 VCC AD22 VSS VSS AR20 G18 VSS VSS R6
F27 VTT VCC_EXP U7 AF27 VCC AD24 AR24 G20 R9
VCC_EXP VSS VSS VSS VSS
G23 VTT U8 AG24 VCC AD27 VSS VSS AR32 G21 VSS VSS T2
H23 VTT VCC_EXP U13 V19 VCC AD29 AR37 G24 T42
VSS VSS VSS VSS
J23 VTT VCC_EXP V5 V20 VCC AD33 VSS VSS AR39 G27 VSS VSS U12
C K23 VTT VCC_EXP V6 V21 VCC AD35 VSS VSS AR43 G29 VSS VSS U14 C
L23 VTT VCC_EXP V7 V22 VCC AD37 VSS VSS AR6 G3 VSS VSS U29
M23 VTT VCC_EXP V9 V23 VCC AD42 VSS VSS AT12 G31 VSS VSS U3
A24 VTT VCC_EXP AE3 V25 VCC AD7 VSS VSS AT17 G32 VSS VSS U31
N23 VTT VCC_EXP V10 V27 VCC AD9 VSS VSS AT18 G35 VSS VSS U33
C26 VTT VCC_EXP V13 W17 VCC AE19 VSS VSS AT21 G38 VSS VSS U36
D23 VTT VCC_EXP Y13 W18 VCC AE21 VSS VSS AT23 G5 VSS VSS U38
D24 VTT VCC_EXP AA5 W19 VCC AE23 VSS VSS AT26 G7 VSS VSS U5
D25 VTT VCC_EXP AA13 W22 VCC AE25 VSS VSS AT27 G9 VSS VSS U9
P23 VTT VCC_EXP AC5 W24 VCC AF1 VSS VSS AT31 H12 VSS VSS V11
F23 VTT VCC_EXP AC6 Y15 VCC AF18 VSS VSS AU12 H17 VSS VSS V12
E27 VTT VCC_EXP AC13 Y17 VCC AF2 VSS VSS AU13 H26 VSS VSS V14
E26 VTT VCC_EXP AD1 Y21 VCC AF20 VSS VSS AU15 H27 VSS VSS V2
E24 VTT VCC_EXP AD2 Y23 VCC AF22 VSS VSS AU17 H32 VSS VSS V24
E23 VTT VCC_EXP AE4 AA15 VCC AF24 VSS VSS AU20 J10 VSS VSS V26
C25 VTT VCC_EXP N11 AA17 VCC AF3 VSS VSS AU21 J12 VSS VSS V29
C23 VTT AA18 VCC AF33 VSS VSS AU24 J2 VSS VSS V34
B26 VTT AA19 VCC AF36 VSS VSS AU26 J21 VSS VSS V36
AB17 VCC AG30 VSS VSS AU6 J43 VSS VSS V43
VCCA_DPLLB B19 VCCA_DPLLB AB19 VCC AG31 AU9 J5 V8
VCCA_SMPLL VSS VSS VSS VSS
2D5V_DAC VCCA_SMPLL B20 AB20 VCC AG33 VSS VSS AV10 J7 VSS VSS W21
VCCA_HPLL C21 VCCA_HPLL AB24 VCC AG36 VSS VSS AV17 K10 VSS VSS W23
2D5V_MCH VCCA_DPLLA C19 VCCA_DPLLA AB25 VCC AG37 AV2 K12 W25
VSS VSS VSS VSS
C18 VCCA_DAC AB26 VCC AG38 VSS VSS AV37 K13 VSS VSS W3
B18 VCCA_DAC AB27 VCC AG39 VSS VSS AW10 K15 VSS VSS Y12
D19 VCC2 7 OF 7 AH42 VSS VSS AY1 K20 VSS VSS Y14
AJ10 VSS VSS B11 K27 VSS VSS Y2
VCCA_EXPPLL B17 VCCA_EXPPLL AJ31 VSS VSS B21 K32 VSS VSS Y22
A18 VSSA_DAC 6 OF 7 AJ33 VSS VSS B22 K34 VSS VSS Y24
1D5V_CORE 1D5V_CORE 1D5V_CORE AK24 B4 K6 Y35
VSS VSS VSS VSS
B
AK26 VSS VSS B6 K7 VSS VSS Y37 B
L16 R200 AK29 VSS VSS B9 L12 VSS VSS Y39
AK30 BA4 L13 Y42
*
VCCA_EXPPLL C490 C489 VSS VSS VSS VSS

AL1 VSS VSS BA42 L2 VSS VSS Y5
1
L0805 1uH
0.5
C175 C185
2D5V_MCH L15 from GMCH to 1st cap must be less than 1 inch
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
AL10
AL12
VSS
VSS
VSS
VSS
BB11
BB14
L24
L26
VSS
VSS
VSS
VSS
Y6
Y9
1
* 10uF
* 0.1uF
* 2D5V_DAC C0603 C0603 AL13 BB19 L29
2
R0603 10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% Dummy Dummy VSS VSS VSS
AL15 VSS VSS BB3 L31 VSS
+/-1% C1206 C0603 AL18 BB34 L42
2
FB L0805 180 Ohm EC19 C173 C174 VSS VSS VSS

1
* 100uF
16V, +/-20% * 0.1uF
16V, Y5V, +80%/-20% * 10nF
25V, X7R, +/-10%
QG82945G<REV> QG82945G <REV>
L12 Double check high-frequency requirements for GMCH in new DG or CRB
CE20D50H110 C0603 C0603
<PART_SYM_NUM> <PART_SYM_NUM>
2
2
*
VCCA_HPLL
1D5V_CORE 1D5V_CORE
C191 2D5V_DAC Filter
L1206 10uH
1
* 0.1uF
16V, Y5V, +80%/-20%
C0603 C492 C491
2
1
L10
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603
2
2
*
VCCA_DPLLA Dummy Dummy

1D5V_CORE from GMCH to 1st cap must be less than 1 inch
EC21 C194
L1206 10uH
1
* 220uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
L20 1 2 L1206 0.1uH 1D5V_PE_GMCH
place GMCH backside
1D5V_CORE
Place in 1D5V_CORE plane as close to the GMCH as possible
*
CE20D50H110 C0603 L19 L0805 0.1uH EC29 C238 C237

2
Dummy * 220uF
6.3V, +/-20% * 10uF
6.3V, Y5V, +80%/-20% * 10uF
6.3V, Y5V, +80%/-20%
L9
CE20D50H110 C0805 C0805 C242 C243 C244
2
2
*
1
VCCA_DPLLB
1D8V_STR Connect ground sides of caps with * 10uF
6.3V, Y5V, +80%/-20% * 10uF
6.3V, Y5V, +80%/-20% * 10uF
6.3V, Y5V, +80%/-20%
EC20 C193 co-layout with inductor traces to GND balls C0805 C0805 C0805
2
L1206 10uH
1
* 220uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20% PCI Express Filter
(less than 100 mils from the package)
CE20D50H110 C0603
2
Place in FSB_VTT plane as close to the GMCH as possible C274 C275 C276 1D5V_CORE Decoupling
1
A
L11
(less than 100 mils from the package) * 2.2uF
6.3V, Y5V, +80%/-20% * 2.2uF
6.3V, Y5V, +80%/-20% * 2.2uF
6.3V, Y5V, +80%/-20%
A
FSB_VTT C0603 C0603 C0603

2
2
*
VCCA_SMPLL
C190
L1206 10uH
1
* 0.1uF C203 C209 C129 C192

1
16V, Y5V, +80%/-20%

* 10uF
* 10uF
* 10uF
* 0.1uF C273 C277 C270
1
C0603 6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
* 2.2uF
* 2.2uF
* 2.2uF
2
C0805 C0805 C0805 C0603 6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20%
FOXCONN PCEG
2
C0603 C0603 C0603

2
FSB_VTT Decoupling Title

from GMCH to 1st cap must be less than 1 inch. Lakeport GMCH -3
If 0.5 Ohm, +/- 1%, R0603 is not easy get, you could replace by GMCH Memory Decoupling
0 Ohm, +/- 1%, R0603.
C 945P01 A

5 4 3 2 1
5 4 3 2 1
DIMM1
DDR2 Channel A DIMM1 DDR2 Channel A Termination
2 VSS NC 68
5 VSS NC/TEST 102
8 VSS NC 19
11 VSS
1D8V_STR 14 VSS M_ODT_A1
17 VSS ODT1 77 M_ODT_A1 13
20 195 M_ODT_A0
VSS ODT0 M_ODT_A0 13
23 VSS
26 VSS green color , P/N: AT24011-H3G
29 VSS
R361 32 42 blue color , P/N: AT24011-H3L
1K VSS CB<0>
35 VSS CB<1> 43
+/-1% 38 48
R0603 VSS CB<2>
41 VSS CB<3> 49
D
44 VSS CB<4> 161 D
47 162 VTT_DDR
VSS CB<5> M_BS_A[2..0] 13
SMVREF_A 50 167 RN20
VSS CB<6>
65
66
VSS CB<7> 168 *1 2
M_MAA_A5
M_MAA_A8
M_MAA_A[13..0] 13
R366 C343 VSS 3 4 M_MAA_A6
79 VSS 5 6
1
1K
+/-1% * 0.1uF
16V, Y5V, +80%/-20%
82
85
VSS
VSS M_DQS_AJ[7..0] 13
7 8
M_MAA_A4
R0603 C0603 88 33
2
VSS M_DQS_A0 +/-5%

91 VSS DQS<0> 7
94 6 8P4R0402
VSS DQS#<0> M_DQS_AJ0 VTT_DDR
97 VSS
100 16 M_DQS_A1 R405 33 R0402 +/-5% M_MAA_A10
VSS DQS<1>
103 VSS DQS#<1> 15
Place this cap at the resistor divider circuit 106 M_DQS_AJ1
VSS M_DQS_A2 RN22 R406 43 R0402 +/-5%
109 VSS DQS<2> 28 M_SCS_A0J 13
112
115
VSS DQS#<2> 27
M_DQS_AJ2
*1 2
M_MAA_A3
M_MAA_A2 R410 43 R0402 +/-5%
M_SCS_A1J 13
VSS M_DQS_A3 3 4 M_MAA_A1
118 VSS DQS<3> 37 5 6
121 36 M_MAA_A0
VSS DQS#<3> M_DQS_AJ3 7 8
124 VSS
127 84 M_DQS_A4 33
1D8V_STR VSS DQS<4> +/-5% R408 43 R0402 +/-5% M_ODT_A0
130 VSS DQS#<4> 83
133 M_DQS_AJ4 8P4R0402
VSS M_DQS_A5
136 VSS DQS<5> 93
139 92 RN19
VSS DQS#<5>
142
145
VSS
105
M_DQS_AJ5
M_DQS_A6
*1 2
M_MAA_A12
M_MAA_A11
R411 43 R0402 +/-5% M_ODT_A1
Dummy
Dummy
VSS DQS<6> 3 4
EC34
EC41
EC53
148 104 M_MAA_A7

VSS DQS#<6> M_DQS_AJ6 5 6 M_MAA_A9
151 VSS 7 8
* * * 154
157
VSS DQS<7> 114
113
M_DQS_A7
33
VSS DQS#<7>
CE25D60H110
6.3V, +/-20%
470uF
CE25D60H110
6.3V, +/-20%
470uF
CE25D60H110
6.3V, +/-20%
470uF
160 M_DQS_AJ7 +/-5%

VSS M_DQS_A[7..0] 13
163 46 8P4R0402
VSS DQS<8> R402 43 R0402 +/-5% M_SCKE_A1
166 VSS DQS#<8> 45
169 R409 33 R0402 +/-5% M_MAA_A13
VSS M_DQM_A0 R403 43 R0402 +/-5% M_SCKE_A0
198 VSS DM0/DQS9 125
201 126 RN21
VSS NC/DQS9#
C 204
207
VSS
134 M_DQM_A1
*1 2
M_BS_A0
M_BS_A1
C
VSS DM1/DQS10 3 4
210 VSS NC/DQS10# 135 5 6 M_RAS_AJ 13
place between Ch A DIMM II 213 VSS 7 8 M_WE_AJ 13
216 146 M_DQM_A2
and Ch B DIMM 1 219
VSS DM2/DQS11
147 33
VSS NC/DQS11# +/-5%
222 VSS
225 155 M_DQM_A3 8P4R0402
VSS DM3/DQS12
228 VSS NC/DQS12# 156
231 R404 33 R0402 +/-5% M_BS_A2
VSS M_DQM_A4
234 VSS DM4/DQS13 202
1D8V_STR 237 203 R407 33 R0402 +/-5%
VSS NC/DQS13# M_CAS_AJ 13
51 VDDQ
1D8V_STR 56 211 M_DQM_A5
VDDQ DM5/DQS14
62 VDDQ NC/DQS14# 212
72 VDDQ
75 223 M_DQM_A6
VDDQ DM6/DQS15
C352
C354
C349
C350
191 VDDQ
194 232 M_DQM_A7
VDDQ DM7/DQS16
1
* * * 82pF
* 181
175
VDDQ
VDDQ
NC/DQS16# 233
M_DQM_A[7..0] 13
10V, Y5V, +80%/-20%
1uF C0603
C0603
C0603
10V, Y5V, +80%/-20%
1uF C0603
170 164
50V, NPO, +/-5%
50V, NPO, +/-5%

2
VDDQ DM8/DQS17
53 VDD NC/DQS17# 165
59 VDD M_DATA_A[63..0] 13
64 3 M_DATA_A0
VDD DQ<0>
82pF
197 4 M_DATA_A1
VDD DQ<1> M_DATA_A2
69 VDD DQ<2> 9
172 10 M_DATA_A3
VDD DQ<3> M_DATA_A4 VTT_DDR
187 VDD DQ<4> 122
184 123 M_DATA_A5
VDD DQ<5> M_DATA_A6
178 VDD DQ<6> 128
Channel A DIMM 1 1.8V high-frequency decoupling caps. 189 129 M_DATA_A7 C446 C477 C470 C472 C447 C478
VDD DQ<7>
1
M_DATA_A8
place as close to DIMM power pins as possible 67 VDD DQ<8>
DQ<9>
12
13 M_DATA_A9 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
21 M_DATA_A10 C0603 C0603 C0603 C0603 Dummy C0603 C0603 Dummy
2
DQ<10> M_DATA_A11
18 RC1 DQ<11> 22
3D3V_SYS 55 131 M_DATA_A12
B RC0 DQ<12> M_DATA_A13 B
238 VDDSPD DQ<13> 132
1 140 M_DATA_A14
10,16,25 SMB_CLK_MAIN VREF DQ<14> M_DATA_A15
120 SCL DQ<15> 141
119 24 M_DATA_A16
10,16,25 SMB_DATA_MAIN SMVREF_A SDA DQ<16> M_DATA_A17 1D8V_STR
DQ<17> 25
C356 101 30 M_DATA_A18
SA2 DQ<18>
1
Place this cap close to DIMM * 0.1uF

16V, Y5V, +80%/-20%
240
239
SA1
SA0
DQ<19>
DQ<20>
31
143
M_DATA_A19
M_DATA_A20 C402 C398 C405 C399 C406 C400 C401
1
M_DATA_A21
C0603 SA2 SA1 SA0 144
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
2
DQ<21> M_DATA_A22 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
13 M_BS_A[2..0] 0 0 0 190 BA1 DQ<22> 149
M_BS_A1 71 150 M_DATA_A23 C0603 C0603 C0603 C0603 C0603 C0603 C0603
2
M_BS_A0 BA0 DQ<23> M_DATA_A24
DQ<24> 33
34 M_DATA_A25
M_SCKE_A1 DQ<25> M_DATA_A26
171 CKE1 DQ<26> 39
13 M_SCKE_A1 M_SCKE_A0 52 40 M_DATA_A27 VTT_DDR
13 M_SCKE_A0 CKE0 DQ<27> M_DATA_A28
DQ<28> 152
153 M_DATA_A29
DQ<29> M_DATA_A30
DQ<30> 158
M_DATA_A31
13 M_SCS_A1J
76
193
S1# DQ<31> 159
80 M_DATA_A32
Channel A VTT_0.9V high-frequency decoupling caps.
13 M_SCS_A0J S0# DQ<32>
221
DQ<33> 81
86
M_DATA_A33
M_DATA_A34
Place as close to termination resistors as possible
13 CK_M_200M_N_DDR2_A CK2#/RFU DQ<34> M_DATA_A35
220 CK2/RFU DQ<35> 87
13 CK_M_200M_P_DDR2_A 138 199 M_DATA_A36
13 CK_M_200M_N_DDR1_A CK1#/RFU DQ<36> M_DATA_A37
137 CK1/RFU DQ<37> 200
13 CK_M_200M_P_DDR1_A 186 205 M_DATA_A38
13 CK_M_200M_N_DDR0_A CK0# DQ<38> M_DATA_A39
185 CK0 DQ<39> 206
13 CK_M_200M_P_DDR0_A 89 M_DATA_A40
13 M_MAA_A[13..0] M_MAA_A0 DQ<40> M_DATA_A41
188 A0 DQ<41> 90
M_MAA_A1 183 95 M_DATA_A42 VTT_DDR
M_MAA_A2 A1 DQ<42> M_DATA_A43
63 A2 DQ<43> 96
M_MAA_A3 182 208 M_DATA_A44
61 A4 DQ<45> 209
180 A6 DQ<47> 215
179 A8 DQ<49> 99
A M_MAA_A9 177 107 M_DATA_A50 A
70 A10/AP DQ<51> 108
M_MAA_A11 57 217 M_DATA_A52 C418 C417
A11 DQ<52>
1
M_MAA_A12 M_DATA_A53
M_MAA_A13
176
196
A12
A13
DQ<53>
DQ<54>
218
226 M_DATA_A54 * 4.7uF
10V, Y5V, +80%/-20% * 4.7uF
10V, Y5V, +80%/-20%
174 227 M_DATA_A55 C0805 Dummy C0805 Dummy
2
A14 DQ<55> M_DATA_A56

13 M_BS_A[2..0] 173 A15 DQ<56> 110
M_BS_A2 54 111 M_DATA_A57
A16/BA2 DQ<57> M_DATA_A58
DQ<58> 116
117 M_DATA_A59
13 M_CAS_AJ 74 CAS#
DQ<59>
DQ<60> 229 M_DATA_A60
M_DATA_A61
Channel A VTT_0.9V Mid Range FOXCONN PCEG
13 M_RAS_AJ 192 RAS# DQ<61> 230
13 M_WE_AJ 73 WE# DQ<62> 235
236
M_DATA_A62
M_DATA_A63
decoupling caps. Title
DQ<63> DDR2 Channel A DIMM1
DDR2_DIMM
CONN, DIMM, DDR II, 1.8V, Tail=2.67mm, Gold Flash, DIP-240P
C 945P01 A
DDR240 Date: Tuesday, July 12, 2005 Sheet 15 of 30
5 4 3 2 1
5 4 3 2 1
DIMM2
DDR2 Channel B DIMM2 2 68
DDR2 Channel A Termination
VSS NC
5 VSS NC/TEST 102
8 VSS NC 19
11 VSS
14 VSS
17 77 M_ODT_B1
VSS ODT1 M_ODT_B1 13
1D8V_STR 20 195 M_ODT_B0
VSS ODT0 M_ODT_B0 13
23 VSS
26 VSS
29 VSS
32 42 VTT_DDR
VSS CB<0> M_BS_B[2..0] 13
35 VSS CB<1> 43
R423 38 48 RN27
VSS CB<2> M_MAA_B[13..0] 13
1K
+/-1%
41
44
VSS CB<3> 49
161
*1 2
M_MAA_B10
M_MAA_B0
R0603 VSS CB<4> 3 4 M_BS_B0
D
47 VSS CB<5> 162 5 6 D
50 167 M_BS_B1
VSS CB<6> 7 8 VTT_DDR
65 VSS CB<7> 168
SMVREF_B 66 33
VSS +/-5%
79 VSS
82 8P4R0402
R424 C420 VSS R460 43 R0402 +/-5%
85 VSS M_DQS_BJ[7..0] 13 M_SCS_B0J 13
1
1K
+/-1% * 0.1uF
16V, Y5V, +80%/-20%
88
91
VSS
VSS DQS<0> 7 M_DQS_B0
*1
RN26
2
M_MAA_B4 R463 43 R0402 +/-5%
M_SCS_B1J 13
R0603 C0603 94 6 M_MAA_B3
2
VSS DQS#<0> M_DQS_BJ0 3 4 M_MAA_B2

97 VSS 5 6
100 16 M_DQS_B1 M_MAA_B1
VSS DQS<1> 7 8
103 VSS DQS#<1> 15
106 M_DQS_BJ1 33 R458 43 R0402 +/-5% M_SCKE_B1
VSS M_DQS_B2 +/-5%
109 VSS DQS<2> 28
Place this cap at the resistor divider circuit 112 27 8P4R0402 R459 43 R0402 +/-5% M_SCKE_B0
VSS DQS#<2> M_DQS_BJ2
115 VSS
118 37 M_DQS_B3 RN25
VSS DQS<3>
121
124
VSS DQS#<3> 36
M_DQS_BJ3
*1 2
M_MAA_B9
M_MAA_B5
VSS M_DQS_B4 3 4 M_MAA_B8 R461 43 R0402 +/-5% M_ODT_B0
127 VSS DQS<4> 84 5 6
130 83 M_MAA_B6
VSS DQS#<4> M_DQS_BJ4 7 8
133 VSS
1D8V_STR 136 93 M_DQS_B5 33
VSS DQS<5> +/-5% R464 43 R0402 +/-5% M_ODT_B1
139 VSS DQS#<5> 92
142 M_DQS_BJ5 8P4R0402
VSS M_DQS_B6
145 VSS DQS<6> 105
148 104 RN24
VSS DQS#<6>
151
154
VSS
114
M_DQS_BJ6
M_DQS_B7
*1 2
M_BS_B2
M_MAA_B12
VSS DQS<7> 3 4 M_MAA_B11
157 VSS DQS#<7> 113 5 6
C353
C355
C419
C351
160 M_DQS_BJ7 M_MAA_B7

VSS M_DQS_B[7..0] 13 7 8
163 VSS DQS<8> 46
1
* * * * 166
169
VSS
VSS
DQS#<8> 45 33
+/-5%
C0603
10V, Y5V, +80%/-20%
C0603 1uF
10V, Y5V, +80%/-20%
C0603 1uF
C0603
198 125 M_DQM_B0 8P4R0402

50V, NPO, +/-5%
50V, NPO, +/-5%

2
VSS DM0/DQS9
201 VSS NC/DQS9# 126
204 R462 33 R0402 +/-5% M_MAA_B13
VSS M_DQM_B1
C 207 VSS DM1/DQS10 134 C
82pF
82pF
210 VSS NC/DQS10# 135

213 RN28
VSS
216
219
VSS DM2/DQS11 146
147
M_DQM_B2
*1 2 M_WE_BJ
M_RAS_BJ
13
13
VSS NC/DQS11# 3 4
222 VSS 5 6 M_CAS_BJ 13
225 155 M_DQM_B3
VSS DM3/DQS12 7 8
228 VSS NC/DQS12# 156
231 33
VSS M_DQM_B4 +/-5%
234 VSS DM4/DQS13 202
1D8V_STR 237 203 8P4R0402
VSS NC/DQS13#
Channel B DIMM1 1.8V high-frequency decoupling caps. 51 VDDQ
place as close to DIMM power pins as possible 56 211 M_DQM_B5
VDDQ DM5/DQS14
72 VDDQ
75 223 M_DQM_B6
VDDQ DM6/DQS15
191 VDDQ
194 232 M_DQM_B7
VDDQ DM7/DQS16
175 VDDQ M_DQM_B[7..0] 13
170 VDDQ DM8/DQS17 164
53 VDD NC/DQS17# 165
59 VDD M_DATA_B[63..0] 13
64 3 M_DATA_B0
VDD DQ<0> M_DATA_B1
197 VDD DQ<1> 4
69 9 M_DATA_B2
VDD DQ<2> M_DATA_B3 VTT_DDR
172 VDD DQ<3> 10
187 122 M_DATA_B4
VDD DQ<4> M_DATA_B5
184 VDD DQ<5> 123
178 128 M_DATA_B6 C403 C474 C475 C473 C476 C404 C407
VDD DQ<6>
1
M_DATA_B7
189
67
VDD
VDD
DQ<7>
DQ<8>
129
12 M_DATA_B8 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
13 M_DATA_B9 C0603 C0603 Dummy C0603 C0603 C0603 Dummy C0603 Dummy C0603
2
DQ<9> M_DATA_B10
DQ<10> 21
18 22 M_DATA_B11
3D3V_SYS RC1 DQ<11> M_DATA_B12
55 RC0 DQ<12> 131
238 132 M_DATA_B13
B VDDSPD DQ<13> M_DATA_B14 B
1 VREF DQ<14> 140
10,15,25 SMB_CLK_MAIN 120 141 M_DATA_B15
SCL DQ<15> M_DATA_B16 1D8V_STR
119 SDA DQ<16> 24
10,15,25 SMB_DATA_MAIN SMVREF_B 25 M_DATA_B17
C421 DQ<17> M_DATA_B18
101 SA2 DQ<18> 30
1
* 0.1uF 240 SA1 DQ<19> 31 M_DATA_B19 C459 C463 C458 C461 C464 C460 C465
1
M_DATA_B20
Place this cap close to DIMM 16V, Y5V, +80%/-20%
C0603 SA2 SA1 SA0
239 SA0 DQ<20> 143
144 M_DATA_B21 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
2
DQ<21> M_DATA_B22 C0603 C0603 C0603 C0603 C0603 C0603 C0603

0 1 0 190 149
2
13 M_BS_B[2..0] M_BS_B1 BA1 DQ<22> M_DATA_B23
71 BA0 DQ<23> 150
M_BS_B0 33 M_DATA_B24
DQ<24> M_DATA_B25
DQ<25> 34
M_SCKE_B1 171 39 M_DATA_B26 VTT_DDR
13 M_SCKE_B1 M_SCKE_B0 CKE1 DQ<26> M_DATA_B27
52 CKE0 DQ<27> 40
13 M_SCKE_B0 M_DATA_B28
DQ<28> 152
153 M_DATA_B29
Channel B VTT_0.9V high-frequency decoupling caps.
DQ<29>
DQ<30> 158 M_DATA_B30
M_DATA_B31
Place as close to termination resistors as possible
76 S1# DQ<31> 159
13 M_SCS_B1J 193 80 M_DATA_B32
13 M_SCS_B0J S0# DQ<32> M_DATA_B33
DQ<33> 81
221 86 M_DATA_B34
13 CK_M_200M_N_DDR2_B CK2#/RFU DQ<34> M_DATA_B35
220 CK2/RFU DQ<35> 87
13 CK_M_200M_P_DDR2_B 138 199 M_DATA_B36
13 CK_M_200M_N_DDR1_B CK1#/RFU DQ<36> M_DATA_B37
137 CK1/RFU DQ<37> 200
13 CK_M_200M_P_DDR1_B 186 205 M_DATA_B38
13 CK_M_200M_N_DDR0_B CK0# DQ<38> M_DATA_B39
185 CK0 DQ<39> 206
13 CK_M_200M_P_DDR0_B 89 M_DATA_B40
13 M_MAA_B[13..0] M_MAA_B0 DQ<40> M_DATA_B41 VTT_DDR
188 A0 DQ<41> 90
M_MAA_B1 183 95 M_DATA_B42
M_MAA_B2 A1 DQ<42> M_DATA_B43
63 A2 DQ<43> 96
61 A4 DQ<45> 209
180 A6 DQ<47> 215
179 A8 DQ<49> 99
M_MAA_B10 A9 DQ<50> M_DATA_B51 C416 C466
A 70 A10/AP DQ<51> 108 A
1
1
M_MAA_B11 M_DATA_B52
M_MAA_B12
57
176
A11
A12
DQ<52>
DQ<53>
217
218 M_DATA_B53 * 4.7uF
10V, Y5V, +80%/-20% * 4.7uF
10V, Y5V, +80%/-20%
M_MAA_B13 196 226 M_DATA_B54 C0805 Dummy C0805 Dummy
2
2
A13 DQ<54> M_DATA_B55
174 A14 DQ<55> 227
173 110 M_DATA_B56
13 M_BS_B[2..0] M_BS_B2 A15 DQ<56> M_DATA_B57
54 A16/BA2 DQ<57> 111
116 M_DATA_B58
DQ<58> M_DATA_B59
74
DQ<59> 117
229 M_DATA_B60
Channel B VTT_0.9V Mid Range decoupling
13 M_CAS_BJ
13 M_RAS_BJ 192
CAS#
RAS#
DQ<60>
DQ<61> 230 M_DATA_B61
M_DATA_B62
caps. FOXCONN PCEG
13 M_WE_BJ 73 WE# DQ<62> 235
236 M_DATA_B63 Title
DQ<63>
DDR2 Channel B DIMM2
DDR2_DIMM
CONN, DIMM, DDR II, 1.8V, Tail=2.67mm, Gold Flash, DIP-240P
DDR240
C 945P01 A
Date: Tuesday, July 12, 2005 Sheet 16 of 30

5 4 3 2 1
5 4 3 2 1
3D3V_SB 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS
PCIE-16
5V_SYS
B1 12V PRSNT1# A1
B2 A2 3D3V_SYS 3D3V_SYS
12V 12V
B3 RSVD 12V A3
B4 A4 -12V_SYS 5V_SYS 12V_SYS
GND GND
18,21,25 SMB_CLK_RESUME B5 SMCLK JTAG2 A5
18,21,25 SMB_DATA_RESUME B6 SMDAT JTAG3 A6
B7 GND JTAG4 A7
B8 A8 PCI1 PCI_SLOT
3.3V JTAG5
B9 JTAG1 3.3V A9 B1 -12V TRST# A1
D
B10 3.3VAUX 3.3V A10 B2 TCK +12V A2 D
WAKEJ B11 A11 PCIE_PLTRSTJ B3 A3
18,21 WAKEJ WAKE# PWRGD PCIE_PLTRSTJ 21,25 GND1 TMS
PCI Riser-Card B4 TDO TDI A4
B5 +5V1 +5V2 A5
KEY B6 A6 INTBJ
CK_33M_PCI1 R52 R0603 CK_33M_PCI1_EXT INTCJ +5V3 INTA# INTDJ
B12 RSVD GND A12 B7 INTB# INTC# A7
0 +/-5% B13 A13 CK_PE_100M_P_16PORT INTAJ B8 A8
GND REFCLK+ CK_PE_100M_P_16PORT 10 INTD# +5V4
EXP_TXP15C56 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B14 A14 CK_PE_100M_N_16PORT B9 A9 3D3V_SB
12 EXP_TXP15 CK_PE_100M_N_16PORT 10
*
EXP_TXN15 C36 HSOP0 REFCLK- PRSNT1# RSV1
12 EXP_TXN15 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B15 A15 B10 A10
*
HSON0 GND RSV2 +5V5
B16 GND HSIP0 A16 EXP_RXP15 12 B11 PRSNT2# RSV3 A11
SDVO_CTRLCLK B17 A17 B12 A12
12 SDVO_CTRLCLK PRSNT2_B17# HSIN0 EXP_RXN15 12 GND2 GND3
B18 GND GND A18 B13 GND4 GND5 A13
B14 RSV4 SB3V A14
B15 GND6 RESET# A15 PCIRSTJ 20,27
EXP_TXP14C57 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B19 A19 10 CK_33M_PCI1 B16 A16
12 EXP_TXP14
*
EXP_TXN14 C37 HSOP1 RSVD CLK +5V6

12 EXP_TXN14 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B20 A20 B17 A17 GNT1J 20
*
HSON1 GND PREQ1J GND7 GNT#
B21 GND HSIP1 A21 EXP_RXP14 12 B18 REQ# GND8 A18
B22 GND HSIN1 A22 EXP_RXN14 12 B19 +5V7 PCI_PME# A19 PMEJ 20,27
EXP_TXP13C38 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B23 A23 AD31 B20 A20 AD30
12 EXP_TXP13
*
EXP_TXN13 C58 HSOP2 GND AD29 AD(31) AD(30)

*
HSON2 GND AD(29) +3.3V1 AD28
B25 GND HSIP2 A25 EXP_RXP13 12 B22 GND9 AD(28) A22
B26 A26 AD27 B23 A23 AD26
EXP_TXP12C59 GND HSIN2 EXP_RXN13 12 AD25 AD(27) AD(26)
12 EXP_TXP12 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B27 A27 B24 A24
*
EXP_TXN12 C39 HSOP3 GND AD(25) GND10 AD24

*
HSON3 GND CBEJ3 +3.3V2 AD(24) IDSEL1
B29 GND HSIP3 A29 EXP_RXP12 12 20,27 CBEJ3 B26 C/BE#(3) IDSEL A26
B30 A30 AD23 B27 A27
SDVO_CTRLDATA RSVD HSIN3 EXP_RXN12 12 AD(23) +3.3V3 AD22
12 SDVO_CTRLDATA B31 PRSNT2_B31# GND A31 B28 GND11 AD(22) A28
B32 A32 AD21 B29 A29 AD20
GND RSVD AD19 AD(21) AD(20)
B30 AD(19) GND12 A30
EXP_TXP11C33 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B33 A33 B31 A31 AD18
12 EXP_TXP11
*
EXP_TXN11C55 HSOP4 RSVD AD17 +3.3V4 AD(18) AD16

* B35
HSON4
GND
GND
HSIP4 A35 EXP_RXP11 12 B33
AD(17)
C/BE#(2)
AD(16)
+3.3V5 A33
B36 A36 20,27 CBEJ2 B34 A34 FRAMEJ
GND HSIN4 EXP_RXN11 12 GND13 FRAME# FRAMEJ 20,27
EXP_TXP10C42 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B37 A37 IRDYJ B35 A35
12 EXP_TXP10 20,27 IRDYJ
*
EXP_TXN10C63 HSOP5 GND IRDY# GND14 TRDYJ

12 EXP_TXN10 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B38 A38 B36 A36 TRDYJ 20,27
*
HSON5 GND DEVSELJ +3.3V6 TRDY#
B39 GND HSIP5 A39 EXP_RXP10 12 20,27 DEVSELJ B37 DEVSEL# GND15 A37
B40 A40 B38 A38 STOPJ
GND HSIN5 EXP_RXN10 12 GND16 STOP# STOPJ 20,27
EXP_TXP9 C54 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B41 A41 LOCKJ B39 A39
12 EXP_TXP9 20 LOCKJ
*
EXP_TXN9 C53 HSOP6 GND PERRJ LOCK# +3.3V7 SMB_CLK_RESUME

C
12 EXP_TXN9 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B42 A42 B40 A40 C
*
HSON6 GND 20,27 PERRJ PERR# SDONE SMB_DATA_RESUME

B43 GND HSIP6 A43 EXP_RXP9 12 B41 +3.3V8 SBO# A41
B44 A44 SERRJ B42 A42
GND HSIN6 EXP_RXN9 12 20,27 SERRJ SERR# GND17
EXP_TXP8 C43 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B45 A45 B43 A43 PAR
12 EXP_TXP8 PAR 20,27
*
EXP_TXN8 C64 HSOP7 GND CBEJ1 +3.3V9 PAR AD15

*
HSON7 GND 20,27 CBEJ1 AD14 C/BE#(1) AD(15)

B47 GND HSIP7 A47 EXP_RXP8 12 B45 AD(14) +3.3V10 A45
B48 A48 B46 A46 AD13
12 GMCH_EXP_EN_HDR PRSNT2_B48# HSIN7 EXP_RXN8 12 GND18 AD(13)
B49 A49 AD12 B47 A47 AD11
GND GND AD10 AD(12) AD(11)
B48 AD(10) GND19 A48
B49 A49 AD9
EXP_TXP7 C60 GND20 AD(9)
12 EXP_TXP7 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B50 A50 A50 B50
*
EXP_TXN7 C40 HSOP8 RSVD A50 B50

12 EXP_TXN7 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B51 A51 A51 B51
*
HSON8 GND AD8 A51 B51 CBEJ0

B52 GND HSIP8 A52 EXP_RXP7 12 B52 AD(8) C/BE#(0) A52 CBEJ0 20,27
B53 A53 AD7 B53 A53
EXP_TXP6 C45 GND HSIN8 EXP_RXN7 12 AD(7) +3.3V11 AD6
*
EXP_TXN6 C46 HSOP9 GND AD5 +3.3V12 AD(6) AD4

*
HSON9 GND AD3 AD(5) AD(4)

B56 GND HSIP9 A56 EXP_RXP6 12 B56 AD(3) GND21 A56
B57 A57 B57 A57 AD2
EXP_TXP5 C61 GND HSIN9 EXP_RXN6 12 AD1 GND22 AD(2) AD0
*
EXP_TXN5 C41 HSOP10 GND AD(1) AD(0)

*
HSON10 GND ACK64J +5V8 +5V9 REQ64_1J

B60 GND HSIP10 A60 EXP_RXP5 12 B60 ACK64# REQ64# A60
B61 GND HSIN10 A61 EXP_RXN5 12 B61 +5V10 +5V11 A61
EXP_TXP4 C62 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B62 A62 B62 A62
X1
X2
12 EXP_TXP4
*
EXP_TXN4 C34 HSOP11 GND +5V12 +5V13

12 EXP_TXN4 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B63 A63
*
HSON11 GND
B64 A64
X1
X2
GND HSIP11 EXP_RXP4 12
B65 GND HSIN11 A65 EXP_RXN4 12
EXP_TXP3 C49 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B66 A66
12 EXP_TXP3
*
EXP_TXN3 C50 HSOP12 GND

12 EXP_TXN3 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B67 A67
*
HSON12 GND AD[31..0]

B68 GND HSIP12 A68 EXP_RXP3 12 AD[31..0] 20,27
EXP_TXP2 C47 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B70 A70 IDSEL1 R54 330 AD17
12 EXP_TXP2
*

12 EXP_TXN2 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B71 A71 R0603 +/-5%
*
HSON13 GND
B72 GND HSIP13 A72 EXP_RXP2 12
EXP_TXP1 C51 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B74 A74
12 EXP_TXP1
*

12 EXP_TXN1 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B75 A75
*
HSON14 GND
B
B77 GND HSIN14 A77 EXP_RXN1 12 B
EXP_TXP0 C65 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B78 A78 -12V_SYS 5V_SYS
12 EXP_TXP0
*

12 EXP_TXN0 1 2 0.1uF C0603 16V, Y5V, +80%/-20% B79 A79 12V_SYS 3D3V_SYS
*
HSON15 GND
B81 PRSNT2_B81# HSIN15 A81 EXP_RXN0 12
B82 RSVD GND A82
PCIE-X16_SLOT
2
C0603 C79 C68 EC3 EC7 C76
1
* 16V, Y5V, +80%/-20%
0.1uF * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
* 100uF
16V, +/-20%
* 100uF
16V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
1
C94 C0603 C0603 CE20D50H110 CE20D50H110 C0603
2
12V_SYS 3D3V_SYS 3D3V_SB 12V_SYS 3D3V_SYS Dummy Dummy
J1
1 C15 C75 C73 EC5 EC6
1
2
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
* 470uF
16V, +/-20%
* 100uF
16V, +/-20%
PCIE_RM C0603 C0603 C0603 CE35D80H200 CE20D50H110
2
PCIE_RM Dummy Dummy

Dummy
3D3V_SYS 5V_SYS
RN3 R104 2.7K R0603 +/-5% REQ64_1J

*1 2
INTCJ
INTAJ
INTCJ
INTAJ
20
20
3 4 INTDJ R105 2.7K R0603 +/-5% ACK64J
5 6 INTDJ 20
INTBJ
7 8 INTBJ 20
5V_DUAL 8.2K
+/-5% 3D3V_SYS
8P4R0603
PMEJ RN9 RN4
*1 2
INTGJ
INTFJ
INTGJ 20 *1 2
DEVSELJ
TRDYJ
D
3 4 INTFJ 20,27 3 4
A WOL INTHJ IRDYJ A
5 6 INTHJ 20 5 6
Q3 1 4 INTEJ FRAMEJ
7 8 INTEJ 20 7 8
2
G 3 8.2K 8.2K
2N7002 +/-5% +/-5%
Dummy Header_1X3 (JWOL) 8P4R0603 8P4R0603
S
R30 Dummy R162 8.2K R0603 +/-5%

PREQ2J 20
10K R159 8.2K R0603 +/-5% RN5
PREQ0J 20,27
+/-5%
R0603
R53 8.2K R0603 +/-5%
PREQ1J 20 *1 2
SERRJ
PERRJ
Dummy
R160 8.2K R0603 +/-5%
3
5
4
6
LOCKJ
STOPJ
FOXCONN PCEG
PREQ5J 20 7 8
R161 8.2K R0603 +/-5% Title
PREQ4J 20
R152 8.2K R0603 +/-5% 8.2K
PREQ3J 20
+/-5% PCI & PCI-E x16 Slot
8P4R0603 Size Document Number Rev
C 945P01 A

5 4 3 2 1
5 4 3 2 1
ICH_RTCX2
ICH_RTCX1 R201 10M R0603 +/-5%

X3_1
X3 XTAL-32.768kHz
2 1
Crystal Retainer
C195 C199
3
1
1
18pF
50V, NPO, +/-5% * * 18pF
50V, NPO, +/-5% 3D3V_SYS
C0603 C0603
2
2
R207
U12F ICH7 10K
+/-5% U12C ICH7
D 19,24,25 L_AD[3..0] R0603 Dummy D
DMI_TXN0 V26 DMI0RXN USBP0N F1 USBP0N ICH7_GPIO23 AA5 LDRQ1*/GPIO23 GPIO0/BM_BUSY* AB18 ICH7_GPIO0
12 DMI_TXN0
DMI_TXP0 V25 DMI0RXP USBP0P F2 USBP0P L_AD0 AA6 LAD0 GPIO6 AC21 ICH7_GPIO6
12 DMI_TXP0
DMI_RXN0 U28 DMI0TXN USBP1N G4 USBP4N L_AD1 AB5 LAD1 GPIO7 AC18 FWH_WPJ
12 DMI_RXN0 FWH_WPJ 19
LPC
DMI_RXP0 U27 DMI0TXP USBP1P G3 USBP4P L_AD2 AC4 LAD2 GPIO8 E21 L_PMEJ
12 DMI_RXP0 DMI_TXN1 USBP1N L_AD3 ICH7_GPIO9 L_PMEJ 25
12 DMI_TXN1 Y26 DMI1RXN USBP2N H1 Y6 LAD3 GPIO9 E20 S1_LED 24
DMI_TXP1 Y25 DMI1RXP USBP2P H2 USBP1P AC3 LDRQ0* GPIO10 A20 ICH7_GPIO10
12 DMI_TXP1 25 L_DRQ0J S3_LED 24
DMI_RXN1 W28 DMI1TXN USBP3N J4 USBP3N AB3 LFRAME* GPIO12 F19 TPM_RSV0
12 DMI_RXN1 USBP3N 28 19,24,25 L_FRAMEJ
DMI
DMI_RXP1 W27 DMI1TXP USBP3P J3 USBP3P GPIO13 E19 TPM_RSV1
12 DMI_RXP1 USBP3P 28
DMI_TXN2 AB26 DMI2RXN USBP4N K1 USBP2N R196 33R0603 +/-5% U1 ACZ_BCLK GPIO14 R4 TPM_RSV2
12 DMI_TXN2 USBP2N 28 22 ICH_BCLK
DMI_TXP2 AB25 DMI2RXP USBP4P K2 USBP2P R5 ACZ_RST* GPIO15 E22 EXTSMI_L
12 DMI_TXP2 USBP2P 28 22,23 ICH_RSTJ
AUDIO
DMI_RXN2 AA28 DMI2TXN USBP5N L4 USBP5N T2 ACZ_SDI_0 GPIO16/DPRSLPVR AC22 TP_ICH7_GPIO16 1 TP16
12 DMI_RXN2 DMI_RXP2 USBP5P TP_ICH7_GPIO18 TP15
12 DMI_RXP2 AA27 DMI2TXP USBP5P L5 T3 ACZ_SDI_1 GPIO18/STPPCI* AC20 1
DMI_TXN3 AD25 DMI3RXN USBP6N M1 USBP6N T1 ACZ_SDI_2 GPIO20/STPCPU* AF21 GPIO20 1 TP26
12 DMI_TXN3 22 ICH_SDIN2
DMI_TXP3 AD24 DMI3RXP USBP6P M2 USBP6P R190 33R0603 +/-5% T4 ACZ_SDOUT GPIO24 R3 GPIO24 1 TP7
12 DMI_TXP3 22 ICH_SDOUT
DMI_RXN3 AC28 DMI3TXN USBP7N N4 USBP7N R421 33R0603 +/-5% R6 ACZ_SYNC GPIO25 D20 GPIO_LAN_DISABLEJ
12 DMI_RXN3 DMI_RXP3 USBP7P 22 ICH_SYNC GPIO_LAN_DISABLEJ 21
12 DMI_RXP3 AC27 DMI3TXP USBP7P N3 10 CK_14M_ICH AC1 CLK14 EL_RSVD/GPIO26 A21
USB
EL_STATE0/GPIO27 B21
EPROM
W1 EE_CS EL_STATE1/GPIO28 E23
HSI_N0 F26 PERN_1 OC0* D3 USB_OCJ_BACK W3 EE_DIN GPIO32/CLKRUN* AG18
21 HSI_N0 HSI_P0 USB_OCJ_BACK 28 TURBOJ 10
21 HSI_P0 F25 PERP_1 OC1* C4 Y2 EE_DOUT GPIO33/AZ_DOCK_EN* AC19
U12_2 HSO_N0 E28 PETN_1 OC2* D5 Y1 EE_SHCLK GPIO34/AZ_DOCK_RST* U2 GPIO34 1 TP10
HSO_P0 E27 PETP_1 OC3* D4 GPIO35 AD21 TP_ICH7_GPIO35 1 TP17
H26 PERN_2 OC4* E5 USB_OCJ_FRONT V3 LAN_CLK GPIO38 AD20 ICH7_GPIO38
U12_3 H25 PERP_2 OC5*/GPIO29 C3 U3 LAN_RSTSYNC GPIO39 AE20 ICH7_GPIO39 FWH_TBLJ 19
G28 PETN_2 OC6*/GPIO30 A2 R151 10K ICH_LAN_RSTJ C19 LAN_RST* CPUPWRGD_GPIO49 AG24
Clip_2P R0603 +/-5% CPU_PWRG 8
G27 PETP_2 OC7*/GPIO31 B3 U5 LAN_RXD0
ICH_THRM_UP
LAN
K26 PERN_3 V4 LAN_RXD1 THRM* AF20
MISC
VRM_PWRGD ICH_THRM_UP 25
K25 PERP_3 T5 LAN_RXD2 VRMPWRGD AD22 VRM_PWRGD 29
J28 PETN_3 USBRBIAS D1 USBRBIAS_ICH R173 22.6 R0603 +/-1% U7 LAN_TXD0 MCH_SYNC* AH20
PCI-EXPRESS
ICH_SYNCJ 12
J27 PETP_3 USBRBIAS* D2 V6 LAN_TXD1 PWRBTN* C23 PWRBTNJ 24
M26 PERN_4 V7 LAN_TXD2 RI* A28 ICH_RIJ
LPCPD_L ICH_RIJ 24
M25 PERP_4 SUS_STAT* A27 LPCPD_L 25
U12_1 Heatsink_ICH PETN_4 ICH_RTCX1 RTCX1 SUSCLK VCCRTC
RTC
L28 AB1 C20 SUSCLK 25
L27 PETP_4 CLK48 B2 CK_48M_ICH ICH_RTCX2 AB2 RTCX2 SYS_RST* A22
CK_48M_ICH 10 RTCRSTJ PLTRSTJ ICH_SYS_RSTJ 8,10,24
P26 PERN_5 19 RTCRSTJ AA3 RTCRST* PLTRST* C26 PLTRSTJ 12,19,24,25
P25 PERP_5 WAKE* F20 WAKEJ 17,21
C N28 PETN_5 3D3V_SB RECOVERY B23 SMBALERT*/GPIO11 INTRUDER* Y5 INTRUDERJ R214 C
Clip_2P N27 PETP_5 C22 SMBCLK PWROK AA4 330K
17,21,25 SMB_CLK_RESUME PWRGD_3V 12,25,27
T25 PERN_6 RN11 B22 SMBDATA RSMRST* Y4 RSMRSTJ +/-5%
17,21,25 SMB_DATA_RESUME RSMRSTJ 25
PERP_6 *1 LINKALERT* INTVRMEN INTVRMEN R0603
SMB
T24 2 A26 W4
R28 PETN_6 B25 SMLINK0 SPKR A19 SPKR
3 4 SPKR 22,24
1D5V_PE_ICH R27 PETP_6 A25 SMLINK1
5 6
7 8 SLP_S3* B24 SLP_S3J 11,24,25
R187 24.9 DMI_COMP_ICH C25 DMI_ZCOMP P5 SPI_MOSI SLP_S4* D23
R0603 +/-1% 10K SLP_S4J 11,25
DMI_IRCOMP SPI_MISO SLP_S5*
SPI
D25 P2 F22 SLP_S5J 24
+/-5% P6 SPI_CS*
CK_PE_100M_N_ICH AE28 DMI_CLKN 8P4R0603 R2 SPI_CLK TP0/BATLOW* C21 ICH_BATLOW_PU
10 CK_PE_100M_N_ICH
CK_PE_100M_P_ICH AE27 DMI_CLKP 2 of 6 P1 SPI_ARB TP1/DPRSTP* AF24 TP_ICH7_AF24 1 TP18
10 CK_PE_100M_P_ICH
TP2/DPSLP* AH25 TP_ICH7_AH25 1 TP19
ICH7_652 TP3 TP_ICH7_F21 TP4
4 of 6 F21 1
ICH7_652
ICH_BCLK SMB_CLK_RESUME SMB_DATA_RESUME

HSO_N0_LAN C163 1 2 0.1uF C0603 16V, Y5V, +80%/-20% HSO_N0 3D3V_SYS 3D3V_SB
21 HSO_N0_LAN
* *
VCCRTC C181 C16 C21 ICH7_GPIO38 R226 10K R0603 +/-5% RN7
1
21 HSO_P0_LAN HSO_P0_LAN C165 1 2 0.1uF C0603 16V, Y5V, +80%/-20% HSO_P0
R453
10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * *1 2
EXTSMI_L
ICH7_GPIO9
1M C0603 C0603 C0603 ICH7_GPIO39 R229 10K R0603 +/-5% 3 4 L_PMEJ
2
R0603 Dummy Dummy 5 6 WAKEJ
+/-5% ICH_THRM_UP R217 10K R0603 +/-5% 7 8
10K
D15 J4 3D3V_SB +/-5%
EXTSMI_L ANODE CATHODE INTRUDERJ 1 8P4R0603
2
1N4148W R163 10K R0603 +/-5% RECOVERY
Header_1X2 TPM_RSV1 R150 10K R0603 +/-5%
R153 10K R0603 +/-5% ICH_RIJ
TPM_RSV2 R189 10K R0603 +/-5%
RN10
B
USB_OCJ_BACK USB_OCJ_FRONT
*1 2
ICH_SYS_RSTJ
ICH_BATLOW_PU B
3D3V_SYS 3 4 ICH7_GPIO10
5 6 TPM_RSV0
C144 C143 RN31 7 8
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
JRECOVERY1
1 RECOVERY
*1 2
ICH7_GPIO21
ICH7_GPIO6 ICH7_GPIO21 19
10K
+/-5%
C0603 C0603 3 4 ICH7_GPIO0 5V_SYS 8P4R0603
2
2
5 6 ICH7_GPIO19
Header_1X2 7 8 ICH7_GPIO19 19
10K C272 1 2 0.1uF
* *
+/-5% C0603 16V, Y5V, +80%/-20%
8P4R0603
C289 1 2 0.1uF
C0603 16V, Y5V, +80%/-20%
USBP0N-JUSB R318 0 Dummy USBP0N

USBP4N C164 1 2 3.3pF Dummy USBP6N C171 1 2 3.3pF Dummy R0603 +/-5%
****
****
C0402 50V, NPO, +/-0.25pF C0402 50V, NPO, +/-0.25pF

USBP4P C161 1 2 3.3pF Dummy USBP6P C170 1 2 3.3pF Dummy
C0402 50V, NPO, +/-0.25pF C0402 50V, NPO, +/-0.25pF USBP0N-JUSB C286 1 2 3.3pF Dummy USBP0P-JUSB R323 0 Dummy USBP0P
****
USBP5N C168 1 2 3.3pF Dummy USBP7N C176 1 2 3.3pF Dummy C0402 50V, NPO, +/-0.25pF R0603 +/-5%
C0402 50V, NPO, +/-0.25pF C0402 50V, NPO, +/-0.25pF USBP0P-JUSB C288 1 2 3.3pF Dummy
USBP5P C166 1 2 3.3pF Dummy USBP7P C180 1 2 3.3pF Dummy C0402 50V, NPO, +/-0.25pF
C0402 50V, NPO, +/-0.25pF C0402 50V, NPO, +/-0.25pF USBP1N-JUSB C278 1 2 3.3pF Dummy USBP1N-JUSB R305 0 Dummy USBP1N
5V_DUAL F3
* SVCC2 C0402 50V, NPO, +/-0.25pF R0603 +/-5%
USBP1P-JUSB C282 1 2 3.3pF Dummy
F1813_2.6A C0402 50V, NPO, +/-0.25pF
USBP1P-JUSB R315 0 Dummy USBP1P
F2
* R0603 +/-5%
F1813_2.6A
SVCC1 SVCC1
R158 +/-5% USB_OCJ_FRONT SVCC2 C269
1
A C162 10K R0603 C188

* 0.1uF
28 USBP0N-1394
R317 0 A
1
* EC25
1000uF * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
C0603
R0603 +/-5%
2
6.3V, +/-20% C0603 R157 C0603

2
CE35D80H200 15K R322 0

+/-5% 28 USBP0P-1394 R0603 +/-5%
R0603 JUSB_HEADER3
JUSB_HEADER2 JUSB_HEADER1 1 2
1 2 1 2 USBP1N-JUSB 3 4 USBP0N-JUSB R304 0
USBP5N USBP4N USBP7N USBP6N USBP1P-JUSB USBP0P-JUSB 28 USBP1N-1394 R0603 +/-5%
3 4 3 4 5 6
USBP5P 5 6 USBP4P USBP7P 5 6 USBP6P 7 8 FOXCONN PCEG
7 8 7 8 X 10
X 10 X 10 R314 0 Title
Header_2X5_9 28 USBP1P-1394 R0603 +/-5%
Header_2X5_9 Header_2X5_9 Dummy ICH7 -1_DIM,PCI-E,USB,MISC
C 945P01 A
Date: Wednesday, August 17, 2005 Sheet 18 of 30

5 4 3 2 1
5 4 3 2 1
3D3V_SYS
ICH7
IDE
U12B
PIDE_D0 AB15 DD0 SATA0RXN AF3 SATA_RXN0

PIDE_D1 AE14 DD1 SATA0RXP AE3 SATA_RXP0
PIDE_D2 AG13 DD2 SATA0TXN AG2 SATA_TXN0
PIDE_D3 AF13 DD3 SATA0TXP
RSVD/SATA1RXN
AH2 SATA_TXP0 SATA R309 R308
PIDE_D4 AD14 DD4 AE5 SATA_RXN1 8.2K 4.7K R307 33 P_IDERSTJ
PIDE_D5 RSVD/SATA1RXP SATA_RXP1 SATA1 +/-5% +/-5% 25 IDE_PCIRSTJ R0603 +/-5%
AC13 DD5 AD5 1
PIDE_D6 AD12 DD6 RSVD/SATA1TXN AG4 SATA_TXN1 SATA_TXP0 C239 1 2 10nF C0603 25V, X7R, +/-10% SATA_TXP0_C 2 SATA R0603 R0603
** **
PIDE_D7 AC12 DD7 RSVD/SATA1TXP AH4 SATA_TXP1 SATA_TXN0 C240 1 2 10nF C0603 25V, X7R, +/-10% SATA_TXN0_C 3 8 placed near IDE connector
PIDE_D8 AE12 DD8 SATA2RXN AF7 4
SATA
PIDE_D9 AF12 DD9 SATA2RXP AE7 SATA_RXN0 C241 1 2 10nF C0603 25V, X7R, +/-10% SATA_RXN0_C 5 9
PIDE_D10 AB13 DD10 SATA2TXN AG6 SATA_RXP0 C245 1 2 10nF C0603 25V, X7R, +/-10% SATA_RXP0_C 6 IDE1
PIDE_D11 DD11 SATA2TXP P_IDERSTJ
IDE
D
AC14 AH6 7 1 2 D
PIDE_D12 AF14 DD12 RSVD/SATA3RXN AD9 PIDE_D7 3 4 PIDE_D8
PIDE_D13 AH13 DD13 RSVD/SATA3RXP AE9 1 SATA2 PIDE_D6 5 6 PIDE_D9
PIDE_D14 AH14 DD14 RSVD/SATA3TXN AG8 SATA_TXP1 C235 1 2 10nF C0603 25V, X7R, +/-10% SATA_TXP1_C 2 SATA PIDE_D5 7 8 PIDE_D10
** **
PIDE_D15 AC15 DD15 RSVD/SATA3TXP AH8 SATA_TXN1 C236 1 2 10nF C0603 25V, X7R, +/-10% SATA_TXN1_C 3 8 PIDE_D4 9 10 PIDE_D11
SATACLKN AF1 CK_SATA_100M_N_ICH 4 PIDE_D3 11 12 PIDE_D12
CK_SATA_100M_N_ICH 10
PIDE_DAKJ AF16 DDACK* SATACLKP AE1 CK_SATA_100M_P_ICH SATA_RXN1 C250 1 2 10nF C0603 25V, X7R, +/-10% SATA_RXN1_C 5 9 PIDE_D2 13 14 PIDE_D13
CK_SATA_100M_P_ICH 10
PIDE_DREQ AE15 DDREQ SATA_RXP1 C252 1 2 10nF C0603 25V, X7R, +/-10% SATA_RXP1_C 6 PIDE_D1 15 16 PIDE_D14
PIDE_IORJ AF15 DIOR* 7 PIDE_D0 17 18 PIDE_D15
PIDE_IOWJ AH15 DIOW* SATARBIASN AH10 SATARBIAS_ICH R221 24.9 R0603 +/-1% 19 X
PIDE_RDY IORDY PIDE_DREQ
AG16 SATARBIASP AG10 SATA_LED
SATA 1 & SATA2-->Master PIDE_IOWJ
21 22
Cable detection
PIDE_A0 DA0 SATALED* AF18 SATA_LED 24
PIDE_IORJ
23 24
AH17 25 26 high: 40-conductor cable(ATA 33)
PIDE_A1 AE17 DA1 GPIO21/SATA0GP AF19 ICH7_GPIO21 PIDE_RDY 27 28 low: 80-conductor cable(ATA 66/100)
ICH7_GPIO21 18
PIDE_A2 AF17 DA2 GPIO19/SATA1GP AH18 ICH7_GPIO19 PIDE_DAKJ 29 30
ICH7_GPIO19 18
GPIO36/SATA2GP AH19 ICH7_GPIO36 SATARBIAS connection IRQ14 31 32
PIDE_CS1J AE16 DCS1* GPIO37/SATA3GP AE19 ICH7_GPIO37 5 mils width, length no longer than 500 mils PIDE_A1 33 34 CBLID_P
PIDE_CS3J AD16 DCS3* PIDE_A0 35 36 PIDE_A2
A20GATE Trace tied together close to pins. PIDE_CS1J PIDE_CS3J
AE22 A20GATE 25 37 38
A20M* AH28 A20MJ 8
HDD_LED 39 40
IRQ14 AH16 IDEIRQ CPUSLP* AG27
IGNNE* AG22 IGNNEJ 8 Header_2X20_20 (IDE) C280 R310
1
INITJ_3D3V
INIT3_3V* AG21
* 47nF 10K
HOST
INIT* AF22 16V, X7R, +/-10% +/-5%

INITJ 8
INTR AF25 HDD1 C0603 R0603
INTR 8
2
FERR* AG26 Dummy
FERRJ 8
NMI AH24 NMI 8
RCIN* AG23 3D3V_SYS
KBRSTJ 25
SERIRQ AH21 SERIRQ 24,25
SMI* AF23 SMIJ 8
ICH7_652 STPCLK* AH22 STPCLKJ 8
3 of 6 THERMTRIP* AF26 THERMTRIPJ 8 IDE data lines should be matched to strobes(IORJ, RDY)within +/- 250 mils,
strobes should be matched to their complement within +/- 10 mils
R311 R234
10K 10K
R0603 R0603
HDD_LED +/-5% +/-5%
C C
24 HDD_LED Dummy Dummy
SATA_LED
24 SATA_LED
FSB_VTT
FWH 3D3V_SYS
3D3V_SYS
R216 62 R0603 +/-5% THERMTRIPJ 3D3V_SYS place near pin25, 27, 32
C493 C494 C495
1
ICH7_GPIO37 R223 10K C127 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20%
1
FERRJ
R220 62 R0603 +/-5% R0603 +/-5%
* 0.1uF C0603 C0603 C1206 Dummy
2
ICH7_GPIO36 R218 10K 16V, Y5V, +80%/-20%
25
32
27
R0603 +/-5% C0603 U13
2
Place at ICH7 end of route
VCCA
VCC_2
VCC_1
1 24 INITJ_3D3V
VPP INITJ
10 CK_33M_FWH 31 CLK RFU_1 22

RFU_2 21
29 IC RFU_3 20
RFU_4 19
FGPI4 30 18
FGPI4 RFU_5
3D3V_SYS 2
3D3V_SB 12,18,24,25 PLTRSTJ RSTJ
FWH4 23 L_FRAMEJ 18,24,25
R211 17 L_AD3
VCCRTC 10K FGPI3 FWH3 L_AD2
3 FGPI3 FWH2 15
R0603 FGPI2 4 14 L_AD1
B
+/-5% FGPI1 FGPI2 FWH1 L_AD0 B
D5 5 13
width 20 mils 3D3V_SYS 3D3V_SYS 3D3V_SYS CBLID_P FGPI1 FWH0
1 6 FGPI0
3 7 WPJ ID0 12
2 R212 330 R0603 +/-5% 8 11
18 FWH_WPJ TBLJ ID1 L_AD[3..0] 18,24,25
C148 C132 C471 10
ID2
1
1
BAT54C
R146
20K * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% 3D3V_SYS R209 4.7K R0603 +/-5% ID3 9
GND3
GND2
GND1
+/-5% C0603 C0603 C0603 Dummy
2
R0603
C137
1
R156
* 1uF RTCRST_L R208 330 R0603 +/-5% RN18
2
4
6
8
16
26
28
BATT1 1K 6.3V, X7R, +/-10% 18 FWH_TBLJ SST49LF004B 100
+/-5% C0603 8P4R0603
2
* 13
5
7
R0603
LITHIUM BATT C136 +/-5%
1
CR2032
* 1uF
6.3V, X7R, +/-10%
3D3V_SYS
+
Battery C0603
2
BAT1 JBLOCK1
Battery Holder JBLOCK1(1-2) H3M R210
For battery cell. Header_1X3 4.7K
-
+/-5% BIOS Boot Block Header
1
2
3
R0603
Dummy Lock JBLOCK1(1-2) Default
1
2
3
Jumper_2P-Blue Dummy
Dummy Unlock JBLOCK1(2-3)
Clear CMOS U13_1
JCMOS1 JCMOS1(1-2)
RTCRST_L 1
GPI[0:4]:
RTCRSTJ 1
2 Unused GPI pins must not be floated.
18 RTCRSTJ
3
2 PLCC
3
32pin
Header_1X3 Jumper_2P-Blue Socket 3D3V_SYS 3D3V_SYS 3D3V_SB 3D3V_SB
A A
R236 R219 R228 R231

Clear CMOS 10K 10K 10K 10K
+/-5% +/-5% +/-5% +/-5%
R0603 R0603 R0603 R0603
Normal JCMOS1(1-2) Default J3 J2
FGPI4 FGPI1 1 FGPI2 1 FGPI3
2 2
Clear JCMOS1(2-3) must change part reference as R235 R224
same as FWH in BOM
10K
+/-5%
10K
+/-5%
Header_1X2 Header_1X2 FOXCONN PCEG
R0603 R0603 Title
Dummy Dummy
ICH7 -2_IDE,SATA,CPU,FWH
For Customer Acer requested C 945P01 A
Date: Friday, August 05, 2005 Sheet 19 of 30

5 4 3 2 1
5 4 3 2 1
VccSATAPLLUpdate
This document is being disclosed under CNDA
Rev 0.41/20/05 ICH7
U12E
U12D ICH7
U12A ICH7 1D5V_CORE REF5V E4 VSS VSS A4
AD[31..0] Change L50 from Bead to AG11 VSS VSS A23
AD[31..0] 17,27
A1 VCC1_5_A Inductor Refer to Intel C27 VSS VSS B1
17,27 PAR PAR E10 PAR AD0 E18 AD0 AB10 VCC1_5_A V5REF AD17 workshop 0405-K.w R14 VSS VSS B8
17,27 DEVSELJ DEVSELJ A12 DEVSEL* AD1 C18 AD1 AB17 VCC1_5_A V5REF G10 R15 VSS VSS B11
10 CK_33M_ICH A9 PCICLK AD2 A16 AD2 AB7 VCC1_5_A REF5V_SUS R16 VSS VSS B14
17,27 PCIRSTJ
PCIRSTJ B18 PCIRST* AD3 F18 AD3 AB8 VCC1_5_A V5REF_SUS F6 VCCRTC R17 VSS VSS B17
17,27 IRDYJ IRDYJ A7 IRDY* AD4 E16 AD4 AB9 VCC1_5_A R18 VSS VSS B20
PMEJ B19 PME* AD5 A18 AD5 AC10 VCC1_5_A VCCRTC W5 1D5V_CORE 1D5V_CORE T6 VSS VSS B26
17,27
17,27
PMEJ
SERRJ SERRJ
STOPJ
B10
F15
SERR*
STOP*
PCI AD6
AD7
E17
A17
AD6
AD7
AC17
AC6
VCC1_5_A
VCC1_5_A VCCUSBPLL C1
T12
T13
VSS
VSS
VSS
VSS
B28
C2
17,27 STOPJ L18
17 LOCKJ LOCKJ E11 PLOCK* AD8 A15 AD8 AC7 VCC1_5_A T14 VSS VSS C6
17,27 TRDYJ TRDYJ F14 TRDY* AD9 C14 AD9 AC8 VCC1_5_A VCCSATAPLL AD2 VCC_SATAPLL 1 2 T15 VSS VSS D10
17,27 PERRJ PERRJ C9 PERR* AD10 E14 AD10 AD10 VCC1_5_A L0805 10uH T16 VSS VSS D13
17,27 FRAMEJ FRAMEJ F16 FRAME* AD11 D14 AD11 AD6 VCC1_5_A VCCDMIPLL AG28 VCCDMIPLL T17 VSS VSS D18
AD12 B12 AD12 AE10 VCC1_5_A 1D05V_ICH R222 0 R0603 +/-5% U4 VSS VSS D21
D
27 GNT0J E7 GNT0* AD13 C13 AD13 AE6 VCC1_5_A VCC1_05 L11 Dummy C229 U12 VSS VSS D24 D
1
AD14 AD14
17 GNT1J D16 GNT1* G15 AF10 VCC1_5_A VCC1_05 L12 C212
*
2.2uF U13 VSS VSS E1
1
AD15 AD15
D17
F13
GNT2*
GNT3* AD16
G13
E12 AD16
AF5
AF6
VCC1_5_A
VCC1_5_A
VCC1_05
VCC1_05
L14
L16
* 10uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C0603
U14
U15
VSS
VSS
VSS
VSS
E2
E8
2
A14 GNT4*/GPIO48 AD17 C11 AD17 AF9 VCC1_5_A VCC1_05 L17 C0805 U16 VSS VSS E15
2
D8 GNT5*/GPIO17 AD18 D11 AD18 AG5 VCC1_5_A VCC1_05 L18 U17 VSS VSS F3
AD19 A11 AD19 AG9 VCC1_5_A VCC1_05 M11 Place LC filter Within 400Mil U24 VSS VSS F4
17,27 PREQ0J D7 REQ0* AD20 A10 AD20 AH5 VCC1_5_A VCC1_05 M18 from ICH7 U25 VSS VSS F5
17 PREQ1J C16 REQ1* AD21 F11 AD21 AH9 VCC1_5_A VCC1_05 P11 U26 VSS VSS F12
17 PREQ2J C17 REQ2* AD22 F10 AD22 F17 VCC1_5_A VCC1_05 P18 V2 VSS VSS F27
17 PREQ3J E13 REQ3* AD23 E9 AD23 G17 VCC1_5_A VCC1_05 T11 V13 VSS VSS F28
17 PREQ4J A13 REQ4*/GPIO22 AD24 D9 AD24 H6 VCC1_5_A VCC1_05 T18 V15 VSS VSS G1
17 PREQ5J C8 GPIO1/REQ5* AD25 B9 AD25 H7 VCC1_5_A VCC1_05 U11 V24 VSS VSS G5
AD26 A8 AD26 J6 VCC1_5_A VCC1_05 U18 C211 V27 VSS VSS G2
1
PIRQA* AD27 AD27
17
17
INTAJ
INTBJ
A3
B4 PIRQB* AD28
A6
C7 AD28
J7
T7
VCC1_5_A
VCC1_5_A
VCC1_05
VCC1_05
V11
V12
* 0.1uF
16V, Y5V, +80%/-20%
V28
W6
VSS
VSS
VSS
VSS
G6
G9
17 INTCJ C5 PIRQC* AD29 B6 AD29 VCC1_05 V14 C0603 W24 VSS VSS G14
2
17 INTDJ B5 PIRQD* AD30 E6 AD30 1D5V_PE_ICH D26 VCC1_5_B VCC1_05 V16 Place near AD2 W25 VSS VSS G18
17 INTEJ G8 GPIO2/PIRQE* AD31 D6 AD31 D27 VCC1_5_B VCC1_05 V17 W26 VSS VSS G21
17,27 INTFJ F7 GPIO3/PIRQF* D28 VCC1_5_B VCC1_05 V18 Y3 VSS VSS G24
17 INTGJ F8 GPIO4/PIRQG* C/BE0* B15 CBEJ0 E24 VCC1_5_B Y24 VSS VSS G25
CBEJ1 CBEJ0 17,27 FSB_VTT
17 INTHJ G7 GPIO5/PIRQH* C/BE1* C12 CBEJ1 17,27 E25 VCC1_5_B Y27 VSS VSS G26
C/BE2* D12 CBEJ2 E26 VCC1_5_B V_CPU_IO AE23 Y28 VSS VSS H3
1 of 6
POWER
CBEJ3 CBEJ2 17,27
C/BE3* C15 CBEJ3 17,27 F23 VCC1_5_B V_CPU_IO AE26 AA1 VSS VSS H4
F24 VCC1_5_B V_CPU_IO AH26 3D3V_SYS AA24 VSS VSS H5
G22 VCC1_5_B AA25 VSS VSS H24
ICH7_652 G23 VCC1_5_B VCC3_3 A5 AA26 VSS VSS H27
H22 VCC1_5_B VCC3_3 AA7 AB4 VSS VSS H28
H23 VCC1_5_B VCC3_3 AB12 AB6 VSS VSS J1
J22 VCC1_5_B VCC3_3 AB20 AB11 VSS VSS J2
J23 VCC1_5_B VCC3_3 AC16 AB14 VSS VSS J5
K22 VCC1_5_B VCC3_3 AD13 AB16 VSS VSS J24
K23 VCC1_5_B VCC3_3 AD18 AB19 VSS VSS J25
L22 VCC1_5_B VCC3_3 AG12 AB21 VSS VSS J26
extra one 47uF(backside) in DG0.7 L23 VCC1_5_B VCC3_3 AG15 AB24 VSS VSS K24
M22 VCC1_5_B VCC3_3 AG19 AB27 VSS VSS K27
M23 VCC1_5_B VCC3_3 AH11 AB28 VSS VSS K28
N22 VCC1_5_B VCC3_3 B13 AC2 VSS VSS L13
N23 VCC1_5_B VCC3_3 B16 AC5 VSS VSS L15
1D05V_ICH P22 VCC1_5_B VCC3_3 B27 AC9 VSS VSS L24
1D5V_CORE P23 VCC1_5_B VCC3_3 B7 AC11 VSS VSS L25
R22 VCC1_5_B VCC3_3 C10 AD1 VSS VSS L26
R23 VCC1_5_B VCC3_3 D15 AD3 VSS VSS M3
R24 VCC1_5_B VCC3_3 F9 AD4 VSS VSS M4
C120 C121 C226 VCC1_5_B VCC3_3 VSS VSS
VCCDMIPLL LRC Filter R25 G11 AD7 M5
1
* 0.1uF
16V, Y5V, +80%/-20% * 10nF
25V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
1D5V_CORE R26
T22
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
G12
G16
AD8
AD11
VSS
VSS
VSS
VSS
M12
M13
C0603 C0603 C0603 T23 VCC1_5_B VCC3_3 U6 3D3V_SB AD15 VSS VSS M14
R215
2
L17 T26 VCC1_5_B VCCSUS3_3 A24 AD19 VSS VSS M15

VCCDMIPLL T27 VCC1_5_B VCCSUS3_3 C24 AD23 VSS VSS M16
C C
T28 VCC1_5_B VCCSUS3_3 D19 AE2 VSS VSS M17
L1206 1uH C213 U22 VCC1_5_B VCCSUS3_3 D22 AE4 VSS VSS M24
1
*1 10uF U23 VCC1_5_B VCCSUS3_3 E3 AE8 VSS VSS M27
Rated at least 100mA R0603 10V, Y5V, +80%/-20% V22 VCC1_5_B VCCSUS3_3 G19 AE11 VSS VSS M28
+/-5% C1206 V23 VCC1_5_B VCCSUS3_3 K3 AE13 VSS VSS N1
2
ICH7 Core decoupling caps. W22 VCC1_5_B VCCSUS3_3 K4 AE18 VSS VSS N2
W23 VCC1_5_B VCCSUS3_3 K5 AE21 VSS VSS N5
Y22 VCC1_5_B VCCSUS3_3 K6 AE24 VSS VSS N6
Y23 VCC1_5_B VCCSUS3_3 L1 AE25 VSS VSS N11
AA22 VCC1_5_B VCCSUS3_3 L2 AF2 VSS VSS N12
Place LRC near pin AG28 AA23 VCC1_5_B VCCSUS3_3 L3 AF4 VSS VSS N13
AB22 VCC1_5_B VCCSUS3_3 L6 AF8 VSS VSS N14
AB23 VCC1_5_B VCCSUS3_3 L7 AF11 VSS VSS N15
AC23 VCC1_5_B VCCSUS3_3 M6 AF27 VSS VSS N16
1D5V_PE_ICH 3D3V_SYS AC24 VCC1_5_B VCCSUS3_3 M7 AF28 VSS VSS N17
AC25 VCC1_5_B VCCSUS3_3 N7 AG1 VSS VSS N18
AC26 VCC1_5_B VCCSUS3_3 P7 AG3 VSS VSS N24
AD26 VCC1_5_B VCCSUS3_3 R7 AG7 VSS VSS N25
C160 C167 C198 C149 AD27 VCC1_5_B VCCSUS3_3 V1 AG14 VSS VSS N26
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% 1D5V_CORE
VCC1_5_B LC Filter
AD28 VCC1_5_B VCCSUS3_3
VCCSUS3_3
V5
W2
AG17
AG20
VSS
VSS
VSS
VSS
P12
P13
C0603 C0603 C0603 C0603 VCCSUS3_3 W7 AG25 VSS VSS P14
2
AH1 VSS VSS P15

VCCSUS1_05 AA2 TP_ICH7_AA2 1 TP14 AH3 VSS VSS P3
1 2 L14 1D5V_PE_ICH VCCSUS1_05 C28 TP_ICH7_C28 1 TP1 VSS P4
VCCSUS1_05 G20 TP_ICH7_G20 1 TP5 VSS P16
Place near B27 L1206 0.47uH EC18 VCCSUS1_05 K7 TP_ICH7_K7 1 TP6 AH7 VSS VSS P17
Place near D28

* 220uF
6.3V, +/-20% 5 of 6 VCCSUS1_05 Y7 TP_ICH7_Y7 1 TP13 AH23
AH27
VSS
VSS
VSS
VSS
P24
P27
L13 CE20D50H110 VSS P28
ICH7_652 VSS VSS
PCI-E decoupling caps. * AH12
VSS
R1
R11
FB L0603 47 Ohm VSS R12
Dummy VSS R13
co-layout with inductor Place LC near pin D28 6 of 6

ICH7_652
Rated at least 1A,
VCCDMIPLL ESR max. 20 mohm
C206
1
* 10nF
25V, Y5V, +80%/-20% 5V_SB_SYS 3D3V_SB
C0603
2
ANODE
3D3V_SYS
Place near AG28 FSB_VTT FSB_VTT FSB_VTT FSB_VTT
B R174 1D5V_CORE 1D5V_CORE B
10 D7
+/-5% SD103AW
DMI decoupling caps. R0603 Dummy
Dummy C222 C224 C338
1 CATHODE
1
* 0.1uF
* 1uF
* 0.1uF C230 C221 C227 C228
1
REF5V_SUS 16V, Y5V, +80%/-20%
C0603
10V, Y5V, +80%/-20%
C0603
16V, Y5V, +80%/-20%
C0603 Dummy * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
10V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20%
2
2
C0603 C0603 C0805 C0603
2
C157
* 0.1uF
16V, Y5V, +80%/-20% Place near AH5 Place near AH9 Place near U6
1D5V_CORE 1D5V_CORE C0603
2
place cap. near pin F6

within 40 mils
C153 Place near AE23 and AE26 Place near AH26
Audio decoupling caps.
1
C150
* 10nF
1
3D3V_SYS
* 0.1uF
16V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
C0603 V5REF_SUS / 3D3V_SB Power Sequencing
2
C0603
CPU decoupling caps.
2
3D3V_SYS
Place near A1 Place near C1 C225

1
* 0.1uF
16V, Y5V, +80%/-20%
5V_SYS 3D3V_SYS C0603
2
3D3V_SB C223
1
ANODE
* 0.1uF
16V, Y5V, +80%/-20% VCCRTC VCCRTC
Place near AH11 C0603
2
R186
1K D6
+/-5% SD103AW Place near AG15
C154 C169 C367 R0603 Dummy C219 C218
1 CATHODE
1
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
Dummy
SATA decoupling caps. * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603 C0603 Dummy REF5V C0603 C0603
IDE decoupling caps.
2
2
C159
* 0.1uF
16V, Y5V, +80%/-20%
C0603
2
place cap. near pin AD17

Place near E3 3D3V_SYS 3D3V_SB
within 40 mils
Place near W5
USB decoupling caps. V5REF / 3D3V_SYS Power Sequencing

A RTC decoupling caps. A
C186
1
C146 C145 C147 C358

* 0.1uF
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
C0603
2
C0603 C0603 C0603 C0603 Dummy

2
2
2
1
Place near V1
U11
2
1
Place near A5, B7, B13, B16 LAN decoupling caps.

5 5 PCI decoupling caps.
BGA609H_118CHANGE
FOXCONN PCEG
4
3
ICH_Hook_Location Title
Dummy
ICH7 -3_PCI,Power/ Gnd,FWH
4
3

Custom 945P01 A
Date: Friday, August 05, 2005 Sheet 20 of 30

5 4 3 2 1
5 4 3 2 1
3D3V_SB
VPD_DATA
Support ASF 2.0
3D3V_SB
VPD_CLK
R372 0
17,18,25 SMB_CLK_RESUME +/-5% R389 R397 C409
U21
1
17,18,25 SMB_DATA_RESUME
R373
R0603
0 1 CS VCC 8
* C313
1uF
4.7K
+/-5%
4.7K
+/-5% * 0.1uF
16V, Y5V, +80%/-20%
+/-5% 2 7 10V, Y5V, +80%/-20% R0603 R0603 C0603
2
X4 R0603 3D3V_SB SO HOLD C0603
3 WP SCK 6
XTALI 1 2XTALO 4 5 U19
GND SI
1 A0 VCC 8
C316 XTAL-25MHz C317 GND AT25F2048 Dummy 2 7
1 A1 WP/NC
1
VPD_CLK
D
* 22pF
50V, NPO, +/-5% * 22pF
50V, NPO, +/-5% VDD
Atmel-AT25F2048 ; ST-M25P20 3
4
A2/NC SCL
VSS/GND SDA
6
5 D
C0603 C0603
2
2
M24C08 VPD_DATA
ST-M24C08 ; Atmel-AT24C08
AVDD25 AVDD25
TRACE TO IC IS 25MIL Dummy for Marvell 88E8053
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
U27 3D3V_SB
(88E8053: No support ASF)
TESTMODE
SMDATA
SMCLK
VPD_DATA
VPD_CLK
SPI_CLK
SPI_CS
SPI_DI
VMAIN_AVAL
VDDO_TTL
VDDO_TTL
SPI_DO
VDD
VDD
VDD
VDD
BC6 1 2 0.1uF C0603 49 32
**
18 HSI_P0 16V, Y5V, +80%/-20% TX_P AVDDL
BC5 1 2 0.1uF C0603 50 31
18 HSI_N0 TX_N MDIN[3] MDIN_3 28
16V, Y5V, +80%/-20%
2
51 30 FB9
AVDDL MDIP[3] MDIP_3 28
CP7
52 AVDDL TSTPT 29 X_COPPER
Dummy FB L0805 100 Ohm
1
53 28 Dummy
18 HSO_N0_LAN RX_N AVDDL
18 HSO_P0_LAN 54 RX_P MDIN[2] 27 MDIN_2 28
10 CK_PE_100M_P_LAN 55 REFCLKP MDIP[2] 26 MDIP_2 28

C359 C366
1
10 CK_PE_100M_N_LAN 56 REFCLKN HSDACN 25
R365 * 0.1uF
16V, Y5V, +80%/-20% * 10uF
6.3V, Y5V, +80%/-20%
57 24 4.7K C0603 C0805
2
AVDDL HSDACP +/-5%
58 23 R0603
E
VDD AVDD Q34
24,28 LED_ACT
LED_ACT
LINK_100J
59 LED_LNK/ACTn 88E8052 AVDDL 22 CTRL12 B
BCP69T1
28 LINK_100J 60 LED_LINK10/100n MDIN[1] 21 MDIN_1 28
VDD
4
C
61 VDDO_TTL MDIP[1] 20 MDIP_1 28
LINK_1000J 62 19 C321 C329
28 LINK_1000J LED_LINK1000n AVDDL
1
* 4.7uF
* 0.1uF
VDDO_TTL_MAIN
C 63 18 10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C
MDIN_0 28
LOM_DISABLEn
LED_LINKn MDIN[0]
SWITCH_VAUX
C0805 C0603
SWITCH_VCC
VAUX_AVLBL
2
64 17 MDIP_0 28
VDDO_TTL
VDD25 MDIP[0]
PERSTn
CTRL12
CTRL25
WAKEn
65
XTALO
EPAD
XTALI
RSET
VDD
VDD
VDD
88E8052-A3-NNC-C000
10
11
12
13
14
15
16
3D3V_SB
2K in E8036 usage
R346 4.87K
+/-1%
R0603
XTALI PLACE PNP TO CHIP ACAP

CTRL12 3D3V_SB XTALO
CP8 X_COPPER CTRL12 PIN TRACE IS
CTRL25 25MIL
R342 3D3V_SB Dummy AVDD33
4.7K FB12
17,25 PCIE_PLTRSTJ +/-5% 2 1
R0603 C306
17,18 WAKEJ
10V, Y5V, +80%/-20%

* 0.1uF FB L0805 100 Ohm C408 C392 R396
1
18 GPIO_LAN_DISABLEJ
R343 0
Dummy
16V, Y5V, +80%/-20% Dummy
C0603 * 10uF
* 0.1uF
16V, Y5V, +80%/-20%
4.7K
+/-5%
2
C0603 R0603
E
C1206
Q38
B
BCP69T1 AVDD25
CTRL25
4
C
C372 C348
1
B
VDD
* 4.7uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
B
C0805 C0603
2
C361 C365 C324 C360 C363 C308 C311 C312
1
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
2
2
PLACE PNP TO CHIP ACAP
CTRL25 PIN TRACE IS
25MIL
Close to Mavell Lan chip Kevin
R17~20, C14~17 NC for E8036
R17~20, C14~17 NC for E8036
3D3V_SB
MDIN_0
MDIP_0
MDIN_1
MDIN_2
MDIN_3
MDIP_1
MDIP_2
MDIP_3
C364 C309 C362 C319 C310

1
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603 C0603
2
R350 R348
49.9 49.9 R356 R353 R360 R358 R368 R364
+/-1% +/-1% 49.9 49.9 49.9 49.9 49.9 49.9 AVDD25
R0603 R0603 +/-1% +/-1% +/-1% +/-1% +/-1% +/-1%
R0603 R0603 R0603 R0603 R0603 R0603
C323 C334 C314 C327 C339 C341 C326 C342 C345 C331
1
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
2
2
A A
16V, Y5V, +80%/-20%
C325 C320 Note: Place Bypass Cap. as close as possible with every
25V, NPO, +/-5%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

1
0.1uF
** 1nF C332 C330 C340 C335 C347 C344
25V, NPO, +/-5%
25V, NPO, +/-5%
25V, NPO, +/-5%

1
power pin.
C0603 C0603
0.1uF
** 1nF 0.1uF
** 1nF 0.1uF
** 1nF
2
C0603 C0603 C0603 C0603 C0603 C0603

2
GND
GND GND GND
FOXCONN PCEG
Title
MARVELL 88E8052 LAN
C 945P01 A
Date: Monday, August 15, 2005 Sheet 21 of 30

5 4 3 2 1
5 4 3 2 1
+5VA 12V_SYS
R432
10
MIC1-VREFO-R +/-5%
MIC1-VREFO-R 23 U24 R0805
LINE2-VREFO 1 3
D LINE2-VREFO 23 OUT IN D
close to Codec as possible MIC2-VREFO
GND
MIC2-VREFO 23
MIC1-VREFO-L C483 C485 C433
MIC1-VREFO-L 23
1
SIDESURR-JD Sense_B
R448 5.1K
* 10uF
* 1uF LM78L05 C436
* * 4.7uF
2
23 SIDESURR-JD +/-1% C430 6.3V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% 0.1uF 25V, Y5V, +80%/-20%
1
R0603
* 10uF C0805 C0603 16V, Y5V, +80%/-20% C1206
2
CEN-JD R449 10K 6.3V, Y5V, +80%/-20% +5VA C0603 Dummy
23 CEN-JD +/-1% C0805
2
R0603
FRONT-IO-SENSE R444 0 C451 C452
23 FRONT-IO-SENSE
1
FRONT-L
Dummy +/-5%
R0603 23 FRONT-L
0.1uF
16V, Y5V, +80%/-20% * * 10uF
6.3V, Y5V, +80%/-20%
FRONT-R C0603 C0805
Analog Area Digital Area
2
23 FRONT-R
+5VA
36
35
34
33
32
31
30
29
28
27
26
25
U22
Sense B
VREF
FRONT-L
LINE2-VREFO
MIC2-VREFO
MIC1-VREFO-L
AVSS1
AVDD1
FRONT-R
DCVOL/NC
MIC1-VREFO-R
LINE1-VREFO-L/NC
C453 C424
1
* 10uF
6.3V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0805 C0603 37 24 LINE1-R
2
LINE1-VREFO-R/NC LINE1-R LINE1-R 23

38 23 LINE1-L
AVDD2 LINE1-L LINE1-L 23
SURR-L 39 22 MIC1-R
23 SURR-L SURR-L MIC1-R MIC1-R 23
40 21 MIC1-L
JDREF MIC1-L MIC1-L 23
SURR-R 41 20 CD_R
R457 23 SURR-R SURR-R CD-R Sense_A R400 5.1K FRONT-JD
20K CD_GND +/-1% FRONT-JD 23
Close to the 42 AVSS2 CD-GND 19
+/-1% codec as R0603
R0603 CEN 43 18 CD_L R401 10K LINE1-JD
possible. 23 CEN CEN CD-L +/-1% LINE1-JD 23
LFE 44 17 MIC2-R R0603
23 LFE LFE MIC2-R MIC2-R 23 R387 20K MIC1-JD
C C
SIDESURR-L MIC2-L +/-1% MIC1-JD 23
23 SIDESURR-L 45 SIDESURR-L MIC2-L 16 MIC2-L 23 R0603
Analog Area 23 SIDESURR-R
SIDESURR-R 46 SIDESURR-R LINE2-R 15 LINE2-R
LINE2-R 23
R388 39.2K
+/-1%
SURR-JD
SURR-JD 23
47 14 LINE2-L R0603
SPDIFI/EAPD(NC) LINE2-L LINE2-L 23
Digital Area SDATA-OUT Sense_A
PCBEEP/NC
48 SPDIFO Sense A 13
GPIO0/NC
GPIO1/NC
close to Codec as possible
SDATA-IN
RESET#
BIT-CLK
DVDD1
DVDD2
DVSS1
DVSS2
SYNC
SPDIF_OUT
ALC880
1
10
11
12
3D3V_SYS R429 2.2 C3891 2 1uF R390 10K
SPKR 18,24
*
R0805 +/-5% C414 C428 C0603 10V, Y5V, +80%/-20% +/-5%
1
10uF
6.3V, Y5V, +80%/-20% * * 0.1uF
16V, Y5V, +80%/-20%
Dummy
C384 R391
R0603
Dummy
1
C0805 C0603 R414 33
ICH_RSTJ 18,23 * 100pF 1K
2
R0603 50V, X7R, +/-10% +/-5%

+/-5% C0603 R0603
2
Dummy Dummy
ICH_SYNC 18
R433 22 ICH_SDIN2 18
PRESENCE_L +/-5%
23 PRESENCE_L R0603
ANTI_POP_GPIO1 R434 0
23 ANTI_POP_GPIO1 ICH_BCLK 18
+/-5%
R0603
ICH_SDOUT 18 For EMI 5V_SYS
B B
CP9 COPPER C445 1 2 0.1uF
*
Dummy 16V, Y5V, +80%/-20% C410
1
C0603
* 0.1uF
16V, Y5V, +80%/-20%
C434 C435 C423 C412 C0603
2
1
* 33pF
50V, NPO, +/-5% * 22pF
50V, NPO, +/-5% * 33pF
50V, NPO, +/-5% * 33pF
50V, NPO, +/-5%
C0603 C0603 C0603 C0603 Tied at one point only under
2
Dummy Dummy Dummy

the codec or near the codec
C328 1 2 0.1uF C3871 2 0.1uF
*
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
C0603 C0603
SPDIF Header
SPDIF_OUT C443 0 R447 0 SPDIF_OUT_L
+/-5% +/-5% JSPDIFOUT1
R0603 R0603 C444 5V_SYS 1 1
1
R442
100 * 100pF
50V, X7R, +/-10% SPDIF_OUT_L 3 3
+/-5% C0603 Dummy 4
2
R0603 4
Dummy HEADER_1X4O2
CEN/LFE OUT LINE IN
CD-IN SURR OUT LINE OUT

CD_R C395 1 2 1uF
* * *
A 16V, Y5V, +80%/-20% CD_IN A

C0805 1
CD_GND C378 1 2 1uF 2 5
16V, Y5V, +80%/-20%
C0805
3
4
SIDE-SURR OUT MIC IN
CD_L C396 1 2 1uF
16V, Y5V, +80%/-20% JST-CON4-2-Black
C0805
Close to Chip SURR KIT for 880 AUDIO PANEL
AUDIO2 AUDIO1 FOXCONN PCEG
Title
Realtek ALC880 Azalia Audio
C 945P01 A
Date: Thursday, July 21, 2005 Sheet 22 of 30

5 4 3 2 1
5 4 3 2 1
Digital Area Analog Area

MIC2-L EC39 100uF
22 MIC2-L
FRONT AUDIO HEADER
*
3D3V_SYS CE20D50H110 16V, +/-20%
C
Control by software driver and S/B GPIO.
GPIO#0 driver low at: R494 1K B Q62
BTD2040N3
*R495
30K
R502 Close to Chip +/-5% +/-5%
1).Initial state R0603 R0603 D17
10K
E
2).Suspend to S1 R0603 2
Q65 MUTE MIC2-VREFO 3D3V_SYS
3).Resume from S1. +/-5% R507 22 MIC2-VREFO 3
MMBT3906 1
R508 0
+/-5% BAT54A R480 R482
R0603 10K MIC2-R EC42 100uF 4.7K 4.7K R450
22 MIC2-R
*
Q63 Q66 C488 R0603 CE20D50H110 16V, +/-20% +/-5% +/-5% 10K
C
D R506
+/-5% D
18,22 ICH_RSTJ
R503 1K Q60
* 22uF +/-5%
*R483 R0603 R0603
*
+/-5% 6.3V, Y5V, +80%/-20% Close to Chip R489 1K B Q54 30K F_AUDIO R0603
R0603 MMBT3906 MMBT3906 MMBT3906 C1206 +/-5% BTD2040N3 +/-5% 1 2
220K R0603 R0603 PRESENCE_L
3 4
E
R0603 5 6 MIC2-JD
+/-5% 7 X
9 10 LINE2-JD
3D3V_SB
R487 R505 Header_2X5_8
R504 1K LINE2-R EC40 100uF 4.7K 4.7K R491 R481
22 ANTI_POP_GPIO1 22 LINE2-R
*
+/-5% CE20D50H110 16V, +/-20% +/-5% +/-5% 39.2K 20K
C
R0603
*R486 D16 R0603 R0603 +/-1% +/-1%
Control line Control circuit

Close to Chip R490 1K B Q64 30K 2 R0603 R0603
+/-5% BTD2040N3 +/-5% LINE2-VREFO 3
22 LINE2-VREFO
R0603 R0603 1
E
BAT54A
FRONT-IO-SENSE
22 FRONT-IO-SENSE
LINE2-L EC43 100uF

22 LINE2-L
*
CE20D50H110 16V, +/-20%
C
PRESENCE_L
Close to Chip R474 1K B Q61
BTD2040N3
*R485
30K
22 PRESENCE_L
+/-5% +/-5%
R0603 R0603
E
Rear AUDIO
Close to Chip Close to Chip
6 Azalia Audio Jacks
FRONT-R EC47 100uF FB15 FB L0603 600 Ohm LINE_OUT_R5 LFE C4551 2 1uF FB10 FB L0603 600 Ohm LFE_C
22 FRONT-R * 22 LFE *
*
*
16V, +/-20% 16V, Y5V, +80%/-20%

C CE20D50H110 C0805 C357 C
C
C
1
C440
*R446 * 100pF
*R378 AUDIOB
1
* 100pF
50V, X7R, +/-10%
B Q45
BTD2040N3
30K
+/-5%
50V, X7R, +/-10%
C0603
B Q37
BTD2040N3
30K
+/-5%
22 LINE1-JD
LINE1_L2
LINE1-JD
62
63
2
C0603 R0603 4.7uF for DA (LF) R0603 64 Light Blue
E
E
2
LINE1_R5 65
Frequency Response
61
LINE_OUT_L2 52
Close to Chip R471 1K MUTE Close to Chip R380 1K MUTE FRONT-JD 53
22 FRONT-JD
+/-5% +/-5% 54 Lime
R0603 R0603 LINE_OUT_R5 55
FRONT-L EC46 100uF FB14 FB L0603 600 Ohm LINE_OUT_L2 CEN C4811 2 1uF FB11 FB L0603 600 Ohm CEN_C
22 FRONT-L * 22 CEN * 51
*
*
16V, +/-20% 16V, Y5V, +80%/-20%

CE20D50H110 C0805 MIC1_L2 42
C
C
C425 MIC1-JD
*R431 C381
*R381 22 MIC1-JD 43
1
1
* 100pF
50V, X7R, +/-10%
B Q43
BTD2040N3
30K
+/-5% * 100pF
50V, X7R, +/-10%
B Q39
BTD2040N3
30K
+/-5% MIC1_R5
44
45
Pink
C0603 R0603 C0603 R0603 41
E
E
2
2
JACK_Azalia 6 Ports
Right Side
R435 1K R395 1K
+/-5% +/-5%
R0603 R0603
AUDIOA
CEN_C 32
CEN-JD 33
22 CEN-JD
34 Orange
Close to Chip Close to Chip LFE_C 35
31
SURR-R C4541 2 1uF FB8 FB L0603 600 Ohm SURR-R_C SIDESURR-R C4571 2 1uF FB7 FB L0603 600 Ohm SIDESURRBACK-R_C SURR-L_C
22 SURR-R * 22 SIDESURR-R * 22
*
*
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% SURR-JD 23
22 SURR-JD
C0805 C0805 C333 24 Black
C
C
1
SURR-R_C
C346
* R369
* 100pF
*R359 25
1
B * 100pF
50V, X7R, +/-10%
B Q36
BTD2040N3
30K
+/-5%
50V, X7R, +/-10%
C0603
B Q35
BTD2040N3
30K
+/-5%
21 B
2
4.7uF for DA (LF) C0603 R0603 4.7uF for DA (LF) R0603 SIDESURRBACK-L_C 2
E
E
2
SIDESURR-JD 3
Frequency Response Frequency Response 22 SIDESURR-JD
4 Gray
SIDESURRBACK-R_C 5
1
Close to Chip R370 1K MUTE Close to Chip R362 1K MUTE
+/-5% +/-5% JACK_Azalia 6 Ports
R0603 R0603
22 SURR-L
SURR-L C4801 2 1uF FB13
* FB L0603 600 Ohm SURR-L_C
22 SIDESURR-L
SIDESURR-L C4561 2 1uF FB18
* FB L0603 600 Ohm SIDESURRBACK-L_C Left Side
*
*
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
C0805 C0805
C
C
C411 R399 C439 R445
* *
1
1
* 100pF
50V, X7R, +/-10%
B Q40
BTD2040N3
30K
+/-5% * 100pF
50V, X7R, +/-10%
B Q44
BTD2040N3
30K
+/-5%
C0603 R0603 C0603 R0603
E
E
2
2
R422 1K R470 1K
+/-5% +/-5%
R0603 R0603
MIC1-VREFO-L
22 MIC1-VREFO-L
MIC1-VREFO-R
22 MIC1-VREFO-R
4.7uF for DA (LF) R469 R451
4.7K 4.7K 4.7uF for DA (LF)
Frequency Response +/-5% +/-5%
R0603 R0603
Frequency Response
MIC1-R C3941 2 1uF FB17 FB L0603 600 Ohm MIC1_R5 LINE1-R C3931 2 1uF FB19 FB L0603 600 Ohm LINE1_R5
22 MIC1-R * 22 LINE1-R *
* *
* *
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%

A C0805 C0805 A
MIC1-L C3801 2 1uF FB16 FB L0603 600 Ohm MIC1_L2 LINE1-L C3791 2 1uF FB20 FB L0603 600 Ohm LINE1_L2
22 MIC1-L
16V, Y5V, +80%/-20% * C437 C438
22 LINE1-L
16V, Y5V, +80%/-20% * C442 C441
1
Close to Chip
C0805 100pF
50V, X7R, +/-10% * * 100pF
50V, X7R, +/-10% Close to Chip
C0805 100pF
50V, X7R, +/-10% * * 100pF
50V, X7R, +/-10%
C0603 C0603 C0603 C0603
2
FOXCONN PCEG
Title
Realtek ALC880 Azalia Audio-2
C 945P01 A
Date: Tuesday, August 16, 2005 Sheet 23 of 30

5 4 3 2 1
5 4 3 2 1
for some power supplies

without pw-ok function
5V_SB_SYS
-12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB_SYS
H5 H6
8
9
4
8
9
4
5V_SYS MH MH FMARK FMARK
R330 5V_SYS 5V_SYS 7 3 7 3 FD40 FD40
8.2K 6 (NPTH) 2 6 (NPTH) 2
+/-5% ATX_POWER 5 1 5 1
R0603 13 1 R332
1
+3.3V3 +3.3V1 100K 5V_SB_SYS 5V_SYS PS_ON MH1 MH3
14 -12V +3.3V2 2
15 3 R0603 Dummy Dummy
GND4 GND1
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

25 PS_ONJ R329 0 PS_ON 16 4 +/-5%
PSON +5V1
1
R0603 +/-5% 17
18
GND5
GND6
GND2
+5V2
5
6
* C303
0.1uF * C293
0.1uF * C294
0.1uF H2 H4
19 7 C0603 C0603 C0603 FMARK FMARK
2
GND7 GND3 PWRG_ATX FD40 FD40
20 RSVD PWR0K 8
D
21 +5V3 +5V_AUX 9 D
22 +5V4 +12V_1 10
8
9
4
8
9
4
23 11 MH MH
1
+5V5 +12V_2 C291
24 GND8 +3.3V4 12 7 3 7 3
1
ATX_2X12 * 0.1uF
16V, Y5V, +80%/-20% -12V_SYS 3D3V_SYS
6
5
(NPTH) 2
1
6
5
(NPTH) 2
1
C0603 H3 H1
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

MH2 MH4 FMARK FMARK
1
* C295
0.1uF * C305
0.1uF
Dummy Dummy FD40 FD40
C0603 C0603
1
PWRG_ATX 11,25
EMI
for 5V_SYS / 5V_SB switching quickly
D
Q29
R328
G
100 R0603 2N7002
+/-5% Dummy Dummy
S
Buzzer
5V_SYS
PS_ON Buzzer
+ +
C
Q30 RN1 BUZZER

11,18,25 SLP_S3J
R326 1K
+/-5%
B
MMBT3904
*1 2
SPKJ - -
R0603 Dummy 3 4 ICH_RIJ
Buzzer ICH_RIJ 18
E
Dummy 5 6
C C
C
7 8 R129
150 26 NRIA NRIA B Q17
+/-5% MMBT3904
8P4R0603 R128 C113
E
10K
1
R0603
1K
+/-5% * 220pF
50V, X7R, +/-10%
+/-5% R0603 C0603
2
3D3V_SYS 5V_SB_SYS 18,22 SPKR R143 1K B Q9 C30
1
MMBT3904
+/-5%
R0603 * 0.1uF
16V, Y5V, +80%/-20%
E
C0603
2
R498 R499 R497 R509 R511 R510
330 330 330 330 330 330
R478 +/-5% +/-5% +/-5% +/-5% +/-5% +/-5%
330 R0603 R0603 R0603 R0603 R0603 R0603
+/-5%
R0603
Front_Panel
1 2 GLED0
Orange Green
3 4 GLED1
19 SATA_LED Orange Green
5 6 C17 C4
8,10,18 ICH_SYS_RSTJ Blue Red PWRBTNJ 18
TPM
1
7 Blue Red 8
10pF
50V, NPO, +/-5% * * 10pF
50V, NPO, +/-5%
C484 C0603 C0603
2
1
C487
0.1uF * 5V_SYS R477 1K
+/-5%
9 Black * 0.1uF
16V, Y5V, +80%/-20%
18,19,25 L_AD0
Dummy Dummy
16V, Y5V, +80%/-20% 3D3V_SYS R476 220 R0603 11 12 220 R514 3D3V_SB C0603 TPM
2
C0603 R0603 +/-5% Orange Green +/-5% R0603

18,19,25 L_AD1 1 1 2 2 SERIRQ 19,25
19 HDD_LED 13 Orange Green 14 LED_ACT 21,28 3 3 4 4
18,19,25 L_AD2 5 5 6 6 PLTRSTJ 12,18,19,25
Header_2X7_10 7 8
7 8 C6 C8
Front_Panel 18,19,25 L_AD3 9 9 10 10 3D3V_SYS
1
B B
18,19,25 L_FRAMEJ
11 11 12 12
* 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5%
Header_2X6 C0603 C0603
2
10 CK_33M_TPM
Dummy Dummy
C5 C7 C9 C10
1
GLED1 GLED0 * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5%
C0603 C0603 C0603 C0603
2
ICH7_GPIO10 Dummy Dummy Dummy Dummy
C
Q55
R512 510 B
18 S3_LED ICH7_GPIO9
C
+/-5% MMBT3904 Q47

Default High R0603 18 S1_LED R513 510 B
E
+/-5% MMBT3904
Default High R0603 L_AD3
E
L_AD2
L_AD[3..0] L_AD1
18,19,25 L_AD[3..0] L_AD0
C
Q48
18 SLP_S5J R452 1K B S0 : Green Steady
+/-5% MMBT3904
R0603
S1/3 : Amber Steady
E
S4/5 : OFF
Will be high in the

Green for system working and amber for suspend
S4 state
GLED0_0
A
SLP4_L A
S5 L
S0(Before ATXPOK) H Green Amber
S0(After ATXPOK) H
S3 H GLED1_1
FOXCONN PCEG
Title
Power / MISC Connectors
C 945P01 A
Date: Monday, July 11, 2005 Sheet 24 of 30

5 4 3 2 1
5 4 3 2 1
5V_SB_SYS 3D3V_SYS 3D3V_SB 5V_SYS
*
C85 2 1 0.1uF C80 1 2 0.1uF
*
C0603 16V, Y5V, +80%/-20% R58 R75 C0603 16V, Y5V, +80%/-20%
SIO_PIN107
3D3V_SYS 1K 1K
SIO_PIN31
SIO_PIN49
SIO_PIN60
SIO_PIN93
SIO_PIN76
SIO_PIN6
+/-5% +/-5% KBMS1
REF5V_SUS REF5V_SUS R0603 R0603 REF5V REF5V 13
CP5 COPPER Dummy 16
R48 RN2 MCLK FB5 FB L0603 80 Ohm

* 11 5
8
6
4
2
123
107
1K 1K Dummy
71
72
31
49
60
93
76
70
9 3
6
+/-5% +/-5% U2 CP4 COPPER Dummy 7 1
7
5
3
1
R0603 8P4R0603
*
8 14
V_5P0_STBY
REF5V_STBY
REF5V
VCC
VCC
VCC
VCC
VCC
VTR
VTR
VTR
MDATA FB4 FB L0603 80 Ohm FB1 2 FB L0805 70 Ohm
* Dummy
1
Dummy
10
12
2
4
22 DRVDEN0 SLCT 33 SLCT 26 6
21 34 SVCC1 BC1 17
DRVDEN1 PE PE 26
INDEX_L
D
20 INDEX- BUSY 35 BUSY 26
CP1 COPPER
* 0.1uF
D
Floppy Interface
Parallel Port Interface

19 36 Dummy 16V, Y5V, +80%/-20% 15
MTR0- ACK- ACKJ 26 UP DOWN
37 C0603
PD7 PD7 26
18 38 PS2-KBMS-2
DS0- PD6 PD6 26
39 CP3 COPPER Dummy
PD5 PD5 26
17 DIR- PD4 40 PD4 26
KCLK FB3 FB L0603 80 Ohm
16
15
STEP-
WDATA-
PD3
PD2
41
42
PD3
PD2
26
26
* Dummy
14 43 KDATA CP2 COPPER Dummy
WGATE- PD1 PD1 26
TRK0_L 13 44
TRK0- PD0 PD0 26
WRTPRT_L FB2 FB L0603 80 Ohm 3D3V_SYS
RDATA_L
12
11
WRTPRT-
RDATA-
SLCTIN-
INITA-
47
48
SLINJ
INIT
26
26
* Dummy
10 HDSEL- ERROR- 45 ERRJ 26
DSKCHG_L 9 50 R96 8.2K SERIRQ
DSKCHG- ALF- AFDJ 26
51 R0603 +/-5%
STROBE- STBJ 26
65 SIO_PIN93 SIO_PIN107 BCN1 R31 10K KBRSTJ 3D3V_SYS
10 CK_14M_SIO CLOCKI14 C69 C23 33pF R0603 +/-5%
18,19,24 L_AD0 62 LAD0 DCD1- 23 DCDAJ 26
1
61 24
* 0.1uF
* 0.1uF
* 50V, NPO, +/-10% C12 0.1uF
Serial Port 1
18,19,24 L_AD1 LAD1 DSR1- DSRAJ 26
LPC Interface
59 25 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 8P4R0603 R28 10K A20GATE 1 2
SINA 26
*
18,19,24 L_AD2 LAD2 RXD1 C0603 C0603 R0603 +/-5% C0603 16V, Y5V, +80%/-20%
57 26 RTSAJ 26
2
18,19,24 L_AD3 LAD3 RTS1-
18,19,24 L_FRAMEJ 56 LFRAME- TXD1 27 SOUTA 26
54 28 5V_SYS
18 L_DRQ0J LDRQ- CTS1- CTSAJ 26 SVCC1
63 30 SIO_PIN76 SIO_PIN31 5V_SYS
12,18,19,24 PLTRSTJ PCIRST- DTR1- DTRAJ 26
55 32 C3 C82 C13 0.1uF
10 CK_33M_SIO PCICLK RI1- RIAJ 26
1
53 127
* 0.1uF
* 0.1uF 1 2
*
19,24 SERIRQ SERIRQ IRRX2 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% R468 4.7K FANPWM1 C0603 16V, Y5V, +80%/-20%
18 LPCPD_L 52 LPCPD- IRTX2 128
125 C0603 C0603 R0603 +/-5%
2
DTR2- Dummy 12V_SYS
124
EMI
Serial Port 2
CTS2- R488 4.7K FANPWM2
18 SUSCLK 91 CLOCKI32 RTS2- 122
99 121 SIO_PIN6 SIO_PIN60 5V_SYS R0603 +/-5% C11 0.1uF
18 L_PMEJ IO_PME DSR2- C98 C97
120 1 2
*
TXD2
1
95
94
YLW_LED2 RXD2 119
126
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% C72 1 2 0.1uF
R501
R0603
4.7K
+/-5%
FANPWM3 C0603
5V_SYS
16V, Y5V, +80%/-20%
*
GRN_LED1 DCD2- C0603 C0603 C0603 16V, Y5V, +80%/-20%
118
2
RI2- C501 0.1uF
for 33MHz & 14MHz change layer
SMB_DATA_RESUME 90 1 2
*
17,18,21 SMB_DATA_RESUME SMB_DAT_R
Keyboard/Mouse
SMB_CLK_RESUME 88 3 KCLK SIO_PIN49 C0603 16V, Y5V, +80%/-20%
17,18,21 SMB_CLK_RESUME SMB_CLK_R KCLK
SMBus
C SMB_DATA_MAIN 89 4 KDATA C1 C35 1 2 0.1uF KBRSTJ 5V_SYS C
* *
10,15,16 SMB_DATA_MAIN SMB_DAT_M KDAT
1
SMB_CLK_MAIN MCLK
10,15,16 SMB_CLK_MAIN 87 SMB_CLK_M MCLK
MDAT
1
2 MDATA * 0.1uF
16V, Y5V, +80%/-20%
Dummy C0603 16V, Y5V, +80%/-20%
*1
RN6
2
MCLK C502 0.1uF
66 7 C0603 C19 1 2 0.1uF A20GATE MDATA 1 2
KBRSTJ 19
*
HD_LED- KBDRST- Dummy C0603 16V, Y5V, +80%/-20% 3 4 KCLK C0603 16V, Y5V, +80%/-20%
67 PRIMARY_LED- GA20M 5 A20GATE 19 5 6
Hardware Monitoring and FAN Control
68 KDATA
SECONDARY_LED- R97 1K 7 8
69 SCSI- 5V_SYS
R0603 +/-5% 4.7K
113 +/-5%
for EMI
12 DDCA_CLK DDCSCL_3V/GP23
115 64 8P4R0603
12 DDCA_DATA DDCSDA_3V/GP22 IDE_RSTDRV- IDE_PCIRSTJ 19
114 73 R57 33
26 DDCSCL_5V DDCSCL_5V/GP21 PCIRST_OUT1- PCIE_PLTRSTJ 17,21
116 74 +/-5% U26
26 DDCSDA_5V DDCSDA_5V/GP20 PCIRST_OUT2- R0603 C81 FANPWM1 24 PWM1/NTESTOUT VCCP_IN 23 VCCP
1
PS_ONJ will active low,after 112 GP17/FAN_TACH2 FPRST- 75 no function: Pin 75
* 33pF
2.5V 22 1D5V_CORE
System Signals
111 82 50V, NPO, +/-5% SMB_DATA_MAIN 1 20

SKTOCC_L gose low and GP16/FAN_TACH1 PWRGD_PS
84
PWRG_ATX 11,24
C0603 SMB_CLK_MAIN 2
SDA 5V
4
5V_SYS
PWRGD_3V 12,18,27 3D3V_SYS
2
SLP_S3J gose high PWRGD_3.3V R46 8 THERMDA C482 SCL 3.3SBY
77 BACKFEED_CUT- 12V 21 12V_SYS
1
79
80
LATCHED_BF_CUT
SCK_BJT_GATE
SLP_S5-
SLP_S3-
86
85
SLP_S4J
SLP_S3J
11,18
11,18,24
10K
+/-5% * 100pF
50V, X7R, +/-10%
18
17
REMOTE1+
REMOTE1-/NTESTIN PWM2 10 FANPWM2 * C503
0.1uF C0603
81 R0603 C0603 REMOTE2+ 16 13 FANPWM3 16V, Y5V, +80%/-20%
2
24 PS_ONJ PS_ON- Dummy REMOTE2- REMOTE2+ PWM3
8 SKTOCC_L 83 CPU_PRESENT- RSMRST- 92 RSMRSTJ 18 8 THERMDC 15 REMOTE2-
11 FAN1
TACH1 FAN2
GP10 103 19 VID4 TACH2 12
R49 100 104 R29 8 9
100K
R0603
101
102
AUD_LINK_RST
CDC_DWN_ENAB/GP24
CDC_DWN_RST
GP11
GP12
GP13
105
106
10K
R0603
System Thermal Sensor 7
6
VID3
VID2
VID1
TACH3
TACH4 14
ICH_THRM_UP 18
+/-5% 108 +/-5% 5 3

Dummy GP14 Dummy VID0 GND
GP15 109
3D3V_SB 98 REMOTE2+ 10 mils GND (recommend) EMC6D103
TEST_EN
F_CAP
10 mils 10 mils GND (recommend)

VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
The SKTOCC# pin will be driven to ground C486 10 mils REMOTE2+
1
by the processor when the processor is LPC47M182
Q53
B
* 100pF
50V, X7R, +/-10% 10 mils 10 mils
10 mils
CPU_TMPA
97
8
29
46
58
78
96
110
117
socketed in the system,otherwise the MMBT3904 C0603 10 mils REMOTE2-
2
SKTOCC# signal will be floating. nearby PWM 10 mils
E
10 mils 10 mils VTIN_GND
REMOTE2- 10 mils GND (recommend)
B B
10 mils
10 mils GND (recommend)
SMB_MAIN SMSC LPC SMB_RESUME 3D3V_SYS

switch logic
CPU FAN1 Peak fan current draw: 1.5A C479
1
Average fan current draw: 1.1A CPU FAN2 * 0.1uF
16V, Y5V, +80%/-20%
Fan start-up current draw: 2.2A C0603
SMBUS Isolation:
2
Fan start-up current draw maximum duration: 1.0 second
FANPWM2 R354 100 R0603 +/-5%
Fan header voltage: 12V +/- 10%
Close EMC6D103 Pin4
3D3V_SB
R392 100
R32 2.7K R0603 +/-5% SMB_DATA_RESUME R0603 +/-5% 12V_SYS
Dummy 12V_SYS
CATHODE
R38 2.7K R0603 +/-5% SMB_CLK_RESUME 12V_SYS R344
12V_SYS 0
3D3V_SYS New FAN Header Definition +/-5%
R0805
R37 2.7K R0603 +/-5% SMB_DATA_MAIN
pin1. GND R340
pin2. +12V D13 4.7K
pin3. Sense 1N4148W +/-5%
4
R43 2.7K R0603 +/-5% SMB_CLK_MAIN CPU_FAN2 Dummy R0603

pin4. Control
S
ANODE
3 U23A Q46 12V_SYS FAN2_4
+ 4 4 FAN2_3 FAN2
1 R473 1K G 3 3
R351 27K +/-1%
CATHODE
SMB_DATA_MAIN SMB_CLK_MAIN FANPWM3 R393 100K 2 +/-5% FAN2_2 R0603

+/-5%
-
LM324 R0603 HJ772-P 2 2 R349 C318
1 1
D
1
R0603 EC44 BC3 10K
* 47pF
11
1
C467 C450 C382 * 100uF HEADER_1X4 (FAN4P)
* 0.1uF +/-5% 50V, NPO, +/-5%
1
10pF
* 10pF
* * 1uF R371 16V, +/-20% 16V, Y5V, +80%/-20% R0603 C0603
2
50V, NPO, +/-5% 50V, NPO, +/-5% 10V, Y5V, +80%/-20% 4.7K CE20D50H110 C0603 Dummy
2
C0603 C0603 C0603 D14 +/-5%
2
A Dummy Dummy CPU_FAN1 1N4148W R0603 A

FANPWM1 Dummy
4 4
1 ANODE
R466 7.15K R367 27K +/-1% FAN1

+/-1% 3 3 R0603
R0603 EC45 2 2
MAIN-->for Clock 1 1
Generator/DIMMs/TPM/Clock Buffer * 100uF BC4 R363
R454 16V, +/-20% Header_1X4 (FAN4P)
* 0.1uF 10K
4
5.1K CE20D50H110 16V, Y5V, +80%/-20% +/-5%
RESUME-->for PCI-E R0603 C0603 R0603 5 U23B
2
+
7
x16/ICH7/LAN/PCI/PCI-E x1/Riser
Card/New Card
+/-1%
6 -
LM324
FOXCONN PCEG
Title
3 Pin & 4 Pin Fan
11
SMSC 47M182 SIO KB/MS/FAN
auto detection Size Document Number Rev
C 945P01 A

5 4 3 2 1
5 4 3 2 1
5V_SYS
D4
CATHODE ANODE
5V_SYS C135
1
SD103AW
* 0.1uF
16V, Y5V, +80%/-20%
RN13 RN15 C0603
2
4
6
8
2
4
6
8
2
R319 5V_SYS 2.7K 2.7K
1K 8P4R0603 8P4R0603
* 13
5
7
* 13
5
7
+/-5%
R0603 +/-5% +/-5%
U16 P_D0
1 14 PD0 P_D1
1A VCC 25 PD0 PD1 7 8 P_D2
12 VSYNC 2 1B 25 PD1 5 6
5V_VSYNC R316 39 R0603 +/-5% 3 13 C279 PD2 P_D3
1Y 4B 25 PD2 3 4
1
D
4 2A
4A
4Y
12
11
* 0.1uF
16V, Y5V, +80%/-20% 25 PD3
PD3
RN14
*
1 2 33 +/-5% 8P4R0603
P_D4
P_D5 D
5 C0603 P_D6
12 HSYNC
2
5V_HSYNC R327 39 R0603 +/-5% 2B P_D7
6 2Y 3B 10
3A 9
7 GND 3Y 8
SN74ACT08DR
PD4 R227 RN8 RN17
2
4
6
8
2
4
6
8
25 PD4 PD5 7 8 2.7K
25 PD5 5 6 2.7K 2.7K
PD6 +/-5% 8P4R0603 8P4R0603
25 PD6 3 4
* 13
5
7
* 13
5
7
PD7 * R0603
25 PD7 RN12 1 2 33 +/-5% 8P4R0603 +/-5% +/-5%
25 STBJ 7 8 SLIN1-
25 AFDJ 5 6 AFD1-
25 INIT * 3 4 25 ERRJ ERR-
25 SLINJ RN16 1 2 33 +/-5% INIT1-
RGB routing 8P4R0603 ACK-
25 ACKJ BUSY
1. from GMCH to the first 150 ohm resistor: 12 mils 25 BUSY PE
2. from the first 150 ohm res. to the second 150 ohm resistor: 7 mils 25 PE SLCT
25 SLCT
3. from the second 150 ohm resistor to connector: 4 mils
4. spacing 20 mils
5. R,G,B should be length matched to 200 mils
PRNT25-M
1
AFD1- 14
P_D0 2
ERR- 15
P_D1 3
INIT1- 16
SLIN1-
P_D2 4
17
PRT PORT
VGA Connector P_D3 5
EMI 5V_SYS P_D4
18
6
C 19 C
2D5V_MCH P_D5 7 28
C264 1 2 0.1uF 20 27
* * * * *
C0603 16V, Y5V, +80%/-20% P_D6 8 26
2
C249 21
* 0.1uF C251 1 2 0.1uF P_D7 9
16V, Y5V, +80%/-20% C0603 16V, Y5V, +80%/-20% 22
1
2
D10 D11 D12 C0603 ACK- 10

Dummy C259 1 2 0.1uF 23
BAT54SLT1G
BAT54SLT1G
BAT54SLT1G
3 3 3 C0603 16V, Y5V, +80%/-20% BUSY 11

24
C265 1 2 0.1uF PE 12
C0603 16V, Y5V, +80%/-20% 25
1
SLCT 13
C429 1 2 0.1uF
C0603 16V, Y5V, +80%/-20%
LPT
*
RED L22 L0603 47nH

12 RED
R250
150
+/-1% C253 CN6 CN4
1
R0603 C254
* 3.3pF 180pF 180pF
1
* 3.3pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF
C0603 5V_SYS * 50V, NPO, +/-10%
8P4R0603 * 50V, NPO, +/-10%
8P4R0603 C231
2
1
C0603 CN3 CN5
* 180pF
2
180pF 180pF 50V, X7R, +/-10%

F4 50V, NPO, +/-10% 50V, NPO, +/-10% C0603
* *
2
F1210_1.5A 8P4R0603 8P4R0603
*
L_RED
*
GREEN L23 L0603 47nH L_GREEN

12 GREEN L_BLUE
B
R259 C258 C257 VGA B
1
VGA
150
+/-1% * 3.3pF
50V, NPO, +/-0.25pF * 3.3pF
50V, NPO, +/-0.25pF 25 DDCSCL_5V
R3
R0603
100
+/-5% DDCSCL 15 SCL GND 5
R0603 C0603 C0603 R1 100 DDCSDA 10 GND 12V_SYS
2
25 DDCSDA_5V 5V_SYS
+/-5% 14 VSYNC ID0 4
R0603 9 NC
13 HSYNC B 3
8 GND U8
12 SDA G 2 20 VCC +12V 1
R4 2.2K 7 GND
16V, Y5V, +80%/-20%

5V_SYS
R0603 +/-5% 11 ID1 R 1 25 RTSAJ 16 DA1 DY1 5 NRTSA
R2 2.2K C233 6 GND C505
25 DTRAJ 15 DA2 DY2 6 NDTRA C504
1
1
-12V_SYS
R0603 +/-5%
* 0.1uF
* 13 8 NSOUTA
* 0.1uF 5V_SYS 12V_SYS
*
BLUE L24 L0603 47nH 16V, Y5V, +80%/-20% VGA15P 25 SOUTA DA3 DY3 NRIA 16V, Y5V, +80%/-20%
19 2 NRIA 24
16
17
12 BLUE C0603 0.1uF 25 RIAJ RY1 RA1 NCTSA C0603 C134 C302
18 3
2
2
C0603 25 CTSAJ RY2 RA2
1
NDSRA C0603
25
25
DSRAJ
SINA
17
14
RY3
RY4
RA3
RA4
4
7 NSINA * 16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
R264 C262 C261 12 9 NDCDA 0.1uF C0603 C0603
2
25 DCDAJ RY5 RA5
1
C133
150
+/-1% * 3.3pF
50V, NPO, +/-0.25pF * 3.3pF
50V, NPO, +/-0.25pF 11 GND -12V 10 -12V_SYS
R0603 C0603 C0603
2
GD75232
placed near GD75232
3D3V_SYS RS232 Drivers and Receivers
2
C184 RS232-9
* 0.1uF 11
2
16V, Y5V, +80%/-20% D8 D9

1
C0603 DDCSCL C2321 2 22pF NDCDA 1

* *
3 3 50V, NPO, +/-5% NDSRA 6

C0603 NSINA 2
DDCSDA C2 1 2 22pF NRTSA 7
BAT54S BAT54S 50V, NPO, +/-5% NSOUTA 3
1
Dummy Dummy C0603 NCTSA 8

NDTRA 4
A NRIA 9 A
5V_VSYNC 5
10
5V_HSYNC CN2 CN1
180pF 180pF COM1
C246 C247 50V, NPO, +/-10% 50V, NPO, +/-10%
* *
1
* 22pF
50V, NPO, +/-5% * 22pF
50V, NPO, +/-5%
8P4R0603 8P4R0603
C0603 C0603
FOXCONN PCEG
2
Title
COM 1 VGA & Serial / Parallel Con
C 945P01 A
Date: Thursday, July 28, 2005 Sheet 26 of 30

5 4 3 2 1
5 4 3 2 1
5V_SYS 3D3V_SYS
R135
4.7K
R0603
+/-5%
C102 1 2 0.1uF
* * *
16V, Y5V, +80%/-20%
C140 C138 C128 C0603
1
D D
CP6 * 1nF
50V, X7R, +/-10% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C109 1 2 10nF
25V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603
2
C105 1 2 1nF
100
107
108
120
50V, X7R, +/-10%
78
62
48
35
20
95
94
27
39
51
59
72
88
15
11
COPPER
1
2
R133 10K U7 C0603
Dummy +/-5%
VDDP
VDDP
VDDP
VDDP
VDDP
TEST8
TEST9
TEST16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
AVDD
AVDD
AVDD
AVDD
AVDD
FB6 R134 4.7K R0603 86
* 3D3V_SYS CYCLEOUT
+/-5% 87
3D3V_SYS CYCLEIN
R0603 7 PLL_VDD
1
1
FB L0805 80 Ohm
Dummy * C115
0.1uF * C112
1nF * C114
10uF PC2
PC1
97
98 TPBIAS0 R108 56.2 TPA0
16V, Y5V, +80%/-20% 50V, X7R, +/-10%6.3V, Y5V, +80%/-20% 99 R115 1K 3D3V_SYS +/-1%
2
2
C0603 C0603 C0805 PC0 +/-5% R0603
17,20 AD31 22 AD31
24 R0603
17,20 AD30 AD30 R113 6.34K R99 56.2 TPA0J
17,20 AD29 25 AD29 RI0 118
26 +/-1% +/-1%
17,20
17,20
17,20
AD28
AD27
AD26
28
29
AD28
AD27
AD26
TSB43AB22 RI1 119 R0603 R0603
17,20 AD25 31 AD25

32 C103 1 21uF
*
17,20 AD24 AD24
17,20 AD23 37 AD23 TEST17 10 R132 4.7K 3D3V_SYS 10V, Y5V, +80%/-20%
38 105 +/-5% C0603
17,20 AD22 AD22 TEST0 R0603
17,20 AD21 40 AD21 TEST1 104
17,20 AD20 41 AD20 TEST2 102
17,20 AD19 42 AD19 TEST3 101
AD[31..0] 43 TPBIAS1 R111 56.2 TPA1
17,20 AD[31..0] 17,20 AD18 AD18
45 +/-1%
17,20 AD17 AD17 R0603
17,20 AD16 46 AD16
17,20 AD15 61 AD15
63 121 TPB1J R112 56.2 TPA1J
17,20 AD14 AD14 TPB1N TPB1J 28
65 122 TPB1 +/-1%
17,20 AD13 AD13 TPB1P TPB1 28
66 123 TPA1J R0603
17,20 AD12 AD12 TPA1N TPA1J 28
67 124 TPA1
17,20 AD11 AD11 TPA1P TPA1 28
69 125 TPBIAS1 C1011 21uF
*
17,20 AD10 AD10 TPBIAS1 10V, Y5V, +80%/-20%
17,20 AD9 70 AD9
71 C0603
17,20 AD8 AD8
C
17,20 AD7 74 AD7
C
17,20 AD6 76 AD6

77 112 TPB0J
17,20 AD5 AD5 TPB0N TPB0J 28
79 113 TPB0
17,20 AD4 AD4 TPB0P TPB0 28
80 114 TPA0J
17,20 AD3 AD3 TPA0N TPA0J 28
81 115 TPA0
17,20 AD2 AD2 TPA0P TPA0 28
82 116 TPBIAS0 IEEE1394a Interface R109 56.2 TPB0
17,20 AD1 AD1 TPBIAS0 +/-1%
17,20 AD0 84 AD0 Trace width 5 mils & 9 mils space.
R0603
Trace mismatch < 150 mils.
17,20 CBEJ3 34 CBE3
47 6 C107 1 2 12pF Maintain 110 +/- 6 ohm differential R100 56.2 TPB0J
17,20 CBEJ2
*
CBE2 XO
2
17,20 CBEJ1 60 50V, NPO, +/-5% impedance. +/-1%
CBE1 X2 C0603 R0603
17,20 CBEJ0 73 CBE0 XI 5
XTAL-24.576MHz
49 C108 1 2 12pF R106 5.11K
17,20 FRAMEJ
*
FRAME 50V, NPO, +/-5% +/-1%
17,20 IRDYJ 50 IRDY
52 C0603 R0603
17,20 TRDYJ TRDY
53 106 R114 390K
17,20 DEVSELJ DEVSEL CPS 1394_POW_CON
54 +/-5% C104 1 2220pF
17,20 STOPJ
*
STOP R0603 R116 4.7K 50V, X7R, +/-10%
17,20 PERRJ 56 PERR CNA 96 3D3V_SYS
57 +/-5% C0603
17,20 SERRJ SERR
58 R0603
17,20 PAR PAR
91 SCL
GROM_SCL SDA R102 56.2 TPB1
17,20 INTFJ 13 INTA GROM_SDA 92
AD19 R154 100 36 R117 220 +/-1%
R0603 +/-5% IDSEL +/-5% R0603
17,20 PCIRSTJ 85 3 C110 1 2 0.1uF R0603
*
PCIRST# FILTER0 16V, Y5V, +80%/-20% R103 56.2 TPB1J
10 CK_33M_1394 16 PCI_CLK FILTER1 4 Dummy
18 C0603 +/-1%
20 GNT0J GNT#
19 89 R130 220 R0603
17,20 PREQ0J REQ# GPIO3
90 +/-5%
R137 10K GPIO2 R0603 R101 5.11K
12 CLKRUN#
17,20 PMEJ R149 0 +/-5% 21 14 R122 220 +/-1%
R0603 +/-5% R0603 PME# G_RST# +/-5% 3D3V_SYS R0603
PLLGND2
PLLGND1
Dummy R0603
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
PME Support for Low Power Modes R141 100K C99 1 2220pF
*
Dummy +/-5% 50V, X7R, +/-10%
R0603 C0603
B B
TSB43AB22A C119 1 2 0.1uF
30
93
9
103
83
75
68
64
55
44
33
23
17
128
127
126
117
111
110
109
8
*
16V, Y5V, +80%/-20%
C0603
Dummy
R140 0
PWRGD_3V 12,18,25
+/-5%
C139 C111 R0603
1
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
C0603 C0603
2
5V_SYS
U6
3 A2
2 A1
R123 R120 1 4
2.7K 2.7K A0 GND
+/-5% +/-5%
R0603 R0603 7 WP
SDA 5 8
SDA VCC 5V_SYS
C122
1
SCL 6 SCL * 0.1uF

16V, Y5V, +80%/-20%
R131 AT24C02N-2.7V C0603
2
2.7K
+/-5%
R0603
A A
FOXCONN PCEG
Title
TI TSB43AB22 1394
C 945P01 A
Date: Monday, July 25, 2005 Sheet 27 of 30

5 4 3 2 1
5 4 3 2 1
Rear Dual USB & 1394

1394_POW_CON 1394_POW_CON
12
9
USB1
1394_POW_CON SVCC1 1
USB1 & 2
BOTTOM
D NUSBP1 2 D
J1394 C126
1
TA1+ TA1- PUSBP1
C263 1 2
* 0.1uF 3
1
0.1uF 50V, Y5V, +80%/-20%
1394_USB1 * 50V, Y5V, +80%/-20% TB1+
3
5
4
6 TB1- C0603 >40V 4
2
C0603 7 8
2
SVCC1 5 9 >40V 10
USBV1 1394VCC X
SVCC1 1 USBVCC0 TB0- Header_2X5_9 SVCC1
1394D0- 11 TPB1J 27 5
NUSBP0
TOP
18 USBP0N-1394 2 -USBD0
12 TB0+ NUSBP0 6
PUSBP0 1394D0+ TPB1 27
18 USBP0P-1394 3 +USBD0 PUSBP0 7
18 USBP1N-1394
NUSBP1 6 -USBD1 1394D1- 13 TA0-
TPA1J 27 Front 1394 Header 8
PUSBP1 7 14 TA0+
18 USBP1P-1394 +USBD1 1394D1+ TPA1 27
17 GND3 1394GND 10
4 USBX2
10
11
GND0
15 19 Dummy
GND9 GND5
16 GND2 GND6 20
18 21 12V_SYS
GND4 GND7
8 GND1 GND8 22
No 1394 Connector
F1
USBX2_1394 D3
1394_POW_CON CATHODE ANODE
*
SVCC1
B340B
F1812_ 1.5A_24V TB1+
R284 47K TPB0 27
C +/-5% USB_OCJ_BACK 18 TB1- C
R0603 TPB0J 27
BC2 R278 TA1+
0.1uF 56K TPA0 27
* 16V, Y5V, +80%/-20% +/-5% TA1-
TPA0J 27
C0603 R0603
5V_DUAL
BACK PANEL ( LAN + 2 USB Connector ) F5 F6
F1813_2.6A
*
*
F1813_2.6A SVCC1
AVDD25 JFM31U10-01U5W without LED

3D3V_SB 3D3V_SB R335 47K
JFM31U1A-01U5W with LED 18 USB_OCJ_BACK
+/-5%
LED Definition: R0603
GIGA stuff R961,R962,C732 R337
1000: Yellow and Green LED C307 56K * EC33
1
R345 470pF +/-5% 1000uF

100: Yellow and Green LED R347 R339 0 * 50V, X7R, +/-10% R0603 6.3V, +/-20%
330 330 R0603 C0603 CE35D80H200
2
10: Only Green LED +/-5% +/-5% +/-5%

B R0603 R0603 B
Dummy Dummy
NIC_USB1
LED caps. should be placed
next to connector 27
22 28
YLW_LED
21 LINK_100J 21 29
C304 C315
USB-2
USB-1
21 LINK_1000J 30
1
0.1uF
16V, Y5V, +80%/-20%* * 0.1uF
16V, Y5V, +80%/-20%
Right Side SVCC1
18 USBP2P USBD_T2+
Dummy C0603 C0603 9 1
2
Dummy 10 5 18 USBP2N USBD_T2-

21 MDIP_0
21 MDIN_0 11
RJ45-MJ2
12 2 USBD_T3-
21 MDIP_1 USBD_T2-
21 MDIN_1 13 6
21 MDIP_2 14
15 3 USBD_T3+
21 MDIN_2 USBD_T2+
21 MDIP_3 16 7
21 MDIN_3 17
18 4 18 USBP3P USBD_T3+
8
18 USBP3N USBD_T3-
GRN_LED
Left Side
20 23
21,24 LED_ACT 19 24
25
26
C292
1
For JFM31U1A-01U5W C299

* 0.1uF
1
A
Connector(with LED)
0.1uF
16V, Y5V, +80%/-20% * USBX2_RJ45 10/100 Mbit LAN 16V, Y5V, +80%/-20%
C0603
Veriton--> supports 4 rear USB ports A
2
C0603 Aspire --> supports 2 rear USB ports

2
Dummy C298 1 2 0.1uF

*
C0603 25V, Y5V, +80%/-20%
R338 0
FOXCONN PCEG
R0603 +/-5% Title
Dummy 1394 & Rear-LANUSB Conn
Custom 945P01 A
Date: Wednesday, July 20, 2005 Sheet 28 of 30

5 4 3 2 1
5 4 3 2 1
CPU Power Controller Intersil ISL6561 (VRD10.1) 12V_POWER

VSS_SENSE VRM_PWRGD 18
C413 VSS_SENSE VSEN
1
VTT_OUT_RIGHT 3D3V_SYS
* 82pF
1
5V_SYS
50V, NPO, +/-5%
* C383
* C390 R427 1K PWM4 R394 0 R0603 +/-5% 5V_SYS C385
4
DIFF 2
C0603
Dummy
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
+/-5%
R0603 C427
Dummy
* 0.1uF
16V, Y5V, +80%/-20% 5
1
*
C0603 C0603
* 1uF C0603
2
Close to VRD R438 R437 RN23 C388 Dummy Dummy 10V, Y5V, +80%/-20% 12V_POWER
7
5
3
1
1
FOR EMI ISSUE
Controller 680 680 680
* 1uF C0603
For 3 Phase Solution:
2
+/-5% +/-5% 8P4R0603 16V, Y5V, +80%/-20% ATX12V
3
8
6
4
2
R0603 R0603 C0805 Dummy R751 , Stuff the R761
2
+/-5% U20 R415
32 38 5.6K ATX12V_P1_2X2
VCC OVP +/-5%
1 39 R0603
8 VID4 VID4 PGOOD
D 8 VID3 2 VID3 D
3 33 R416 1K
8 VID2 VID2 EN
4 R0603 +/-5%
8 VID1 VID1
5 25 PWM1
8 VID0 VID0 PWM1
8 VID5 6 VID5 (12.5)
8 VSS_SENSE 24 ISEN1+ R384 453 Phase1 VCCP VTTPWRGD
R420 100 VTTPWRGD ISEN1+ +/-1% Phase1_L 8 VTTPWRGD
34 ENLL ISEN1- 23
+/-5% R0603 VTT_OUT_RIGHT
2
TO CPU VCORE R0603 C386 VSSSEN 18 26 PWM2
* 10nF RGND PWM2
SENSE PIN Close to VRD
25V, X7R, +/-10% VSEN 17 27 ISEN2+ R383 453 Phase2 VCCP R419
Controller
1
C0603 Dummy VSEN ISEN2+ +/-1% Phase2_L 680
ISEN2- 28
DIFF 16 R0603 VTT_OUT_RIGHT 3D3V_SB +/-5%
8 VCC_SENSE DIFF
VCCP R398 100 20 PWM3 R0603
+/-5% PWM3
R0603 21 ISEN3+ R377 453 Phase3 VCCP R425
D
ISEN3+ +/-1% Phase3_L 10K
15 COMP ISEN3- 22
R0603 R413 +/-5% Q42
14 31 PWM4 2.74K R0603
IDROOP PWM4 +/-1% G
C422 1 2 120pF FB 13 30 ISEN4+ R382 453 Phase4 VCCP R0603 2N7002
*
R418 R417 50V, X7R, +/-10% FB ISEN4+ +/-1% Phase4_L
29
S
2.1K 487 Dummy C0603 ISEN4- R0603 Q41
+/-1% +/-1% Dummy Phase1 R412 22.1K B
R0603 R0603 11 Switch Freq=200kHz Phase2 +/-1% MMBT3904
C426 1 REF Phase3
2 1nF R428 27K +/-1% R0603
E
*
C0603 50V, X7R, +/-10% R0603 36 R426 150K Phase4
FS +/-1%
*
C391
10 DAC
41 C415 1
R0603
2 1nF
* C370
0.1uF * C369
0.1uF * C371
0.1uF * C368
0.1uF
C3972 11uF
10V, Y5V, +80%/-20%
*
41
1
* 5.6nF 37 50V, X7R, +/-10% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C0603
2
50V, X7R, +/-10% GND1 C0603 C0603 Dummy C0603 Dummy C0603 Dummy C0603 Dummy
8 OFS GND2 35
R430 210 C0603 Dummy C432 R436 40 Dummy
2
GND3
1
* 10nF
25V, X7R, +/-10%
1K
+/-1% 9 TCOMP
GND4
GND5
19
12
Close to VRD Controller
R0603 +/-1% C0603 R0603 7
2
GND6
ISL6561
C R440 R439 C
20K 56K R441
+/-5% +/-1% 2.4K
R0603 R0603 +/-5%
5V_SYS Dummy R0603
*
VIN_PWM L26 Chock 1.2uH 12V_POWER
C296 C83 EC36 C373
1
12V_POWER R352 2.2 C322 1 2 0.1uF
* 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
* 1500uF
16V, +/-20% * 10uF
16V, X5R, +/-10%
*
+/-5% 16V, X7R, +/-10% 7mOhm@10V C0603 C1206 CE50D100H300 C1206
2
R0805 C0603 Dummy
Q31
R355 4.7 BOOT1 R376 11K Phase1_L
+/-5% R334 0 G R0603 +/-5% C376
1
R0805 +/-5%
R0805 AOD412 * 0.1uF
16V, Y5V, +80%/-20%
Ripple Current Calculation:
*
C336 R325 10K L25 C0603
2
1
* 1uF
16V, Y5V, +80%/-20%
+/-5%
R0603 R312
VCCP
D
C0805 2.2 Choke Coil 0.4uH
Intel 2005A: IDC=85A
2
Q32 Q33 +/-5%

5.7mOhm@10V R0805
R341 0 G G Icap(85 degree)=2.55A*4*1.7=17.34A
+/-5% C271
1
R0805 AOD412 AOD412
* 1nF Icap(rms)=Iout*(D/N-D*D)1/2
S
S
50V, X7R, +/-10%
C0603 =85*(0.117/4-0.117*0.117)1/2=10.60A
14
2
5
U17
BOOT1 11 12 VIN_PWM
VCC
PVCC
BOOT1 UGATE1 R357 2.2 C337 1 2 0.1uF

Intel 2004B: IDC=101A
*
13 +/-5% 16V, X7R, +/-10% C123 EC37

D
PHASE1
1
1
PWM1 1 4
R0805 C0603
Q28 * C125
0.1uF * 4.7uF
16V, Y5V, +80%/-20%
* 1500uF
16V, +/-20%
Icap(85 degree)=2.55A*4*1.7=17.34A
PWM1 LGATE1 BOOT2 16V, Y5V, +80%/-20% C1206 CE50D100H300 R375 11K Phase2_L Icap(rms)=Iout*(D/N-D*D)1/2
2
2
BOOT2 10 9 R289 0 G C0603 R0603 +/-5% C375
BOOT2 UGATE2
1
8
+/-5%
R0805 AOD412 * 0.1uF
16V, Y5V, +80%/-20%
=101*(0.117/4-0.117*0.117)1/2=12.6A
S
B PHASE2
PGND
*
R282 10K L21 C0603
GND
2
PWM2 2 7 +/-5% VCCP
PWM2 LGATE2 R0603 R320
D
ISL6614A 2.2 Choke Coil 0.4uH

3
Q26 Q27 +/-5%

R0805
R331 0 G G
+/-5% C287
1
R0805 AOD412 AOD412
* 1nF
S
50V, X7R, +/-10%

C0603
2
VIN_PWM
12V_POWER R56 2.2 C78 1 2 0.1uF
*
+/-5% 16V, X7R, +/-10% C297 EC1

D
U1
R0805 C0603
Q16 * C84
0.1uF * 4.7uF
16V, Y5V, +80%/-20%
* 1500uF
16V, +/-20%
R50 4.7 7 2 16V, Y5V, +80%/-20% C1206 CE50D100H300 R385 11K Phase3_L
2
+/-5% PVCC BOOT R98 0 C0603 R0603 +/-5% C377

G
1
*
C71 2 1 1uF R0805

16V, Y5V, +80%/-20%
6 VCC UGATE 1 +/-5%
R0805 AOD412 * 0.1uF
16V, Y5V, +80%/-20%
S
*
C0805 PWM3 3 8 R107 10K L8 C0603
2
PWM PHASE +/-5% VCCP
4 5 R0603 R144
D
R45 GND LGATE 2.2 Choke Coil 0.4uH

499K ISL6612 Q15 Q19 +/-5%
+/-1% R0805
R0603 R110 0 G G
Dummy +/-5% C131
1
R0805 AOD412 AOD412

* 1nF
S
Close to U1 50V, X7R, +/-10%

C0603
2
VIN_PWM
12V_POWER R118 2.2 C100 1 2 0.1uF
*
+/-5% 16V, X7R, +/-10% C300 EC2

D
A
U4
R0805 C0603
Q11 * C301
0.1uF * 4.7uF
16V, Y5V, +80%/-20%
* 1500uF
16V, +/-20%
A
R93 4.7 7 2 16V, Y5V, +80%/-20% C1206 CE50D100H300 R374 11K Phase4_L
2
+/-5% PVCC BOOT R47 0 C0603 R0603 +/-5% C374

G
1
*
C95 2 1 1uF R0805

16V, Y5V, +80%/-20%
6 VCC UGATE 1 +/-5%
R0805 AOD412 * 0.1uF
16V, Y5V, +80%/-20%
S
*
C0805 PWM4 3 8 R51 10K L3 C0603
2
PWM PHASE +/-5% VCCP
4 5 R0603 R119
D
R121 GND LGATE 2.2 Choke Coil 0.4uH

499K
+/-1%
ISL6612 Q12 Q14 +/-5%
R0805
FOXCONN PCEG
R0603 R94 0 G G Title
Dummy +/-5% C106
VRD10.1 Intersil ISL6561
1
R0805 AOD412 AOD412

* 1nF
S
Close to U4 50V, X7R, +/-10% Size Document Number Rev

C0603 C 945P01 A
2

5 4 3 2 1
5 4 3 2 1
Change list Ver 0A to 0B

Schematic BOM
Item Description Page Date modified modified Comment
1 Audio: Add 10K to R449 and R401. 22 2005.6.05 YES YES
2 BITCLK: Add 10pF to C181 18 2005.6.05 YES YES
3 CLK: R71,R72,R73,R74 change from 33ohm to 27ohm, R5 change from 33ohm to
4 15ohm and R20 change from 33ohm to 10ohm. 10 2005.6.05 YES YES
D 5 USB: F5 and F6 change from 1.5A to 2.6A, 28 2005.6.05 yes yes D
6 the Q25 and Q23 change from 45N03 to AOD412. 10 2005.6.05 yes yes
7 VGA: the C246 and C247 change from 100pF to 22pF. 26 2005.6.05 yes yes
8 2004B change list for PWM
9 1.change R418 to 1.3K ohm 29 2005.6.05 yes yes
10 2.change R428 to 9.1K ohm. 29 2005.6.05 yes yes
11 3.change R439 to 56K ohm. 29 2005.6.05 yes yes
12 4.change R376,R375,R385,R374 to 11K ohm. 29 2005.6.05 yes yes
13 5.change C376,C375,C377,c374 to 0.1uf. 29 2005.6.05 yes yes
14 6.change all low-side high-side mosfet to 06N03 (12pcs):Q31,Q32,Q33,
15 Q28,Q26,Q27,Q16,Q15,Q19,Q11,Q12,Q14 29 2005.6.05 yes yes
16 7.change all mlcc in CPU socket to 22uf X5R(18 pcs):C179,C182,C187,
17 C196,C201,C205,C189,C197,C202,C207,C210,C215,C204,C208,C214,C216,C217,C220 9 2005.6.05 yes yes

18 8.change choke (TRIO)from 5 turns to 4 turns:L3,L8,L21,L25 29 2005.6.05 yes yes
19 9.R384,R383,R377,R382 to 453ohm. 29 2005.6.05 yes yes
20 10.change R352,R357,R56,R118 to 2.2ohm. 29 2005.6.05 yes yes
21 11.change R430 to 680ohm 29 2005.6.05 yes yes
22 12.add R417 to 487 ohm 29 2005.6.05 yes yes
C
23 13.add C391 to 5.6nf. 29 2005.6.05 yes yes C
24 14.remove C368,C369,C370,C371,EC11,EC26,EC31. 29,9 2005.6.05 yes yes

25 Change list for 1.8V
26 1.Add 60K ohm to R475(60.4K) 11 2005.6.05 yes yes
27 2.REMOVE: 470　F--> EC34,EC41, 15 2005.6.05 yes yes
28 3.REMOVE: 1　F--> C349,C350,C351,C353,C354,C355 15,16 2005.6.05 yes yes
29 Change list for 0.9V
30 1.REMOVE:4.7　F : --> C416,C417,C418,C466 15,16 2005.6.05 yes yes
31 2.REMOVE: 0.1　F: --> C404,C476,C478,C472,C474 15,16 2005.6.05 yes yes
32 PSU compatibility issue: Add 100Kohm to R332 24 2005.6.05 yes yes
33 For EMI ISSUE: Add 2.7K ohm to RN8,RN13,RN15,RN17 26 2005.6.07 yes yes
34 Add 33 ohm to RN12,RN14,RN16 26 2005.6.07 yes yes
35 Add 180pF to CN3,CN4,CN5,CN6 26 2005.6.07 yes yes
36 Add 220pF to C231 26 2005.6.07 yes yes
37
Add 22pF to C232,C435. 26 2005.6.08 yes yes
38 Add 0.1uF to C85,C19,C35,C184,C82 25,26 2005.6.08 yes yes

39 FAN RPM: change R454 1.3K ohm --> 5.1K ohm 25 2005.6.08 yes yes
B B
40 For 1.5V switch voltage:C131--> change 16V to 25V 2005.6.11 yes yes
41 ATX12V: change 4 pins to 5 pins 2005.6.11 yes yes
42 For PCI-E: Remove EC6,EC7 2005.6.11 yes yes
43 For 5V_dual: Add 10uF to C495,0.1uF to C494,C493;Q67 2005.6.11 yes yes
44 For 5V_dual voltage: Add 10uF to C495,0.1uF to C494,C493;Q67 2005.6.11 yes yes
45 For LAN: Add 1uF to C313 2005.6.11 yes yes
For 1394_POW_CON: Remove C142 2005.6.11 yes yes
46
For SIO: Add 0.1uF to C85 2005.6.11 yes yes
47
For change BOOT: Change C130(0.1uF) from 16V to25V 2005.6.11 yes yes
48
For PCI-E: Add 0 ohm to R52 2005.6.11 yes yes
49
50 For 2.5v_mch: Add 10uF to C497 11 2005.6.13 yes yes
A A
FOXCONN PCEG
Title
Modify List
C 945P01 A

5 4 3 2 1

52f2c Foxconn 945P01 PC Mainboard Schematics

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52f2c Foxconn 945P01 PC Mainboard Schematics

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5 4 3 2 1

Page Title of Schematic :

Date: Wednesday, July 20, 2005 Sheet 1 of 30

Prescott, Smithfield &

For Intel 2005A & Intel 2004B

PCI Express x 16 Channel A DDR2

GMCH DDR2 533/667 Channel B DDR2

Header Serial ATA

LPC I/F Intel HD Audio

Date: Monday, June 13, 2005 Sheet 2 of 30

CPU (Tejas / Prescott)

PLTRST# PCI Express x16

Date: Monday, June 13, 2005 Sheet 3 of 30

XDP 133/200 MHz Diff Pair

DDR2 2 Slots 12 Diff CLKs

PCI Express/DMI 100 MHz Diff Pair

FWH 33 MHz FWH

SIO 14 MHz Super I/O

SATA 100 MHz Diff Pair

Date: Monday, June 13, 2005 Sheet 4 of 30

1.8V +2.5V=tbdA BJT

*Power derived through filter FOXCONN PCEG

Date: Monday, June 13, 2005 Sheet 5 of 30

+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

Date: Monday, June 13, 2005 Sheet 6 of 30

ICH7 GPIO Summary FWH GPIO Summary

GPIO41 N/A N/A Not Implemented Normal JCMOS1(1-2) Default

Super I/O GPIO Summary

Date: Monday, June 13, 2005 Sheet 7 of 30

R293 62 R0603 +/-5% TESTHI_12 * 0.1uF

R270 62 R0603 +/-5% TESTHI_13 VTT16

R0603 R0603 R0603 R0603 R0603

place TCK/TDI/TMS terminations near

HTDI C0603 Dummy

Date: Saturday, August 20, 2005 Sheet 8 of 30

VCCP VCCP VCCP

Put under CPU Heat-Sink

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

6.3V, X5R, +/-20% 2

Date: Saturday, July 16, 2005 Sheet 9 of 30

to a pre_programmed under or over clock C0603 C0603 C0603 C0603

100 MHz(PCIEX) 100 MHz(SRC SATA)

PCIEX2 ICH7 BSEL TABLE 470

Dummy Dummy Dummy R0603 +/-5%

C93 C92 C86