Feedback Circuits

1
ANALYSIS OF FEEDBACK CIRCUITS
1.1 The invention of negative feedback

1.2 Properties of ideal feedback circuits
1.3 Positive and negative feedback
1.4 Real circuits with negative feedback
1.5 Evaluation of the loop gain
1.6 Iterative biasing
1.7 Calculation of input and output impedance
1.8 Ideal transfer and real transfer
1.9 Input and output dynamic
1.10 The emitter follower as a feedback circuit
The invention of negative feedback 3
1.1 THE INVENTION OF NEGATIVE FEEDBACK
The idea of negative feedback came to Harold S. Black, an american

engineer, on the morning of 2 august 1927, while he was crossing the Hudson
River on the Lackawanna boat, directed to his work in Manhattan. He was 29, and
since six years he worked at the american telephone company (that eventually
became the Bell Telephone Laboratories). Research efforts were then aimed to the
long distance telephone communication systems, with the purpose to link
efficiently the two coasts of the USA, and the USA and Europe. Many problems
were encountered, partly due to the quality of the devices employed, but mainly
because the available amplifiers were not sufficiently stable and linear, and
introduced excessive distortion in the signals. This was due to non-linearities in the
main component of the amplifier, the electron tube, which generate unwanted
harmonics in the output signal (today we can think of the exponential law in the
BJTs, or of the quadratic on in the JFETs). Moreover, the tube’s characteristics
varied with temperature and aging of the device, giving a continuous and
unpredictable drift of the amplifier performances, especially the gain. The research
of Harold S. Black was devoted to improve the characteristics of the amplifiers
employed as repeaters along the telephone lines; the ultimate scope was the
transmission of many channels on the same line over long distances. Soon he
realized that the performances required to the amplifiers were unattainable with
only marginal circuital improvements. A totally new idea was necessary. It came
on the morning of 2 august 1927, and Harold S. Black sketched on a page of the
New York Times the diagram of a feedback circuit (the same as in Fig. 1.1b), and
deduced its fundamental properties (eq. 1.1-1.4). He signed its notes at the bottom
of the page, and at the laboratory he showed it to his director, Earl C. Blessing. He
was convinced of the invention importance, and signed the page of the paper as a
witness. The idea contained in those notes was that the signal distortion could be
greatly reduced, and the amplification made reproducible with very good precision,
if the output signal were fed back to the input, inverted and summed to the applied
signal. Four days later, on 6 august, H. S. Black deduced the effects of feedback on
the input and output impedance; this was another important point, because in this
manner the amplifier’s impedance become stable and reproducible, and can be
matched to the transmission cable’s impedance. That year, on 29 December, H. S.
Black verified experimentally for the first time the properties of its circuit: by
employing the first amplifier ever with negative feedback, the distortion was
reduced by a factor 100.000 for input signals of frequencies between 4 and 45 kHz.
The patent request was submitted to the U.S. Patent Office the next year,
but it took more than 9 years for the final approval (21 December 1937, No.
2.102.171). The concept was so new and apparently contrary to the common sense
that the Patent Office didn’t believe to its effectiveness, and this was one reason for
this delay. Furthermore, the documentation for the patent was extremely long and
4 Analysis of feedback circuits
detailed (84 pages in total, with 75 figures), because the field opened by the
invention was completely new, and all the principles of amplifiers with negative
feedback were described. Harold S. Black himself wrote the most part of the
patent.
We will see that the negative feedback stabilizes the gain of a circuit,
improves its input and output impedance, reduces the distortion and optimizes the
frequency behavior. In short, it allows the design of linear circuits that are accurate
and stable, and have the desired characteristics. Today, practically every good
linear circuit is based on the feedback concept.
1.2 PROPERTIES OF IDEAL FEEDBACK CIRCUITS
Let us consider the system in Fig.1.1a, composed by an amplifier whose

behavior and characteristics (arbitrarily complex) are contained in the transfer
function A(s). In such a circuit, every modification of the parameters (due to
variations of temperature, or substitution of components) changes the circuit
performances, varying continuously its biasing point, gain, position of poles, etc.
Furthermore, non-linearities in the amplifier’s components generate unwanted
harmonics which are amplified and appear in the output signal.
These problems can be avoided if the circuit topology is changed as in Fig.1.1b, by
adding a stage with transfer function F(s), which takes the output signal, su, and
generates a signal f proportional to it. This signal is called the feedback signal and
is summed to the input signal sin in a summation node. The resulting signal
instead of sin, is now fed to the amplifier A(s). The system thus obtained is called
a feedback system, and its fundamental elements, the forward amplifier A(s) and
the feedback network F(s), form a loop, called the feedback loop.
Obviously, the presence of the feedback network changes the transfer
function so/sin of the original system. With reference to Fig.1.1b, simple node
equations give the following relations:
  sin  su  F( s) ,
su = .A(s) = ( sin + su.F(s)).A(s)
From these equations the transfer function of the feedback amplifier is readily
obtained:
su A(s) A(s)
G(s) = = = (1.1)
sin 1- A(s)F(s) 1- Gloop (s)
Properties of ideal feedback circuits 5
where the adimensional quantity Gloop(s) = A(s).F(s) is called the loop gain. From
the same equations are obtained the signal , which drives the amplifier A(s):
sin sin
= = , (1.2)
1- A(s)F(s) 1- Gloop (s)
and the feedback signal f:

sinGloop (s)
 =   A(s)  F(s) = . (1.3)
1- Gloop (s)
If Gloop>>1, the unity becomes negligible in the denominator of Eq.1.1,

and the transfer function is given with good approximation by:
su 1
G(s) =  . (1.4)
sin F(s)
Thus, when the loop gain becomes very high, the transfer function doesn’t depend
on the amplifier, but only on the feedback circuit.
In order to maintain simplicity and graduality in introducing the feedback
circuits, their frequency behavior is not considered in this chapter, and will be
delayed until Chapter 8. Therefore, from now on, unless otherwise stated, the
circuits are supposed to operate at middle frequencies, such that the decoupling
capacitors are already shorted but the circuit poles due to the devices are not yet
effective. In this range of frequency, whose jargon name is middle band, or medium
frequency, the transfer function A(s) and F(s) are independent on frequency.
1.3 NEGATIVE AND POSITIVE FEEDBACK
It is worthwhile to study Eq.1.1 in the two cases of positive and negative

sign of the Gloop, because this is of fundamental importance for the properties of the
feedback circuits.
Let us suppose that the two transfer functions A and F have opposite signs
(for instance A>0 and F<0): therefore it is Gloop<0. If a positive step signal sin is
applied to the input of this circuit (Fig.1.2a), the amplifier A gives at the output a
positive signal. This generates a feedback signal f that is negative and, when fed to
the input node, opposes to sin, and hence <sin. This kind of feedback, where the
feedback signal tends to reduce the portion of the input signal fed to amplifier, is
called negative feedback. It happens when the product AF (i.e. the Gloop) is
negative.
Now let us suppose the two blocks in the loop have a gain with the same
sign (Fig.1.2b), for instance A>0 and F>0, thus giving a Gloop>0. In this case the
s in +
 A(s) su
a)
ƒ
F(s)
s in  su
+ A(s)
b)
ƒ
F(s)
Fig. 1.2 System with negative feedback (a) and system with positive
feedback (b).
feedback signal has the same sign as the input, and adds to it (>sin). Such a circuit
is said to have positive feedback. The feedback is positive when the product A.F
(i.e. the Gloop) is positive. Note that in circuits with positive feedback and
Gloop<1,the quantity 1- Gloop is positive but less than one. The transfer function
given by Eq.1.1 is greater than the amplifier gain. If Gloop1 the system becomes
unstable, and even a small perturbation causes the output to diverge exponentially,
until some active devices exit their linear region and the system saturates, i.e. its
output variable reaches a stable value, maximum or minimum.
Eq.1.1 and following don’t seem to imply the instability of a system with
positive feedback, but it has to be taken into account that in every real system there
exists at least one reactive element, and thus a pole associated to it. If in Eq.1.1 A(s)
is substituted by A0/(1+s) and F(s) is taken as constant, it is easily verified that for
Gloop(0)=A0F>1 the pole of the circuit becomes real and positive; therefore the
response of the system to any input signal would diverge exponentially. In circuits
with positive feedback the noise itself of the electronic devices is enough to start
the instability.
Both positive and negative feedback find applications in electronics. In the

first category are found, for instance, oscillators and clock generators; in the second
one are amplifiers, shapers and filters. In the following we will consider, unless
otherwise stated, only circuits with negative feedback.
Having introduced the topology and the classification of the feedback
circuits, it is now possible to evaluate the reproducibility of the transfer function
Positive and negative feedback 7
for variations of the amplifier’s parameters. Using the scheme of H. S. Black, and
differentiating Eq.1.1 with respect to A:
dG dA 1
 . ( 7.5)
G A 1- Gloop
Thus, if Gloop<0, the higher is |Gloop| the smaller are the variations of the global
transfer G due to changes in amplifier’s transfer A(s).
Hence, in a system with negative feedback, the gain is reduced by a factor
(1-Gloop) with respect to A, but the circuits is less sensitive to the variations of A(s)
by the same factor. In Chapter 4 similar results were obtained for a single transistor
stage with the degeneration resistor on the source (emitter). It will be shown in §1.9
that this was not accidental: these stages are actually feedback circuits, where the
amplifier is merely the transistor. For a circuit with positive feedback (stable for
Gloop<1), the transfer is greater than the amplifier gain A, but more sensitive to the
variation of A(s) by the same factor (1-Gloop).
These considerations find immediate practical application. Let us suppose

that an amplifier has to be designed, with gain stability better than 0.1%. If this
circuit were made as in the open loop configuration (see Fig. 1.1a) all its
characteristics would depend critically on the parameters of transistors and passive
components, on temperature, etc. Each device has then to be selected accurately,
and its working point must be stabilized. An alternative way for the design of this
circuit is a negative feedback scheme as in Fig.1.1b. If an amplifier with gain
1000.1% is required, is much easier and less expensive to made an amplifier with
gain 510450% and employ it in a negative feedback circuit with loop gain of 500.
It has to be pointed out that the negative feedback makes the transfer
function less sensitive to changes in the amplifier A, but it hasn’t the same effect
on the variations of parameters of the feedback function F(s). In fact, after Eq.1.4,
it is precisely the function F(s) which determines the system transfer function.
Hence, the transfer is reproducible if so are the parameters of F(s). In practice this
is accomplished by employing passive components (e.g. resistors) with strict
tolerances. The amplification A(s) has only to ensure a high loop gain at the
working frequencies, even for changes in the parameters of the block A(s).
1.4 REAL CIRCUITS WITH NEGATIVE FEEDBACK
The elementary properties of the feedback circuits, so far obtained on the

basis of the block scheme in Fig.1.2, are based on the hypothesis of
unidirectionality of the circuits represented by A(s) and F(s). Thus, it is supposed
that in each block the signals can only propagate from the input to the output,
following the feedback direction in the loop. Unfortunately, this is usually not the
case, because the feedback circuit F(s) is often a resistor network, then intrinsically
bi-directional. Moreover, in a real circuit it is difficult to identify the transfer
functions A(s) and F(s): too often the elements grouped in the feedback block F(s)
establish even the parameters of A(s), and reciprocally. Hence for the analysis of
feedback circuits a more specific method is needed.
Let us begin with the circuit of Fig.1.3, made with an operational amplifier
A with a very high gain, at whose input a positive voltage signal is applied. If the
input impedance of the amplifier is much higher than the output impedance R of
the signal generator (as usually happens), the signal vin can be thought as applied to
the non-inverting input, then increasing the voltage which drives the amplifier. This
causes an increase in the output voltage that, in turn, is brought back by the resistor
R2 to R1 where it appears as a positive signal vf. It opposes to the increase of v
initially given by the input signal. The circuit has a negative feedback, because the
signal that drives the operational amplifier is given by the input minus the feedback
signal. The feedback tends to reduce the driving signal, hence is named negative.
The summing node of Fig.1.1b is here made by the input loop.
The limits are reached when the driving signal v of the operational
amplifier is infinitesimal, i.e. when the signal vf brought back by the feedback loop
to the input is equal to the applied signal vin. From Eq.1.2 and 1.3 this happens
when the loop gain Gloop tends to infinite and hence v0. This means (Fig.1.4) that
the input signal is applied practically unchanged to the non-inverting input of the
operational amplifier; hence vƒ=vin. Now the current signal in R1, given by
vƒ/R1=vin/R1, flows in R2 and the output voltage vo referred to the ground is:
R   R1
v u  v in . (7.6)
R1
R
+ vu
v in v A
-
vƒ R2
R1
Fig. 1.3 Feedback circuit with operational amplifier. The higher is G loop the
closer to vin is vf.
Real circuits with negative feedback 9
R v in
+ vu
v in 0 A
-
R2
v in R1
i = vin /R 1
Fig. 1.4 Behavior of the feedback amplifier of Fig.1.3 for an infinite G loop,
corresponding to an infinite differential gain A of the operational
amplifier.
The circuit of Fig.1.3 is then a voltage amplifier whose gain, after the (1.4), doesn’t
depend on the parameters of the forward amplifier (namely the gain A of the
opamp) but only on the external resistors R1 and R2 that make up the feedback
network.
It is interesting to note how simple topological modifications of the circuit

in Fig.1.3 can result in circuits with completely different characteristics. For
instance, let us consider the circuit of Fig.1.5, different from the former in having
the signal applied to resistor R1 instead to R, which is now grounded. A fraction of
the signal vin is now applied to the inverting input of the opamp; the other input is
tied to the ground because no current can flow in R, and hence that fraction of vin is
the entire signal v applied between the two opamp’s inputs. This signal decreases
the potential of the output node and, in turn, through resistors R1 and R2, produces a
decrease in the potential of the inverting input. This opposes to the original
increase of that potential. Then in this circuit too, the feedback aims to reduce the
voltage v (which drives the amplifying stage) with respect to the value it had: the
feedback is then negative. The summing node is the inverting input of the opamp.
R
0
+ vu
v A
-
1
v in R1
R2
Fig. 1.5 Feedback circuit where a virtual ground originates.

In the limit of infinite loop gain, the signal v approaches zero (Fig.1.6). Because
the non-inverting input is grounded and v is infinitesimal, the potential of the
inverting input tends to be constant. The applied signal vin causes a current
injection through R1, given by:
v in
i in 
R1
which will driven through R2 by the decrease of the output voltage. The potential
drop across R2 is equal to the variation vo of the output voltage, because the
potential of the inverting input is held constant. Hence:
v u  i in R 2
and the voltage gain of the circuit turns out to be, in our hypothesis of Gloop,
R
G (1.7)
R1
Even in this case the transfer function of the feedback circuit doesn’t depend on the
characteristics of the forward amplifier, but only on the elements of the feedback
loop. The node (1) is called a virtual ground node. This name emphasizes the fact
that the potential of node (1) doesn’t change, whatever current is injected into it;
the node behaves like a ground, but unlike a real ground it doesn’t drain the current,
which is instead available over a parallel path: the feedback loop.
R
0
+ vu
v 0 A
-
1
v in R1
iin = vin /R 1
R2
v = iin R 2
Fig. 1.6 Behavior of the feedback amplifier of Fig.1.5 for an infinite Gloop.
These first simple considerations introduced us to the analysis of the

feedback circuits, and show how is it possible to quickly understand the
fundamental characteristics of a circuit. It may be doubted that this method is
effective only for simple circuits; let then us apply it for a circuit apparently more
complex, such the one of Fig.1.7 in which the circuit response is required for a
positive voltage signal applied to the input.
+V
R2
-A vu
v in 1
v be = v
2
vƒ Rƒ
R1
-V
Fig. 1.7 Example of voltage amplifier with feedback.
The fraction of the input signal which increases the Base-Emitter voltage
generates an increase in the transistor current, and hence a reduction of the
Collector potential. By the inverting gain stage (-A) a positive variation of the
output potential is obtained, which, through resistor Rf, is applied across R1 and
generates a positive signal vf. The circuit has a feedback, because a fraction of the
output is brought back and summed (algebraically) to the input signal vin. This sum
happens along the input path. Particularly, the feedback signal vf opposes to the
increase of vbe initially produced by the input signal. Indeed, the feedback signal
subtracts from the input in establishing the effective Base-Emitter voltage of the
transistor, which is the driving signal  of the amplifier. Because the feedback tends
to reduce the driving signal, it is negative. In this sort of analysis it is important to
walk through the feedback loop in the right direction, namely the one which
encounters first the forward amplifier, and then the feedback network. The input
path is the summing node in Fig.1.1b. The limit situation is reached when vbe, the
driving signal of the transistor, becomes infinitesimal, i.e. when the signal vƒ, fed
back to the input by the feedback network, balances the signal vin. After eq. (1.2)
and (1.3) this happens for Gloop.
The requirement vbe=v0 implies that no current flows through the impedance
existing between the nodes (1) and (2); then the current signals in the Base and in
the Emitter are both infinitesimal.
This has two effects (Fig.1.8): first, the input signal is brought, virtually unchanged,
to the node (2) and thus vƒ=vin. Second, the current signal in R1, vƒ/R1=vin/R1,
flows almost entirely through Rƒ. The output voltage vu, referred to the ground, is
then given by:
R   R1
v u  v in . (7.8)
R1
It has to be observed that, after eq. (1.4), the amplification doesn’t depend on the
parameters of the forward amplifier (gm and  of the transistor, A of the amplifier)
but only on the external resistors Rƒ and R1 of the feedback network.
The signal current which flows into the Base of the transistor is now reduced by the
feedback, and hence the input impedance (given by the ratio between the applied
voltage vin and the current thus absorbed by the same node) of the feedback
amplifier tends to be much higher than for the same circuit without feedback. In the
limit of Gloop the Base current vanishes, and the input impedance becomes
infinite. A circuit of this kind is useful for building a voltage amplifier that doesn’t
load its driving stage. In §1.7 methods will be given for obtaining the exact
expression of the impedance in real circuits, where Gloop is finite.
In this case too, simple modifications bring to a circuit with completely
different characteristics. The circuit of Fig.1.9 differs from the former in having the
output signal applied directly to the transistor Base by Rƒ, instead to the Emitter by
the resistors Rƒ and R1, and having now a non-inverting amplifier (still with gain
A).
+V
R2
A vu
i in i
1
v be
iƒ Rƒ
Fig. 1.9 Example of feedback circuit with virtual ground at the input.
Let now inject into the input node, as the driving signal, a current step i in. The
fraction of iin which flows into the transistor Base increases the voltage vbe. Being
the Emitter grounded, the increase in vbe produces an increase of the Base potential
and then a decrease of the Collector potential and, after the noninverting amplifier
A, a decrease in the output potential. This variation draws, through the resistor Rƒ,
a fraction of the signal current iin and produces a reduction of the potential at node
(1) which opposes to its original increase. Thus, even in this circuit the feedback
tends to reduce the voltage vbe, which drives the amplifying stage, with respect to
the value it had before the feedback action: the feedback is then negative. The
current summing node is now the node (1), where both the input current signal and
the feedback current come together, giving rise to the current which drives the Base
of the transistor.
It has to be noticed how the most part of the input current signal flows
through the feedback path, drawn by the decrease in the output potential. In the
limit of infinite loop gain the current flowing into the Base vanishes, and all the
current signal iin flows into the feedback path, iƒ=iin (Fig.1.10). At the same time,
the variation of the voltage vbe tends to vanish as well.
1 i = 0
i in
vu
v be = 0
Rƒ
v = iin R ƒ
Fig. 1.10 Behavior of the circuit in Fig.1.9 for Gloop .
Differently from what happened for the circuit of Fig.1.7, now the Emitter is
grounded, and when vbe becomes infinitesimal the potential of the Base node tends
to become constant too: this node becomes a virtual ground. In the limit of infinite
loop gain, the variation of the output voltage with respect to the ground is then
given by:
vu = - iin Rƒ . (1.9)
In this case too, the transfer function of the feedback circuit doesn’t depend on the
characteristics of the gain stage, but only on the elements of the feedback network.
The input impedance of the circuit, given by the ratio between the potential
variation at node (1) and the injected current iin, tends to decrease for increasingly
higher loop gains, and to vanish in the limit.
Thanks to it low input impedance, this circuit is typically employed as input stage
in current amplifiers, or in transimpedance amplifier.
E 1.1 For the feedback circuit of the following figure:

a) obtain the biasing currents;
b) describe qualitatively its operation when a positive voltage step is
applied at the input, and calculate the gain between input and output
in the hypothesis of infinite Gloop;
c) evaluate, for the same hypothesis, the input resistance.
+12V
R3 700
R1 24k  = 400
T2
T1
+ Rƒ
v in v vu
R2 24k 47k
R4 5.3k 4m A .
-6V
-12V
(a) - Having the transistors a high  the base currents can be neglected in a first
estimate. The voltage drop of 0.7V across R3 produces a current I31mA. In the
same manner, across R4 there is a voltage drop of 5.3V and then I4=1mA as well.
Through Rf wouldn’t flow any current, and hence Vu=-0.7V. Taking into account
the finite  of the transistors, a current of 12.5A is found in Rƒ and the potential
at the output node is Vu=-1.29V. The current T2 is still about 4mA.
(b) - Let us first verify that the circuit has a negative feedback. The sign of the
feedback and its loop are found in the same manner shown for the circuit of
Fig.1.1. Let us suppose to apply a positive voltage signal at the circuit with the
generator vin. The increase in vbe produces an increase in Collector current; the
Collector potential of T1 decreases and therefore the potential at the Collector of
T2 increases. This variation (positive) is brought back to R4 by the Rƒ and
opposes to the original increase in the driving voltage vbe of the first transistor.
The system has indeed a negative feedback, because the feedback tends to reduce
the fraction of the signal vin which drives the amplifying circuit. It is easy to
verify that if the opposite direction was erroneously chosen for walking along the
loop, it would have been impossible to come back to the input, due to the
amplifying stage (T1 and T2) which is effectively unidirectional, at least at
medium frequencies and in the hypothesis of neglecting ro.
If the circuit had an infinite loop gain, after (1.2) it would be v be=0 and the signal
across R4 would be equal to the applied signal vin. Moreover, the variation of the
Emitter current of T1 would be infinitesimal. Hence, the current vin/R4 would
flow entirely into Rf and the voltage across it would be vinRf/R4. The total
variation of the output potential, referred to the ground, would be given by
vout=vin(1+Rf/R4). The circuit is therefore a voltage amplifier, whose gain tends,
for an increasingly higher loop gain, to G=1+Rf/R4=+9.9.
(c) - For what regards the input impedance, it has to be noted that the feedback
reduces the vbe (and hence the current flowing into the Base of T 1) to an
infinitesimal, even if the applied signal vin is finite. The feedback tends then to
increase the input impedance of the circuit. In the limit of ideal feedback the
input impedance becomes infinite. Note that the feedback reduces only the
current flowing into the Base of T 1; it doesn’t change the current flowing into the
biasing voltage divider (R1//R2=12k). The feedback hasn’t any effect on the
impedance of this divider, which then sets a limit on the maximum input
impedance of the circuit.
E 1.2 Consider the circuit in the following figure: at its input a sinusoidal
current signal is applied, with an amplitude of 0.1mA and a frequency of
10kHz.
a) calculate the biasing of the circuit;
b) describe its behavior and obtain the output signal assuming an ideal
feedback (Gloop);
c) describe qualitatively how the input impedance changes by varying the
value of Gloop.
+6
RC 5.3k  = 100
Rƒ
vu
1k
i in
(a) - Neglecting the Base current of the transistor, the biasing voltages and
currents are immediately found: Vu=0.7V and IC=1mA. It is easy to check that a
Base current of 10A changes the value of Vu by only 10mV. For a comparison,
the Kirchoff equations for the circuit can be solved, in order to verify that the
difference between the approximate and the exact solution (which takes into
account the IB) are negligible. An iterative method for evaluate the biasing is
explained in § 1.6.
(b) - It is immediately verified that the circuit has a negative feedback. Indeed,
let us apply a positive current step to the input; it is initially divided into the two
paths afferent to the input node, in relationship to their impedances: /gm for the
path entering the transistor Base, and Rƒ+RC for the other. The signal into the
base produces an increase in vbe and hence a decrease in the Collector potential.
The feedback network brings this negative signal back to the input, with the
same sign and attenuated by the partition between Rƒ and /gm. The circuit
opposes to the original increase in the potential at the input node with an
opposite signal coming from the feedback network, then reducing the signal v be
which drives the amplifier. The feedback is indeed negative, and the input node
is a virtual ground whose potential changes negligibly even for the injection of a
current iin.
It is useful to analyze the circuit behavior by looking at the currents. From this
point of view the application of a current signal into the Base, produces a  times
greater current signal in the Collector. This divides partially into Rc and partially
into the feedback, accordingly to the impedances of these two paths. This way, a
part of the current signal injected at the input flows through Rf and the Base
current is reduced. The greater the transistor  and the higher Rc if compared to
(Rƒ+/gm), the more current will be drawn by the feedback path. It will be
shown that the loop gain of the circuit is proportional to the product RC.
The variation of the output potential can be evaluated by noting that the potential
across Rƒ varies. Hence vu-iinRƒ. This circuit is a simple transresistance
amplifier, because it changes the current signal at the input in a voltage signal at
the output, proportional to Rƒ. For the sinusoidal 0.1mA input, the output is a
sinusoidal voltage signal, with the same frequency and 0.1V amplitude, but 180
degree out of phase.
(c) - The potential at the input node tends to stay constant, whatever current is
injected, and thus the input impedance (viewed between the input node and the
ground) tends to be small; the higher the Gloop, the smaller the input impedance.
This circuit is a good detector for the current possibly coming from a previous
stage.
E 1.3 For the circuit in the following figure, employing a BJT with =300 and
a nJFET with VP=-2V and IDSS=60mA:
a) obtain the value of resistor RL necessary in order to have a dc voltage
Vu=0V at the output.
b) describe its behavior when a signal is applied, and calculate its
transfer functions vu/vin and iu/iin for the hypothesis of Gloop,
c) with this hypothesis, estimate the input resistance.
+10V
RD 200
Rƒ
3V
115
i in Rs
T1 T2
+ 70 iu
v in
IG RG vu
10mA 40k RL
-5V
(a) - The resistor RG represents the resistance of the current generator I=10mA.
Without signal, the BJT is biased in active region, the Emitter potential is +0.7V
and the current generator I enforces a Collector current of at least 10mA.
Moreover, through resistor Rs a current of 10 mA flows into the ground. The sum
of these two currents comes from the feedback network. The potential of the
JFET Drain is then given by 0.7V+20mAR=3V. The power rail supplies,
through RD, 35mA, and 15mA flow into the JFET, whose driving voltage has
then to be VGS=-1V. In order to have Vu=0V, an RL=333 has to be chosen. The
Gate potential is VG=-1V and the current in RG is 0.1mA. This value should be
added to the 10mA before estimated for the Collector current, but this refinement
would change the calculated bias only by less than 1%. This correction is safely
negligible.
+10V
RD 200
Rƒ 3V
115
Rs
T1 T2
+ 70 A
v in = 0
IG RG Vu = 0
10mA 40k RL
-5V
(b) - The sign of the feedback can be found by applying a positive voltage signal
vin at the input. The voltage of the node A has a positive variation as well,
although less than vin because the partition between the resistor Rs and the
resistance viewed from A to the ground (1/g m||(Rƒ+RD)). This change in the
potential at A corresponds to the signal vbe and produces an increase in the BJT
current, which can only flow into RG then increasing the Gate potential. The
current of the JFET increases and its Drain potential decreases. This variation is
brought back to the node A by the feedback network, with the same sign and
attenuated by the partition between Rƒ and (Rs||1/gm). The circuit tends to
counter the original increase in the potential at node A, with an opposite signal
coming from the feedback network. The feedback is negative. When the loop
gain is infinite, the feedback signal cancels out exactly the initial change in the
potential of A, and vbe is infinitesimal. The node A is a virtual ground. Being
vA0, a signal vin produces a current iin=vin/Rs which cannot flow into the BJT
because vbe=vA0, and is then entirely drawn into the feedback resistor. The
voltage drop across Rƒ is iin.Rƒ and corresponds to a change in the Drain
potential given by:
v in
v d  i in  R    R .
Rs
The current balance at the Drain requires a current flowing into the JFET of:
v v R
i u  i in  d  in (1  ) ,
RD Rs RD
this is the current supplied to the load RL (shown as iu in the figure).

As will be shown in Exercise E1.8, and in the hypothesis of G loop, this

corresponds to a resistance RG which diverges, so that even the infinitesimal
current signal injected into the BJT Emitter is enough for producing the finite
variation required by the Gate potential.
RD
i in R ƒ i in R ƒ
RD
i in vin
vA
iu
RL
As a result, in the hypothesis of Gloop, the transfer function between the

injected current iin and the current iu is:
iu R
1  158
. .
i in RD
If the voltage signals vin=iin.Rs and vu=iu.RL are instead required, it is found that:
vu RL R
 (1  )  7.5 .
v in R s RD
(c) - Because the potential at node A tends to stay constant, the input resistance of
the circuit, as viewed from the voltage signal generator, is only made by the
resistor Rs=70.
E 1.4 In order to increase the voltage gain of the circuit of exercise E1.3, the
value of resistor RL could be increased, or it can be replaced by an ideal
current generator with value 15mA. Discuss this choice by inspecting the
behavior of the such modified circuit.
+10V
RD 200
Rƒ
115
i in Rs
T1 T2
+ 70 iu
v in
vu
IG RG
10mA 40k IL 15m A
-5V
This idea is wrong, because this way the feedback is removed. Indeed, the
current generator IL sets the current into the JFET and hence the voltage signal at
its Gate cannot change the VGS (and then the ID). The Source potential follows
the Gate variations, but the current of the JFET doesn’t change. The Drain
potential doesn’t change and cannot then draw more current through R ƒ. On the
contrary, when a positive signal is applied to the input, a positive change is
obtained in the Emitter and the Drain potentials (this latter due to the partition
between RD and R). The input doesn’t receive any information on the signal at
the output node; should the loop gain be calculated (see exercise E1.8) the value
Gloop=0 would be obtained. Neglecting (RD+R) if compared to 1/gm, the signal
current flowing into the BJT is given by vin/(Rs+1/gm) and the output potential
variation vu is vinRG/(Rs+1/gm).
E 1.5 For the circuit in the following figure, whose MOSFETs have
|k|=1.25mA/V2 and |VT|=1V:
a) calculate the biasing;
b) explain why the feedback is connected between the point 1 and V1
and not between 1 and V2;
c) evaluate the gain between vin. and v1 for the hypothesis of infinite loop
gain;
+10V
10mA
5k RC 5k
T2
Ri
T1 V1
+ 1k V2
vin
1k RL 1k
1mA
-5V
(a) - Assuming a balanced differential pair T 1, into each transistor flows a current
of 0.5mA, the Drains are at +1.5V and the Sources at -1.6V. The pair T2 is then
also balanced, with a current of 5mA in each transistor. The potential V 1 is 0V,
like the input potential without applied signal (thus confirming the balancedness
of the pair T1). Note that along the loop there aren’t decoupling capacitors: the
feedback is then present even for DC. Therefore, should an unbalanced pair T 1 be
assumed, it would soon be realized that the circuit tends to restore the balance.
Let us assume that for T1 the Gate potential of the left transistor is higher than the
one of the right transistor. The current flowing into the left T1 transistor would be
greater than the one flowing into the right transistor, and the potential of the left
Drain would be lower. This way, the pair T 2 is such biased that more current
would flow into its right transistor. The resulting V1 potential would be greater
than 0V, thus opposing to the original unbalance of the pair T 1.
(b) - The signal behavior of the circuit is the same as the one just described for
the bias. Indeed, suppose that a positive voltage signal is applied to the input; it
produces initially an increase of the differential voltage between the two Gates of
T1. Specifically, the Vgs of the left T1 transistor increases (and so does its current)
and at the same time the Vgs and the current of the right transistor decrease. Being
the load resistors at the Drains of the JFETs identical, a purely differential signal
is obtained, whose action on the T 2 pair is such to increase the current in the T 2
right transistor and to decrease the current in the left one. The resulting positive
potential variation at the output V1 is sent to the Gate of the right transistor in the
input pair, then opposing to the original differential signal applied to the pair T 1.
In the limit, the variation of V1 will be equal to the original differential signal,
such to cancel it out. The feedback is then negative.
If the loop is closed by connecting the output V2 to the input Gate, a
circuit with positive feedback is obtained. In fact, the signal brought back to the
input along the loop would increase the original unbalance due to the input signal.
(c) - If the loop gain of the circuit is very high, the voltage gain tends to be unity.
This happens because the feedback tends to make infinitesimal the driving
differential voltage at the Gates of pair T 1; hence every variation of the potential
at the left Gate of T1 (which is the circuit input) is balanced by an identical
variation of the potential at the right Gate (which is connected to the output). It is
then v1=vin and the circuit voltage gain is equal to one.
E 1.6 Analyze the behavior of the following circuit, obtained from the one in the
previous exercise by adding the resistor Rƒ=1k.
+10V
10mA
5k RC 5k
T2
V1
Rf 1k
Ri
T1
+ 1k
v in
1k RL 1k
1mA
-5V
The bias is identical to the previous circuit, except for the DC value of the output
potential, which is now V1=+5V. The working principle is still the same, apart
from the fact that the Gate of the right T 1 transistor is no more directly tied to the
output, but instead through the divider RL-Rƒ. Hence, if the loop gain is very high,
the differential voltage across the pair T1 is infinitesimal, and the potential
variation over RL is equal to vin. This produces in RL a current vin/RL which cannot
flow into the Gate of the right T 1 transistor, and hence flows entirely into R . The
variation of the output potential is then given by:
RL  R
v1  v in  .
RL
Therefore the voltage gain is equal to 2.
1.5 EVALUATION OF THE LOOP GAIN
The loop gain, Gloop, is the characteristic quantity of a feedback loop, and
its evaluation is one of the most important steps in the analysis of a circuit. After its
definition, introduced in §1.2, the loop gain is the product of all the transfer
functions of the stages the signal encounters along the feedback loop. In order to
evaluate it on the schematic, or to measure it in the circuit, a test signal has to be
applied at a point of the loop, and the magnitude and sign have to evaluated, with
which the signal comes back to the same point after having traveled the entire loop.
In practice the following steps must be followed in order to evaluate the
loop gain (see Fig.1.11):
Rs
A(s) vu
+
v in
F(s)
Rs
A(s) vu
vƒ Z=R
F(s) .
+
vs
R
Fig. 1.11 Schematic example of feedback loop cutting for the evaluation
of the loop gain.
Evaluation of the loop gain 23
(a) - disconnect the external signal generators; namely, short the voltage
generators and open the current ones. This is because the Gloop can be
correctly evaluated if the signal traveling the loop is due only to the test
signal, and not to the superposition of the test with signals coming from
other generators;
(b) - cut the feedback loop at some point. Ideally, the loop can be cut at every
point. However, it will be shown that, at least when the loop gain evaluation
is concerned, there are points where it is more convenient to make the cut.
(c) - reconstruct before the cut the impedance viewed after it. This way
when the signal propagating along the loop comes to the cutting point, it
encounters the same impedance it would have if no cut were made.
Otherwise, the cut would perturbate substantially the circuit, and the loop
gain would be different from the real one of the feedback circuit. Remember
that the loop has to be traveled the same direction it is traveled by the signal
before the cut is made;
(d) - apply after the cut a test signal (choosing a voltage or a current signal is
a matter of convenience) and evaluate the corresponding signal (voltage or
current) which returns to the same point after having traveled the loop. The
ratio between the two currents or voltages is the required loop gain. The loop
gain is adimensional.
The test signal is to be viewed as a small signal, and therefore the circuit where it
is applied is the linearized small signal equivalent circuit, where the values of the
circuit parameters (gm, C, Cgs) are those evaluated from the bias prior to cutting
the loop. When the loop gain of a circuit is to be measured in the laboratory, care
must be taken that the cut doesn’t alter the bias currents of the circuit (in order to
not alter the working point of the nonlinear elements), and that the test generator
doesn’t alter the network when put into it (in series if it’s a voltage generator, in
parallel if it’s a current one).
In order to show the arbitrariness of the point where the cut is made and what test
generator is employed, and how all the possible choices bring to the same value of
Gloop, we will use as an example the circuit of Exercise E 1.2. After having
calculated the bias and disconnected the current signal generator, four possibilities
are obtained, graphically shown in the following figure.
RC RC
Rƒ Rƒ
s' i's
 s
Z =g v's + Z
m is
vs
a) b)
RC RC
Rƒ vs Rƒ is
+
s
s' i's
v's 
Z = R C ( R ƒ+ ) Z
gm
c) d)
(1) –The loop is cut on the transistor Base. After the cut the resistance R=/gm has
to be re-established, as viewed from the point before the cut, S’, by looking into the
transistor Base.
(1.a) - Apply a test voltage signal vs to the point S, and read the voltage at the
corresponding point S’ (Fig. a):
RC
vs gm    / g m   v s ,
RC  R   / gm
v s  RC
G loop    60 .
vs RC  R   / gm
Note how in the evaluation of Gloop it was implicitly assumed that the
bias of the nonlinear elements remained unchanged, notwithstanding the
cut. Indeed, the value of the gm was the same already obtained from the
bias calculation for the circuit with closed loop (exercise E1.2). Should
the loop gain be measured in a real circuit, after having cut the loop and
re-established the impedance viewed before the cut, the same current
should be reinstated into the transistor, as it was by closed loop.
Maintaining the bias conditions is the most critical point in the
laboratory measurements of the loop gain.
(1.b) - Apply to S a current test signal is, and read the current at the
corresponding point S’. Now the current circulating in the re-established
impedance Z has to be measured, and referred to the test signal applied
after the cut (Fig. b):
RC
is     i s ,
RC  R   / gm
i s R C
G loop    60 .
is RC  R   / gm
(2) – The loop is cut at the transistor Collector. In this case the resistance to be
restored before the cut is given by R=RC||(Rƒ+/gm).
(2.a) - Apply to S a voltage test signal vs and read the voltage at the
corresponding point S’ (Fig. c):
1 R C  (R    / g m )
vs     v s ,
R   / gm RC  R   / gm
v s  RC
G loop    60 .
vs RC  R   / gm
(2.b) - Apply to S a current test signal is and read the current flowing into the
reconstructed resistor R (Fig. d):
RC
is     i s ,
RC  R   / gm
i s R C
G loop    60 .
is RC  R   / gm
Note how in this case the reconstructed resistor R is irrelevant for the
calculation of the loop gain.
Recapitulating, if the resistance is correctly reconstructed, every choice results in

the same value of the loop gain, whose negative sign confirms that the feedback is
negative. If the loop were erroneously traveled the opposite direction, a Gloop=0
would be found, because trying to vary the Collector current has no effect on the
vbe.
In discussing the case (2.b) it was found that the reconstructed impedance
was immaterial for the loop gain calculation. This comes not to surprise, because
the cut was made after an ideal current generator (the Collector of the bipolar
transistor with r0=) and a current signal was employed for the test. Hence the
signal to be measured before the cut is the Collector current, which doesn’t depend
on the load R it flows into, thanks to the ideally infinite impedance of the Collector.
Only if the BJT had a finite Early resistance (as happens actually) the partition
between R and r0 would be present in the loop gain.
From this example a general concept can be deduced: reconstructing the
impedance is superfluous every time the cut is made after an ideal current
generator and a current test signal is adopted. Even if the loop gain doesn’t
depend on the point where the loop is cut, it is expedient, especially for complex
circuits, to cut at the points where the impedance reconstruction can be avoided (or
simplified). The practical rule suggested from the previous example can be
summarized as follows:
- if in the feedback loop there is an ideal current generator, it is convenient to cut

the loop after it;
- choose a current signal as the test signal.

In this case the impedance reconstruction is not necessary, because at the end of
the loop there is already the comparison current, independently from the
impedance connected to its generator.
It is easy to verify that all this holds as well for the dual situation:
- if in the feedback loop there is an ideal voltage generator, it is convenient to cut

the loop after it;
- choose a voltage signal as the test signal;

In this case the impedance reconstruction is not necessary, because at the end of
the loop there is already the comparison voltage, independently from the
reconstructed impedance it views.
The first situation is common in the analysis of circuits with transistors, where it
can be advantageous to cut the loop after a BJT Collector or a FET Drain. The
second choice is typical for circuits with operational amplifiers. In these devices,
which have a very low output impedance, the output can be represented with an
almost ideal Thevenin equivalent circuit. The loop can then be cut after their output
node.
E 1.7 Calculate the loop gain for the circuit of exercise E 1.1.
After having biased the circuit, the voltage signal generator must be switched off.
This way, it grounds the Base of the input transistor, and separates from the
network the two biasing resistors R1 e R2. As shown in the previous exercise, it is
convenient to open the loop on a Collector, e.g. the one of the input transistor,
and to apply a current as test signal. The loop has to be traveled clockwise. These
operations are demonstrated in the following figure.
R3
is
T2
i's
T1
Rƒ
R4
It is easily verified that:

i s R3 R4
G loop    2   87 .
is R 3   2 / g m2 R 4  1 / g m1
Such a high value for the loop gain makes the real behavior of the circuit close to
the ideal behavior described in exercise E1.1. Indeed, neglecting 1 against 87 in
equations (1.1)÷(1.3) implies errors slightly greater than 1%.
Among the many possible cutting points one of the most advantageous is the
Gate of the JFET. In this case the resistance to reconstruct before the cut is the
one viewed when looking into the Gate, which is infinite (at least in a
low-frequency analysis). The impedance reconstruction is readily made by
leaving the circuit open before the cut, without putting any finite resistance in
parallel to RG. After the injection of a voltage test signal, one has to evaluate the
voltage across RG, which returns to the cutting point after having traveled the
loop. The traveling direction (see figure) is counterclockwise: only this way the
signal goes through the transistors, from their input (vbe or vgs) to their output (ic
or id).
RD
Rƒ
Rs
T1 T2
+
vs
RG v's RL
The loop gain is then given by:

RG RD RS
G loop      66 .
1 1 1
RL  R D  R   RS RS 
g m2 g m1 g m1
The value of Gloop, much greater than one, ensures that the considerations made
for exercise E1.3 are correct, and that the results then found differ from the
actual ones by less than 2%.
When the resistor RL is replaced by a current generator (R L), as proposed in
exercise E1.4, then Gloop0 and the feedback disappears.
The loop can be opened at the Drain of the transistor connected to output V 1, and
a test current generator can be inserted as shown in the following figure.
10mA
5k RC 5k
T2
i' s
Ri is
T1
1k
1k RL 1k
1mA
It is then obtained:
i s g
G loop    R L  m1  R C  g m2  19.8 .
is 2
Note how the feedback loop is made by two wires, in the part comprised between
the two differential pairs. They are the wires that connect the Gates of pair T 2 to
the Drain resistors of pair T1 and ensure that the differential signal is collected
from the first stage and amplified by the second. If, in order to calculate G loop, we
want to open this side of the loop, both wires must be cut, the differential
impedance has to be reconstructed that is viewed by looking into the Gates of pair
T2 (in this case it is infinite), a differential signal generator must be applied
between the two Gates of T 2 and the differential signal has to be evaluated which
appears before the cut across the reconstructed differential impedance. Verify that
this approach yields the already obtained value for the G loop.
1.6 THE ITERATIVE BIASING
The bias of a feedback circuit could be ideally obtained without the need
for approximations, like neglecting the Base current in bipolar transistors. One
could view the circuit as a generic network, then writing down and solving all the
node and loop equations, inclusive of the equations for the nonlinear elements.
However, for the feedback circuit there is an alternate approach, which will be
demonstrated for the circuit of Fig.1.12.
The iterative method starts by assigning an arbitrary value to a selected
variable. This variable has to be chosen such that, after its value is set, the
remaining bias can be univocally obtained. For the circuit of Fig.1.12 the current IB
can be chosen, and set at first IB=0. The voltage VBE is assumed to be 0.7V as usual.
With these hypothesis it is found that:
IB = 0  Iƒ = 0 VU = 0 V IL = 1 mA IC = 1 mA 
IB = 20 A .
The original variable is again obtained, its two values are compared and, if
different (as in this case), the calculations are repeated starting from its new value:
+0.7V
IB
i in 10k 1  = 50
+
v in 50k IC
vu
Iƒ IL
5k
-5V
Fig. 1.12 Feedback circuit.
IB = 20 A  Iƒ = 20 A VU = - 1 V IL = 0.8 mA
IC = 0.78 mA  IB = 16 A ,
IB = 16 A  Iƒ = 16 A VU = - 0.8 V IL = 0.84 mA
IC = 0.82 mA  IB = 16.4 A .
When the last value doesn’t differ significantly from the previous iteration, the
procedure is completed. Usually one iterates until the difference between two
successive values of the variable is less than some percent.
It is important to point out some features of the iterative method. First, the
method works as long as the system is linear. At every step it must be checked that
the nonlinear devices don’t exit their linear region. In this case it is necessary to
redo the iterations starting from a different value of the variable. Furthermore, note
that in the shown example the IB was first chosen, and the other variables then
calculated but traveling the loop in the direction opposite to the feedback. Indeed,
the feedback signal Iƒ was first obtained, then the output voltage and the Collector
current and, at the end, we come back to the starting point with a new estimate for
IB. This was not fortuitous. In fact, if the estimate would advance along the loop in
the same direction as the feedback, small errors in the initial value would be
amplified, producing large fluctuations in the feedback signal If and, in turn, in
value of IB obtained from the iteration. The method converges only if the initial
estimate is already very close to the real value. By traveling the loop in the
opposite direction, the fluctuations arrive attenuated at the initial variable, and the
convergence is smooth.
Normally, in the analysis of transistor circuits it is convenient to employ as
iteration variable the Base current of a bipolar transistor (putting it equal to zero in
the first iteration), or the Gate-Source voltage of a FET, putting it first somewhere
in the middle between zero and its pinch-off voltage VP or threshold voltage VT. A
bad initial choice can drive the circuit out of their correct operating region.
Generally speaking, it is appropriate to choice the first value of the iteration
variable after a preliminary evaluation of the range of values which keep all the
nonlinear elements in their active operating region.
The iterative biasing 31
E 1.10 Calculate with the iterative method the bias of the following feedback
circuit.
+12V
R3 700
 = 100
I3
R1 24k
T2
I B2
0V T1 I C2
Iƒ Rƒ
vu
I1
47k
I5
R4 5.3k
R2 24k R1 2.4k
-6V
-12V
For the bipolar transistor it is reasonable to assume anyway VBE=0.7V. Thus

I1=I3=1mA. If initially IB2=0mA is assumed, one obtains:
IB2 = 0  Iƒ = IB2 = 0 mA Vu = - 0.7 V
I5 = 4.7 mA IC2 = 4.7 mA ,
and from here IB2=47A results. This value, different from the initial one, is the
starting value for the next iteration:
IB2 = 47 A  Iƒ = 47 A Vu = - 2.9 V
I5 = 3.8 mA IC2 = 3.75 mA ,
and the result is now IB2=37A. This new value differs from the previous by
25%. With another iteration one obtains:
IB2 = 37 A  Iƒ = 37 A Vu = - 2.4 V
I5 = 4 mA IC2 = 3.94 mA ,
whose result IB2=39A differs from the previous iteration only by 5%. If this
precision is satisfactory the calculation is stopped here; otherwise other iterations
are carried out. Considering the 25% tolerances of the passive components, and
the far greater ones of the  in the transistors, it is rarely sound to push the
calculations to a great precision. In this circuit Iƒ=IB2, thus the output voltage
depends strongly on the  of T2. A higher value of  (and then of the loop gain)
would increase the bias stability. The Gloop is only -2: compare this circuit to the
one shown in exercise E1.1, whose loop gain has been calculated in exercise
E1.1.
E 1.11 For the following feedback circuit with a single JFET transistor:
a) calculate the bias;
b) describe its behavior and evaluate the gain between input and output
in the hypothesis of Gloop;
c) calculate the actual loop gain, and comment the findings of point b).
-2V
V P = +2 V
I1 R1
I DSS = - 8 mA
+ 1k Rƒ
v in vu
Iƒ 3k IL
RL 1k
-12V
(a) - The circuit can be investigated with the iterative method. The Gate voltage
can have a value between -2V<VG<0V. Choose for the first trial the mean value
VG=-1V:
VG = - 1 V  Iƒ = I1 = 1 mA Vu = - 4 V
IL = 8 mA ID = 7 mA .
From the JFET quadratic equation VGS=+0.2V is obtained, which corresponds to

VG= -1.8V. This is exploited as the new starting value:
VG = - 1.8 V  Iƒ = I1 = 1.8 mA Vu = - 1.2 V
IL = 4.8 mA ID = 3 mA ,
from here VGS=0.7V and VG=-1.3V result. Another iteration gives:

VG = - 1.3 V  Iƒ = I1 = 1.3 mA Vu = - 5.2 V
IL = 6.8 mA ID = 5.5 mA ,
The values are now VGS = 0.35V and VG = -1.65V. Note how the values oscillate
around an ideal asymptotic limit, and how the oscillations grow smaller at every
iteration. It is useful, for these situations, to estimate soon the asymptotic value
and to start from it for a new series of iterations. With VG=-1.5 one obtains:
VG = - 1.5 V  Iƒ = I1 = 1.5 mA Vu = - 6 V
IL = 6 mA ID = 4.5 mA ,
from here the exact starting value VG= -1.5V is attained. It is possible to
demonstrate that a system of node and loop balance equations arrives at the same
result. Note how for every iteration the transistor works in the saturation region,
with VGD>VP. This is the prerequisite for employing the quadratic relation
between ID and VGS. The value of the JFET transconductance is gm=6mA/V.
(b) - In order to analyze the circuit behavior, let us apply a positive voltage signal
at the input node. The signal divided between R1 and Rƒ+RL, still positive, is
applied to the JFET Gate and decreases the Drain current, and hence the output
voltage decreases. By the resistive divider Rƒ-R1 this variation is fed back to the
Gate, where it opposes to the original potential increase produced by the input
signal. The circuit has then a negative feedback. The JFET Gate tends to be a
virtual ground, the more better as the loop gain increases. For G loop the
voltage signal vin is entirely across R1 and establishes the value of the injected
current the circuit draws from the resistor Rƒ. In this limit the variation of the
output potential is given by:
v in
vu    R .
R1
The circuit is an inverting voltage amplifier, whose gain tends to G=-3. Note
how RL is immaterial for the transfer function, because vu is only established by
the voltage drop across Rƒ. The current balance at the output node is maintained
by the Drain current generated in the circuit for a small variation of its v gs
voltage (infinitesimal in the limit of Gloop).
(c) - In order to evaluate the loop gain, the circuit can be opened at the Gate, and
a voltage test signal is used. The infinite impedance viewed when looking into
the JFET Gate makes redundant (at medium frequencies) the reconstruction of
the impedance before the cut. The partition between R ƒ and R1 yields the
voltage signal returning to S':
vs
+
R1
v's
Rƒ
RL
The result is:

v s R L R1
G loop    gm    12
. .
vs R L  R   R1
With such a low loop gain a different circuit behavior is to be expected with
respect to the ideal one obtained at point b). Indeed, an analytic evaluation (e.g.
with a nodal analysis) of the transfer function yields a gain G=-1.54 instead of
the ideal value of -3.
E 1.12 Suggest how to modify the circuit of exercise E1.11 in order to improve
its loop gain.
E 1.13 In the following feedback circuit the JFETs have |IDSS|=10mA and
|VP|=2V, and the  of the BJT is 100:
a) calculate the bias;
b) outline its behavior, and evaluate the transfer function assuming an
ideal feedback;
c) calculate the actual loop gain, and discuss the validity of what
obtained at point b).
+12V
RD 890
T1 T2
vu
+5V R 10k
i in C
+0.5V
400
Rƒ -12V
20k
(a) - The circuit doesn’t permit an immediate calculation of the bias, because at
many nodes the voltage is unknown. The iterative method can be used; it is more
interesting than the solution of the circuit as a generic network with node and
loop balance equations.
Thanks to the bipolar transistor in a Cascode configuration, the Drain potential is
set to VD=+5.7V and establish a current I=1.1mA flowing into RD. Of this current
no more than 1.7mA can flow into the BJT: otherwise it would saturate (it must
be VEC>0.2V). As a consequence, the current flowing into the input JFET can be
1.1mA to 5.4mA. For the first try, let us choose a value I D=6.2mA, from which a
value of VGS=-0.425V is obtained. Note how the previous reflections have
narrowed the possible initial choices, bringing to a value possibly close to the
final one. Because no current can flow into R it must be Vu=-75mV.At this point,
after only few iterations one obtains the values of the following figure.
+12V
7.1mA
T1 ~ -1V
T2
45mV 1.1mA
6mA Vu = 45mV
+5V
i in 2.5mA
+0.5V
-12V
I=0
(b) - In the circuit structure a common Source amplifying stage can be recognized
at the input, followed by a Cascode BJT stage for reducing the Miller effect on
the first stage, and an output follower that lowers the output impedance.
Following the usual method, let us apply a positive voltage step to the input: it is
readily obtained that the circuit has a negative feedback, and that the input node
tends to be a virtual ground. It is interesting to point out that, being the input
transistor a JFET, the injected current signal would flow anyway through the
feedback resistor Rƒ, given the extremely high impedance of the Gate (at least at
medium frequency, where its capacitances can be neglected). But, without
feedback, the driving signal would change the potential of the input node. The
feedback compensates exactly this variation and freezes the Gate potential. From
here it is now easy to calculate the ideal transfer function:
v u   R f  i in   20000  i in
The circuit is then an inverting transimpedance amplifier. It reads the input

current and outputs, at low impedance, a voltage signal proportional to the
feedback resistor Rƒ.
(c) - There are many points where it is convenient to cut the loop in order to
evaluate the loop gain. Any choice gives as a result:
RD
G loop   g mF1   R C  75 .
R D  1 / g mB
Calculation of input and output impedances 37
1.7 CALCULATION OF INPUT AND OUTPUT

IMPEDANCES
In the introduction to feedback circuits and in some examples it was

already observed how the feedback changes the input and output impedances of the
circuit. In this section the method will be explained for calculating these
impedances, and the connection will be shown between the circuit topology and the
effect the feedback has on the impedances.
In order to evaluate the input and output impedances of a feedback circuit
it could be applied, as usual, a current or voltage signal generator between the input
node and the ground, after having disconnected the external driving generators. For
the circuit of exercise E1.2, for example, the input resistance could be calculated
either by using a test current signal is and evaluating the correspondent voltage
variation vs (Fig.1.13a), or the dual way (Fig.1.13b).
RC RC
Rƒ Rƒ
B B
A is
+ A
vs vs
is
a) b)
Fig. 1.13 Possible different methods for the calculation of input impedance
in the circuit of exercise E1.2. Only the choice a) maintains the
feedback active and makes its effects apparent.
Let us suppose the configuration in Fig.1.13a is employed, and obtain the

ratio vs/is by superposing the effects of the driving generator is and of the dependent
generator of the transistor Collector, ic=-gmvbe=-gmvs. If the dependent generator is
turned off, the Collector current cannot change and therefore the test signal i s is
divided at node (A) into two components i1 and i2:
R  RC  / gm
i1  i s i2  is .
R  RC   / gm R   RC   / gm
The potential variation at the Base node, due only to the current is (Fig.1.14a), is
given by:
i2 RC i2 RC
Rƒ Rƒ
B B
A A i3
vs vs
i1 i1
is is
a) b)
Fig. 1.14 Method for calculation of the input impedance for the exercise
E1.2 with feedback turned off (a) and on (b).
(R   R C )   / g m
vs  is   R 0in  i s .
R  RC   / gm
After having disconnected the generator is, we can study the effect of the
Collector dependent generator. Given a variation vs of the Base potential, this
generator draws from the Base, through Rƒ, the current:

RC
i3  g m  vs  .
(R C  R    g m )
Therefore, superposing the effects the current signal which flows through R is
(i2+i3), being (i1-i3) the variation of the Base current of the transistor (Fig. 1.14b).
Correspondingly, the total variation of the Base potential is given by:

vs   (i 1  i 3 ) .
gm
By substituting to i1 and i3 their formulations, the input resistance is obtained:
v s (R C  R  )   g m 1
R in     30  .
is RC  R    / gm   RC
1
RC  R   / gm
It is now possible to understand the meaning of the various terms. The denominator
of the second factor is easy recognized as the explicit expression of (1-Gloop),
where Gloop is the loop gain of the circuit Fig.1.14, i.e. of the circuit as it is
arranged for the input impedance calculation. In this case, the circuit has the same
0
configuration as in the example of §1.5. The first factor is instead R in . It was
already shown that this would be the input resistance if the transistor dependent
generator wouldn’t draw the current i3 through R. In other words, this is the input
resistance of the circuit with the feedback turned off. Therefore, the total input
0
resistance of the feedback circuit is given by its value R in without feedback
divided by the factor (1-Gloop). This finding agrees with the qualitative analysis of
the circuit behavior; it was repeatedly shown how the feedback opposes to
variations of the potential at node (A), which is a virtual ground node, by drawing
through R the most part of the signal is. The input impedance is then reduced, and
in the limit of Gloop it vanishes.
Now let us see what happens if a voltage generator is employed as test
generator (Fig.1.13b). The impedance is independent on what test generator is
employed, and hence the same expression is obtained. But in this case the result
cannot be described as the impedance measured with the feedback turned off,
divided by the factor (1-Gloop) of the circuit. Indeed, if the loop gain of the circuit
in Fig.1.13b is evaluated (after having disconnected the driving generator) a
Gloop=0 is found. This result is not surprising, because in the circuit of Fig.1.13b a
voltage test generator hinders the feedback. This latter opposes to changes in the
Base potential, but the driving generator forces anyway a variation in this potential
which is equal to the input signal. Formally, the obstacle the feedback encounters is
represented by the result Gloop=0.
These considerations can be summarized as follows:
(a) - In a feedback circuit, the effect of the feedback is to increase or decrease,

by a factor of (1-Gloop), the resistance viewed between the input or output
nodes if the signal doesn’t travel the loop (i.e. if the feedback is turned off).
The loop gain Gloop here mentioned is obviously the one of the circuit as it is
configured for the impedance calculation, with the test generator disconnected.
(b) - In order to represent the impedance with the noteworthy structure

mentioned in point (a), the driving test signal must not hinder the feedback,
otherwise the loop gain would trivially evaluate as Gloop=0. Therefore, if in the
impedance expression the feedback effect is to be pointed out, the test
generator cannot be equally voltage or current. The generator has to be chosen
such that the feedback loop isn’t blocked, and hence the loop gain doesn’t
vanish.
There are two advantages in following this procedure, instead to analyze the circuit
as if it were a generic electrical network. First, a crude calculation doesn’t make
apparent, until the end, what effect the feedback has on the impedance, and if this
latter increases or decreases when the loop gain increases. Second, by representing
the impedance with the structure explained in point (a) the result is rapidly
achieved, because one can go through five steps that are usually simpler and make
more sense than the crude solution of the balance equations. These five steps are:
(1) - understand, with the qualitative analysis of the circuit behavior, if the
feedback tends to increase or decrease the desired impedance;
(2) - apply to the circuit a test generator which doesn’t hinder the feedback;
(3) - evaluate the impedance obtained when the feedback is turned off;
(4) - evaluate the loop gain of the circuit as modified at point (2);
(5) - multiply or divide the impedance obtained without feedback by the factor
(1-Gloop), depending on the analysis at point (1).
With reference to Fig.1.13a, let us explain how the impedance has to be evaluated
when the feedback is turned off. For the circuit of Fig.1.13a, to turn off the
feedback means to hinder the variation of the Collector (B) potential (and the
consequent current drawn into R) when a positive driving signal vbe is applied.
Therefore, in order to discontinue the feedback loop, it is enough to ignore the
increase in the Collector current due to the driving signal. Without a current signal
at the Collector, it is easily verified that the impedance viewed from the input
toward the points at constant potential is given by /gm||(Rƒ+RC), i.e. precisely the
R 0in obtained before.
It has to be pointed out that isn’t always easy to turn off the feedback. It happens
that there isn’t a single element that, if turned off, blocks completely the signal
propagation in the feedback loop. Furthermore, the circuit can have more than one
feedback loop. In these cases, either is possible to simplify the circuit by
introducing reasonable approximations, or it is necessary to switch to more general
methods, like the flow schemes, which are outside the scope of this book.
As an additional example, let us now evaluate the output resistance of the

investigated circuit (Fig.1.15). First, the effect of the feedback on the output
impedance has to be qualitatively deduced. After having disconnected the input
signal generator, suppose to drive the output node with a voltage signal generator.
A positive variation of the voltage at node (B) induces an increase of the Base
current i2 and hence the Collector current is drawn from the node (B). The driving
generator must then supply a current higher than it would if it there weren’t the
feedback. Being the output impedance given by the ratio vs/is, a higher supplied
current implies a lower impedance. If the injected signal is a current, similar
considerations do apply. The test current is would increase the potential of the node
(B) and hence the Base current. The corresponding Collector current drawn from
node (B) reduces its potential variation. The feedback then opposes to the
variations of the voltage at node (B) and the output impedance (which is the ratio
between such variations and the injected test current) decreases.
This qualitative analysis permits to find not only in which direction the
feedback acts on the impedance, but even what kind of test generator doesn’t
hinder the feedback. Because this latter opposes to variations of the voltage at node
(B) a current test generator has to be employed in evaluating the output impedance.
In order to evaluate the resistance without feedback, R 0u , it is sufficient to
ignore the effect of the feedback, i.e. to neglect the currents at node (B) which
appear after having traveled the entire loop. In this example that means the current
drawn by the Collector, labeled i3 in Fig.1.15. When the feedback is turned off, it’s
easy to find that the resistance viewed from the node (B) to the ground is given by
vs 
R 0u   R C ||( R f  )
i1  i 2 gm
The feedback action reduces R 0u by a factor (1-Gloop), where Gloop is the loop gain
for the circuit of Fig.1.15. Also in this example the loop gain is the same as already
RC i1
Rƒ B vs
i3
i2
is
A
Fig. 1.15 Circuit for calculating the output resistance of the circuit of
figure 1.14.
calculated; the output resistance is then:

v s (R    / g m )  R C 1
Ru     35 .
is RC  R   / gm   RC
1
RC  R   / gm
As already stated at the beginning of this section, this result could be

achieved by carrying out a nodal analysis at point (B) and calculating the ratio vs/is.
In this case, for retaining a feeling of what happens in the circuit, the calculations
could be carried out via the superposition principle, separating the effects due to
the generator is from those due to the Collector. After turning off the Collector
generator, the two currents i1 and i2 are given by:
R   / gm RC
i1  i s i2  is .
RC  R   / gm RC  R   / gm
and the potential variations at the node (B) is isRC||(R+/gm)=is R 0u . The feedback
action introduces the additional:

i3   i2  vs
R   / gm
and then reduces the potential at the node (B) by the factor i3RC||(R+/gm)=i3 R 0u .
Superposing the effects and imposing the consistence of the voltage signals at node
(B) one obtains:
v s  i s  R 0u  i 3  R 0u .
It is found again the expression already obtained and elucidated for the output
resistance.
Note how in this example the feedback has stabilized the potential at both
the input and output nodes. This result can be generalized as follows: in a circuit
with negative feedback, this latter acts always in order to reduce the potential
variations at every node in the feedback loop. Especially, if an external current
generator injects a current into a node, the potential variation it produces is reduced
by a factor (1-Gloop) from the value it would have without feedback. This explains
why the feedback reduces the node impedances by a factor of (1-Gloop). Therefor,
if a low input impedance is wanted, the circuit input must be a node of the feedback
loop (it will be a virtual ground). Otherwise stated, the input summing node has to
be accomplished as the node (A) of Fig.1.13a. Similarly, if it necessary to reduce
the output impedance, the output has to be picked up from a loop node, as for the
node (B) of Fig.1.13a.
Besides the loop node potentials, the feedback stabilizes also the currents
flowing into the sides of the feedback loop. Hence, if an external generator attempts
to change the current flowing along the loop, the feedback responds by reducing
the variation by the factor (1-Gloop). As an example, this action explains the effect
of feedback on the input resistance in the circuit of Fig.1.1. The voltage generator
applied to the Base attempts to increase the Emitter (and Base) current, and the
circuit opposes to it by increasing the Emitter potential. For an applied voltage
signal, the feedback reduces the current supplied by the generator, the input
impedance of the stage increases, and is given by the resistance without feedback
multiplied by the usual factor (1-Gloop).
It remains now to be explained what happens if the input or output of the
circuit aren’t directly taken from a loop node. Let us suppose to have a resistor R in
series to the node (B) (Fig.1.16). It is obvious that the feedback hasn’t any effect on
it. Indeed, for Gloop vanishes only the resistance between the node (B) and
ground. Resistor R is simply connected in series to it.
In these situations, for a correct evaluation of the impedances, it is
necessary to recognize the feedback loop and to separate this part of the circuit
from the other elements connected in series or parallel to it (Fig.1.17a). At this
point, the input impedance of the feedback part (Fig.1.17b) is to be evaluated with
the before explained procedure. The loop gain which reduces or increases the
impedance of the feedback part is the one pertaining to the circuit arranged for the
impedance calculation (Fig.1.17b), i.e. possibly without the external circuit
elements. This circuit can differ from the one already employed in calculating the
overall transfer function.
R tot
RC R tot B R vs
Rƒ R vs
B Ru is
is
Fig. 1.16 Example of resistor put in series to the feedback loop. The total
resistance viewed from the test generator is the sum of R and the R u
of the feedback circuit: Rtot=R+Ru.
R2 R5 R5
R1 R4
vs R3
a) b)
Fig. 1.17 a) In this circuit the part with the feedback is enclosed in the box.
The total impedance viewed from the driving generator is
R1+[R2//R3//(R4+R5)]; b) the impedance of the feedback part R5 is
evaluated after having insulated the loop from the other elements
connected to it in series or parallel.
E 1.14 Calculate the input and output resistances of the circuit of exercise E1.1.
Input resistance
The input resistance is given by the parallel among R1, R2 and the resistance
viewed between the T1 Base and the ground. This happens because only the
transistor T1 belongs to the feedback loop. The divider R1, R2 is then
disconnected from the circuit, and the resistance viewed into the T 1 Base is
evaluated taking into account the feedback action. A voltage test generator has to
be employed in order to allow the feedback action; a current generator would
impose a constant current into the BJT Collector, thus in a side of the feedback
loop.
R3 700
T2
is
T1
+ Rƒ
vs ve
47k
R4 5.3k
In this circuit, as in the one of Fig.1.7, the feedback opposes to changes in the
driving T1 voltage vbe. In fact, for a positive driving voltage vs, the Collector
potential of T2 increases and this variation is fed to the Emitter of T 1 through R.
The reduction in the vbe voltage of T1 implies a reduction in the signal current
entering the Base of T1. The feedback tends to increase the input impedance of
the circuit.
0
In order to evaluate the input resistance without feedback, R in , the feedback
effect has to be ignored, then neglecting the fact that the current signal from the
T1 Collector travels the entire loop and comes back to the T 1 Emitter. Therefore,
0
R in is given by the resistive components crossed by the signal current when the
feedback action is frozen. They are outlined in the following figure.
R3
is
+ Rƒ
vs
R4
R 0in  1  R 4  1 g m1
here (1+1) was approximated with 1. In this expression the resistor Rƒ doesn’t
appear, because it is connected to the Collector of T2, whose resistance is here
assumed to be infinite.
The loop gain has now to be calculated, for the circuit as configured for the
impedance calculation. Fortuitously, this Gloop is the same already calculated in
0
exercise E1.7 for the transfer function vu/vin. Therefore, by multiplying R in by
(1-Gloop), one obtains the resistance viewed by looking into the T 1 base when the
feedback is active.
1 R3 R4
R in  (  1  R 4 )  (1  2 )  187M .
g m1 R 3   2 g m2 R 4  1 g m1
The total input resistance is then the parallel among R, R1 and R2; its value is:
R Tin  R in || R1 || R 2  12k .
Being Rin much higher than the two biasing resistors, the actual value of the
circuit input resistance is limited by these latter. In such cases, the high input
impedance of the feedback circuit can be fully exploited only by choosing high
values for the R1 and R2, consistently with the biasing needs.
Now, as an example let us obtain analytically the input resistance. With
reference to the following figure an equation can be written:
vs  ve
 is .
1 g m1
R3 R3
is is
vs i1 =  1·is vs i1 = 1·is
ve' ve
R3
Rƒ i2= 1·i s··

2
R4 R4 R3 + 2
gm2
i1+ i2
a) b)
When the feedback is still turned off (Fig. a), i.e. when the current of T 1 is
forbidden to travel the entire loop, the current flowing R4 is:
i 1  i s  1 .
On the other side, the feedback current is (Fig. b):

R3
i 2  i s  1   2  .
R 3   2 g m2
Hence, the total variation of the Emitter potential is given by:

R3
v e  ( i 1  i 2 )  R 4  i s  1  R 4  i s  1   2  R 4 .
R 3   2 g m2
By inserting this expression into the starting equation, one finds the resistance
viewed between the T1 Base and the ground when the feedback is active. It is
easily verified that the result is the same as obtained before, with the concise
method.
As an additional checking, the input resistance could be calculated by
resolving the system of balance equations for the nodes and loops. Note that so
far (and in the loop gain calculations of exercise E1.7), the factor 1 has been
always neglected if compared to . Hence, in order to have an identical
comparison between the two expressions it has to be taken into account that:
R 0in  1 g m  (1  1 )  R 4 ,
R3 R4 1
G loop    2   .
R 3   2 / g m2 1 1 (1  1 )
R4 
g m1 (1  1 )
Output resistance
The output of the circuit is directly connected to a node of the feedback loop.
Thanks to the feedback, we expect an output resistance lower than it would be
without feedback. For its calculation, it is convenient to choose a current
generator, because it doesn’t oppose to the stabilization in the potential of the
output node. With reference to the following figure,
R3
Rƒ vs
R4 is
it is immediately found that the output resistance without feedback (i.e. without
the current signal drawn from the T 2 Collector after having traveled the loop) is
given by:
1
R 0u  R f  ( R 4 || )  47 k .
g m1
Since the feedback tends to reduce the output resistance, this will be:
1
R   R 4 ||
R 0u g m1
Ru    530 .
(1  G loop ) R3 R4
(1  2 )
R 3   2 g m2 R 4  1 g m1
If the output resistance needs to be further reduced, the loop gain has to be
increased, for instance by adding an additional gain stage between T1 and T2.
E 1.15 Calculate the input and output resistance of the circuit of exercise E 1.3.
Input resistance
The input resistance is given by the sum of Rs and the resistance between the
virtual ground node and the ground:
Rs
R
v in R in Terra
virtuale
Let us calculate this latter independently on Rs, by applying a test current

generator (so that the feedback still works), as shown in the following figure:
RD 200
Rƒ
115
vs
T1 T2
is IG RG
10mA 40k RL 333
Without feedback the resistance between the input node and the ground is:
1
R 0in  ||( R f  R D )  2.5 .
g m1
This already small resistance is further reduced by the feedback. The loop gain of
the circuit without Rs can be obtained from the one already calculated in exercise
E1.8 by putting Rs=; it is given by:
RG RD
G loop     69 .
R L  1 g m2 R D  R f  1 g m1
The input resistance of the feedback stage is then:
R 0in
R in   36m .
1  G loop
The input resistance of the whole circuit is:
R Tin  R s  R in  70 .
This result can be confirmed by the same considerations already illustrated in the
previous example, or by a nodal analysis. In this second method, it has to be
taken into account that in the BJT analysis the factor 1 has been neglected
compared to .
Output resistance
The output resistance of the circuit is given by the parallel between R L, outside
the feedback loop, and the output resistance of the feedback stage. This latter has
to be calculated by applying a voltage generator to the output node, as shown in
the figure, so that the current in a side of the loop is not imposed:
RD 200
Rƒ
Rs 115
T1 T2
70 is
IG RG
10mA 40k +
vs
Let us suppose that a positive signal vs is applied. It would originally inject a

current gm2vs into the FET, with the shown direction. This current flows
counterclockwise into the feedback loop (see the figure); a fraction of it arrives at
the bipolar transistor Emitter, is conveyed to the Collector and increases the
potential of the JFET Gate.
RD 200
Rƒ
Rs
T1 T2
70 is
IG RG
10mA 40k +
vs
As a final effect, the feedback opposes to the variation of the Gate-Source voltage
of the JFET, and thus it opposes to a current injection into the loop. The presence
of the feedback decreases the current supplied by the generator, with respect to
the value it would have without feedback: the output impedance is then increased,
and grows higher with the loop gain.
It is interesting to note how the circuit topology is here different from the one
already investigated in the previous exercise, where the output was connected to a
node of the feedback loop. In this case isn’t the potential of the output node
which is stabilized, but the current flowing into the load resistor R L. Indeed, this
current is flowing in a side of the loop, and its stabilization which increases the
output impedance.
It’s apparent now that the feedback effect on the output impedance cannot be
demonstrated with a current test generator. This would enforce a current into the
JFET Drain (and hence in a side of the feedback loop) precluding the feedback
from opposing to it.
The resistance, without feedback, between the output node and the ground is
simply given by the resistance viewed by looking into the JFET Source:
R 0u  1 g m2  33 .
The loop gain of the circuit, without the load resistor, can be obtained from the
expression obtained in exercise E1.8 by RL=0. It is:
RD RS
G loop  g m2  R G    727 .
R D  R f  R S 1 g m1 R S  1 g m1
The resistance of the feedback stage is then given by:
R u  R 0u  (1  G loop )  24k
and the total output resistance of the circuit is:
R Tu  R L || R u  330 .
E 1.16 Calculate the input and output resistance for the circuit of exercise E1.5,
and compare their values to the ones obtained if BJTs (=100) are
employed instead of MOSFETs.
Input resistance
Although it is easily verified that the feedback tends to increase the input
resistance, no practical effects are observed because it is already extremely high,
thanks to the MOSFET Gate. The situation is different if BJTs are employed. In
this case, the input resistance is given by the sum of Ri and the resistance viewed
between the T1 Base and the ground.
10mA
5k RC 5k
T2
T1
+
v in is
1k RL 1k
1mA
This latter can be obtained, without feedback, by following the path traveled by
the current signal from the test voltage generator to the points with constant
potential. This path is shown in the figure. It is found that:
R 0in  2  g m1  R L  11k .
Upon turning on the feedback, the input resistance increases. Indeed, the current
is, originally injected by a positive test signal, travels the loop and comes back to
the input node with the opposite sign. This demonstrates how the feedback
reduces the current injected by the test voltage generator, thus increasing the
input resistance with respect to the value it has without feedback.
The loop gain of the circuit without Ri is:
RL RC
G loop    1    2  826 .
R L  2 1 g m1 R C   2 g m2
Hence, the resistance viewed between the T 1 Base and the ground is given by:
R in  R 0in  (1  G loop )  9.1M .
The total input resistance of the circuit is then:
R Tin  R i  R in  91
. M .
Output resistance
In order to evaluate the output resistance, the output node has to be tested. This
latter is a node of the loop, and hence the feedback will reduce the output
resistance. A current generator must be used for the test. For a MOSFET circuit,
the resistance viewed toward the ground without feedback is:
R 0u  R L  1k .
The loop gain is the same already calculated in exercise E1.9 and is G loop=-20.
The resistance of the feedback stage, which corresponds to the circuit output
resistance, is given by:
R 0u 1000
Ru    50 .
1  G loop 1  20
For the same circuit with BJTs a similar procedure yields the value Ru1.
E 1.17 In the following feedback circuit the JFET T1 and T2 have |VP|=1V and
|IDSS|=4mA, and T3 has |VP|=1V and |IDSS|=1mA. Furthermore, suppose
that the current generator T3 has an output resistance r0=100k
a) Calculate the circuit biasing.
b) Describe its behavior and evaluate the transfer function between input
and output assuming an ideal feedback.
c) Calculate the loop gain, and comment the result obtained at point b).
d) Calculate the input and output resistance.
+6V
R3 6.5k
2
T3 ro vu
1
T2
Rs
T1
+ 50 4
Rƒ 3
v in
2k
R1 500 R2 6.5k
-6V
(a) - It is easily verified that the biasing current is 1mA for each JFET, and the dc
potential at the output node is Vu=+2.5V.
(b) - For a voltage signal vin, the T1 Gate increases its potential, then increasing
its current. The node (1) decreases its potential, the current flowing into T 2
increases and so does the potential at node (3). This signal is brought back to the
node (4) by the feedback resistor Rƒ. The feedback signal has the same sign as
vin, thus reducing the fraction of driving signal which changes the V GS voltage
of the first transistor. The feedback is then negative, and the error signal, v, (Fig.
1.1) is the VGS voltage of T1.
If the system had an infinite loop gain, then would be v=0, and the node (4)
would increase its potential exactly by vin. The current signal in T1 would be
infinitesimal and the current through R1, given by vin/R1, would flow entirely
into Rƒ, eventually coming to the node (3). The potential variation at node (3)
would be equal to vin(1 + Rƒ/R1). It follows that the current through R2 would
be given by vin(1 + Rƒ/R1)/R2. The sum of these two currents comes from the
Drain of T2 and can drive a load at the output on the Source of T 2. Its value is
precisely given by:
1 1 R
i u  v in (   )
R1 R 2 R1R 2
This current produces an output voltage signal across R3 given by vu=-iu.R3.

This is the ideal transfer function of the circuit. By substituting the numerical
values one obtains vout/vin=-9.1.
+6V
R3
ro
i u = i1 + i 2
Rs
+ Rƒ
v in R 1+ R ƒ
i2 = vin
v in R1 R 2
R1 i1 = R
1 R2
-6V
(c) - In order to evaluate the loop gain, the circuit can be cut before the Gate of
T2, after having switched off the generator vin. Then, a test signal vs is applied
and the feedback signal vƒ is read across the r0 of T3. It is found that:
ro R2 R1
G loop      13 .
R 3  1 g m2 R 2  R f  R 1 ||1 g m1 R 1  1 g m1
(d) - At low frequencies the input resistance of the circuit is infinite, thanks to the
Gate of T1. This happens independently on the effect of feedback, which tends
anyway to increase it (the input stage topology is the same as in the circuit of
exercise E1.1).
The topology of the output resembles instead the one of exercise E1.3. Being R 3
not directly connected to a loop node, it has to be thought as in parallel to the
resistance viewed by looking into the Source. In order to retain the feedback, a
voltage test generator has to be employed, as shown in the following figure.
R3
ro
is
+
vs
Rs
Rƒ
R1 R2
After having applied the test signal vs, a current gm2vs flows through 1/gm2.
This current increases the potential of node (3), and then the one of nodes (4) and
(1), i.e. it increases the VG. The original diminution of V GS2 is then countered
by the feedback, which opposes to the variations in V GS2 due to the test signal vs.
Correspondingly the current in T 2 tends to be stabilized as well. Therefore, it can
be concluded that the variation in the T 2 current, due to vs, is less than it would
be without feedback. It can be shown, by an exact calculation, that the variation
of this current is attenuated exactly by the (1-Gloop). The loop gain Gloop can be
obtained from the one already calculated by putting R3=0 (the resistance R3 is
shorted by the test generator) and is Gloop=-200. The resistance viewed by
looking into the Source of T 2, by closed loop, is R 0u =1/gm2.(1-Gloop)=50k.
This resistance is in parallel to R3=3.5k, and these two set the total output
resistance of the circuit.
E 1.18 For the differential pair of exercise E 5.18:

a) investigate how the circuit biasing is modified if all the transistors
have an Early voltage of VA=25V.
b) Evaluate the output resistance Ro taking into account the negative
feedback due to the current mirror.
+5V
C Ru
T3 T4
vu
RL = 10k
+2V
v1 T1 T2 v2
(b) - The current mirror produces a feedback which decreases the output
resistance Ru. In fact, let us suppose to inject a current before RL. This current is
partitioned between r04 and the fraction i2 which enters T1 and T2. This latter
component comes to T3, is mirrored by T 4 and tends to decrease the output node
potential.
In order to maintain the feedback, a current test generator has to be employed.
r o3 r o4
iƒ
i1
i1 i2
is
r o1 r o2
The resistance viewed by looking into the output node without feedback is the
parallel between r04 and the resistance viewed by looking into T 2. This latter is
about 2r02. In fact, the Collector resistance of T 2 is to be found with a resistor
1/gm (due to T1) connected in series to the Source. Hence:
R 0u  r04 2r02 .
The loop gain can be evaluated as shown in the following figure, by cutting the
loop before T2 and reconstructing the impedance before the cut.
r o3 r o4
vƒ
2ro2
+
vs
r o1 r o2
By applying a voltage signal to the cutting point, a current given by v s/2r02

flows into T1 and T2. This current is mirrored by T 3, T4 and before the cut a
voltage signal is produced, which is given by:
r04
v   v s  .
2 r02  r04
Therefore, the output resistance with the feedback active is:
R 0u
Ru  r r .
1  r04  2r02  r04  02 04
E 1.19 Obtain, by using the properties of the feedback circuits, the input and
output resistances of the Wilson mirror, already calculated in exercise E
5.16.
i in
A T3 r o3
r o1 T1 T2 r o2
-V
Input resistance
The circuit has a negative feedback, and it can be easily verified that the input
node (A), on the T3 Base, is a virtual ground. In order to evaluate the loop gain,
the loop can be cut on the Collector of T1 and a current test signal has to be
employed. If the Collector resistances, r 0, of the transistor are finite, the
resistance before the cut has to be reconstructed, then obtaining the situation
shown in the following figure:
is
T3 r o3
R 2/g m
r o1 T1 T2 r o2
The effect of the finite resistances r02 and r03 can be neglected for the loop gain
evaluation, because the current signal from the T 3 emitter flows almost entirely
into the transdiode T2, whose differential resistance is only 1/gm<< r02,r03.
Furthermore, if r01>>2/gm, the signal loss due to the partition between r 01 and
2/gm is negligible as well; thus the loop gain is nearly equal to -.
The input resistance without feedback is the resistance viewed (toward the
ground) by looking into the node (A). It evaluates as about R0in  2  gm . Thus
the input resistance with feedback, reduced by the quantity (1+), is about
Rin  2 gm .
Output resistance
In order to evaluate the resistance viewed by looking into the Collector of T 3, it
has to be taken into account that the test generator (a voltage one, for instance)
must supply the current flowing into r03 and the one drawn by the transistor T 3.
i3 +
vs
A T3 r o3
vs
i' B r o3
i'
T1 T2
-V
The node (B) on the Collector of T 2 belongs to the feedback loop, and its
potential variations are then very attenuated. Furthermore, even without feedback
the resistance viewed between node (B) and ground is very low, about 1/g m.
Therefore, as a first approximation, the potential variations of the node (B) can
be neglected, and the current flowing through r 03 is about ir=vs/r03. This current
comes to the node (B), where it is partitioned. If we call i' the portion flowing
into the transdiode T2, this is the same current drawn by T 1 and (+1)i' is the
current drawn by the Emitter T 3. In order to satisfy the current balance at node
(B) it is i'=ir/(+2), and the signal current supplied from the Collector of T 3 is
given by ir/(+2). Finally, the signal current supplied by the test generator is
2ir/(+2) and the output resistance of the current mirror turns out to be about
r03/2.
Note how the topology of this circuit differs from the ones already encountered:
here there are two paths from the output into the loop, one through the Collector
of T3 and one through r03; the test generator sees the two signal combined.
Therefore it is not surprising that the output resistance isn’t given anymore by
the resistance viewed from the Collector of T 3 without feedback, about r03,
multiplied by the loop gain .
1.8 IDEAL TRANSFER AND REAL TRANSFER
Until now the transfer function between input and output has been
evaluated in the hypothesis of infinite loop gain, and after that the actual loop gain
Gloop has been calculated, sometimes finding a gain only slightly greater than one.
Although this method yields all the major characteristics of the circuit, and here
resides its importance, it cannot answer the question of what is the real transfer
function of the circuit.
The real transfer between input and output of a feedback system could be
readily obtained from (1.1), should one know the transfer function of the forward
amplifier A(s) and the loop gain Gloop(s)=A(s)F(s). But, even if the loop gain can
be accurately evaluated as explained in the previous sections, isn’t always simple to
separate in a circuit the amplifier and to calculate its transfer function A(s), because
its input and output are loaded by the feedback network. As an example, let us
consider the circuit in exercise E1.2, for convenience repeated here in Fig.1.18.
Although it is apparent to label the resistor Rf as an element of the feedback
network, and the transistor as an element of the amplifier, it is questionable if A(s)
can be evaluated simply by pulling Rƒ out of the circuit. Commonly it is very
difficult, or even impossible, to calculate the correct value of the amplifier transfer
function without the feedback network.
A different approach to the calculation of the real transfer that avoids the
problems pointed out, is based on a different formulation of equation (1.1). Upon
dividing both numerator and denominator in the (1.1) by the loop gain Gloop=AF
one obtains:
+6V
RC
Rƒ
vu
i in
Fig. 1.18 Evaluation of the real transfer for the feedback circuit of figure
1.13a.
Ideal transfer and real transfer 61
1

F(s) G id (s)
G (s)   . (7.10)
1 1
1 1
A (s)  F(s) G loop (s)
This expression emphasizes how the real transfer can be calculated once the loop
gain Gloop=AF of the real circuit and the ideal transfer Gid=-1/F are known. This
latter can be easily obtained simply assuming an infinite loop gain. Namely, for the
circuit of figure Fig.1.18 the ideal transfer is vu/iin= - Rƒ., and the loop gain, already
obtained in §1.5, is:
  RC
G loop   .
RC  R   gm
After the (1.10) the real transfer of the feedback amplifier should be given by:
vu R f
G  .
i in RC  R f   gm
1
  RC
Being the circuit of Fig.1.18 very simple, it is possible to verify this result by
writing and solving the balance equations for the nodes and the loops, without any
assumption or approximation. In this way one obtains:
RC
vu R f g m (R C  R f   g m )
G   . (7.11)
i in RC  R f   gm RC
1 1
 RC RC  R f   gm
This result differs from what is expected. Notably, the transfer evaluated after
equation (1.11) is only the first of two terms.
This discrepancy is due to the unidirectionality assumed in the transfer functions
A(s) and F(s) in the (1.1) and hence in the (1.10). The considerations based on the
blocks representation of the circuit of Fig.1.1 assume that the signal propagates
from the input to the output only through A(s), and returns to the input node only
through F(s). The signal was banned from arriving at the output even through F(s).
In practice, the feedback network is often made by resistive elements, which are
intrinsically bi-directional. In the circuit of Fig.1.18, for example, the signal iin can
directly change the output potential. Indeed, let us suppose to stop the feedback by
ignoring the current signal at the Collector, as was done in evaluating the resistance
viewed between the input node and ground without feedback. A test signal is
injected into the input is divided into two components, i1 and i2, as shown in Fig.
+6V
RC
Rƒ
v'u
i2
i1
i in
Fig. 1.19 Direct transfer in the circuit of Fig. 1.15.
1.16. Without feedback, the potential at the output increases, due to the injected
current, by a quantity:
RC   gm
v 'u  i s  .
RC  Rf   gm
This transfer is similar to the direct transfer that originates the zero with positive
real part in the common Emitter (Source) stage (see §6.3). The numerator of the
second term in (1.11) is precisely the expression of this direct transfer; the
denominator is the usual quantity (1-Gloop).
Following these considerations, the (1.11) can be explained by stating that
the real transfer of the circuit in Fig.1.15 is the sum of the transfer expected for a
perfectly unidirectional system and of the direct transfer through only the feedback
path divided by the quantity (1-Gloop):
G id (s) G diretto (s)
G (s)   . (7.12)
1 1  G loop (s)
1
G loop (s)
This result can be generalized to the analysis of feedback circuits of whatever

complexity1, and offers a simple and intuitive method for adjusting the result
obtained by applying the (1.10).
Summarizing, the real transfer of a feedback circuit can be evaluated by
following these steps:
1
The equation (1.12) is based on the sole assumption that the loop can be traveled only in
one direction and not in the opposite. This hypothesis is actually satisfied in almost every
electronic circuit which employs active components.
(a) - obtain the ideal transfer of the circuit by assuming an infinite loop gain;
(b) - cut the feedback loop and calculate the finite loop gain;
(c) - after eq. (1.12) evaluate the first member of the real transfer expression;
(d) - turn off the feedback, evaluate the direct transfer and divide it by the
quantity (1-Gloop);
(e) - sum algebraically the two quantities found in (c) and (d) to obtain eq.
(1.12).
In the normal applications the direct transfer is usually very small, and the loop
gain is sufficiently high to make the real transfer very close to the (readily
calculated) ideal one.
E 1.20 In the circuit of the following figure the bipolar transistor has =100, the
MOSFET has threshold voltage VT=1V and k=1mA/V2.
a) Evaluate the ideal transfer;
b) Calculate the real transfer, and verify that by introducing the
MOSFET in the circuit of Fig.1.18 the direct transfer is eliminated;
c) verify the same result via the balance equations.
+6V
RC 3.3k
Rƒ 1k
i in R1 6.7k
-6V
E 1.21 Confirm the real transfer of the circuit of exercise E1.11 (then obtained
analytically) by applying the concise analysis introduced in this chapter.
Gid=-3; Gloop=-1.2; the direct transfer is given by:
v'u RL
  0.2 .
vin R1  R f  R L
The real transfer is:

3 0.2
  154
.
1 1  12
.
1
12
.
The low value of the loop gain produces a real transfer significantly different
from the ideal one.
E 1.22 Evaluate the real transfer for the circuit of exercise E 1.3 emphasizing
the contribution due to the bi-directionality of the feedback network.
The ideal amplification, calculated in exercise E1.3, is given by G id=1.5. The

loop gain, calculated in exercise E1.8, is Gloop=-66. Therefore, without the direct
transfer, the real transfer would be:
7.5
G  7.39
1
1
66
The additive correction due to the direct transfer is obtained by turning off the
forward path of the circuit. It is easily verified that, being the circuit output on
the JFET Source and being r 0 of the transistor infinite, an input signal cannot
propagate directly to the output through the feedback path. In fact, the input
signal produces directly an increase in the potential of the T 2 Drain given by:
RD 1 g m1
v 'u  v in   ,
R s  ( R f  R D ) 1 g m1 ( R D  R f  1 g m1 )
but, being the Drain resistance infinite, cannot produce a current variation in T 2
and hence in the output potential. Even taking a finite r0 for T2, the contribution
of the direct transfer to the (1.10) would be very small, thanks to the low value of
1/gm1=2.5, to the high loop gain and to the voltage partition between r 0 and RL.
E 1.23 Evaluate the real transfer for the circuit of exercise E 1.1.
The ideal transfer is given by Gid=(1+R/R4)=9.9. The loop gain is Gloop=-87

(exercise E 1.7). The direct transfer is:
v 'u (  1)  R 4
G dir    0.99 .
v in  g m  (  1)  R 4
It is then obtained:
9.9 0.99
G (s)    9.8
1 1  87
1
87
In this case the contribution of the direct transfer is only 0.01 and is therefore
negligible.
E 1.24 Evaluate the real transfer for the circuit of E 1.5.
Gid=1; Gloop=-19.8 and the direct transfer is zero; therefore:

1
G (s)   0.95 .
1
1
19.8
1.9 INPUT AND OUTPUT DYNAMIC
The application of large signals to the input of a feedback circuit produces

large variations in the node potentials and loop currents. The circuit dynamic is
defined as the maximum variation of a signal just before an active device exits the
active region (entering the saturation or interdiction region for a BJT, the
interdiction region for a MOSFET, and even direct biasing the Gate-Source for a
JFET). It can be calculated, for the feedback circuits, by supposing the feedback
remains active within the dynamic, and thus the circuit behavior is the same for
both small and large signals. For example, a feedback circuit having a virtual
ground and a given input-output gain (both obtained for small signals) maintains
them even for large signals. This is because the nonlinearities produced by the
large signal are localized in the elements of the forward amplifier and, as long as
these elements work and the Gloop remains high, they do not act upon the overall
transfer function, which depends on the feedback network, assumed as ideally
linear. Therefore the analysis of the dynamic for a feedback circuit is carried out by
evaluating the range of the input signal for which the forward amplifier works
correctly. This is made assuming as a circuit gain the one found for the small signal.
In practice, a “quasi-static” analysis is carried out, increasing or decreasing the
input signal and finding what transistor exit first from the active region.
The exercise E1.28 shows instead how to analyze a feedback circuit when its loop
gain is very low.
E 1.25 Find the input and output dynamic of the circuit of exercise E1.1,
supposing that the lowest voltage across the current generator is 0.2V.
Positive dynamic. For every mV of increase in vin, the Emitter potential increases
practically by the same quantity, and the potential of the output node increases
tenfold (precisely, it becomes 9.8mV, if the real transfer is taken into account).
The Collector potential of T1 practically doesn’t change, being clamped to about
+11.3V by the Base-Emitter junction of T2. The limit to the positive dynamic is
given by the saturation of T 1 or T2. When vin=0V, the output node potential is
Vu=-0.1V, and it could rise to the maximum value of +11.8V. In the linear
approximation, this maximum swing of 11.9V corresponds to an input signal
given by 11.9V/9.8=+1.2V. In this situation, T 1 is still in the active region, so the
input dynamic of the circuit has an upper bound due to the saturation of T 2. At
the saturation edge, a current of 0.24mA would flow into R f toward the T1
emitter, the current in T 1 would be still about 1mA and the current supplied by T 2
would be 4.2mA.
Negative dynamic. Now, let us suppose to diminish the input potential;
accordingly, the potential of the T 1 Emitter and the output potential both decrease.
It is immediately evident that the dynamic isn’t limited by the transistor
saturation, but by their possible interdiction. In order to have the current
generator correctly working, the potential at the output node cannot grow smaller
than -11.8V. The negative swing of -11.7V corresponds to a decrease in the input
voltage vin given by 11.7V/9.8=-1.2V. Accordingly, the T1 Emitter potential is
-1.9V, through R a current (11.8V-1.9V)/47k=0.2mA flows, thus T 2 supplies
4mA-0.2mA=3.8mA while the current in T 1 is again about 1mA.
Concluding, the output dynamic is of -11.8V<Vu<+11.8V corresponding to a
practically symmetrical input dynamic of -1.2V<vin<+1.2V. In this circuit the
dynamic is limited by the power supplies. Note how we have assumed that, even
to the dynamic limits, the circuit maintains a Gloop sufficiently high to keep the
feedback effective.
Input and output dynamic 67
E 1.26 Obtain the input dynamic of the circuit of exercise E1.3, neglecting the
non-linearities of the active devices.
Positive dynamic. If the vin potential increases, the Emitter voltage of T 1 doesn’t
change significantly, and the injected current is mainly drawn through R f. The
Drain potential of T2 decreases of about Rf/Rs=1.6mV for every mV of increase
in vin, and the Source potential increases correspondingly of 1.5mV. The
potential of the T1 Collector (which is connected to the Gate of T 2) increases by
the same quantity. It has to be evaluated which transistor exits first the active
region, and for what value of vin (or vu) this happens. On a positive input signal
T1 enters strong saturation when its Collector goes higher than 0.5V. Recalling
that after the biasing (E1.3) it is VC=-1V for vin=0V, the allowed swing for VC is
1.5V. In the linear approximation (assuming constant transfers) this would allow
an increase in vin given by 1.5V/1.5=200mV. Let’s look what happens in the
meantime to T2. It enters the ohmic region when VDG<VP=2V. The decrease
of VDG is (1.5mV+1.6mV)=9.1mV for every mV increase in vin. Because the bias
sets VDG=4V, the permitted VDG swing of 2V allows for a vin increase of
2V/9.1=219mV. The limit is then set by T 1 entering the saturation, and the
maximum positive swing of vin is about 200mV.
Negative dynamic. When the input signal is negative, the current drawn from the
input node increases the current flowing through R . The potential increases at
the Drain and decreases at Source the Gate. The transistor T 2 moves toward
interdiction, where the VGS voltage of T2 is equal to the pinch-off voltage (-2V).
It follows that the Gate potential of T 2 can decrease from its biasing value of -1V
to no more than -5V. Accordingly, the minimum value of vin would be
-4V/1.5=-530mV. Actually, the maximum negative swing of vin would be
bounded by the operation of the biasing current generator.
Concluding, the input dynamic is -530mV<vin<200mV.
E 1.27 Found the input and output dynamic for the circuit of exercise E1.5,
assuming that the correct operation of the biasing current generators
requires at least 0.2V across them.
In order to study the stage dynamic, recall that for vin=0V the Drains of the first
differential pair T1 are at +1.5V, while the Drains of the second pair are at 0V.
The two pairs are balanced.
For positive vin signals, V1 increases and so does the current in the right branch
of the second stage. The maximum increase is when all the biasing current
I=10mA flows into the right branch; this situation corresponds to a v in=V1=+5V.
It is easily verified that this is just the dynamic limit, because the other
components still operate correctly.
When the vin potential decreases, V1 is reduced by the same quantity. The correct
operation of the biasing current generator of the first pair requires a v in greater
than -5V+0.2V+1.6V=-3.2V. The same limit holds for the swing of V1. The V2
potential changes by the same quantity as V1 but phase-shifted by 180 degrees.
Thus, the limit for V2 is +3.2V, a value still allowing a correct operation for the
T2 pair.
Concluding, the dynamic is -3.2V<vin<+5V, and is the same at input and output,
having the circuit an unity gain. We assumed again a G loop sufficiently high to
maintain the feedback effective, even at the dynamic limits.
E 1.28 Find the input and output dynamic for the circuit of exercise E1.11.
Positive dynamic. The circuit has a gain G=-1.54 and the bias sets Vu=-6V when
Vin=0; therefore one could think that the positive input dynamic is given by the
6V swing of the output to the negative supply, divided by the gain, i.e.
vin=6/1.54=+3.9V. Actually, the small loop gain produces wide fluctuations in
the FET current and in its Gate voltage as well. This latter isn’t then a good
virtual ground. When the JFET becomes interdict, the input voltage is already 0V.
The output potential vu is set by the divider R and RL and is given by Vu=-9V.
The current drawn through R is 3mA and the signal vin is only +3V.
Negative dynamic. On the other side, if the input voltage vin decreases by 1mV,
the output node increases by 1.54mV and the potential of the virtual ground
decreases by 1mV R in /(R1+ R in )=0.64mV. The VGD of the JFET decreases on
the whole by 2.18mV. In standby, for vin=0V is VGD=4.5V, where, at the limit of
the ohmic region VGD=2V. The swing allowed for VGD is of 4.5V-2V=2.5V and
corresponds to a decrease in the vin potential of about 2.5V/2.18=1.15V.
The Emitter Follower as an example of feedback circuit 69
1.9 THE EMITTER FOLLOWER AS A FEEDBACK

CIRCUIT
An interesting example of a very compact feedback circuit is the Emitter
(Source) follower. This circuit was investigated in detail in Chapter 4, and we will
refer to the results already obtained in order to make a comparison. In this section it
will studied in the framework of feedback circuits.
Let us consider the Emitter Follower shown in Fig.1.20, and its small
signal equivalent circuit. A positive voltage step applied on the Transistor Base
increases the vbe voltage, accordingly to the partition between the two resistances
/gm and RE. This produces a current signal, i=gmvbe, a part of which flows into RE
and increases the voltage vu. The circuit has then a negative feedback, and responds
to the original increase of vbe with a signal which opposes to it. In the limit of
infinite loop gain, the variation of vbe would vanish, and the signal applied to the
Base would be identical to the potential variation at the Emitter.
The loop can be recognized by noticing that a side of it is the connection between
vbe and ic hidden into the dependent current generator. The loop gain is
immediately obtained by cutting the loop after the same generator, and injecting a
current test signal, as shown in Fig.1.21. It is then found:
+V CC
vin
+
v be 
+ gm i = gmv be
vin vu
RE
RE
-V EE
Fig. 1.20 Emitter follower circuit, and its small signal equivalent circuit.
G loop   ( g m || R E )  g m .

v be
gm i s = gmvbe
RE is
Fig. 1.21 Calculation of the loop gain for the Emitter follower.
It is now interesting to obtain the real transfer of the stage. The ideal transfer
is unity, and the direct one is:
RE
G dir  .
RE   gm
Hence, similarly to the (1.9), one obtains:
vu 1 RE 1    R E
   ,
v in RE   gm    R  1    R E   g m
1
  RE  R E   g m  1  E

 RE   gm 
that agrees exactly to the expected result.

The input resistance of the Emitter follower can be obtained as for every
feedback circuit. Namely:
R in  R 0in  (1  G loop ) ,
where
R 0in   g m  R E .
After the calculations one obtains the well-known expression:
R in   g m  (  1)  R E .
Similarly, for the output resistance it is found that:
R 0u
Ru 
(1  G loop )
with
R 0u   g m || R E
The Emitter Follower as an example of feedback circuit 71
This leads to the well-known expression:

R u   g m || R E ||1 g m  R E ||1 g m .
Concluding, it is interesting to use the stage with degeneration resistance as
an example of the effects of feedback on nonlinearities and distortions. Both the
configurations of Fig.1.22 can amplify by a factor -5 a signal of 10mV. But, in the
common Emitter stage (Fig.1.22a), the 10mV signal is entirely applied across the
Base-Emitter junction, giving rise to a 23% non-linearity.
In the stage with Emitter degeneration (Fig.1.22b), the negative feedback

reduces the transistor driving voltage to only 0.16mV. In this case the voltage gain
is still the same, but the non-linearity is reduced to 0.3%. Generally speaking, in a
negative feedback system the voltage which drives the amplifier A(s) is reduced by
a factor equal to the loop gain, and hence a reduction is expected in the
nonlinearities due to the elements of A(s). A price is paid for this improvement,
and it’s, as usual, the gain which could be obtained from the amplifier. The stage
without feedback of Fig. 1.19a could amplify by -5 even with a supply voltage
reduced from +12V to +1.5V; if its Collector resistance were increased, its gain
could reach -300. The circuit with feedback requires instead a supply voltage of
+9.5V at least; or, without changing the supply, its gain can be at most -1. However,
only the feedback stages can strongly reduce the nonlinearities of the active devices
and the harmonic distortion of the signals.
+12V
+12V
7.5k
125 9.8k
1.13M vu
vu C
C
+
+ v in
vin
2.2k 1.5k
a) b)
Fig. 1.22 Non-linearity comparison at constant gain between a common

Emitter stage (a) and one with degeneration resistance (b).
E 1.31 Analyze the transfer function of an Emitter follower stage when the
driving generator has a series resistance Rg. Obtain the loop gain and the
output and input resistances, and compare them to the expected
expressions.
E 1.32 Study the transfer function of a Source follower stage by viewing it as a

feedback circuit. Calculate the loop gain and the input and output
resistances, and compare them to the expressions already obtained in
Chapter 4.
E 1.33 a) Analyze the behavior of the following circuit, and compare it to the
one of an emitter follower.
b) In order to improve its performances, which transistor of the mirror
would you choose with a greater area?
+5V
50
+
v in vu
430
-5V
E 1.34 Review in the framework of the feedback circuits the expression which
gives the resistance viewed across the VBE multiplier of exercise E5.21.

Feedback Circuits

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1

ANALYSIS OF FEEDBACK CIRCUITS

1.1 The invention of negative feedback

1.1 THE INVENTION OF NEGATIVE FEEDBACK

The idea of negative feedback came to Harold S. Black, an american

1.2 PROPERTIES OF IDEAL FEEDBACK CIRCUITS

Let us consider the system in Fig.1.1a, composed by an amplifier whose

and the feedback signal f:

If Gloop>>1, the unity becomes negligible in the denominator of Eq.1.1,

1.3 NEGATIVE AND POSITIVE FEEDBACK

It is worthwhile to study Eq.1.1 in the two cases of positive and negative

Both positive and negative feedback find applications in electronics. In the

These considerations find immediate practical application. Let us suppose

1.4 REAL CIRCUITS WITH NEGATIVE FEEDBACK

The elementary properties of the feedback circuits, so far obtained on the

It is interesting to note how simple topological modifications of the circuit

Fig. 1.5 Feedback circuit where a virtual ground originates.

These first simple considerations introduced us to the analysis of the

Fig. 1.7 Example of voltage amplifier with feedback.

E 1.1 For the feedback circuit of the following figure:

this is the current supplied to the load RL (shown as iu in the figure).

As will be shown in Exercise E1.8, and in the hypothesis of G loop, this

As a result, in the hypothesis of Gloop, the transfer function between the

Therefore the voltage gain is equal to 2.

1.5 EVALUATION OF THE LOOP GAIN

Recapitulating, if the resistance is correctly reconstructed, every choice results in

- if in the feedback loop there is an ideal current generator, it is convenient to cut

- choose a current signal as the test signal.

- if in the feedback loop there is an ideal voltage generator, it is convenient to cut

- choose a voltage signal as the test signal;

It is easily verified that:

The loop gain is then given by:

1.6 THE ITERATIVE BIASING

For the bipolar transistor it is reasonable to assume anyway VBE=0.7V. Thus

IB2 = 0  Iƒ = IB2 = 0 mA Vu = - 0.7 V

I5 = 4.7 mA IC2 = 4.7 mA ,

I5 = 3.8 mA IC2 = 3.75 mA ,

From the JFET quadratic equation VGS=+0.2V is obtained, which corresponds to

VG = - 1.8 V  Iƒ = I1 = 1.8 mA Vu = - 1.2 V

from here VGS=0.7V and VG=-1.3V result. Another iteration gives:

VG = - 1.3 V  Iƒ = I1 = 1.3 mA Vu = - 5.2 V

The result is:

The circuit is then an inverting transimpedance amplifier. It reads the input

1.7 CALCULATION OF INPUT AND OUTPUT

In the introduction to feedback circuits and in some examples it was

Let us suppose the configuration in Fig.1.13a is employed, and obtain the

generator draws from the Base, through Rƒ, the current:

(a) - In a feedback circuit, the effect of the feedback is to increase or decrease,

(b) - In order to represent the impedance with the noteworthy structure

As an additional example, let us now evaluate the output resistance of the

calculated; the output resistance is then:

As already stated at the beginning of this section, this result could be

On the other side, the feedback current is (Fig. b):

Hence, the total variation of the Emitter potential is given by:

Let us calculate this latter independently on Rs, by applying a test current

The input resistance of the feedback stage is then:

The input resistance of the whole circuit is:

Let us suppose that a positive signal vs is applied. It would originally inject a

The resistance of the feedback stage is then given by:

and the total output resistance of the circuit is:

R in  R 0in  (1  G loop )  9.1M .

The total input resistance of the circuit is then:

This current produces an output voltage signal across R3 given by vu=-iu.R3.

E 1.18 For the differential pair of exercise E 5.18:

By applying a voltage signal to the cutting point, a current given by v s/2r02

Therefore, the output resistance with the feedback active is:

1.8 IDEAL TRANSFER AND REAL TRANSFER