Microsyst Technol
DOI 10.1007/s00542-016-2971-7
TECHNICAL PAPER
Ultra high gain CMOS Op‑Amp design using self‑cascoding
and positive feedback
Subhra Chakraborty1 · Abhishek Pandey1 · Vijay Nath1 
Received: 8 July 2015 / Accepted: 7 May 2016
© Springer-Verlag Berlin Heidelberg 2016
Abstract  This paper presents an ultra high gain two stage
CMOS Operational Amplifier which is designed using
self-cascoding and positive feedback technique in order to
provide gain enhancement. By comparing the circuit with
other designed circuits it has been shown that applying pos-
itive feedback increases the gain of the Op-Amp without
affecting other properties of the amplifier. The proposed
circuit is designed in 45 nm technology using Cadence
Virtuoso Analog Design Environment tool at ±1 V supply.
The Op-Amp is designed to achieve a high gain of 141 dB
while maintaining a UGB of 101 MHz and phase margin
of 60°. The simulation results conforms the estimated theo-
retical improvements. The dependence of various proper-
ties such as slew rate, UGB, settling time and phase margin
of the designed Op-Amp on compensating capacitor CC
has also been analyzed in this paper. Finally, the simulation
results have been compared with a previously reported Op-
Amp utilizing positive feedback technique.
1 Introduction
In recent years, Op-Amp has become most important integral
part in electronic instrumentation and measurement circuits.
Due to its huge applications, it has become a necessary part
in analog electronics in the same way as logic gates in digital
electronics. Since, the past decades, extensive research work
has been going on for improving the performance of the Op-
Amp. The performance of Op-Amp has been improved on
* Abhishek Pandey
a.p.bitmesra@gmail.com
1
VLSI Design Group, Department of Electronics
and Communication Engineering, Birla Institute
of Technology, Mesra, Ranchi, Jharkhand 835215, India
the basis of chip area, power consumption, gain, bandwidth,
CMRR, PSRR etc. For instrumentation applications, where
the signals are of very low strength, the high gain Op-Amps
are required. In today’s CMOS technology, the channel
length is being constantly reduced for low voltage applica-
tions. This gate channel length reduction gives rise to a major
problem; it decreases the output resistance of the MOSFETs.
Due to this fact the small signal gain of the Op-Amp reduces.
This small signal gain is further reduced by the short channel
effect in submicron levels (Razavi 2001; Allen and Holberg
2002; Baker 2005).
For sub-50 nm MOSFET designs it becomes necessary
to employ additional gain enhancement techniques for
instrumentation applications of Op-Amp. There are many
techniques to enhance gain, but most of them employ add-
ing additional gain stages. While employing additional gain
stages makes the compensation methods more complex.
Also the chip area can be utilized effectively if fewer num-
bers of gain stages are used.
Many CMOS Op-Amps with high gain have been devel-
oped and reported in the past decades. These designs typi-
cally achieve gains of 100–120 dB. The highest reported
gain was 140 dB, where three comparators were cascaded
(Purcell and Abdel-Aty-Zohdy 1997). The higher gain
CMOS Op-Amps typically use 3–5 gain stages or gain-
boosting schemes to achieve the high gain and generally
require several compensation capacitors. The Op-Amp pre-
sented in this paper utilizes composite cascode connections
and positive feedback for enhancing the gain.
2 Positive feedback
Addition of the positive feedback circuit in the differen-
tial pair of the Op-Amp results in gain improvement. Now
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 Microsyst Technol

that MOS transistors are significantly being scaled down where, gm is the small signal transconductance, go is the
positive feedback circuits can be a solution to increase small signal output conductance and CL is the load capaci-
the small signal gain. The major problem associated with tance of the amplifier.
positive feedback is the possibility of amplifier instabil- If it is assumed that β(s) > 0, we can rewrite the Eq. (1)
ity. However, amplifier with positive feedback can be sta- as
bilized if it is properly designed assuming amplifier open
Y (s) gm
loop gain is small. The degradation in maximum intrinsic H(s) = = (3)
X(s) go + sCL − gm β(s)
gain (gmro) of a transistor due to transistor scaling helps
maintaining the stability when the positive feedback circuit β(s) can be realized as a constant or zero order system.
is added. Another problem of the most positive feedback Hence, we can assume that β(s) = k.
implementation is a strong dependence of the amplifier’s The position of pole for the feedback part can be given
gain on transistor matching. All of these problems can be as
eliminated by the proper selection of W/L ratio and com-
go − g m k
pensation capacitance. PPFB = − (4)
CL
A lot of research has been done in the application of
positive feedback in Op-Amps. It has been already dis- And DC gain is given as
cussed in several publications that by applying a positive gm
feedback a compensating negative conductance is gener- ADC = (5)
go − gm k
ated which in turn enhances the amplifier gain (Schlarmann
et al. 2002; Wang and Harjani 1995). In most of the pro- where, k is carefully chosen so that the value of the denom-
posed structures a negative resistance is generated from the inator of ADC is small enough to result in high gain. But if
feedback generated at the output node which helps generate too much high gain is applied by increasing the DC value
high DC gain by compensating some of the positive resist- of β(s) or increasing k, the pole of the positive feedback
ance at the output (Pude et al. 2010; Khameh et al. 2010; part may end up in the right hand side of the plane which
Dadashi et al. 2011, 2012). One of the initial implemen- will make the system unstable. However, these shortcom-
tations of the application of positive feedback in differen- ings are eliminated when the positive feedback is an inter-
tial pair was implemented in a comparator (Allstot 1982). nal part of the circuit and the circuit is utilized in negative
Then a positive-feedback transconductance amplifier was feedback configuration.
designed for high-frequency applications (Young et al.
1988). Several new CMOS amplifiers with very high DC- 2.2 Positive feedback within a negative feedback block
gain that used internal positive feedback techniques were
presented (Amourah and Geiger 2001, 2002). A differen- The shortcomings of the previous section are eliminated
tial pair positive feedback topology was introduced for when the positive feedback is an internal part of the circuit
enhanced transconductance gain (Ramírez-Angulo et al. and the circuit is utilized in negative feedback configuration.
2010) which was further improved and the improvement In the system shown in Fig. 2 the positive feedback
resulted in the higher small signal gain (Tran et al. 2010; provides gain enhancement while the negative feedback
Chakraborty et al. 2015a, b). But most of these circuits ensures the system stability. The transfer function of the
were implemented with differential output. system can be written as
Y (s)
2.1 Classic positive feedback block H(s) =
X(s)
gm (6)
The transfer function of a positive feedback circuit (Fig. 1) is =
go + sCL − gm β(s) + gm β ′ (s)
Y (s) α(s)
H(s) = = (1) Y (s)
X(s) 1 − α(s)β(s)
H(s) =
X(s)
where, X(s) is the input transfer function and Y(s) is the (7)
gm
output transfer function, α(s) is the amplifier transfer func- =
go + sCL + gm (β ′ (s) − β(s))
tion and β(s) is the feedback transfer function.
If a first order model is utilized to analyze the amplifier In this case also we can take β(s)  = k and β’(s)  = k′.
gain it can be written as (Schlarmann et al. 2002) Therefore, the location of the pole can be given as

gm go + gm (k ′ − k)
α(s) = PPNFB = − (8)
go + sCL (2) CL

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Microsyst Technol

Fig. 1  Block diagram of positive feedback system

Fig. 3  Cross coupled differential amplifier

Fig. 2  Block diagram of positive feedback system within a negative

feedback system

And the DC gain as

gm
ADCP =
go + gm (k ′ − k) (9)

From the above equations it can be said that for the sys-

both β(s) and β′(s). Since gmk′  ≫ go−gmk the stability of

tem in Fig. 2, the gain and location of the pole depends on

the system is ensured.

2.3 Implementation of positive feedback in differential Fig. 4  Self-cascode structure

amplifier

The circuit shown in Fig. 3 uses the positive feedback strat-

egy (Tran et al. 2010). This circuit is a simple gm enhanced
differential pair amplifier based on positive feedback. The
cross coupled MOS transistors placed at the centre of the
circuit is the feedback circuit. A negative transconductance
–gmFB is generated by these cross coupled MOS transistors.
This negative transconductance –gmFB is comparable to the
term −β(s)gm in Eqs. (3) and (6).
The small signal gain of the circuit in Fig. 3 is given as

VoD gm1
Av = = 1 1 1 (10)
ViD ro1 + ro3 + RoFB − GmFB

where, GmFB and RoFB is the transconductance and output

resistance of the cross coupled MOS transistors respec-
tively, ro1 and ro3 is the resistance of transistor M1 and M3, Fig. 5  First and second stage of Op-Amp using self-cascode struc-
gm1 is the transconductance of M1. And ture

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 Microsyst Technol

Fig. 6  Proposed circuit apply-

ing positive feedback and self-
cascode structure in Op-Amp

Fig. 7  Other configurations from Fig. 6

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Microsyst Technol

Fig. 8  Simplified Small signal model of differential stage of the proposed circuit

Fig. 9  Schematic diagram of the proposed Op-Amp with biasing applied using MOS voltage divider

gm1c two transistors M1 and M2 shown in Fig. 4 is known as

GmFB = ro1c +ro3c (11) self-cascode (Rajput and Jamuar 2002). The self-cascode
ro1c + ro3c (gm1c + gmb1c )
structure offers a larger effective channel length and a
larger effective output resistance. The output resistance of
RoFB = ro1c + ro3c + (gm1c + gmb1c )ro1c ro3c (12) this structure can be enhanced if the W/L ratio of the tran-
where, ro1c and ro3c is the output resistance of M1c and M3c sistor M2 is kept larger than M1 (Comer et al. 2004). The
respectively, gm1c and gmb1c is the transconductance and transistor M1 is similar to a resistor whose value depends
bulk transconductance of M1c respectively. on input (Comer et al. 2010a, b). If the W/L ratio of M2 is
taken very large with respect to M1, then the drain current
can be written as
3 Self cascoding

Sometimes the composite cascode structures are also    (VG − VT )2 (13)

ID = K W L M1 ×
referred as self-cascode structure. The combination of the 2

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 Microsyst Technol

Table 1  W/L ratio of the transistors used in the proposed circuit And the voltage gain of second stage (Fig. 5b) is given by
MOSFET W/L ratio (m) gm1 gm4 (gm2 + gmb2 )
A2nd = (16)
M1a 30u/45n gds1 gds2 (gm2 + gm4 + gmb2 )
M1b 4.19u/45n where, gm1, gm2, gm4 is the transconductance of M1, M2,
M2a 30u/45n and M4 respectively. gmb2 is the bulk transconductance of
M2b 4.19u/45n M2. And gds1 and gds2 is the drain to source transconduct-
M3a 110n/45n ance of M1 and M2.
M3b 30u/45n
M4a 110n/45n
M4b 30u/45n 4 Proposed circuit
M1c 4.43u/45n
M2c 4.43u/45n From the previous sections it is evident that a higher gain
M3c 60n/45n can be achieved if self-cascoding and positive feedback tech-
M4c 60n/45n niques are applied in an Op-Amp. The circuit given in Fig. 6
M5c 4.43u/45n is a differential input, single output operational amplifier uti-
M6c 60n/45n lizing self-cascoding and positive feedback technique. In this
M5 2.57u/45n circuit M1a, M1b, M2a, M2b, M3a, M3b, M4a, M4b, M7a,
M6 2.57u/45n M7b, M8a and M8b forms the composite cascode structured
M7a 7.29u/45n Op-Amp. M1c, M2c M3c, M4c, M5c and M6c are used for
M7b 7.23u/45n the positive feedback. M5c and M6c transistors form a resis-
M8a 4.56u/45n tive load at the output. M5c is diode connected load in series
M8b 4.56u/45n with M6c. In this circuit, by placing biasing transistors M5
M9 60n/45n and M6 and applying Vb2 in their gate, increases the small
M10 120n/45n signal resistance of the differential amplifier which in turn
M11 120n/45n increases the small signal gain of the amplifier. Along with
M12 12.04u/45n that, it also provides a transconductance between the feed-
M13 500n/45n back and output of the circuit. So, mainly the Ro of the circuit
M14 12.39u/45n will improve and it will finally enhance the small signal gain
M16 730n/45n of the circuit. In this circuit high level of transistor matching
is required in order to optimize the circuit for high gain.
Three more designed circuits are given in Fig. 7. If the
biasing transistors M5 and M6 are removed from Figs. 6,
If the output voltage is taken from the drain of M2 then the Fig. 7a can be realized. Similarly, if the cross coupled MOS
voltage gain of the self cascode connection ignoring M2’s transistors providing feedback are removed from the cir-
body effect is given as cuits of Figs. 6 and 7a, the circuits given in Fig. 7b, c are
formed respectively.
ACC = −gm1 gm2 rds1 rds2 (14) In the differential stage of the circuit 7a, let us consider
3.1 Op‑Amp using self‑cascode structure that transistor M1a and M1b, M2a and M2b, M3a and M3b
and M4a and M4b forms self cascode structures SC1, SC2,
Op-Amp designed using composite cascode structures SC3 and SC4 respectively. Then we can say that without
are bound to give better results due to the greater output considering the positive feedback circuit of the circuit in
resistance exhibited by the composite cascode structures. Fig. 7a the small signal gain of the differential stage of the
The voltage gain of the differential stage (Fig. 5a) is given circuit given in Fig. 7c is
below (Comer et al. 2004). ADiff = gmSC1 Ro(Diff )
(17)
 
2 g (g
gm5 = gmSC1 Ro(SC2) ||Ro(SC4)
m6 m8 + gmb8 )
A1st = (15) If the positive feedback circuit is added then the small
gm5 gm6 gds7 gds8 + gm5 (gm8 + gmb8 )gds5 gds6
signal gain of the circuit given in Fig. 7a becomes
where, gm5, gm6 and gm8 is the transconductance of M5, M6
ADiffFB1 = − gmSC1 Ro(DiffFB1)
and M8. gds5, gds6, gds7 and gds8 is drain to source conduct-  
ance of M5, M6, M7 and M8 respectively. And gmb8 is the −1
= − gmSC1 Ro(SC2) ||RoFB1 || (18)
bulk transconductance of M8 GmFB

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Microsyst Technol

Fig. 10  Phase and gain plot of the proposed circuit

Table 2  Performance analysis of the proposed Op-Amp with respect

to CC

CC (fF) Slew rate Settling UGB Phase

(V/us) time (ns) (MHz) margin (°)

100 192.7 917.6 350 8.5

200 135.1 909 241.3 30
300 102.4 908.1 241.3 30
400 81.48 907.3 144 50.7
500 67.78 907.7 118.7 55.7
600 57.74 906.6 101 60
700 50.13 907.3 88 63
800 44.41 908 87.5 63.5
900 39.46 908.7 69 67
Fig. 11  Output response with a step input at various value of CC in 1000 35.75 909.6 62.5 68.5
the proposed circuit

The second stage is basically a common source ampli-

ACmSrc = − gmSC7 Ro(CmSrc)
fier utilizing the self cascode structure. In this stage also  
a positive feedback is used to enhance the gain of the cir- −1
= − gmSC7 Ro(SC7) ||Ro(SC8) ||RoFB2 || (19)
cuit. This stage acts as a secondary gain stage with a small GmFB2
gain and mostly provides stability to the circuit. If we
consider that M5c and M6c forms another feedback cir- From the simplified small signal model of the differ-
cuit FB2 then the gain provided by the second stage can ential stage of the circuit, the gain of the proposed circuit
be given by given in Fig. 8 can be written as

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 Microsyst Technol

Table 3  THD of proposed circuit using different load resistances

Load resistance (Ω) Vop-p (V) THD (%)

0.5 0.875 5.6

1 0.875 5.65
5 0.875 5.77
10 0.875 5.65
20 1.156 5.27
50 1.156 5.13
100 1.172 3.54
1 K 1.625 3.48
10 K 1.187 3.46
100 K 1.187 3.46
Fig. 12  THD analysis of proposed circuit with 1 KΩ load resistance 1 M 1.187 3.46
at 1 kHz frequency at different Vop−p

ADiffFB = − gmSC1 Ro(DiffFB)

  
= − gmSC1 (Ro(SC2) ||(1 gm6 )) + Ro6
(20)
 
||Ro(SC4) ||RoFB ||(−1 GmFB )

And for the second stage, the gain will remain same as
given in Eq. (19).
In Fig. 6 the voltage biasing Vb1 and Vb2 can be applied
using MOS voltage dividers. The proposed circuit modified
by the MOS voltage dividers is shown in Fig. 9.

5 Simulation result and discussion

The proposed Op-Amp circuit has been designed in
45 nm technology using cadence. The responses of the
circuits designed using positive feedback are very much
dependent on the W/L ratio of the transistors used.
The W/L ratio of the different transistors used for the
Fig. 14  Common mode gain of the proposed circuit
proposed circuit with voltage biasing applied using MOS
voltage divider is given in Fig. 9 has been tabulated in
Table 1.

Fig. 13  THD analysis of
proposed circuit with 1 KΩ load
resistance and 2 V Vop−p at dif-
ferent harmonics of 500 Hz

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Microsyst Technol
Fig. 15  PSRR of the proposed circuit
For the proposed circuit a compensating capacitor of
600 fF was chosen, which resulted in phase margin of 60°
and unity gain bandwidth of 101 MHz along with 141 dB
DC-gain, which is shown in Fig. 10. The bandwidth is low
because the product of gain bandwidth is always constant.
Therefore if gain is increases then bandwidth is decreases.
A ±1 V power supply used for this circuit. For proper
working of the device high level of transistor and capaci-
tor matching is required. As we know that slew rate and
settling time is very much dependent on the compensating
capacitor CC. Figure 11 shows the transient response of the
proposed circuit with a step input of ±100 mV for various
capacitance values of the compensating capacitor and load
resistance of 1 KΩ. Table 2 lists the results in terms of slew
rate, settling time, phase margin, and unity gain bandwidth
with respect to the values of compensating capacitor. The
phase margin graph is started from 180°, because the out-
put is referred to the inverting input. 180° and −180° both
are same in AC simulation.
Table  2 shows that with increasing CC the UGB and
slew rate of the circuit decreases as they should be. The
Fig. 16  ICMR of the proposed
circuit
Fig. 17  Output voltage noise of the proposed circuit in form of expo-
nential decay
settling time of the circuit almost remains the same with
the changing value of CC. And the phase margin of the cir-
cuit improves with increasing CC. From the result we can
conclude that 600 fF produces an overall satisfactory result.
Now a day’s THD (Total Harmonic Distortion) is used
to quantify the distortions caused by amplifier non linear-
ity. THD is generally measured in terms of dB or percent-
age. The THD of the proposed circuit with respect to output
peak to peak voltages at 1 kHz frequency and with a load
resistance of 1 KΩ is given in Fig. 12. Another THD plot
is given with respect to different harmonic frequencies of
0.5 kHz with Vop-p (peak to peak output voltage) of 2 V and
load resistance of 1 KΩ is given in Fig. 13.
The THD analysis has been done with respect to Vop-
p using different load resistances at 1 kHz frequency and
the highest peak of the graph has been noted along with
the Vop-p at which the highest THD peak has resulted. The
result has been tabulated in Table 3.
The common mode gain, PSRR, ICMR and output
voltage noise of the proposed circuit has been plotted in
Figs. 14, 15, 16 and 17 respectively. From Fig. 14 it can be
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 Microsyst Technol

Fig. 18  Phase and gain com-

parison of designed circuits in
Figs. 6 and 7

Table 4  Performance comparison with other designed Op-Amps

Parameter Figure 7a Figure 7b Figure 7c Dadashi et al. Taherzadeh- Assaad et al. Ahmadi Chakraborty et al.Proposed
(2012) Sani et al. (2009) (2006) (2015b) circuit
(2011

Technology (nm) 45 45 45 350 65 180 180 180 45

Power supply 2 2 2 3.3 1 1.8 1.8 2 2
(V)
DC gain (dB) 88 49.5 41.5 68 56 60.9 80 124 141
Phase margin (°) 59.4 63.3 64.8 68 77 70.6 73 69.5 60
Power consump- 1.08 1.12 1.25 6.4 1.6 1.44 3.8 0.221 1.2
tion (mW)
UGB (MHz) 101.2 98.5 94 484 450 134.2 660 307 101
THD (dB) −60 −63 −68 −71.5 – – – −63 −80
CL (pF) 1 1 1 0.3 – 5.6 1 1 1

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Microsyst Technol
seen that for low frequencies the common mode gain of the
circuit is −5 dB. So, the CMRR of the circuit is 136 dB.
From Fig. 15 the value of |PSRR+| and |PSRR−| can be
obtained as 57.43 and 67.1 dB. The ICMR plot given in
Fig. 16 suggests that the output is faithful the input within
the range of −755.4 to 259 mV. Figure 17 shows that the
proposed circuit exhibits maximum noise of 3.8 V/sqrt(Hz)
at 0 Hz and above 150 kHz it produces a flat response.
A comparison between the circuits with positive feed-
back and without positive feedback given in Figs. 6 and 7
has been done. Figure 18 shows the different gain plots and
phase plots of the circuits designed respectively.
The addition of the feedback circuit just enhances the gain
of the designed circuit. From the figure it can be seen that the
difference of gain between the circuit with feedback (Fig. 6)
and the circuit without feedback (Fig. 7b) is almost 90 dB.
When comparing with other amplifiers utilizing differ-
ent feedback configuration in different Op-Amps, the pro-
posed circuit produce far better results in terms of gain. The
simulation result of the proposed Op-Amp and Op-Amps
shown in Fig. 7a, b, c along with the Op-Amps previously
reported has been compared in Table 4.
6 Conclusion
In this paper, a novel Op-Amp design is presented in which
the gain of the Op-Amp is enhanced by applying positive
feedback and self cascoding. The main advantage of this
design is that it achieves a higher gain without increasing
the complexity of the circuit and without affecting other
properties of the Op-Amp very much. From the results it is
evident that applying this positive feedback configuration
almost doubles the gain produced in dB. But for accom-
plishing this type of gain, high level of transistor matching
is required in the feedback circuit which can be achieved
by carefully designing. Among the high gain CMOS Op-
Amps designed in the past, this Op-Amp design produces
the highest gain (141 dB).
It is known that as the transistors are scaled down the
small signal output resistance of the transistors decreases,
and hence the small signal gain also decreases. If we con-
sider the technology in which it is designed then it can be
realized that the proposed circuit produces a very large gain.
The proposed circuit also consumes less power and
operates on low voltage. The gain margin of the system is
also good. However, the UGB of the circuit is on the lower
side which is a fair trade off in terms of the gain produced.
Acknowledgments We are thankful to Department of Science and
Technology, New Delhi and Defense Research Development Labora-
tory, Hyderabad, India for funding this project. We are also thankful
to our Vice-Chancellor, Dr. M. K. Mishra and our Head of department
Dr. V. R. Gupta for their constant inspiration and encouragement.
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