CH 03

Chapter 3
S i
Semiconductor
d t Memories
M i
Jin-Fu Li
Department of Electrical Engineering
National Central University
Jhongli Taiwan
Jhongli,
Outline
Introduction
Random Access Memories
Content Addressable Memories
Read Only Memories
Flash Memories
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Overview of Memory Types
Semiconductor Memories
Read/Write Memory or
Random Access Memory (RAM) Read Only Memory (ROM)
Random Access Non-Random Access

Memory (RAM) Memory (RAM) •Mask (Fuse) ROM
•Programmable ROM (PROM)
•Erasable
E bl PROM (EPROM)
•Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM)
•Dynamic RAM (DRAM) •Shift Register •Flash Memory
•Register File •Content Addressable •Ferroelectric RAM (FRAM)
Memory (CAM) •Magnetic RAM (MRAM)

Memory Elements – Memory Architecture
Memory elements may be divided into the
following categories
Random access memory
Serial access memory
C nt nt addressable
Content ddr bl m
memory
m r
Memory architecture
2m+k bits
row decoder
row decoder
2n-k words
row decoder
row decoder
column decoder
k column mux,
n-bit address sense amp,
2m-bit data I/Os write buffers

1-D Memory Architecture
S0 S0
Word0 Word0
S1 S1
Word1 Word1
S2 S2
Word2 Word2
A0
S3 S3
Decoder
A1
Ak-1
Sn-2 Storage Sn-2

Wordn-2 element Wordn-2
Sn-1 Sn-1
Wordn-1 Wordn-1
m-bit m-bit
Input/Output Input/Output
n select signals: S0-S

Sn-1 n select signals are reduced
to k address signals: A0-Ak-1
S0
Word0 Wordi-1
S1
A0
ecoder
A1
Row De
Ak-1
Sn-1
Wordni-1
A0
Aj-1 Column Decoder
Sense Amplifier
Read/Write Circuit
m-bit Input/Output
Row
Column
ock
Blo
Input/Output

Conceptual 2-D Memory Organization
Address oder
Row Deco
R Memory Cell
Column decoder
Data I/Os

Memory Elements – RAM
Generic RAM circuit
Bit line conditioning Clocks
RAM Cell
n-1:k
Sense Amp
Amp, Column Write
k-1:0 Mux, Write Buffers Clocks
Address write data read data

RAM – SRAM Cells
6-T SRAM cell
word line
bit - bit
4-T SRAM cell
word line
bit - bit

RAM – DRAM Cells
4-T dynamic RAM (DRAM) cell
word line
bit - bit
3-T DRAM cell

Read
Write
Write Read
data data

RAM – DRAM Cells
1-T DRAM cell
word line word line
Vdd or bit bit

Vdd/2
Layout of 1-T DRAM (right)

Vdd word line
bit

RAM – DRAM Retention Time
Write and hold operations in a DRAM cell
WL=1 WL=0
on + off +
+ Cs Vs Cs Vs
Input Vdd - -
-
Write Operation Hold
V s = V max = V DD − V tn
Q max = C s (V DD − V tn )

RAM – DRAM Retention Time
Charge leakage in a DRAM Cell
Vs(t)
WL 0
WL=0
Vmax
IL Minimum logic 1
V1 voltage
off +
Cs Vs(t)
-
t
th
dQ s
IL = −( )
dt
dV s
IL = −C s ( )
dt
ΔVs
IL ≈ −C s ( )
Δt
Cs
t h = | Δ t |≈ ( )Δ Vs
IL
RAM – DRAM Refresh Operation
As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the
hold time is
50 × 10 −15
t h= −9
× 1 = 0.5μs
1× 10
Memory units must be able to hold data so long as the power is
applied. To overcome the charge leakage problem, DRAM arrays
employ a refresh operation where the data is periodically read from
every cell
cell, amplified
amplified, and rewritten
rewritten.
The refresh cycle must be performed on every cell in the array with a
minimum
i i refresh
f h ffrequency off about
b t
1
f refresh≈
2t h

RAM – DRAM Read Operation
WL=1
IL
on +
Cbit Cs Vs Vf
+ -
Vbit Vf
-
Q s = C sV s
Q s = C sV f + C bit V f
Cs
Vf = ( )V s
C s + C bit
This shows that Vf<Vs for a store logic 1. In practice, Vf is usually
reduced to a few tenths of a volt, so that the design of the sense
p
amplifier becomes a critical factor

RAM – SRAM Read Operation
Vdd precharge
precharge
precharge
p g
bit, -bit
word line
word
data
- bit bit
data

Vdd-Vtn precharge
precharge
precharge
p g
Vdd
bit, -bit
word line
word
data
- bit bit
data

bit, -bit
word
data
- bit bit
load
V2
sense + sense - pass
V1
sense common pulldown

RAM – Write Operation
N5 N6
write data
word
write
N3 N4
word
bit, -bit
- bit bit
N1 N2
write
cell, -cell
write data

RAM – Write Operation
- bit bit
Pbit
5V -cell cell 0V
Nbit - write
write
ND PD write-data

RAM – Row Decoder
word<3> word<0>
word<2> word<1>
word<1>
d<1> word<2>
d<2>
word<0> word<3>
1 a<0>
a<1> 0 1 a<0>
a<1> 0

RAM – Row Decoder
word
a1
a0 a0 a1 a2 a3
Complementary AND gate Pseudo-nMOS gate

RAM – Row Decoder
Symbolic layout of row decoder
output
Vss Vdd Vss

RAM – Row Decoder
Symbolic layout of row decoder
Vdd
output
p
Vss
a3 -a3 a2 -a2 a1 -a1 a0

RAM – Row Decoder
Predecode circuit
word<7>
word<6>
d<6>
word<5>
word<4>
word<3>
word<2>
word<1>
word<0>
a2 a1 a0
RAM – Row Decoder
Actual implementation
a0
a4
a3
a2 word
a1
-a0 clk
Pseudo-nMOS example
a0 word
od
a1 a2 en

RAM – Column Decoder
bit<7>
bit<6>
bit<5>
bit<4>
selected-data
bit<3>
bit<2>
bit<1>
bit<0>
to sense amps and write ckts

-bit<7>
-bit<6>
-bit<5>
-bit<4>
-selected-data
-bit<3>
-bit<2>
bt
-bit<1>
-bit<0>
a0 -a0 a1 -a1 a2 -a2

RAM – Multi-port RAM
write
read0
read1
-rbit1
rbit1 -rbit0
rbit0 -rwr_data
rwr data rwr data rbit0
rwr_data rbit1
write
read0
read1
-rbit1 -rwr_data rwr_data rbit0

RAM – Expandable Reg. File Cell
wr-b addr<3:0>
rd-a addr<3:0>
rd-b addr<3:0>
write data
write-data read data 0 read-data
read-data read data 1
write-data
write-enable(row)
read0
read1
Write-enable (column)
Specific Memory – FIFO
Two port RAM
Write Data
Write-Data Read Data
Read-Data
Write-Address Read-Address
Write-Clock Read-Clock
Full Empty
FIFO Write (Read) address control design
WP (RP)
0
0
1
1
Write
(Read)
rst 1
clk incrementer

Specific Memory – LIFO
LIFO (Stack)
Require:
Single port RAM
One address counter
Empt /F ll detector
Empty/Full
Algorithm:
g
Write: write current address
Address=Address+1
Read: Address=Address-1
read current address
Address
Empty: Address=0
F ll : Address=FFF…
Full Add FFF

Specific Memory – LIFO
LIFO address control design
0 -1
0 decrementer
1 0
1
1
rst 1
Write
clk
lk incrementer
Empty
Read
Write
Full

Specific Memory – SIPO
SIPO cell design
Read
Parallel-data
Sh-In Sh-Out
Clk
-Clk
SIPO
Read
Sh-In
Clk

Specific Memory – Tapped Delay Line
delay<5>
y delay<4>
y delay<3>
y delay<2>
y delay<1>
y delay<0>
y
0 0 0 0 0 0
din
1 1 1 1 1 1 dout
Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR

Read-Only Memories
Read-Only Memories are nonvolatile
Retain their contents when p
power is removed
Mask-programmed ROMs use one transistor per
bit
Presence or absence determines 1 or 0

Non-volatile Memory – ROM
4x4 NOR-type ROM
Vdd
WL0
GND
WL1
WL2
GND
WL3
BL0 BL1 BL2 BL3

Non-volatile Memory – ROM
4x4 NAND-type ROM
Vdd
BL0 BL1 BL2 BL3

WL0
WL1
WL2
WL3

ROM Example
4-word x 6-bit ROM
Represented
p with dot diagram
g
Word 0:
0 010101
Dots indicate 1’s in ROM
Word 1: 011001
weak W d 2
Word 2: 100101
A1 A0 pseudo-nMOS
pullups
Word 3: 101010
2:4
DEC
ROM Array
Y5 Y4 Y3 Y2 Y1 Y0
Looks like 6 4-input pseudo-nMOS NORs

ROM Array Layout
Unit cell is 12 x 8 λ (about 1/10 size of SRAM)
Unit
Cell

Row Decoders
ROM row decoders must pitch-match with ROM
Only
y a single
g track p
per word!

Complete ROM Layout

Building Logic with ROMs
Use ROM as lookup table containing truth table
n inputs,
p k outputs
p requires
q 2n words x k bits
Changing function is easy – reprogram ROM
Finite State Machine
n inputs, k outputs, s bits of state
Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
inputs
n ROM Array
inputs outputs
2n wordlines
n ROM k k
DEC
s
C
s
state
k outputs

Specific Memory – CAM
Content addressable memories (CAMs) play an
important
p role in digital
g systems
y and applications
pp
such as communication, networking, data compression,
etc.
Each storage element of a CAM has the hardware
capability
p y to store and compare
p its contents with
the data broadcasted by the control unit
CAM types
dynamic or static
binary or ternary
The binary static CAM is discussed

Difference Between RAM and CAM
Address
RAM Data
R/W
Hit
Data
CAM
C d
Cmd Address

CAM – Applications
CAM architecture
CAM Memory Array

Data Match
NxM-bit words
Cache architecture
CAM RAM
Match 0
Word 0
Match 1
Word 1
CAM Memory Array Match 2
Match 3
Word 2
Data In NxM-bit words Word 3
Match 4
Word 4
Match 5
Word 5
Data I/Os

CAM – Architecture
Comparand Register
ess Decoder Mask Register
der
Address Hit
Valid Bitt
espond
Input
Memory Array
Address
Addre
Re
V
Output
I/O Register

CAM – Basic Components
Comparand Register
It contains the data to be compared
p with the content of the memory
y
array
Mask Register
It is used to mask off portions of the data word(s) which do not
participate in the operations
M
Memory Array
A
It provides storage and search (compare) medium for data
R d
Responder
It indicates success or failure of a compare operation

CAM – Binary Cell
CAM cell
-bit bit
WL
-d d
M2 M1
Match
3
M3

CAM – Word Structure
bit[0]
[ ] bit[0]
[ ] bit[w-1]
[ ] bit[w-1]
[ ]
Wi
1 0
Vdd
P
Mi
10 0
1
comparison logic

CAM – Organization
CAM circuit Read Data (Test)
Match Data In
Normal RAM Read/Write Circuitry
Hit
Match0
Match1
Match2
Match3
precharge

Non-volatile Memory – Flash Memory
Flash memory
A nonvolatile, in
in-system-updateable,
system updateable, high
high-density
density memory
technology that is per-bit programmable and per-block or per-
chip erasable
In-system updateable
A memory whose contents can be easily modified by
the system processor
Block size
The number of cells that are erased at the same time
C l
Cycling
The process of programming and erasing a flash
memory cell
Flash Memory – Definition
Erase
To change a flash memory cell value from 0 to 1
Program
To change a flash memory cell value from 1 to 0
Endurance
The capability of maintaining the stored information
p g
after erase/program/read cycling
y g
Retention
The capability of keeping the stored information in time

Basics
How can a memory cell commute from one state
to the others independently of external condition?
One solution is to have a transistor with a threshold voltage that can
change repetitively from a high to a low state
The high state corresponding to the binary value “1” 1
The low state corresponding to the binary value “0”
Threshold voltage of a MOS transistor
VT = K − Q' / Cox
K is a constant depending on the gate and substrate material,
doping, and gate oxide thickness
Q’ is the charge in the gate oxide
Cox is the gate oxide capacitance

Floating Gate Transistor
Floating gate (FG) transistor
Control Gate
CFC
Floating Gate
CFS CFB CFD
Source Drain
Substrate
e gy band
Energy ba d d
diagram
ag a of
o an
a FG
G ttransistor
a s sto
Substrate Floating Control

Gate Gate

Flash Memory – Threshold Voltage
When the voltages (VCG & VD) are applied to the control
gate and the drain, the voltage at the floating gate (VFG) by
capacitive
iti coupling
li is i expressedd as
V FG = Q FG + C FC VCG + C FD V D
C C C
C = Ctotal + Ctotal + C +total
C FD
total FC FS FB
The minimum control gate voltage required to turn on the
control gate is
C Q C
VT (CG ) = C VT ( FG ) − C − C VD
total FG FD
FC FC FC
where VT(FG) is the threshold voltage to turn on the floating gate
t
transistor
i t
The difference of threshold voltages between two memory
data states (“0”
( 0 and “1”
1 ) can be expressed as
ΔVT (CG ) = − ΔQFG
C FC

Flash Memory – Structures
Two major flash memory structures
NOR & NAND
NOR structure
Simplest
Dual power supply
Large block size
NAND structure
Intermediate block size
High-speed and high density
For storage applications

Flash Memory – Structures
Bit line Basic Bit line Basic
unit unit
Select
WL 1 gate
g
(d i )
(drain)
WL 2 WL 1
WL 2
WL 3
WL 3
WL 4
WL N
WL N Select
gate
(source)
Source line
NOR structure NAND structure
Flash Memory – Program Operation
Program operation of the Intel’s ETOX flash cells (NOR structure)
Apply 6V between drain and source
Generates hot electrons that are swept p across the channel from source
to drain
Apply 12 V between source and control gate
The high voltage on the control gate overcomes the oxide energy
barrier, and attracts the electrons across the thin oxide, where they
accumulate on the floating gate
Called channel hot-electron
hot electron injection (HEI)
+12V
Control Gate
GND Floating Gate +6V
Source Drain
Substrate

Flash Memory – Erase Operation
Erase operation of the Intel’s ETOX flash cells (NOR
structure)
Floating
l the
h ddrain, grounding
d the
h controll gate, and
d applying
l 12V to the
h
source
A high electric field pulls electrons off the floating gate
Called Fowler-Nordheim (FN) tunneling
GND
Control Gate
+12V
Floating Gate
S
Source D i
Drain
Substrate

Flash Memory – Erase Operation
Threshold voltage depends on oxide thickness
Flash memory y cells in the array
y may
y have slightly
g y
different gate oxide thickness, and the erase
mechanism is not self-limiting
After an erase pulse we may have “typical bits” and
“fast erasing bits”
VT
typical bit
fast erasing bit
0 log t
Flash Memory – Read Operation
Read operation of the Intel’s ETOX flash cells (NOR
structure)
Apply 5V on the control gate and drain, and source is grounded
In an erased cell, the VC>VT
The drain to source current is detected by the sense amplifier
In a programmed cell, the VC<VT
The applied voltage on the control gate is not sufficient to turn it on.
Th absence
The b off current results
l iin a 0 at the
h corresponding
di flash
fl h
memory output
+5V
Control Gate
GND +5V
Floating Gate
Source Drain
S b t t
Substrate

Flash Memory –Concept of Multi-Level Flash Memories
Source: Proceedings of
IEEE, 2003
Flash Memory – Basic Building Blocks of NOR Flash
Source: Proceedings of
IEEE, 2010
Flash Memory – NAND Flash Functional Block Diagram
Source: Micron
Flash Memory – NAND Flash Array Organization
Source: Micron

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Chapter 3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Random Access Non-Random Access

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

Sn-2 Storage Sn-2

n select signals: S0-S

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

Address write data read data

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

3-T DRAM cell

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

word line word line

Vdd or bit bit

Layout of 1-T DRAM (right)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

Write Operation Hold

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

sense + sense - pass

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

Complementary AND gate Pseudo-nMOS gate

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

to sense amps and write ckts

a0 -a0 a1 -a1 a2 -a2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

FIFO Write (Read) address control design

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

BL0 BL1 BL2 BL3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

BL0 BL1 BL2 BL3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

Looks like 6 4-input pseudo-nMOS NORs

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

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Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

CAM Memory Array

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46

ess Decoder Mask Register

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48