FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY

Assignment # 1
Subject: FPGA Based System Design Instructors: M. Amin Qureshi & Taha Hasan
Allocated Marks: 10

Question: Recall the 1-bit comparator circuit from your Digital Logic course. The working of 1-
bit comparator is as follows:

 It has two inputs of 1-bit each (a and b).

 There are three outputs of 1-bit each (L, Eq and G).
 When both inputs are equal, Eq produces a 1, otherwise it produces a 0.
 When a is less than b (a<b), L produces a 1, otherwise it produces a 0.
 When a is greater than b (a>b), G produces a 1, otherwise it produces a 0.

You have to perform the following tasks:

a) Design the truth table for above and derive the consolidated logic circuit from it.
b) Write the Verilog code for the above circuit using gate-level coding technique.
c) Write the Verilog code for the above circuit using behavioural coding technique.
d) Write the Verilog code for a 4-bit comparator using behavioural coding technique (using
if-else or case with vector signals) and then write the Verilog code for an 8-bit
comparator using cascaded 4-bit comparators (hierarchical modeling).
Hint: You have to first draw the circuit block diagram with 2 4-bit comparators and use
some additional logic gates to achieve the operation of 8-bit comparator