Clevo m720t m730t m728t m729t

Preface
Notebook Computer
M720T/M728T/M729T/M730T
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
July 2008
Trademarks
Intel, Celeron and Intel Core are trademarks of Advanced Micro Devices, Inc.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and./or registered trademarks of their respective companies.
II
Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the M720T/
M728T/M729T/M730T series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
III
Preface
FCC Statement
(Federal Communications Commission)
You are cautioned that changes or modifications not expressly approved by the party responsible for compliance could
void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
Warning installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in ac-
Use only shielded ca- cordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee
bles to connect I/O de- that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or
vices to this
equipment. You are
television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct
cautioned that chang- the interference by one or more of the following measures:
es or modifications not • Re orient or relocate the receiving antenna.
expressly approved by
• Increase the separation between the equipment and receiver.
Preface
the manufacturer for

compliance with the • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
above standards could • Consult the service representative or an experienced radio/TV technician for help.
void your authority to
operate the equip-
Operation is subject to the following two conditions:
ment.
1. This device may not cause interference.
If your purchase option
And
includes both Wire-
less LAN and 3.5G 2. This device must accept any interference, including interference that may cause undesired operation of the device.
modules, then the ap-
propriate antennas will FCC RF Radiation Exposure Statement:
be installed. Note that
In order to comply with
FCC RF exposure 1. This Transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
compliance require- 2. This equipment complies with FCC RF radiation exposure limits set forth for an uncontrolled environment. This equipment
ments, the antenna should be installed and operated with a minimum distance of 20 centimeters between the radiator and you body.
must not be co-located
or operate in conjunc-
tion with any other an-
tenna or transmitter.
IV
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit (DC Output 19V, 3.42A OR 18.5V, 3.5A (65W) mini-
mum AC/DC Adapter).
Preface
CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.
TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

TELECOMMUNICATION LINE CORD
This Computer’s Optical Device is a Laser Class 1 Product
V
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
VI
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:
• Only use a power adapter approved for use with this computer.
• Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
• The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do Power Safety
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one. Warning
• When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire. Before you undertake
• Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices. any upgrade proce-
• Before cleaning the computer, make sure it is disconnected from any external power supplies. dures, make sure that
you have turned off the
power, and discon-
Do not plug in the power Do not use the power cord if Do not place heavy objects nected all peripherals
cord if you are wet. it is broken. on the power cord. and cables (including
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VII
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not remove any batteries from the computer while it is powered on.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Preface

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of
its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal
waste stream. Check with your local solid waste officials for details in your area for recycling options or proper
disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommend-
ed by the manufacturer. Discard used battery according to the manufacturer’s instructions.
Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
VIII
Preface
Contents
Introduction ..............................................1-1 Part List Illustration Location ........................................................ A-2
Top with Fingerprint (M720T) ...................................................... A-3
Overview .........................................................................................1-1 Top without Fingerprint (M720T) ................................................. A-4
System Specifications ................................. 1-2 Bottom (M720T) ............................................................................ A-5
................................................... 1-4 LCD (M720T) ................................................................................ A-6
External Locator - Top View with LCD Panel Open ......................1-5 HDD (M720T) ............................................................................... A-7
External Locator - Front & Right side Views .................................1-6 COMBO (M720T) ......................................................................... A-8
External Locator - Left Side & Rear View .....................................1-7 DVD-Dual Drive (M720T) ............................................................ A-9
External Locator - Bottom View .....................................................1-8 Top with Fingerprint (M728T) .................................................... A-10
Mainboard Overview - Top (Key Parts) .........................................1-9 Top without Fingerprint (M728T) ............................................... A-11
Mainboard Overview - Bottom (Key Parts) ..................................1-10 Bottom (M728T) .......................................................................... A-12
Mainboard Overview - Top (Connectors) .....................................1-11 LCD (M728T) .............................................................................. A-13
Mainboard Overview - Bottom (Connectors) ...............................1-12
Preface
HDD (M728T) ............................................................................. A-14
Disassembly ...............................................2-1 COMBO (M728T) ....................................................................... A-15
Overview .........................................................................................2-1 DVD-Dual Drive (M728T) .......................................................... A-16
Maintenance Tools ..........................................................................2-2 Top with Fingerprint (M729T) .................................................... A-17
Connections .....................................................................................2-2 Top without Fingerprint (M729T) ............................................... A-18
Maintenance Precautions .................................................................2-3 Bottom (M729T) .......................................................................... A-19
Disassembly Steps ...........................................................................2-4 LCD (M729T) .............................................................................. A-20
Removing the Battery ......................................................................2-5 HDD (M729T) ............................................................................. A-21
Removing the Hard Disk Drive .......................................................2-6 COMBO (M729T) ....................................................................... A-22
Removing the Optical (CD/DVD) Device ......................................2-8 DVD-Dual Drive (M729T) .......................................................... A-23
Removing the System Memory (RAM) ........................................2-10 Top with Fingerprint (M730T) .................................................... A-24
Removing the Inverter Board ........................................................2-12 Top without Fingerprint (M730T) ............................................... A-25
Removing the Processor ................................................................2-13 Bottom (M730T) .......................................................................... A-26
Removing the Wireless LAN Module ...........................................2-15 LCD (M730T) .............................................................................. A-27
Removing the Bluetooth Module ..................................................2-16 HDD (M730T) ............................................................................. A-28
Removing the Keyboard ................................................................2-17 COMBO (M730T) ....................................................................... A-29
Removing the Modem ...................................................................2-18 DVD-Dual Drive (M730T) .......................................................... A-30
Part Lists ..................................................A-1 Schematic Diagrams................................. B-1
IX
Preface
System Block Diagram ................................................................... B-2 Multi I/O Board 1/2 ......................................................................B-34
Intel Penryn (Socket-P) 1/2 ............................................................ B-3 Multi I/O Board 2/2 ......................................................................B-35
Intel Penryn (Socket-P) 2/2 ............................................................ B-4 Finger Printer Board .....................................................................B-36
Cantiga 1/6 - Host .......................................................................... B-5 Click Board ...................................................................................B-37
Cantiga 2/6 - VGA, CRT ................................................................ B-6 M730T ODD Bridge Board ..........................................................B-38
Cantiga 3/6 - DDR .......................................................................... B-7 M730T Audio Board .....................................................................B-39
Cantiga 4/6 - Power ........................................................................ B-8 Power Sequence Diagram .............................................................B-40
Cantiga 5/6 - Power ........................................................................ B-9 Power Sequence v3.0 ....................................................................B-41
Cantiga 6/6 - GND ....................................................................... B-10
DDRII CHANNEL A ................................................................... B-11
DDRII CHANNEL B ................................................................... B-12
Panel, Inverter, CRT ..................................................................... B-13
ICH9-M 1/5 - SATA .................................................................... B-14
ICH9-M 2/5 - PCIE, PCI, USB .................................................... B-15
Preface
ICH9-M 3/5 - GPIO, PWR Management .................................... B-16

ICH9-M 4/5 - Power .................................................................... B-17
ICH9-M 5/5 - GND ...................................................................... B-18
Clock Generator ........................................................................... B-19
Multi I/O, ODD, CCD, BT, TPM ................................................ B-20
New Card, Mini PCIE .................................................................. B-21
LED, FAN, TP, FP, USB ............................................................. B-22
JMB385 Card Reader ................................................................... B-23
PCI-E LAN RTL8111C ............................................................... B-24
Audio Codec ALC662 .................................................................. B-25
Audio AMP2056 .......................................................................... B-26
KBC-ITE IT8512E ....................................................................... B-27
System Power, LED BKLT .......................................................... B-28
Power VDD3, VDD5 ................................................................... B-29
Power 1.5VS, 1.05VS, 3.3V, 5V .................................................. B-30
Power 1.8V, 0.9VSM ................................................................... B-31
Power VCORE ............................................................................. B-32
Power AC-IN, Charger ................................................................. B-33
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the M720T/M728T/M729T/M730T series notebook
computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual.
Information about drivers (e.g. VGA & audio) is also found in User’s Manual. That manual is shipped with the computer.
Operating systems (e.g. Windows XP, Windows Vista, etc.) have their own manuals as do application software (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
The M720T/M728T/M729T/M730T series notebook is designed to be upgradeable. See “Disassembly” on page 2 - 1
1.Introduction
for a detailed description of the upgrade procedures for each specific component. Please note the warning and safety in-
formation indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
System Specifications
Feature Specification
Processor Intel® Core™2 Duo Processor 45nm (45 Nanometer) Process Technology
35W - (478-pin) Micro-FC-PGA Package - Socket-P 6MB On-die L2 Cache & 1006MHz FSB
T9400/ T9600 2.53/ 2.8 GHz
Intel® Core™2 Duo Processor 45nm (45 Nanometer) Process Technology

25W - (478-pin) Micro-FC-PGA Package - Socket-P 3MB On-die L2 Cache & 1006MHz FSB
P8400/ P8600 2.4/ 2.53 GHz
Core Logic Intel GM45 + ICH9M Chipset
LCD M720T/M728T/M729T: M730T:

12.1" WXGA (1280 * 800) TFT LCD 13.3" WXGA (1280 * 800) TFT LCD
1.Introduction
Memory 64-bit Wide DDRII (DDR2) Data Channel

Supports Dual Channel DDRII (DDR2) SDRAM
Two 200 Pin SO-DIMM Sockets Supporting DDRII (DDR2) 667MHz/800MHz RAM Modules
Memory Expandable up to 4GB (1024/2048 MB DDR2 Modules)
Video Adapter Intel GM45 Integrated Video

High Preference 3D/2D Graphic Accelerator
Supports Dynamic Video Memory Technology DVMT (up to 256MB dynamically allocated from system memory where
needed)
Supports DirectX10 3D Graphics Engine Accelerator
Security Security (Kensington® Type) Lock Slot BIOS Password

Fingerprint ID Reader Module (Factory Option) Trusted Platform Module
BIOS One 32Mb SPI Flash ROM Phoenix™ BIOS
Storage One Changeable 12.7mm(h) SATA (Serial) Optical Device (CD/DVD) Type Drive (see “Optional” on page 1 - 4)
Easy Changeable 2.5" 9.5 mm (h) SATA (Serial) HDD
Audio High Definition Audio (HDA) Direct Sound 3D™ Compatible

Compliant with Microsoft UAA (Universal Audio 2 * Built-In Speakers
Architecture) Built-In Microphone
Keyboard & Winkey Keyboard Built-In TouchPad with Scrolling Function

Pointing Device
1 - 2 System Specifications
Introduction
Interface Three USB 2.0 Ports One RJ-11 Modem Jack
One Headphone-Out Jack One RJ-45 LAN Jack
One Microphone-In Jack One DC-In Jack
One S/PDIF Out Jack One External Monitor Port
One Internal Microphone
Card Reader Embedded 7-in-1 Card Reader (MS/ MS Pro/ SD/ Mini SD/ MMC/ RS MMC/ MS Duo) Note: MS Duo/ Mini SD/ RS
MMC Cards require a PC adapter
ExpressCard Slot One ExpressCard/34(54) Slot
Communication 10M/ 100/ 1000Mb Base-TX Ethernet LAN

Azalia 56K Modem V.90 & V.92 Compliant
*Note: The 3.5G Intel® WiFi Link 5300 Series (3*3 - 802.11a/g/n) Wireless LAN Mini-Card Module (Option)
1.Introduction
and Intel Turbo Intel® WiFi Link 5100 Series (1*2 - 802.11a/g/n) Wireless LAN Mini-Card Module (Option)
Memory Modules 3rd Party 802.11b/g Wireless LAN Mini-Card Module with USB interface (Option)
cannot coexist. There Bluetooth 2.0 + EDR (Enhanced Data Rate) Module (Factory Option)
is only one slot avail- 1.3M or 2.0M Pixel PC Camera Module with USB interface (Factory Option)
able for either of
these factory option 3.5G Module (see sidebar):
modules. *UMTS/HSPDA-based 3.5G Mini-Card Module with USB Interface (Factory Option)
Quad-band GSM/GPRS (850 MHz, 900 MHz, 1800 MHz, 1900 MHz)
UMTS WCDMA FDD (2100 MHz)

UMTS Modes
Note that UMTS modes CAN NOT be used in North America.
Power Supports ACPI 3.0 Supports Wake on LAN

Management Supports Resume from Modem Ring
Power Full Range AC/DC Adapter AC Input 100 - 240V, DC Output 50 - 60Hz, 19V, 3.42A or 18.5V, 3.5A (65 Watts)
Battery 4 Cell Smart Lithium-Ion Battery Pack, 14.8V/2.4AH

8 Cell Smart Lithium-Ion Battery Pack, 14.8V/4.4AH (Option)
System Specifications 1 - 3
Introduction
Environmental Temperature Relative Humidity
Spec Operating: 5°C - 35°C Operating: 20% - 80%
Non-Operating: -20°C - 60°C Non-Operating: 10% - 90%
Dimensions M720T/M728T/M729T: M730T:

& Weight 299mm (w) * 219mm (d) * 26.5-35.7mm (h) 310mm (w) * 233mm (d) * 30-36mm (h)
1.88 kg With 4 Cell Battery and ODD 2.0 kg With 4 Cell Battery and ODD
Optional Optical Drive Module Options: Fingerprint ID Reader Module (Factory Option)
SATA DVD/CD-RW Combo Drive Module
*Note: The 3.5G SATA DVD Dual (Super Multi) Drive Module *Intel Turbo Memory (Robson) NAND Flash Memory
and Intel Turbo Card Module (Factory Option)
Memory Modules Intel® WiFi Link 5300 Series (3*3 - 802.11a/g/n) Wireless OR
*UMTS/HSPDA-based 3.5G Module with Mini Card
1.Introduction
cannot coexist. There LAN Mini-Card Module

is only one slot avail- Intel® WiFi Link 5100 Series (1*2 - 802.11a/g/n) Wireless Interface (Factory Option)
able for either of LAN Mini-Card Module Quad-band GSM/GPRS (850 MHz, 900 MHz, 1800
these factory option 3rd Party 802.11b/g Wireless LAN Mini-Card Module with MHz, 1900 MHz)
modules. USB interface UMTS WCDMA FDD (2100 MHz)
8 Cell Smart Lithium-Ion Battery Pack

1.3M or 2.0M Pixel USB PC Camera Module (Factory UMTS Modes
Option)
Note that UMTS modes CAN NOT be used in
Bluetooth 2.0 + EDR (Enhanced Data Rate) Module North America.
(Factory Option)
1 - 4
Introduction
External Locator - Top View with LCD Panel Open Figure 1

Top View
1 1
1. Optional Built-In
PC Camera
2. LCD
3. Speakers
2 4. Power Button
2 5. Hot Key Buttons
6. LED Status
Indicators
7. Keyboard
3 3 8. Touchpad &
1.Introduction
4
4 11 6 5 Buttons
6 5 9. LED Power &
Communication
7
7 Indicators
10. Fingerprint
(Optional)
11. Built-In
8 Microphone
8
9 11 9 10 *Note: This model may have
10
M720T/M728T/M729T M730T either a fingerprint module or
card reader module, depend-
ing on your purchase configu-
6 ration.
6
5 4
5 4
External Locator - Top View with LCD Panel Open 1 - 5

Introduction
Figure 2 External Locator - Front & Right side Views

Front Views
1. LED Power &
Communication
Indicators
2. 7-in-1 Card
1
M720T/M728T/M729T
Reader
3. S/PDIF-Out Jack 2 3 4 5
4. Microphone-In
Jack M730T
5. Headphone-Out 1
Jack 2 3 4 5
1.Introduction
Figure 3
Right Side Views
1. Optical Device M720T/M728T/M729T
Drive Bay 1 4
2 3
2. USB 2.0 Port
3. RJ-11 Phone
Jack
4. Security Lock M730T
Slot 1
2 3 4
1 - 6 External Locator - Front & Right side Views

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. RJ-45 LAN Jack
M720T/M728T/M729T 3. External Monitor
6 Port
2 3 4 4. Vent/Fan Intake/
1 5 5 Outlet
5. 2 * USB 2.0 Ports
6. ExpressCard Slot
M730T
6
1.Introduction
2 3 4
1 5 5
1 M720T/M728T/M729T Figure 5
Rear View
1. Battery
1 M730T
External Locator - Left Side & Rear View 1 - 7

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery (M730T 8
Cell Battery 1 1
Pictured)
2
2. Hard Disk Bay
Cover 2
(3.5G Module 3
Location) 3
3. RAM & CPU Bay
1.Introduction
Cover
4. Vent/Fan Intake/ 4
Outlet
(M730T Only) 5 5 4
5. Speakers
(M730T Only) M720T/M728T/M729T M730T

Overheating
To prevent your com-

puter from overheating
make sure nothing
blocks the vent/fan in-
takes while the com-
puter is in use.
1 - 8 External Locator - Bottom View

Introduction
Mainboard Overview - Top (Key Parts) Figure 7

Mainboard Top
Key Parts
1. Transformer
2. VT6103L
3. ExpressCard
Connector
4. ENE MR510
5. KBC ITE IT8512E
1.Introduction
2
3 5
Mainboard Overview - Top (Key Parts) 1 - 9

Introduction
Figure 8 Mainboard Overview - Bottom (Key Parts)

Mainboard Bottom
Key Parts
1. CPU Socket (no

CPU installed)
2. Northbridge
3. Memory Slots
DDR2 SO-DIMM
4. ICS
5. Card Reader 1
Socket 8
6. Southbridge
1.Introduction
7. Audio Codec
8. Mini-Card
Connector (WLAN
Module)
2
4
6
7
1 - 10 Mainboard Overview - Bottom (Key Parts)

Introduction
Mainboard Overview - Top (Connectors) Figure 9

Mainboard Top
Connectors
1. Hot-key
1 Connector
2
2. LCD Cable
Connector
3. Keyboard Cable
Connector
4. Audio Board
Connector
5. Microphone
1.Introduction
Cable Connector
6. TouchPad Cable
Connector
4
6 5
Mainboard Overview - Top (Connectors) 1 - 11

Introduction
Figure 10 Mainboard Overview - Bottom (Connectors)

Mainboard Bottom
Connectors
7
1. BT Cable
Connector
2. Multi Board
Connector 1
3. CD-ROM 4
Connector
4. HDD Connector
5. CMOS Bat. 2
Connector
1.Introduction
6. CPU Fan Cable

Connector
7. DC-In Jack
8. USB Port
5 6 8
3
8
1 - 12 Mainboard Overview - Bottom (Connectors)

Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the M720T/M728T/M729T/M730T series notebook’s
parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re-
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
machine on.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Wireless LAN Module:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the wireless LAN page 2 - 15
To remove the HDD:
1. Remove the battery page 2 - 5 To remove the Bluetooth Module:
2. Remove the HDD page 2 - 6 1. Remove the battery page 2 - 5
2. Remove the Bluetooth page 2 - 16
2.Disassembly
To remove the Optical Device:

1. Remove the battery page 2 - 5 To remove the Keyboard:
2. Remove the Optical device page 2 - 8 1. Remove the battery page 2 - 5
2. Remove the keyboard page 2 - 17
To remove the System Memory:
1. Remove the battery page 2 - 5 To remove the Modem:
2. Remove the system memory page 2 - 10 1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 6
To remove the Inverter Board: 3. Remove the system memory page 2 - 10
4. Remove the Optical device page 2 - 8
1. Remove the battery page 2 - 5
5. Remove the processor page 2 - 13
2. Remove the inverter board page 2 - 12
6. Remove the keyboard page 2 - 17
7. Remove the modem page 2 - 18
To remove and install a Processor:
1. Remove the battery page 2 - 5
2. Remove the processor page 2 - 13
2 - 4 Disassembly Steps
Disassembly
Removing the Battery

1. Turn the computer off, and turn it over.
Figure 1
2. Slide the latch 1 in the direction of the arrow.
Battery Removal
3. Slide the latch 2 in the direction of the arrow, and hold it in place.
4. Slide the battery 63 in the direction of the arrow 4 . a. Slide the latch and hold
in place.
b. Slide the battery in the di-
a. rection of the arrow.
2.Disassembly
1
b.
3

3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual) when setting up a new hard disk.
a. Locate the HDD bay Hard Disk Upgrade Process

cover and remove the
screw(s).
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screw 1 & 2 .
a.
1
Note:
2.Disassembly
2
Only one model is pictured
here, however the compo-
nent locations are the same
for both models.

HDD System Warning
New HDD’s are blank. Before you begin make sure:
You have backed up any data you want to keep from your old HDD.
• 2 Screws You have all the CD-ROMs and FDDs required to install your operating system and programs.
If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan
to install. Copy these to a removable medium.
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 .

4. Grip the tab and slide the hard disk in the direction of arrow 4 . Figure 3
5. Lift the hard disk out of the bay 5 . HDD Assembly
Removal (cont’d.)
6. Remove the screw 6 & 7 and the adhesive cover 68 from the hard disk 69 .
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
c. Grip the tab and slide the
b. HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screw and
3
e. adhesive cover.
6
2.Disassembly
8
c.
7
d.
5

3. HDD Bay Cover
7. Adhesive Cover
8. HDD
• 2 Screws
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
Removal
2. M720T/M728T/M729T: (see over for M730T) Locate the component bay cover 1 and remove screws 2 - 5 .
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
a. Remove the screws.
b. Disconnect the fan cable 4. Carefully disconnect the fan cable 6 , and remove the cover 1 .
and remove the cover. 5. Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 .
c. Remove the screw. 6. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
d. Push the optical device screw holes should line up).
out off the computer at 7. Restart the computer to allow it to automatically detect the new device.
point 8.
a. c.
4
2.Disassembly
2 3 5
7
1
M720T/M728T/M729T
b. d.

1. Component Bay Cover
9. Optical Device 1 8
9
• 5 Screws 6
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
8. M730T: Locate the component bay cover 1 and remove screws 2 & 5 .
9. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover. Figure 5
10. Carefully disconnect the fan cable 6 and remove the bay cover 1 . Optical Device
11. Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 . Removal (cont’d.)
12. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
e. Remove the screws.
screw holes should line up).
f. Disconnect the fan cable
13. Restart the computer to allow it to automatically detect the new device. and remove the cover.
g. Remove the screw.
e. g. h. Push the optical device
4 out off the computer at
point 8.
2 3 5
2.Disassembly
1 7
M730T
f. h.

1 9 1. HDD Bay Cover
8 8. Optical Device
• 4 Screws
6
Removing the Optical (CD/DVD) Device 2 - 9

Disassembly
Figure 6
Removing the System Memory (RAM)
RAM Module The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
Removal DDR2 667/800MHz. The main memory can be expanded up to 4GB. The SO-DIMM modules supported are 1024MB,
and 2048MB and DDRII Modules. The total memory size is automatically detected by the POST routine once you turn
a. Remove the screws. on your computer.
b. Remove the cover.
Memory Upgrade Process

1. Turn off the computer, remove the battery (page 2 - 5).
2. Locate the component bay cover 1 , and remove screws 2 - 5 .
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
4. Carefully disconnect the fan cable 6 , and remove the cover 1 .
Contact Warning
2.Disassembly
Be careful not to touch a.

the metal pins on the 4 4
module’s connecting 3
2 5 2 3 5
edge. Even the clean-
est hands have oils
which can attract parti- 1
cles, and degrade the 1
module’s perfor-
mance.
M720T/M728T/M729T M730T
b.
Note:

1. Component Bay 1 Only one model is pictured
Cover here, however the compo-
• 3 Screws for both models.
2 - 10 Removing the System Memory (RAM)

Disassembly
5. Gently pull the two release latches ( 7 & 8 ) on the sides of the memory socket in the direction indicated by the Figure 7
arrows (Figure 7c). RAM Module
c. d. Removal (cont’d.)
c. Pull the release

7
latch(es).
d. Remove the module(s).
9
2.Disassembly
6. The RAM module(s) 9 will pop-up (Figure 7d), and you can then remove it.
7. Pull the latches to release the second module if necessary.
8. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
9. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
10. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
11. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
cover).
e.
Note:
here, however the compo-
for both models.
9. RAM Module(s)
12. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
Removing the System Memory (RAM) 2 - 11

Disassembly
Figure 8 Removing the Inverter Board

Inverter Board
Removal
2. Remove any rubber covers, screws 1 - 6 (Figure 8a), then run your finger around the middle of the frame to
carefully unsnap the LCD front panel module 7 from the back.
a. Remove the 6 screws
and unsnap the LCD 3. Discharge the remaining system power (see “Inverter Power Warning” below).
front panel module from 4. Remove screws 8 - 9 (Figure 8b) from the inverter, and carefully lift the inverter board up slightly.
the back. 5. Disconnect cables 10 & 11 (Figure 8c) from the inverter, then remove the inverter 12 (Figure 8d) from the top
b. Remove the screw and case assembly.
discharge the remaining
power from the inverter
board and lift the board a. b.
up slightly. 2 3 4 5
c. Disconnect the cables
2.Disassembly
from the inverter.

8 9
d. Remove the inverter.
c.
1 6
10 11
7
d.
12
7. LCD Front Panel Inverter Power Warning
12. Inverter Board
In order to prevent a short circuit when removing
the inverter it is necessary to discharge any re-
• 8 Screws maining system power. To do so, press the com-
puter’s power button for a few seconds before
disconnecting the inverter cable.
2 - 12 Removing the Inverter Board

Disassembly
Removing the Processor Figure 9

1. Turn off the computer, and remove the battery (page 2 - 5) and the CPU/RAM bay cover (page 2 - 10). Processor Removal
2. The CPU heat sink will be visible at point 1 on the mainboard.
3. Loosen screws 2 - 4 from the heat sink in the order indicated. a. Remove the cover and
4. Carefully lift up the heat sink 5 (Figure c) off the computer. Iocate the heat sink.
b. Remove the 3 screws in
the order indicated.
a. Note: c. Remove the heat sink.

1 here, however the compo-
for both models.
2.Disassembly
b.
3
c. 4

5. Heat Sink
Removing the Processor 2 - 13

Disassembly
5. Turn the release latch 6 towards the unlock symbol , to release the CPU (Figure d).
Figure 10 6. Carefully (it may be hot) lift the CPU 7 up out of the socket (Figure e).
Processor Removal 7. Reverse the process to install a new CPU.
Sequence 8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.
6
6
2.Disassembly
Unlock Lock
e.
7
Caution
The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Allow
the area time to cool before remov-
ing these parts.
7. CPU
2 - 14 Removing the Processor

Disassembly
Removing the Wireless LAN Module Figure 11

1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 10). Wireless LAN
2. The Wireless LAN module will be visible at point 1 on the mainboard. Module Removal
3. Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket.
4. The Wireless LAN module 5 will pop-up. a. Remove the cover.
b. Disconnect the cables
5. Lift the Wireless LAN module (Figure 11d) up and off the computer.
and remove the screw.
c. The WLAN module will
a. b. pop up.
d. Lift the WLAN module
out.
1 Note: 4
Only one model is pic- Note: Make sure you
2.Disassembly
tured here, however reconnect the antenna
the component loca- 3
cable to “1” + “2”
tions are the same for socket (Figure b).
both models. 2
c. d.

5 5. WLAN Module.
• 1 Screw
Removing the Wireless LAN Module 2 - 15

Disassembly
Figure 12 Removing the Bluetooth Module

Bluetooth Removal
1. Turn off the computer, remove the battery (page 2 - 5).
2. The Bluetooth module will be visible at point 1 on the mainboard.
a. Remove the cover and
locate the Bluetooth 3. Remove screw 2 and carefully disconnect the cable 3 and separate the module from the connector 4 .
module. 4. Lift the Bluetooth module 5 up and off the computer.
b. Remove the screw and
disconnect the cable and a. c.
seperate the connector.
c. Lift the Bluetooth module
out. 1
Note: 5
Only one model is pic-
2.Disassembly
tured here, however

the component loca-
tions are the same for
both models.
b.
2 3 4

5. Bluetooth Module
• 1 Screw
2 - 16 Removing the Bluetooth Module

Disassembly
Removing the Keyboard Figure 13

1. Turn off the computer, and remove the battery (page 2 - 5). Keyboard Removal
2. Press the three keyboard latches at the top of the keyboard to elevate the keyboard from its normal position (you
a. Press the three latches
may need to use a small screwdriver to do this).
to release the keyboard.
3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable (Figure 13b). b. Lift the keyboard up and
4. Disconnect the keyboard ribbon cable 4 from the locking collar socket 5 . disconnect the cable
5. Carefully lift up the keyboard 6 (Figure 13c) off the computer. from the locking collar.
c. Remove the keyboard.
a. b.
1 2 3
4

2.Disassembly
5
Re-Inserting the Key-
board
When re-inserting the

c. keyboard firstly align
the three keyboard
tabs at the bottom of
the keyboard with the
slots in the case.
6
6. Keyboard Module.
Keyboard Tabs
Removing the Keyboard 2 - 17

Disassembly
Removing the Modem

Figure 14
Modem Removal 1. Turn off the computer, remove the battery (page 2 - 5), HDD (page 2 - 6), component bay cover (page 2 - 10),
optical device (page 2 - 8), CPU (page 2 - 13), bluetooth (page 2 - 16) and keyboard (page 2 - 17).
a. Disconnect the connec-
2. Disconnect the connectors 1 - 3 from under the keyboard and turn it over.
tors from under the key- 3. Remove screws 4 - 5 from the rear of the computer.
board. a.
b. Remove the screws.
b.
c. Remove the screws and
disconnect the connec- 4 5
tors from the main-
board.
2
d. Remove the top case. 3
1
2.Disassembly
4. Remove the screws 6 - 21 from the bottom case and disconnect the connectors 22 - 23 on the mainboard.
5. Carefully lift up the top case 24 off the computer.
c. d.
16
7 6 15
18
22 21
17 23
24
8 19 14
20
13
24. Top Case
• 18 Screws 9 10 11 12
2 - 18 Removing the Modem

Disassembly
6. Remove screws 25 - 27 and disconnect the connectors 28 - 30 from the mainboard. Figure 15
7. Separate the bottom case 31 from the mainboard 32 and turn it over. Modem Removal
8. Remove the screws 33 - 34 and disconnect the connector 35 from the modem. Sequence
9. Lift the modem 37 up off the socket 36 .
e. g. e. Remove the screws and
and disconnect the con-
25 26
30 nectors.
28 33
f. Separate the bottom
29 34 case from the main-
board.
35 g. Remove the screws and
and disconnect the con-
nector.
h. Lift the modem up off
the socket.
2.Disassembly
27
f. h.
37
31 32
36
31. Bottom Case
32. Main Board
37. Modem
• 5 Screws
Removing the Modem 2 - 19

Disassembly
2.Disassembly
2 - 20
Part Lists
Appendix A: Part Lists

This appendix breaks down the M720T/M728T/M729T/M730T series notebook’s construction into a series of illustra-
tions. The component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part Lists
Part List Illustration Location

The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
Parts M720T M728T M729T M730T
Top with Fingerprint page A - 3 page A - 10 page A - 17 page A - 24

Top without Fingerprint page A - 4 page A - 11 page A - 18 page A - 25
Bottom page A - 5 page A - 12 page A - 19 page A - 26

A.Part Lists
LCD page A - 6 page A - 13 page A - 20 page A - 27

HDD page A - 7 page A - 14 page A - 21 page A - 28
COMBO page A - 8 page A - 15 page A - 22 page A - 29
DVD-Dual Drive page A - 9 page A - 16 page A - 23 page A - 30
A - 2 Part List Illustration Location

Part Lists
Top with Fingerprint (M720T)
Figure A - 1
Top with
A.Part Lists
Fingerprint
(M720T)
黑色無鉛
白色無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
型無鉛
型無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
材質無鉛
設變材質無鉛
Top with Fingerprint (M720T) A - 3

Part Lists
Top without Fingerprint (M720T)
Figure A - 2
Top without
A.Part Lists
Fingerprint
(M720T)
黑色無鉛
白色無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
型無鉛
型無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
材質無鉛
設變材質無鉛
A - 4 Top without Fingerprint (M720T)

Part Lists
Bottom (M720T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
凱碩無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
Figure A - 3
無鉛
Bottom
A.Part Lists
無鉛
無鉛
無鉛
(M720T)
無鉛
無鉛
無鉛
海華無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
側壁加肉無鉛
無鉛
無鉛
拉帶加長無鉛
無鉛
藍天3 互億無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
Bottom (M720T) A - 5
Part Lists
LCD (M720T)
Figure A - 4
LCD
A.Part Lists
(M720T) 無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
灰色精乘無鉛
黑色精乘無鉛
黑色精乘無鉛
無鉛
富佑鴻無鉛
無鉛
無鉛
無鉛
無鉛
中性無鉛
無鉛
無鉛
無鉛
無鉛
黑色精乘無鉛
無鉛
無鉛
無鉛
硬式保護膜透明無鉛
無鉛
A - 6 LCD (M720T)
Part Lists
HDD (M720T)
Figure A - 5
HDD
A.Part Lists
(M720T)
無鉛
無折切痕(設變)(無鉛)
HDD (M720T) A - 7
Part Lists
COMBO (M720T)
Figure A - 6
COMBO
A.Part Lists
(M720T)
無鉛
無鉛
無鉛
無鉛
觸點高度降低 (世華)無鉛
A - 8 COMBO (M720T)
Part Lists
DVD-Dual Drive (M720T)
Figure A - 7
DVD-Dual Drive
A.Part Lists
(M720T)
無鉛
無鉛
無鉛
無鉛
DVD-Dual Drive (M720T) A - 9

Part Lists
Figure A - 8
Top with
A.Part Lists
Fingerprint
(M728T)
黑色無鉛
無鉛
無鉛
無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
A - 10 Top with Fingerprint (M728T)

Part Lists
Figure A - 9
Top without
A.Part Lists
Fingerprint
(M728T)
黑色無鉛
無鉛
無鉛
無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
Top without Fingerprint (M728T) A - 11

Part Lists
Bottom (M728T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
凱碩無鉛
無鉛
無鉛
無鉛
無鉛
Figure A - 10
無鉛
無鉛
無鉛
Bottom
A.Part Lists
無鉛
無鉛
(M728T) 無鉛
無鉛
無鉛
無鉛
海華無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
側壁加肉無鉛
無鉛
無鉛
拉帶加長無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 12 Bottom (M728T)
Part Lists
LCD (M728T)
Figure A - 11
LCD
A.Part Lists
(M728T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
灰色精乘無鉛
黑色精乘無鉛
黑色精乘無鉛
無鉛
富佑鴻無鉛
無鉛
無鉛
無鉛
無鉛
中性電鑄薄膜鍍亮鉻偉鎮(無鉛
無鉛
無鉛
背膠無鉛
無鉛
LCD (M728T) A - 13
Part Lists
HDD (M728T)
Figure A - 12
HDD
A.Part Lists
(M728T)
無鉛
A - 14 HDD (M728T)
Part Lists
COMBO (M728T)
Figure A - 13
COMBO
A.Part Lists
(M728T)
無鉛
無鉛
無鉛
無鉛
COMBO (M728T) A - 15
Part Lists
Figure A - 14
DVD-Dual Drive
A.Part Lists
(M728T)
無鉛
無鉛
無鉛
無鉛
A - 16 DVD-Dual Drive (M728T)

Part Lists
Figure A - 15
Top with
A.Part Lists
Fingerprint
(M729T)
黑色無鉛
無鉛
無鉛
無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
Top with Fingerprint (M729T) A - 17

Part Lists
Figure A - 16
Top without
A.Part Lists
Fingerprint
(M729T)
黑色無鉛
無鉛
無鉛
無鉛
型無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
鋁箔無鉛
A - 18 Top without Fingerprint (M729T)

Part Lists
Bottom (M729T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
凱碩無鉛
無鉛
無鉛
無鉛
無鉛
Figure A - 17
無鉛
無鉛
無鉛
Bottom
A.Part Lists
無鉛
無鉛
無鉛
無鉛
(M729T)
無鉛
無鉛
海華無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
側壁加肉無鉛
無鉛
無鉛
拉帶加長無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
Bottom (M729T) A - 19
Part Lists
LCD (M729T)
Figure A - 18
LCD
A.Part Lists
(M729T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
灰色精乘無鉛
黑色精乘無鉛
黑色精乘無鉛
無鉛
富佑鴻無鉛
無鉛
無鉛
無鉛
無鉛
中性電鑄薄膜鍍亮鉻偉鎮(無鉛
無鉛
無鉛
無鉛
A - 20 LCD (M729T)
Part Lists
HDD (M729T)
Figure A - 19
HDD
A.Part Lists
(M729T)
無鉛
HDD (M729T) A - 21
Part Lists
COMBO (M729T)
Figure A - 20
COMBO
A.Part Lists
(M729T)
無鉛
無鉛
無鉛
無鉛
A - 22 COMBO (M729T)
Part Lists
Figure A - 21
DVD-Dual Drive
A.Part Lists
(M729T)
無鉛
無鉛
無鉛
無鉛
DVD-Dual Drive (M729T) A - 23

Part Lists
Figure A - 22
Top with
A.Part Lists
Fingerprint
(M730T)
黑色無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 24 Top with Fingerprint (M730T)

Part Lists
Figure A - 23
Top without
A.Part Lists
Fingerprint
(M730T)
黑色無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
Top without Fingerprint (M730T) A - 25

Part Lists
Bottom (M730T)
無鉛
兩個孔徑尺寸由改為無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
凱碩無鉛
Figure A - 24
無鉛
無鉛
無鉛
Bottom
A.Part Lists
無鉛
無鉛
(M730T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
黑色惠貿無鉛
無鉛
無鉛
無鉛
海華無鉛
無鉛
全卡無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
拉帶加長無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 26 Bottom (M730T)
Part Lists
LCD (M730T)
Figure A - 25
LCD
A.Part Lists
(M730T)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
黑色惠貿無鉛
無鉛
黑色惠貿無鉛
無鉛
無鉛
黑色惠貿無鉛
無鉛
中性電鑄薄膜鍍亮鉻無鉛
無鉛
無鉛
無鉛
黑色惠貿無鉛
無鉛
LCD (M730T) A - 27
Part Lists
HDD (M730T)
Figure A - 26
HDD
A.Part Lists
(M730T)
無鉛
A - 28 HDD (M730T)
Part Lists
COMBO (M730T)
Figure A - 27
COMBO
A.Part Lists
(M730T)
無鉛
無鉛
無鉛
無鉛
無鉛
COMBO (M730T) A - 29
Part Lists
Figure A - 28
DVD-Dual Drive
A.Part Lists
(M730T)
無鉛
無鉛
無鉛
無鉛
無鉛
A - 30 DVD-Dual Drive (M730T)

Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the M720T/M728T/M729T/M730T notebook’s PCB’s. The following table indi-
cates where to find the appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page Table B - 1

Schematic
System Block Diagram - Page B - 2 ICH9-M 3/5 - GPIO, PWR Management - Page B - 16 Power 1.5VS, 1.05VS, 3.3V, 5V - Page B - 30
Diagrams
Intel Penryn (Socket-P) 1/2 - Page B - 3 ICH9-M 4/5 - Power - Page B - 17 Power 1.8V, 0.9VSM - Page B - 31
B.Schematic Diagrams
Intel Penryn (Socket-P) 2/2 - Page B - 4 ICH9-M 5/5 - GND - Page B - 18 Power VCORE - Page B - 32
Cantiga 1/6 - Host - Page B - 5 Clock Generator - Page B - 19 Power AC-IN, Charger - Page B - 33
Cantiga 2/6 - VGA, CRT - Page B - 6 Multi I/O, ODD, CCD, BT, TPM - Page B - 20 Multi I/O Board 1/2 - Page B - 34
Cantiga 3/6 - DDR - Page B - 7 New Card, Mini PCIE - Page B - 21 Multi I/O Board 2/2 - Page B - 35
Cantiga 4/6 - Power - Page B - 8 LED, FAN, TP, FP, USB - Page B - 22 Finger Printer Board - Page B - 36
Cantiga 5/6 - Power - Page B - 9 JMB385 Card Reader - Page B - 23 Click Board - Page B - 37

Cantiga 6/6 - GND - Page B - 10 PCI-E LAN RTL8111C - Page B - 24 M730T ODD Bridge Board - Page B - 38
Version Note
DDRII CHANNEL A - Page B - 11 Audio Codec ALC662 - Page B - 25 M730T Audio Board - Page B - 39
The schematic dia-
grams in this chapter
DDRII CHANNEL B - Page B - 12 Audio AMP2056 - Page B - 26 Power Sequence Diagram - Page B - 40
are based upon ver-
Panel, Inverter, CRT - Page B - 13 KBC-ITE IT8512E - Page B - 27 Power Sequence v3.0 - Page B - 41 sion 6-7P-M72T6-005.
If your mainboard (or
ICH9-M 1/5 - SATA - Page B - 14 System Power, LED BKLT - Page B - 28 other boards) are a lat-
er version, please
ICH9-M 2/5 - PCIE, PCI, USB - Page B - 15 Power VDD3, VDD5 - Page B - 29 check with the Service
Center for updated di-
agrams (if required).
B - 1
Schematic Diagrams
System Block Diagram
A C- IN ,Ch ar ge r Sy st em Po we r
CLEVO M720T System Block Diagram
M ul ti I/ O Bo ar d VD D3 ,VD D5
14.318 MHz
S PK _R, R J- 11, L ED
C ol ck Ge ne rat or
Sy ste m Me mo ry
L ID , H OT K EY, U SB , 3 G
ID T In te l Pe nr yn Memory Termination 1. 05 VM, 1. 5V S
IC S9 LPR 36 3EG LF
64pins TSSOP Pr oc es sor
M 72 0T /M7 30 T Cl ic k 17. 1*8. 1*1. 2mm
D DR 2 1. 8V ,0. 9V
B oa rd 478pins uFCPGA
S O- DI MM 0
Soket P
M 73 0T OD D Bo ar d D DR 2 VC OR E
S O- DI MM 1
M 73 0T Au di o Bo ar d CR T Con ne ct or FS B
Sheet 1 of 40
< 15 " 0 .5" ~5 .5 " 667/800/1066 MHz 533/667/800 MHz
System Block LC D Con ne ct or,

< 8"
No rt h Br id ge Multi I/O
Board
Diagram
In ve rte r M730T
To uc h Pad
Co nn ec tor Ca nt ig a GM CH RJ-11 SPDIF MIC HP
INT SPK R
Sy na pt ic OUT IN OUT INT SPK L
M73 0T 1329 FCBGA
810602-1703 EC S PI RO M LED B AC KLI GH T
51 2K b DRI VE R 2 5*21 *2 .0 5mm M720T
Az al ia INT SPK L
MD C Aza li a C od ec
32.768 KHz AM P.
TP M1 .2 Mo du le Re alt ek ANP AC
M720T
EC X4 AL C66 2 A PA2 05 6A
I TE < =8 " INT SPK R
DM I MD C 48pins LQFP 28pins TSSOP
IT 85 12E /E X Co nn ec tor 9*9*1. 6mm 9. 8*6.4 *1.2 mm
128pins LQFP LP C 33 MHz
0 .5 "~ 11" 0. 1" ~1 3
14 *1 4*1. 6mm
S PI RO M
S ou th B ri dge INT MIC
A za li a 24 MHz
16 Mb
IC H9 -M 1" ~16 "
P CI 33 MHz
INT K /B EC S MB US
676 mBGA
P CI e 100 MHz <1 2"
Th erm al S ma rt Sm ar t 3 1*31 *2 .5 mm
Se nso r F AN Ba tt ery
32.768KHz Multi I/O LAN Ca rd Re ad er
aS C75 25 Board
Ne w Car d Min i ca rd REALTEK JMicron
SA TA
HD D 3G Ca rd / S oc ket S oc ke t RTL8111C JMB385
<1 2" Ra bos on ( US B4) ( US B2 ) 64pins QFN 128pins LQFP
SA TA I /II 3 .0 Gb /s
( USB 5) 9 *9*1.0 mm 14 *1 4*1. 4mm
SA TA I /II 3 .0 Gb /s <1 2" 25
SA TA M Hz
OD D
U SB 2. 0 480 Mbps 1 "~ 16 "
Min i PC Ie 7 IN1
Multi I/O
Board FINGER PRINTER BOARD Ech o Pe ak RJ-45 SO CKE T
U SB0 US B1 US B3 Bl ue too th C CD (U SB 11) WiF i/ Wi Max
( US B9) (U SB 7) Fin ge rP rin t
12 MHz
B - 2 System Block Diagram

Schematic Diagrams
Intel Penryn (Socket-P) 1/2
CPU ONLY SUPPORT TO 35W
U9 B
[4 ] H _ D # [ 6 3: 0 ] H _D # [ 63 : 0 ] [4 ]
H_ D# 0 E2 2 Y2 2 H _D # 32
U9 A H_ D# 1 F24 D [0 ]# D [ 32 ] # AB2 4 H _D # 33
[4 ] H _ A #[ 3 5 : 3 ] D [1 ]# D [ 33 ] #
H _A # 3 J4 H1 H_ A DS # [ 4] H_ D# 2 E2 6 V2 4 H _D # 34
H _A # 4 L5 A[3 ]# A DS # E2 H_ D# 3 G 22 D [2 ]# D [ 34 ] # V2 6 H _D # 35
GROUP_0
ADDR
DATA GRP 0
A[4 ]# BN R# H_ B NR # [4 ] D [3 ]# D [ 35 ] #
DATAGRP 2
H _A # 5 L4 G5 H_ B P RI# [ 4] H_ D# 4 F23 V2 3 H _D # 36
H _A # 6 K5 A[5 ]# B P RI# H_ D# 5 G 25 D [4 ]# D [ 36 ] # T 22 H _D # 37
H _A # 7 M3 A[6 ]# H5 H_ D# 6 E2 5 D [5 ]# D [ 37 ] # U2 5 H _D # 38
A[7 ]# D E F ER# H_ DE F E R # [4 ] D [6 ]# D [ 38 ] #
Sheet 2 of 40
H _A # 8 N2 F21 H_ D# 7 E2 3 U2 3 H _D # 39
H _A # 9 J1 A[8 ]# DRD Y # E1 H_ DR DY # [ 4] H_ D# 8 K2 4 D [7 ]# D [ 39 ] # Y2 5 H _D # 40
A[9 ]# D BSY# H_ DB S Y # [4 ] D [8 ]# D [ 40 ] #
H _A # 1 0 N3 H_ D# 9 G 24 W22 H _D # 41
H _A # 1 1 P5 A [1 0 ]# F1 H_ D# 1 0 J24 D [9 ]# D [ 41 ] # Y2 3 H _D # 42
Intel Penryn
A [1 1 ]# B R 0# H_ B RE Q # [4 ] D [ 1 0] # D [ 42 ] #
H _A # 1 2 P2 H_ D# 1 1 J23 W24 H _D # 43
H _A # 1 3 L2 A [1 2 ]# D2 0 H _I E R R # H_ D# 1 2 H 22 D [ 1 1] # D [ 43 ] # W25 H _D # 44
CONTROL
H _A # 1 4 P4 A [1 3 ]# IER R# B3 H_ D# 1 3 F26 D [ 1 2] # D [ 44 ] # AA2 3 H _D # 45
A [1 4 ]# I N I T# H_ INIT # [1 3 ] D [ 1 3] # D [ 45 ] #
H _A # 1 5 P1 H_ D# 1 4 K2 2 AA2 4 H _D # 46
(Socket-P) 1/2
H _A # 1 6 R1 A [1 5 ]# H4 H_ D# 1 5 H 23 D [ 1 4] # D [ 46 ] # AB2 5 H _D # 47
A [1 6 ]# LO C K # H _ L OC K # [ 4] D [ 1 5] # D [ 47 ] #
[ 4 ] H _ A D S TB # 0 M1 [4 ] H _ DS T B N# 0 J26 Y2 6 H _D S T B N # 2 [ 4 ]
A D S TB [ 0] # C1 H _C P U R S T# H 26 D S T B N[0 ]# DS T B N[2 ]# AA2 6
[ 4] H _ R E Q #[ 4 : 0 ] H _R E Q# 0 K3 R E S E T# F3 H_ CP U RS T # [4 ] [ 4 ] H _D S TB P #0 H 25 D S T B P [ 0] # D S TB P [ 2 ] # U2 2 H _D S T B P #2 [ 4]
R E Q[ 0 ] # RS[0 ]# H_ RS # 0 [4 ] [ 4 ] H _D I N V # 0 D INV [0 ]# DINV [2 ]# H _D I N V # 2 [ 4 ]
H _R E Q# 1 H2 F4
H _R E Q# 2 K2 R E Q[ 1 ] # RS[1 ]# G3 H_ RS # 1 [4 ]
R E Q[ 2 ] # RS[2 ]# H_ RS # 2 [4 ] [4 ] H _ D # [ 6 3: 0 ] H _D # [ 63 : 0 ] [4 ]
H _R E Q# 3 J3 G2 H_ T RDY # [4 ] H_ D# 1 6 N 22 AE2 4 H _D # 48
H _R E Q# 4 L1 R E Q[ 3 ] # T RD Y # H_ D# 1 7 K2 5 D [ 1 6] # D [ 48 ] # A D2 4 H _D # 49
R E Q[ 4 ] # D [ 1 7] # D [ 49 ] #
[4 ] H _ A #[ 3 5 : 3 ] G6 H_ HIT # [4 ] H_ D# 1 8 P2 6 AA2 1 H _D # 50
H _A # 1 7 Y2 H I T# E4 H_ D# 1 9 R 23 D [ 1 8] # D [ 50 ] # AB2 2 H _D # 51
H _A # 1 8 U5 A [1 7 ]# H I T M# H _ H I T M# [ 4] H_ D# 2 0 L23 D [ 1 9] # D [ 51 ] # AB2 1 H _D # 52
H _A # 1 9 R3 A [1 8 ]# AD 4 H_ D# 2 1 M 24 D [ 2 0] # D [ 52 ] # A C2 6 H _D # 53
DATA GRP 1
H _A # 2 0 W6 A [1 9 ]# B P M[ 0 ] # AD 3 H_ D# 2 2 L22 D [ 2 1] # D [ 53 ] # A D2 0 H _D # 54
GROUP_1
ADDR
DATAGRP 3
A [2 0 ]# B P M[ 1 ] # D [ 2 2] # D [ 54 ] #
H _A # 2 1 U4 AD 1 H_ D# 2 3 M 23 AE2 2 H _D # 55
XDP/ITP SIGNALS
H _A # 2 2 Y5 A [2 1 ]# B P M[ 2 ] # AC 4 H_ D# 2 4 P2 5 D [ 2 3] # D [ 55 ] # AF2 3 H _D # 56
A [2 2 ]# B P M[ 3 ] # D [ 2 4] # D [ 56 ] #
H _A # 2 3 U1 AC 2 H_ D# 2 5 P2 3 A C2 5 H _D # 57
H _A # 2 4 R4 A [2 3 ]# P RD Y # AC 1 H _P R E Q# H_ D# 2 6 P2 2 D [ 2 5] # D [ 57 ] # AE2 1 H _D # 58
H _A # 2 5 T5 A [2 4 ]# P R E Q# AC 5 H _T C K H_ D# 2 7 T24 D [ 2 6] # D [ 58 ] # A D2 1 H _D # 59
H _A # 2 6 T3 A [2 5 ]# TC K AA6 H _T D I H_ D# 2 8 R 24 D [ 2 7] # D [ 59 ] # A C2 2 H _D # 60
H _A # 2 7 W2 A [2 6 ]# T DI AB3 H_ D# 2 9 L25 D [ 2 8] # D [ 60 ] # A D2 3 H _D # 61
A [2 7 ]# TD O D [ 2 9] # D [ 61 ] #
H _A # 2 8 W5 AB5 H _T M S Layout Note: H_ D# 3 0 T25 AF2 2 H _D # 62
H _A # 2 9 Y4 A [2 8 ]# TM S AB6 H _T R S T# H_ D# 3 1 N 25 D [ 3 0] # D [ 62 ] # A C2 3 H _D # 63
A [2 9 ]# T R S T# D [ 3 1] # D [ 63 ] #
H _A # 3 0 U2 C2 0 0.5" max, Zo= 55 Ohms [ 4 ] H _D S TB N # 1 L26 AE2 5 H _D S T B N # 3 [ 4 ]
H _A # 3 1 V4 A [3 0 ]# D BR# M 26 D S T B N[1 ]# DS T B N[3 ]# AF2 4
H _A # 3 2 W3 A [3 1 ]# [ 4] H _ D S T B P # 1 N 24 D S T B P [ 1] # D S TB P [ 3 ] # A C2 0 H _D S T B P #3 [ 4]
A [3 2 ]# [ 4] H _ D I N V # 1 D INV [1 ]# DINV [3 ]# H _D I N V # 3 [ 4 ]
H _A # 3 3 AA4 THERM AL
H _A # 3 4 AB2 A [3 3 ]# AD 2 6 R2 6 C OM P 0
A [3 4 ]# G TL R E F C O MP [ 0 ]
H _A # 3 5 AA3 D 2 1 H _ P R OC H OT # C 23 MISC C O MP [ 1 ] U2 6 C OM P 1
V1 A [3 5 ]# P R OC H O T# A 2 4 H _ T H E R MD A _ R R 1 96 *1 0 mi l _s h o rt H_ T HE RM DA D 25 TEST1 AA1 C OM P 2
[4 ] H _ A D S TB # 1 A D S TB [ 1] # TH E R MD A H_ T HE RM DC TEST2 C O MP [ 2 ]
B 2 5 H _ T H E R MD C _ R R 1 95 *1 0 mi l _s h o rt C 24 Y1 C OM P 3
A6 T H E R MD C AF2 6 TEST3 C O MP [ 3 ]
[ 1 3 ] H _A 2 0 M# A5 A 2 0 M# C7 AF 1 TEST4 E5
I CH
[ 1 3] H _ F E R R # F E R R# T H E R MT R I P # P M_ T H R M T R I P # [ 5 , 1 3, 2 8 ] TEST5 DP RS T P # H _ D P R S T P # [ 5 , 1 3 , 31 ]
C4 A2 6 B5
[ 13 ] H _ I GN N E # IG NNE # C 3 TEST6 DP S L P # D2 4 H _ D P S L P # [ 1 3]
TEST7 D P W R# H _ DP W R# [ 4]
[1 3 ] H_ S T P CL K # D5 [ 4, 1 8 ] C P U_ B S E L 0 CP U_ B S E L 0 B2 2 D6 H _ P W R GD [ 1 3 ]
C6 S T P CL K # CP U_ B S E L 1 B2 3 B S E L[ 0 ] P W R G OO D D7
[ 1 3 ] H _I N TR L INT 0 HCLK [ 4, 1 8 ] C P U_ B S E L 1 B S E L[ 1 ] SL P# H _ CP US L P # [4 ]
[ 1 3 ] H _N MI B4 A2 2 C L K _ C P U _ B C LK [ 1 8] [ 4, 1 8 ] C P U_ B S E L 2 CP U_ B S E L 2 C 21 AE6 P S I # [ 31 ]
A3 L INT 1 BCL K[0 ] A2 1 B S E L[ 2 ] P S I#
[ 1 3 ] H _S M I # SM I# BCL K[1 ] C L K _ C P U _ B C LK # [ 18 ] MOL E X _ 47 4 30 -6 2 15
M4 C P U _ GT L R E F
N5 R S V D[0 1 ]
R S V D[0 2 ] 12mils
T2 R5 1 K _ 1 %_ 0 4 1. 0 5 V S
V3 R S V D[0 3 ]
R S V D[0 4 ]
B2
RESERVED
R S V D[0 5 ] CPU_GRFE=0.7V
D2 Layout Note: C7 C8 R4
D 22 R S V D[0 6 ]
R S V D[0 7 ]
D3 Put it at central of *1 U _ 6 . 3V _ X 5 R _ 06 0. 0 1 U _ 1 6V _ X 7R _ 04 2 K _1 % _0 4
F6 R S V D[0 8 ]
R S V D[0 9 ] CPU socket
TR 1
10mils
C P U TE M P [2 6 ] Layout note:
MOL E X _ 47 4 30 -6 2 15
*T S M 1A 1 0 3 H 3 4D 3R COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
COMP1, COMP3: 0.5" Max, Zo=55 Ohms
Best estimate is 18 mils wide trace for outer
layers and 14 mils wide trace if on internal
1. 0 5 V S layers.
R 19 7 56 _ 0 4 H _I E R R # R2 1 0 *1 0 m li _ sh o rt
3 .3 V V _ TH R M V _T H R M C OM P0
R 7 54 . 9 _ 1% _ 04 H _P R E Q# Q 18 *A O 3 40 9 C OM P1
S D C OM P2
R 18 1 54 . 9 _ 1% _ 04 H _T D I C OM P3
C3 3 7
R 17 4 54 . 9 _ 1% _ 04 H _T MS *0 . 0 1U _ 16 V _ X 7R _0 4 R2 0 0 C 3 36 R1 9 4
G
R 19 8 54 . 9 _ 1% _ 04 H _P R OC H OT # *1 0 0K _ 0 4 1 U _6 . 3 V _ 04 1 0K _ 0 4 R8 R6 R1 8 2 R1 8 3
R 2 09
R 19 *5 1 _1 % _0 4 H _C P U R S T# R2 1 1 5 4. 9 _ 1 %_ 0 4 2 7. 4 _ 1 %_ 0 4 5 4. 9 _ 1 %_ 0 4 2 7. 4 _ 1 %_ 0 4
* 33 0 K _ 04 *1 00 K _ 0 4 U1 3 R1 9 2 *1 0 mi l _s h o rt D 15
1 4 A S D 7 5 1V T H E R M_ A L E R T # [ 2 6]
VD D T HER M
H _ TH E R M D A 2 6 R1 9 3 * 0_ 0 4 C A P M _T H R M# [1 5 ]
D + AL ER T
H _T C K
D
R 17 3 54 . 9 _ 1% _ 04 Q1 9 C 3 35
1 0 0 0P _ 5 0 V _X 7 R _ 0 4
R 17 1 64 9 _ 1% _ 06 H _T R S T# G 3 7
[2 6 ] T H E R M_ R S T # D - S D A TA S M D _ C P U _T H E R M [ 26 ]
*2 N 7 0 02 W H _ TH E R M D C 5 8
G ND S C LK S M C _ C P U _T H E R M [ 26 ]
S
aS C 75 2 5
? ADT7421 Colay
Layout Note: Layout Note:

Route H_THERMDA and Near to Thermal
H_THERMDC on same layer. IC
10 mil trace on 10 mil spacing.
[ 3 . . 5 , 7 , 8, 1 3 , 16 , 2 9 ] 1 . 0 5V S
[ 1 2. . 1 7 , 1 9, 2 0 , 23 , 2 9 , 30 ] 3. 3 V
Intel Penryn (Socket-P) 1/2 B - 3

Schematic Diagrams
Intel Penryn (Socket-P) 2/2
VCO R E
V C OR E V C OR E U 9D
U9 C 47A A4 P6
VS S [ 0 0 1] VSS [ 0 82 ]
A7 AB2 0 A8 P2 1
A9 V CC [ 0 0 1] VC C[ 06 8 ] AB7 A1 1 VS S [ 0 0 2] VSS [ 0 83 ] P2 4 C3 2 3 C 321 C 319 C 2 82 C 28 3
V CC [ 0 0 2] VC C[ 06 9 ] VS S [ 0 0 3] VSS [ 0 84 ]
A1 0 A C7 A1 4 R2
V CC [ 0 0 3] VC C[ 07 0 ] VS S [ 0 0 4] VSS [ 0 85 ]
A1 2 A C9 A1 6 R5 10 U _ 6 . 3V _ X5 R _ 08 1 0 U _ 6. 3 V _X 5 R _0 8 1 0 U _6 . 3 V _ X 5 R _ 0 8 1 0 U_ 6 .3 V _ X 5 R_ 0 8 1 0 U_ 6 .3 V _ X 5 R_ 0 8
A1 3 V CC [ 0 0 4] VC C[ 07 1 ] A C1 2 A1 9 VS S [ 0 0 5] VSS [ 0 86 ] R2 2
A1 5 V CC [ 0 0 5] VC C[ 07 2 ] A C1 3 A2 3 VS S [ 0 0 6] VSS [ 0 87 ] R2 5
V CC [ 0 0 6] VC C[ 07 3 ] VS S [ 0 0 7] VSS [ 0 88 ]
A1 7 A C1 5 AF2 T1
A1 8 V CC [ 0 0 7] VC C[ 07 4 ] A C1 7 B6 VS S [ 0 0 8] VSS [ 0 89 ] T4
A2 0 V CC [ 0 0 8] VC C[ 07 5 ] A C1 8 B8 VS S [ 0 0 9] VSS [ 0 90 ] T 23 VCO R E
V CC [ 0 0 9] VC C[ 07 6 ] VS S [ 0 1 0] VSS [ 0 91 ]
B7 A D7 B1 1 T 26
B9 V CC [ 0 1 0] VC C[ 07 7 ] A D9 B1 3 VS S [ 0 1 1] VSS [ 0 92 ] U3
B1 0 V CC [ 0 1 1] VC C[ 07 8 ] A D1 0 B1 6 VS S [ 0 1 2] VSS [ 0 93 ] U6
V CC [ 0 1 2] VC C[ 07 9 ] VS S [ 0 1 3] VSS [ 0 94 ]
B1 2 A D1 2 B1 9 U2 1 C2 8 0 C 320 C 318 C 3 22 C 33 3
B1 4 V CC [ 0 1 3] VC C[ 08 0 ] A D1 4 B2 1 VS S [ 0 1 4] VSS [ 0 95 ] U2 4
B1 5 V CC [ 0 1 4] VC C[ 08 1 ] A D1 5 B2 4 VS S [ 0 1 5] VSS [ 0 96 ] V2 22 U _ 6 . 3V _ X5 R _ 08 2 2 U _ 6. 3 V _X 5 R _0 8 2 2 U _6 . 3 V _ X 5 R _ 0 8 2 2 U_ 6 .3 V _ X 5 R_ 0 8 2 2 U_ 6 .3 V _ X 5 R_ 0 8
V CC [ 0 1 5] VC C[ 08 2 ] VS S [ 0 1 6] VSS [ 0 97 ]
B1 7 A D1 7 C 5 V5
B1 8 V CC [ 0 1 6] VC C[ 08 3 ] A D1 8 C 8 VS S [ 0 1 7] VSS [ 0 98 ] V2 2
B2 0 V CC [ 0 1 7] VC C[ 08 4 ] AE9 C1 1 VS S [ 0 1 8] VSS [ 0 99 ] V2 5
V CC [ 0 1 8] VC C[ 08 5 ] VS S [ 0 1 9] VSS [ 1 00 ]
C9 AE1 0 C1 4 W1
C1 0 V CC [ 0 1 9] VC C[ 08 6 ] AE1 2 C1 6 VS S [ 0 2 0] VSS [ 1 01 ] W4 VCO R E
C1 2 V CC [ 0 2 0] VC C[ 08 7 ] AE1 3 C1 9 VS S [ 0 2 1] VSS [ 1 02 ] W23
V CC [ 0 2 1] VC C[ 08 8 ] VS S [ 0 2 2] VSS [ 1 03 ]
C1 3 AE1 5 C 2 W26
C1 5 V CC [ 0 2 2] VC C[ 08 9 ] AE1 7 C2 2 VS S [ 0 2 3] VSS [ 1 04 ] Y3
C1 7 V CC [ 0 2 3] VC C[ 09 0 ] AE1 8 C2 5 VS S [ 0 2 4] VSS [ 1 05 ] Y6 C3 3 0 C 37 C 281 C 38 C 36
V CC [ 0 2 4] VC C[ 09 1 ] VS S [ 0 2 5] VSS [ 1 06 ]
C1 8 AE2 0 D 1 Y2 1
V CC [ 0 2 5] VC C[ 09 2 ] VS S [ 0 2 6] VSS [ 1 07 ]
D9 AF9 D 4 Y2 4 22 U _ 6 . 3V _ X5 R _ 08 2 2 U _ 6. 3 V _X 5 R _0 8 2 2 U _6 . 3 V _ X 5 R _ 0 8 2 2 U_ 6 .3 V _ X 5 R_ 0 8 2 2 U_ 6 .3 V _ X 5 R_ 0 8
D1 0 V CC [ 0 2 6] VC C[ 09 3 ] AF1 0 D 8 VS S [ 0 2 7] VSS [ 1 08 ] AA2
V CC [ 0 2 7] VC C[ 09 4 ] VS S [ 0 2 8] VSS [ 1 09 ]
D1 2 AF1 2 D1 1 AA5
V CC [ 0 2 8] VC C[ 09 5 ] VS S [ 0 2 9] VSS [ 1 10 ]
D1 4 AF1 4 D1 3 AA8
D1 5 V CC [ 0 2 9] VC C[ 09 6 ] AF1 5 D1 6 VS S [ 0 3 0] VSS [ 1 11 ] AA1 1
Sheet 3 of 40
V CC [ 0 3 0] VC C[ 09 7 ] VS S [ 0 3 1] VSS [ 1 12 ] VCO R E
D1 7 AF1 7 D1 9 AA1 4
V CC [ 0 3 1] VC C[ 09 8 ] VS S [ 0 3 2] VSS [ 1 13 ]
D1 8 AF1 8 D2 3 AA1 6
E7 V CC [ 0 3 2] VC C[ 09 9 ] AF2 0 1 . 05 V S D2 6 VS S [ 0 3 3] VSS [ 1 14 ] AA1 9
V CC [ 0 3 3] VC C[ 10 0 ] VS S [ 0 3 4] VSS [ 1 15 ]
Intel Penryn
E9 2.5A E3 AA2 2
V CC [ 0 3 4] VS S [ 0 3 5] VSS [ 1 16 ]
E1 0 G2 1 E6 AA2 5 C2 9 6 C 302 C 295 C 3 01 C 27 8 C3 3 2
E1 2 V CC [ 0 3 5] VC CP [0 1 ] V6 E8 VS S [ 0 3 6] VSS [ 1 17 ] AB1
V CC [ 0 3 6] VC CP [0 2 ] VS S [ 0 3 7] VSS [ 1 18 ]
E1 3 J6 E1 1 AB4 1U _ 6 . 3 V _ 0 4 1 U _ 6 . 3V _ 04 1 U _ 6. 3 V _0 4 1 U _6 . 3 V _ 0 4 1 U_ 6 .3 V _ 0 4 1 U_ 6 .3 V _ 0 4
(Socket-P) 2/2
V CC [ 0 3 7] VC CP [0 3 ] VS S [ 0 3 8] VSS [ 1 19 ]
E1 5 K6 E1 4 AB8
E1 7 V CC [ 0 3 8] VC CP [0 4 ] M6 E1 6 VS S [ 0 3 9] VSS [ 1 20 ] AB1 1
E1 8 V CC [ 0 3 9] VC CP [0 5 ] J2 1 E1 9 VS S [ 0 4 0] VSS [ 1 21 ] AB1 3
V CC [ 0 4 0] VC CP [0 6 ] VS S [ 0 4 1] VSS [ 1 22 ]
E2 0 K2 1 Layout Note: E2 1 AB1 6
F7 V CC [ 0 4 1] VC CP [0 7 ] M2 1 E2 4 VS S [ 0 4 2] VSS [ 1 23 ] AB1 9 VCO R E
F9 V CC [ 0 4 2] VC CP [0 8 ] N2 1 F5 VS S [ 0 4 3] VSS [ 1 24 ] AB2 3
V CC [ 0 4 3] VC CP [0 9 ] Place near pin B26, C26 VS S [ 0 4 4] VSS [ 1 25 ]
F10 N6 F8 AB2 6
F12 V CC [ 0 4 4] VC CP [1 0 ] R2 1 1. 5 V S F11 VS S [ 0 4 5] VSS [ 1 26 ] AC 3
F14 V CC [ 0 4 5] VC CP [1 1 ] R6 F13 VS S [ 0 4 6] VSS [ 1 27 ] AC 6 C3 2 9 C 305 C 39 C 3 34 C 32 4 C3 0 3
V CC [ 0 4 6] VC CP [1 2 ] 0.5A VS S [ 0 4 7] VSS [ 1 28 ]
F15 T2 1 F16 AC 8
F17 V CC [ 0 4 7] VC CP [1 3 ] T6 F19 VS S [ 0 4 8] VSS [ 1 29 ] A C 11 1U _ 6 . 3 V _ 0 4 1 U _ 6 . 3V _ 04 1 U _ 6. 3 V _0 4 1 U _6 . 3 V _ 0 4 1 U_ 6 .3 V _ 0 4 1 U_ 6 .3 V _ 0 4
F18 V CC [ 0 4 8] VC CP [1 4 ] V2 1 C 3 28 C 32 7 F2 VS S [ 0 4 9] VSS [ 1 30 ] A C 14
V CC [ 0 4 9] VC CP [1 5 ] VS S [ 0 5 0] VSS [ 1 31 ]
F20 W21 F22 A C 16
AA7 V CC [ 0 5 0] VC CP [1 6 ] 0 .0 1 U_ 1 6 V _ X 7 R_ 0 4 1 0 U_ 6 .3 V _ X 5 R_ 0 8 F25 VS S [ 0 5 1] VSS [ 1 32 ] A C 19
AA9 V CC [ 0 5 1] B2 6 G 4 VS S [ 0 5 2] VSS [ 1 33 ] A C 21
V CC [ 0 5 2] V C CA [0 1 ] VS S [ 0 5 3] VSS [ 1 34 ] VCO R E
AA1 0 C2 6 G 1 A C 24
AA1 2 V CC [ 0 5 3] V C CA [0 2 ] G2 3 VS S [ 0 5 4] VSS [ 1 35 ] AD 2
AA1 3 V CC [ 0 5 4] A D6 G2 6 VS S [ 0 5 5] VSS [ 1 36 ] AD 5
V CC [ 0 5 5] VI D[0 ] H _V ID0 [3 1 ] VS S [ 0 5 6] VSS [ 1 37 ]
AA1 5 AF5 H _V ID1 [3 1 ] H 3 AD 8
AA1 7 V CC [ 0 5 6] VI D[1 ] AE5 H 6 VS S [ 0 5 7] VSS [ 1 38 ] A D 11 C2 9 9 C 298 C 279 C 3 31 C 30 4 C2 9 1
AA1 8 AF4 H2 1 A D 13
AA2 0 AE3 H _V ID4 [3 1 ] H2 4 A D 16 0. 01 U _ 16 V _X 7 R _0 4 0 . 1 U _ 10 V _X 7 R _0 4 0 . 1 U _1 0 V _ X 7 R _ 0 4 0 .1 U_ 1 0 V _ X 7 R_ 0 4 0 .1 U_ 1 0 V _ X 7 R_ 0 4 0 . 0 1U _ 1 6 V _ X7 R _ 0 4
V CC [ 0 5 9] VI D[4 ] VS S [ 0 6 0] VSS [ 1 41 ]
AB9 AF3 H _V ID5 [3 1 ] J2 A D 19
A C1 0 V CC [ 0 6 0] VI D[5 ] AE2 J5 VS S [ 0 6 1] VSS [ 1 42 ] A D 22
AB1 0 J22 A D 25
V CC [ 0 6 2] VS S [ 0 6 3] VSS [ 1 44 ]
AB1 2 J25 AE1
AB1 4 V CC [ 0 6 3] AF7 K1 VS S [ 0 6 4] VSS [ 1 45 ] AE4
V CC [ 0 6 4] V CC S E N S E C P U_ V C C S E N S E [ 3 1] VS S [ 0 6 5] VSS [ 1 46 ]
AB1 5 K4 AE8
V CC [ 0 6 5] VS S [ 0 6 6] VSS [ 1 47 ]
AB1 7 K2 3 AE1 1
AB1 8 V CC [ 0 6 6] AE7 K2 6 VS S [ 0 6 7] VSS [ 1 48 ] AE1 4
V CC [ 0 6 7] VS SSEN SE C P U_ V S S S E N S E [3 1 ] VS S [ 0 6 8] VSS [ 1 49 ] 1 .0 5 VS
L3 AE1 6
VS S [ 0 6 9] VSS [ 1 50 ]
MO L E X _4 7 4 3 0 -6 21 5 L6 AE1 9
L21 VS S [ 0 7 0] VSS [ 1 51 ] AE2 3
. VS S [ 0 7 1] VSS [ 1 52 ]
L24 AE2 6
VS S [ 0 7 2] VSS [ 1 53 ]
M2 A2 C3 1 3 C 309 C 316 C 3 11 C 31 C1 7
M5 VS S [ 0 7 3] VSS [ 1 54 ] AF6
M2 2 VS S [ 0 7 4] VSS [ 1 55 ] AF8 15 0 U _ 4V _B 2 0 . 1 U _ 10 V _X 7 R _0 4 0 . 1 U _1 0 V _ X 7 R _ 0 4 0 .1 U_ 1 0 V _ X 7 R_ 0 4 0 .1 U_ 1 0 V _ X 7 R_ 0 4 0 . 1 U _ 1 0 V _ X 7R _ 0 4
VS S [ 0 7 5] VSS [ 1 56 ]
M2 5 AF1 1
N 1 VS S [ 0 7 6] VSS [ 1 57 ] AF1 3
N 4 VS S [ 0 7 7] VSS [ 1 58 ] AF1 6
VS S [ 0 7 8] VSS [ 1 59 ]
N2 3 AF1 9
N2 6 VS S [ 0 7 9] VSS [ 1 60 ] AF2 1 1 .0 5 VS
P3 VS S [ 0 8 0] VSS [ 1 61 ] A2 5
VS S [ 0 8 1] VSS [ 1 62 ]
AF2 5
VSS [ 1 63 ]
M O LE X_ 4 7 4 3 0- 62 1 5 C3 1 2 C 308 C 315 C 35 C 36 2
.
*0 . 1 U _ 1 0 V _ X 7 R _ 0 4 * 0 .1 U_ 1 0 V _ X 7 R_ 0 4 * 0 . 1 U _ 1 0 V _ X 7R _ 0 4 * 0. 1U _ 1 0V _ X7 R _ 04 0 .1 U_ 1 0 V _ X 7 R_ 0 4
[ 2 , 4 , 5 , 7, 8, 13 , 1 6 , 2 9 ] 1. 05 V S
[ 8 , 13 , 1 4 , 1 6 , 1 9 , 2 0, 29 ] 1 . 5 V S
[ 31 ] V C OR E
B - 4 Intel Penryn (Socket-P) 2/2

Schematic Diagrams
Cantiga 1/6 - Host

U15A
H_A#[ 35: 3
] [2]
A14 H_A#3
[2] H_D#[63:0] H_D#0 F2 H_
A#_3 C15 H_A#4
H_D#1 G8 H_D#_0 H_
A#_4 F16 H_A#5
H_D#_1 H_
A#_5
H_D#2 F8 H13 H_A#6
H_D#_2 H_
A#_6
H_D#3 E6 C18 H_A#7
H_D#_3 H_
A#_7
H_D#4 G2 M16 H_A#8 CPU_BSEL[2:0] (FSB) D AEFULT SETTING
H_D#5 H6 H_D#_4 H_
A#_8 J13 H_A#9
H_D#6 H2 H_D#_5 H_
A#_9 P16 H_A#10
H_D#_6 H_A#_10 CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
H_D#7 F6 R16 H_A#11
H_D#_7 H_A#_11
H_D#8 D4 N17 H_A#12 266 L L L
H_D#9 H3 H_D#_8 H_A#_12 M13 H_A#13
H_D#10 M9 H_D#_9 H_A#_13 E17 H_A#14
H_D#_10 H_A#_14 200 L H L
H_D#11 M11 P17 H_A#15
H_D#_11 H_A#_15
H_D#12 J1 F17 H_A#16 166 L H H
H_D#13 J2 H_D#_12 H_A#_16 G20 H_A#17
H_D#14 N12 H_D#_13 H_A#_17 B19 H_A#18
H_D#15 J6 H_D#_14 H_A#_18 J16 H_A#19
H_D#_15 H_A#_19
H_D#16 P2 E20 H_A#20
H_D#_16 H_A#_20
H_D#17 L2 H16 H_A#21
H_D#18 R2 H_D#_17 H_A#_21 J20 H_A#22
H_D#19 N9 H_D#_18 H_A#_22 L17 H_A#23
H_D#_19 H_A#_23
H_D#20 L6 A17 H_A#24
H_D#_20 H_A#_24
H_D#21 M5 B17 H_A#25
H_D#22 J3 H_D#_21 H_A#_25 L16 H_A#26
H_D#23 N2 H_D#_22 H_A#_26 C21 H_A#27 1.05VS
H_D#_23 H_A#_27
H_D#24 R1 J17 H_A#28
H_D#_24 H_A#_28
H_D#25 N5 H20 H_A#29
H_D#_25 H_A#_29
H_D#26 N6 B18 H_A#30
H_D#27 P13 H_D#_26 H_A#_30 K17 H_A#31 R208
H_D#28 N8 H_D#_27 H_A#_31 B20 H_A#32
H_D#_28 H_A#_32
H_D#29 L7 F21 H_A#33 *56_04
H_D#_29 H_A#_33
H_D#30
H_D#31
H_D#32
N10
M3
Y3
H_D#_30
H_D#_31
H_D#_32
H_A#_34
H_A#_35
K21
L20
H_A#34
H_A#35
[2,18] CPU_BSEL0 CLK_BSEL0 [2,18] Sheet 4 of 40
H_D#33 AD14 H12
H_D#34
H_D#35
H_D#36
Y6
Y10
Y12
H_D#_33
H_D#_34
H_D#_35
H_
H_
H_ADS#
ADST
ADST
B#_0
B#_1
B16
G17
A9
H_ADS# [2]
H_ADSTB#0 [2]
H_ADSTB#1 [2]
R202
1K_04
R203
1K_0
4
Cantiga 1/6 - Host
H_D#_36 H_BNR# H_BNR# [2]
H_D#37 Y14 F11
H_D#_37 H_BPRI # H_BPRI# [2]
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BREQ# [2] MCH_BSEL0 [ 5
]
HOST
H_D#39 W2 E9 H_DEFER# [2]
H_D#40 AA8 H_D#_39 H_DEFER# B10
H_D#_40 H_DBSY# H_DBSY# [2]
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK [18] 1.05VS
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# [ 1
8]
H_D#43 AA9 J11
H_D#44 AA11 H_D#_43 H_DPWR# F9 H_DPWR# [ 2 ]
H_D#_44 H_DRDY# H_DRDY# [2]
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HI T
# [2]
H_D#46 AD10 E12 R206
H_D#_46 H_HITM# H_HI T
M# [2]
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LO CK# [2]
H_D#48 AE12 C9 H_TRDY# [2] 1K_0
4
H_D#49 AE9 H_D#_48 H_TRDY#
H_D#50 AA2 H_D#_49
H_D#_50 [2,18] CPU_BSEL1 CLK_BSEL1 [2,18]
H_D#51 AD8
H_D#_51
H_D#52 AA3
H_D#53 AD3 H_D#_52 J8 R207
H_D#_53 H_DINV#_0 H_DI NV#0 [2]
C PU R 213 R29 H_D#54 AD7 L3
H_D#_54 H_DINV#_1 H_DI NV#1 [2]
H_D#55 AE14 Y13 1K_0
4
H_D#_55 H_DINV#_2 H_DI NV#2 [2]
Dual Core 100_1%_04 24.9_1%_04 H_D#56 AF3 Y1
H_D#57 AC1 H_D#_56 H_DINV#_3 H_DI NV#3 [2]
H_D#_57 MCH_BSEL1 [ 5
]
Quad Core 75_1%_04 16.9_1%_04 H_D#58 AE3 L10
H_D#_58 H_DSTBN#_0 H_DSTBN#0 [2]
H_D#59 AC3 M7
H_D#_59 H_DSTBN#_1 H_DSTBN#1 [2] 1.05VS
H_D#60 AE11 AA5
H_D#_60 H_DSTBN#_2 H_DSTBN#2 [2]
H_D#61 AE8 AE6 H_DSTBN#3 [2]
H_D#62 AG2 H_D#_61 H_DSTBN#_3
H_D#63 AD6 H_D#_62 L9
H_SWING H_D#_63 H_
DSTBP#_0 H_DSTBP#0 [2]
M8 R205
H_
12mils AA6
R2
12 221_1%_04 C5 H_
DSTBP#_2 AE5 H_DSTBP#2 [2] 1K_0
4
1.05VS H_SWING H_
E3
H_RCOMP
B15
H_REQ#_0 H_REQ#0 [2] [2,18] CPU_BSEL2 CLK_BSEL2 [2,18]
R213 C353 R29 24.9_1
%_04 K13
H_REQ#_1 H_REQ#1 [2]
F13 H_REQ#2 [2]
100_
1%_04 0.1U_10V_X
7R_04 H_REQ#_2 B13 R204
H_REQ#_3 H_REQ#3 [2]
C12 B14
H_CPURST# H_REQ#_4 H_REQ#4 [2]
E11 1K_0
4
H_CPUSLP#
B6
H_VREF H_RS#_0 F12 H_RS#0 [2]
[2] H_CPURST# H_RS#_1 H_RS#1 [2] MCH_BSEL2 [ 5
]
C8
[2] H_CPUSLP# H_RS#_2 H_RS#2 [2]
12mils A11
H_AVREF
R2
19 1K_1%_04 B11
1.05VS H_DVREF
CANTIGA-EB8
8CTGM
R218 C366 C363
2K_1%_04 0.1U_10V_X
7R_04 0.1U_10V_X7R_04
[2,3,5,7,8,13,16
,29] 1.05VS
Cantiga 1/6 - Host B - 5

Schematic Diagrams
Cantiga 2/6 - VGA, CRT

1. 0 5 V M_ P E G
U 15 B
M3 6 U 1 5C
N3 6 RS V D 1 AP2 4 R 64
RS V D 2 SA_ C K _0 M _C LK _D D R 0 [ 10 ]
DDR CLK/ CONTROL/COMPENSATION

R3 3 AT2 1 M _C LK _D D R 1 [ 10 ]
T3 3 RS V D 3 SA_ C K _1 AV2 4 49 . 9 _1 % _ 04
AH9 RS V D 4 SB_ C K _0 A U 20 M _C LK _D D R 2 [ 11 ] L 32
RS V D 5 SB_ C K _1 M _C LK _D D R 3 [ 11 ] L _ B K L T_ C T R L
A H1 0 G 32 T3 7
A H1 2 RS V D 6 A R 24 [1 2 ] G M_ B L ON M 32 L _ B K L T_ E N P E G_ C O MP I T3 6
RS V D 7 S A _C K # _0 M _C LK _D D R #0 [1 0 ] L _ CT RL _ CL K P E G_ C OM P O
A H1 3 A R 21
K1 2 RS V D 8 S A _C K # _1 A U 24 M _C LK _D D R #1 [1 0 ] M 33
RS V D 9 S B _C K # _0 M _C LK _D D R #2 [1 1 ] L _ CT RL _ DA T A
A L3 4 AV2 0 M _C LK _D D R #3 [1 1 ] [ 12 , 2 7 ] P _ D D C _ C L K K 33 H4 4
AK3 4 RS V D 10 S B _C K # _1 J 33 L _ DD C_ CL K P E G_ R X # _ 0 J4 6
RS V D 11 [ 12 , 2 7 ] P _ D D C _ D A T A L _ DD C_ DA T A P E G_ R X # _ 1
A N3 5 B C 28 M _C KE0 [1 0 ] L4 4
A M3 5 RS V D 12 SA_ C K E _0 A Y 28 R2 3 6 P E G_ R X # _ 2 L4 0
T2 4 RS V D 13 SA_ C K E _1 A Y 36 M _C KE1 [1 0 ] 2 . 3 7 K _1 % _0 4 M 29 P E G_ R X # _ 3 N4 1
RS V D 14 SB_ C K E _0 M _C KE2 [1 1 ] [ 12 ] E NA V D D L _ V D D _E N P E G_ R X # _ 4
BB3 6 C 44 P 48
B3 1 SB_ C K E _1 M _C KE3 [1 1 ] B 43 L V D S _I B G P E G_ R X # _ 5 N4 4
R SV D
RS V D 1 5 L V D S _V B G P E G_ R X # _ 6
B2 BA1 7 M _C S# 0 [ 10 ] E 37 T4 3
M1 RS V D 1 6 S A _C S # _0 A Y 16 E 38 L V D S _V R E F H P E G_ R X # _ 7 U4 3
RS V D 1 7 S A _C S # _1 M _C S# 1 [ 10 ] L V D S _V R E F L P E G_ R X # _ 8
AV1 6 M _C S# 2 [ 11 ] [ 1 2 , 27 ] L V D S -LC L K N C 41 Y4 3
S B _C S # _0 A R 13 C 40 L V D S A _C L K # P E G_ R X # _ 9 Y4 8
LVDS
AY2 1 S B _C S # _1 M _C S# 3 [ 11 ] [ 12 , 2 7 ] L V D S -L C LK P B 37 L V D S A _C L K P E G _R X# _ 1 0 Y3 6
RS V D 2 0 B D 17 A 37 L V D S B _C L K # P E G _R X# _ 1 1 A A 43
S A _ O D T _0 A Y 17 M _O D T 0 [1 0 ] L V D S B _C L K P E G _R X# _ 1 2 AD3 7
S A _ O D T _1 M _O D T 1 [1 0 ] P E G _R X# _ 1 3
BF1 5 H 47 AC4 7
B G2 3 S B _ O D T _0 A Y 13 M _O D T 2 [1 1 ] 1. 8 V 1. 8 V [ 1 2 , 27 ] LV D S -L 0N E 46 L VD S A _D A T A #_ 0 P E G _R X# _ 1 4 AD3 9
RS V D 22 S B _ O D T _1 M _O D T 3 [1 1 ] [ 1 2 , 27 ] LV D S -L 1N L VD S A _D A T A #_ 1 P E G _R X# _ 1 5
BF2 3 [ 1 2 , 27 ] LV D S -L 2N G 40
B H1 8 RS V D 23 B G 22 S M_ R C OMP R2 2 6 8 0 . 6 _1 % _0 4 LV D S _ L3 N A 40 L VD S A _D A T A #_ 2 H4 3
RS V D 24 S M _R C O MP L VD S A _D A T A #_ 3 P E G_ R X _ 0
BF1 8 B H 21 S M_ R C OMP # R2 2 2 8 0 . 6 _1 % _0 4 J4 4
RS V D 25 S M_ R C O MP # P E G_ R X _ 1
GRAPHICS
R 68 H 48 L4 3
BF2 8 [ 1 2 , 27 ] LV D S -L 0P D 45 L VD S A _D A T A _0 P E G_ R X _ 2 L4 1
S M_ R C OMP _ V O H S M _ R C O MP _ V OH S M _V R E F [ 1 2 , 27 ] LV D S -L 1P L VD S A _D A T A _1 P E G_ R X _ 3
B H 28 1 0 K _ 1% _ 0 4 F 40 N4 0
S M _R C O MP _ V OL S M _ R C O MP _ V OL [ 1 2 , 27 ] LV D S -L 2P LV D S _ L3 P B 40 L VD S A _D A T A _2 P E G_ R X _ 4 P 47
12mils L VD S A _D A T A _3 P E G_ R X _ 5
AV4 2 N4 3
T2 5 S M _V R E F A R 36 S M_ P W R O K A 41 P E G_ R X _ 6 T4 2
[4 ] M CH_ B S E L 0 CF G _0 S M_ P W R OK L V D S B _D A T A #_ 0 P E G_ R X _ 7
[4 ] M CH_ B S E L 1 R2 5 BF1 7 S M_ R E X T H 38 U4 2
Sheet 5 of 40
P2 5 CF G _1 S M_ R E XT B C 36 C1 3 1 R 69 G 37 L V D S B _D A T A #_ 1 P E G_ R X _ 8 Y4 2
[4 ] M CH_ B S E L 2 M C H _ C F G3 P2 0 CF G _2 S M_ D R A MR S T# J 37 L V D S B _D A T A #_ 2 P E G_ R X _ 9 W 47
M C H _ C F G4 P2 4 CF G _3 B3 8 0 . 1 U _ 10 V _ X 7R _0 4 1 0 K _ 1% _ 0 4 L V D S B _D A T A #_ 3 P E G_ R X _ 1 0 Y3 7
C2 5 CF G _4 DP L L _ RE F _ CL K A3 8 C L K _D R E F [ 1 8] B 42 P E G_ R X _ 1 1 A A 42
[ 9] MC H _ C F G 5 CF G _5 D P LL _ R E F _ C LK # C L K _D R E F # [ 18 ] 96MHz L V D S B _D A T A _0 P E G_ R X _ 1 2
Cantiga 2/6 - [ 9] MC H _ C F G 6
N2 4
M2 4 CF G _6 D P L L _R E F _ S S C L K
E4 1
F41 C L K _D R E F S S [ 1 8]
100MHz
G 38
F 37 L V D S B _D A T A _1 P E G_ R X _ 1 3
AD3 6
AC4 8
CL K
[ 9] MC H _ C F G 7 CF G _7 D P LL _ R E F _ S S C LK # C L K _D R E F S S # [ 18 ] L V D S B _D A T A _2 P E G_ R X _ 1 4
M C H _ C F G8 E2 1 K 37 AD4 0
CF G _8 L V D S B _D A T A _3 P E G_ R X _ 1 5
PCI-EXPRESS
C2 3 F43
C FG
VGA, CRT
[ 9] MC H _ C F G 9 CF G _9 P E G_ C L K C L K _P C I E _ 3G P L L [ 1 8]
[ 9 ] M C H _C F G1 0 C2 4 E4 3 C L K _P C I E _ 3G P L L# [ 18 ] 100MHz J4 1
M C H _ C F G1 1 N2 1 CF G _ 10 P E G_ C LK # P E G_ TX # _ 0 M4 6
P2 1 CF G _ 11 R 42 7 5 _0 4 F 25 P E G_ TX # _ 1 M4 7
[9 ] M C H _C F G1 2 CF G _ 12 T VA _ DAC P E G_ TX # _ 2
T2 1 R 43 7 5 _0 4 H 25 M4 0
[9 ] M C H _C F G1 3 M C H _ C F G1 4 R2 0 CF G _ 13 AE4 1 R 44 7 5 _0 4 K 25 T VB _ DAC P E G_ TX # _ 3 M4 2
CF G _ 14 D MI _ R XN _0 D MI _ T XN 0 [ 1 4] T V C _D A C P E G_ TX # _ 4
M C H _ C F G1 5 M2 0 AE3 7 R4 8
TV
CF G _ 15 D MI _ R XN _1 D MI _ T XN 1 [ 1 4] P E G_ TX # _ 5
L2 1 AE4 7 H 24 N3 8
[9 ] M C H _C F G1 6 CF G _ 16 D MI _ R XN _2 D MI _ T XN 2 [ 1 4] T V _ RT N P E G_ TX # _ 6
M C H _ C F G1 7 H2 1 A H 39 D MI _ T XN 3 [ 1 4] T4 0
M C H _ C F G1 8 P2 9 CF G _ 17 D MI _ R XN _3 P E G_ TX # _ 7 U3 7
R2 8 CF G _ 18 AE4 0 P E G_ TX # _ 8 U4 0
[9 ] M C H _C F G1 9 CF G _ 19 D M I _R X P _0 D MI _ T XP 0 [ 14 ] P E G_ TX # _ 9
T2 8 AE3 8 C 31 Y4 0
[9 ] M C H _C F G2 0 CF G _ 20 D M I _R X P _1 AE4 8 D MI _ T XP 1 [ 14 ] E 32 T V _ D C ON S E L_ 0 P E G_ T X# _ 1 0 A A 46
D M I _R X P _2 D MI _ T XP 2 [ 14 ] T V _ D C ON S E L_ 1 P E G_ T X# _ 1 1
A H 40 A A 37
D M I _R X P _3 D MI _ T XP 3 [ 14 ] P E G_ T X# _ 1 2 A A 40
Zdiff= 100O? 5%
DM I
P E G_ T X# _ 1 3
[ 1 5] P M_ S Y N C # R 55 *1 0m i l _s h or t AE3 5 D MI _ R X N 0 [ 14 ] AD4 3
R 2 16 *1 0m i l _s h or t R 2 9 D MI _ T XN _0 AE4 3 P E G_ T X# _ 1 4 AC4 6
[ 2 , 1 3, 3 1 ] H _D P R S T P # P M_ S Y N C # D MI _ T XN _1 D MI _ R X N 1 [ 14 ] P E G_ T X# _ 1 5
B7 AE4 6 D MI _ R X N 2 [ 14 ]
P M_ E X T TS _ E C # N3 3 P M_ D P R S T P # D MI _ T XN _2 A H 42 D A C_ B L UE E 28 J4 2
P M_ E X T TS _ D D R # P3 2 P M_ E X T _T S # _ 0 D MI _ T XN _3 D MI _ R X N 3 [ 14 ] 1. 0 5 V S [ 1 2] D A C _B L U E C R T _ B LU E P E G _T X _ 0 L4 6
PM
[ 1 0 , 1 1] P M_ E X T TS _ D D R # P M_ E X T _T S # _ 1 P E G _T X _ 1
A T4 0 A D 35 D A C _ GR E E N G 28 M4 8
[ 1 7, 3 1 ] D E LA Y _ P W R G D R 30 1 0 0_ 0 4 A T1 1 PW RO K D MI _ T X P _0 AE4 4 D MI _ R X P 0 [1 4 ] [1 2 ] D A C _ GR E E N C R T _ GR E E N P E G _T X _ 2 M3 9
[ 1 4 , 1 9] P L T_ R S T# RS T IN # D MI _ T X P _1 D MI _ R X P 1 [1 4 ] D A C_ RE D P E G _T X _ 3
[ 2, 13 , 2 8] P M_ T H R MT R I P # R 32 *1 0m i l _s h or t T2 0 AF4 6 D MI _ R X P 2 [1 4 ] [1 2 ] D A C_ RE D J 28 M4 3
R 60 *1 0m i l _s h or t R 3 2 T H E R MT R I P # D MI _ T X P _2 A H 43 R 63 C RT _ RE D P E G _T X _ 4 R4 7
VGA
[ 1 5 , 31 ] P M_ D P R S LP V R DP R S L P V R D MI _ T X P _3 D MI _ R X P 3 [1 4 ] P E G _T X _ 5
G 29 N3 7
1 K _ 1% _ 0 4 C RT _ IRT N P E G _T X _ 6 T3 9
P E G _T X _ 7
12mils [ 12 ] D A C _ D D C A C L K H 32 U3 6
J 32 C RT _ DDC _ CL K P E G _T X _ 8 U3 9
B G4 8 C L _V R E F [ 12 ] D A C _ D D C A D A T A R5 3 3 0 . 1_ 1 % _0 4 J 29 C RT _ DDC _ DA T A P E G _T X _ 9 Y3 9
GR AP HI CS V ID
NC _1 [1 2 ] DAC _ HSY N C C RT _ HS Y N C P E G_ TX _ 1 0
BF4 8 R5 2 1 K _ 1% _ 0 4 E 29 Y4 6
B D4 8 NC _2 C1 1 8 R 62 L 29 C R T _ TV O _ I R E F P E G_ TX _ 1 1 A A 36
NC _3 GF X _V ID0 C RT _ VSY N C P E G_ TX _ 1 2
B C4 8 B3 3 A A 39
B H4 7 NC _4 G F X_ V I D _0 B3 2 GF X _V ID1 0 . 1U _1 0 V _ X7 R _0 4 5 1 1_ 1 % _0 4 R5 4 3 0 . 1_ 1 % _0 4 P E G_ TX _ 1 3 AD4 2
NC _5 G F X_ V I D _1 GF X _V ID2 [ 12 ] D A C _V S Y N C P E G_ TX _ 1 4
B G4 7 G 33 AD4 6
BE4 7 NC _6 G F X_ V I D _2 F33 GF X _V ID3 P E G_ TX _ 1 5
B H4 6 NC _7 G F X_ V I D _3 E3 3 GF X _V ID4
BF4 6 NC _8 G F X_ V I D _4 1 .8 V C A N T I G A -E B 8 8C TG M
B G4 5 NC _9
NC _1 0
B H4 4 3. 3V S
NC
B H4 3 NC _1 1 C 34 GF X _V R E N
NC _1 2 G F X _V R _ E N MC H _ C L K R E Q#
BH6 R 23 2 R6 5 10 K _ 04
BH5 NC _1 3 P M_ E X T TS _ E C # R5 8 10 K _ 04
NC _1 4 S M_ R C OMP _ V O H P M_ E X T TS _ D D R #
B G4 1 K _ 1 %_ 0 4 R5 9 10 K _ 04
BH3 NC _1 5
BF 3 NC _1 6 A H 37 D A C _ B LU E R4 9 15 0 _1 % _ 04
NC _1 7 CL _ CL K C L_ C L K 0 [ 1 5 ] D A C _ GR E E N
BH2 A H 36 R4 7 15 0 _1 % _ 04
B G2 NC _1 8 CL _ DA T A A N 36 C L_ D A TA 0 [ 15 ] C 3 99 C3 9 8 DA C _ RE D R4 8 15 0 _1 % _ 04
NC _1 9 C L_ P W R OK C L_ P W R OK [ 12 , 1 5 , 17 , 2 6]
ME
BE2 AJ 3 5 C L_ R S T# 0 [ 1 5 ]
B G1 NC _2 0 C L_ R S T# A H 34 2 . 2 U _ 6 . 3V _0 6 0 . 01 U _1 6 V _X 7 R _ 0 4 S M_ R E XT R2 2 1 49 9 _1 % _ 04
NC _2 1 C L _V R E F CL _ V RE F S M_ P W R OK
BF 1 R 23 0 R6 1 *1 0 m li _ sh o rt
BD1 NC _2 2
BC1 NC _2 3 3 . 0 1 K _1 % _ 04
F1 NC _2 4 N 28
A4 7 NC _2 5 DDP C _ CT RL CL K M 28 S M_ R C OM P _V OL
NC _2 6 DDP C _ CT RL DA T A
G 36
SDVO _ CT RL CL K E3 6
S DV O _ CT RL DA T A
K 3 6 M C H _ C L K R E Q# M C H _ C LK R E Q# [ 1 8 ]
C LK R E Q# H 36
MI SC
I CH_ S Y NC# M CH_ IC H_ S Y N C# [1 5 ]

A2 8 C 3 92 C3 9 5 R 22 9
C2 9 HD A _ S Y NC
H DA
B2 9 HD A _ SDO B1 2 R 3 61 5 6 _0 4 2 . 2 U _ 6 . 3V _0 6 0 . 01 U _1 6 V _X 7 R _ 0 4 1 K _ 1 %_ 0 4
HD A _ SDI T S A T N# 1 . 05 V S
B3 0
B2 8 HD A _ RS T #
HD A _ BCL K
[ 8 ] 1 . 05 V M _P E G
[ 8 . . 1 6, 1 8 . . 2 7, 3 1 ] 3 . 3 V S
C A N T I GA -E B 8 8 C T GM [ 2 . . 4 , 7, 8 , 1 3 , 16 , 2 9] 1 . 05 V S
[ 7 , 8, 10 , 1 1, 3 0 ] 1 . 8 V
B - 6 Cantiga 2/6 - VGA, CRT

Schematic Diagrams
Cantiga 3/6 - DDR
[ 1 0] M_ A _ D Q [ 63 : 0 ] U1 5 D [ 1 1] M_ B _ D Q [ 63 : 0 ] U1 5 E
M_ A _ D Q 0 AJ 3 8 BD2 1 M_ A B S 0 M_ B _ D Q 0 AK4 7 B C1 6 M_ B B S 0
S A _ D Q_ 0 SA_ BS_ 0 M _ ABS0 [ 1 0] S B _ D Q_ 0 SB_ BS_ 0 M _B B S 0 [ 1 1]
M_ A _ D Q 1 AJ 4 1 B G1 8 M_ A B S 1 M _ ABS1 [ 1 0] M_ B _ D Q 1 A H4 6 BB1 7 M_ B B S 1 M _B B S 1 [ 1 1]
M_ A _ D Q 2 AN3 8 S A _ D Q_ 1 SA_ BS_ 1 A T 25 M_ A B S 2 M_ B _ D Q 2 AP4 7 S B _ D Q_ 1 SB_ BS_ 1 BB3 3 M_ B B S 2
S A _ D Q_ 2 SA_ BS_ 2 M _ ABS2 [ 1 0] S B _ D Q_ 2 SB_ BS_ 2 M _B B S 2 [ 1 1]
M_ A _ D Q 3 A M3 8 M_ B _ D Q 3 AP4 6
M_ A _ D Q 4 AJ 3 6 S A _ D Q_ 3 BB2 0 M_ A _ R A S # M_ B _ D Q 4 AJ 4 6 S B _ D Q_ 3
M_ A _ D Q 5 AJ 4 0 S A _ D Q_ 4 S A _R A S # BD2 0 M_ A _ C A S # M _ A _R A S # [ 1 0 ] M_ B _ D Q 5 AJ 4 8 S B _ D Q_ 4 A U1 7 M_ B _ R A S #
S A _ D Q_ 5 S A _C A S # M _ A _C A S # [ 1 0 ] S B _ D Q_ 5 S B _R A S # M _B _R A S # [ 1 1]
M_ A _ D Q 6 A M4 4 AY2 0 M_ A _ W E # M_ B _ D Q 6 A M4 8 B G1 6 M_ B _ C A S #
M_ A _ D Q 7 A M4 2 S A _ D Q_ 6 SA_ W E# M _ A _W E # [ 10 ] M_ B _ D Q 7 AP4 8 S B _ D Q_ 6 S B _C A S # BF1 4 M_ B _ W E # M _B _C A S # [ 1 1]
S A _ D Q_ 7 S B _ D Q_ 7 SB_ W E# M _B _W E # [ 11 ]
M_ A _ D Q 8 AN4 3 M_ B _ D Q 8 A U4 7
M_ A _ D Q 9 AN4 4 S A _ D Q_ 8 M_ B _ D Q 9 A U4 6 S B _ D Q_ 8
S A _ D Q_ 9 S B _ D Q_ 9
M_ A _ D Q 10 AU4 0 M _A _D M[ 7 : 0 ] [1 0 ] M_ B _ D Q 10 BA4 8
M_ A _ D Q 11 AT 3 8 S A _ D Q_ 1 0 A M3 7 M_ A _ D M0 M_ B _ D Q 11 AY4 8 S B _ D Q_ 1 0
S A _ D Q_ 1 1 S A _D M_ 0 S B _ D Q_ 1 1 M _B _D M[ 7 : 0 ] [1 1 ]
M_ A _ D Q 12 AN4 1 A T 41 M_ A _ D M1 M_ B _ D Q 12 AT4 7 A M4 7 M_ B _ D M0
M_ A _ D Q 13 AN3 9 S A _ D Q_ 1 2 S A _D M_ 1 AY4 1 M_ A _ D M2 M_ B _ D Q 13 A R4 7 S B _ D Q_ 1 2 S B _D M_ 0 AY4 7 M_ B _ D M1
M_ A _ D Q 14 AU4 4 S A _ D Q_ 1 3 S A _D M_ 2 AU3 9 M_ A _ D M3 M_ B _ D Q 14 BA4 7 S B _ D Q_ 1 3 S B _D M_ 1 B D4 0 M_ B _ D M2
S A _ D Q_ 1 4 S A _D M_ 3 S B _ D Q_ 1 4 S B _D M_ 2
M_ A _ D Q 15 AU4 2 BB1 2 M_ A _ D M4 M_ B _ D Q 15 B C4 7 BF3 5 M_ B _ D M3
M_ A _ D Q 16 AV3 9 S A _ D Q_ 1 5 S A _D M_ 4 AY6 M_ A _ D M5 M_ B _ D Q 16 B C4 6 S B _ D Q_ 1 5 S B _D M_ 3 B G1 1 M_ B _ D M4
M_ A _ D Q 17 AY4 4 AT 7 M_ A _ D M6 M_ B _ D Q 17 B C4 4 BA3 M_ B _ D M5
M_ A _ D Q 18 BA4 0 S A _ D Q_ 1 7 S A _D M_ 6 AJ 5 M_ A _ D M7 M_ B _ D Q 18 B G4 3 S B _ D Q_ 1 7 S B _D M_ 5 AP1 M_ B _ D M6
A
M_ A _ D Q 19 BD4 3 M_ B _ D Q 19 BF4 3 AK2 M_ B _ D M7
M _A _D QS [ 7 : 0 ] [1 0 ]
B
M_ A _ D Q 20 AV4 1 S A _ D Q_ 1 9 A J 44 M_ A _ D QS 0 M_ B _ D Q 20 BE4 5 S B _ D Q_ 1 9 S B _D M_ 7
S A _ D Q_ 2 0 S A _D QS _ 0 S B _ D Q_ 2 0 M _B _D QS [ 7 : 0 ] [1 1 ]
M_ A _ D Q 21 AY4 3 A T 44 M_ A _ D QS 1 M_ B _ D Q 21 B C4 1 A L 47 M_ B _ D QS 0
M_ A _ D Q 22 BB4 1 S A _ D Q_ 2 1 S A _D QS _ 1 BA4 3 M_ A _ D QS 2 M_ B _ D Q 22 BF4 0 S B _ D Q_ 2 1 S B _D QS _ 0 AV4 8 M_ B _ D QS 1
M_ A _ D Q 23 BC4 0 S A _ D Q_ 2 2 S A _D QS _ 2 BC3 7 M_ A _ D QS 3 M_ B _ D Q 23 BF4 1 S B _ D Q_ 2 2 S B _D QS _ 1 B G4 1 M_ B _ D QS 2
MEMORY
S A _ D Q_ 2 3 S A _D QS _ 3 S B _ D Q_ 2 3 S B _D QS _ 2
M_ A _ D Q 24 AY3 7 AW 1 2 M_ A _ D QS 4 M_ B _ D Q 24 B G3 8 B G3 7 M_ B _ D QS 3
MEMORY
M_ A _ D Q 25 BD3 8 S A _ D Q_ 2 4 S A _D QS _ 4 BC8 M_ A _ D QS 5 M_ B _ D Q 25 BF3 8 S B _ D Q_ 2 4 S B _D QS _ 3 B H9 M_ B _ D QS 4
M_ A _ D Q 26 AV3 7 AU8 M_ A _ D QS 6 M_ B _ D Q 26 B H3 5 BB2 M_ B _ D QS 5
Sheet 6 of 40
M_ A _ D Q 27 AT 3 6 A M7 M_ A _ D QS 7 M_ B _ D Q 27 B G3 5 A U1 M_ B _ D QS 6
M_ A _ D Q 28 AY3 8 M _A _D QS # [ 7 : 0] [ 1 0] M_ B _ D Q 28 B H4 0 A N6 M_ B _ D QS 7
M_ A _ D Q 29 BB3 8 S A _ D Q_ 2 8 A J 43 M_ A _ D QS #0 M_ B _ D Q 29 B G3 9 S B _ D Q_ 2 8 S B _D QS _ 7
S A _ D Q_ 2 9 S A_ DQ S #_ 0 S B _ D Q_ 2 9 M _B _D QS # [ 7 : 0] [ 1 1]
M_ A _ D Q 30 AV3 6 A T 43 M_ A _ D QS #1 M_ B _ D Q 30 B G3 4 A L 46 M_ B _ D QS #0
Cantiga 3/6 -DDR

M_ A _ D Q 31 AW 3 6 S A _ D Q_ 3 0 S A_ DQ S #_ 1 BA4 4 M_ A _ D QS #2 M_ B _ D Q 31 B H3 4 S B _ D Q_ 3 0 S B _ D QS #_ 0 AV4 7 M_ B _ D QS #1
M_ A _ D Q 32 BD1 3 S A _ D Q_ 3 1 S A_ DQ S #_ 2 BD3 7 M_ A _ D QS #3 M_ B _ D Q 32 B H1 4 S B _ D Q_ 3 1 S B _ D QS #_ 1 B H4 1 M_ B _ D QS #2
S A _ D Q_ 3 2 S A_ DQ S #_ 3 S B _ D Q_ 3 2 S B _ D QS #_ 2
M_ A _ D Q 33 AU1 1 AY1 2 M_ A _ D QS #4 M_ B _ D Q 33 B G1 2 B H3 7 M_ B _ D QS #3
M_ A _ D Q 34 BC1 1 S A _ D Q_ 3 3 S A_ DQ S #_ 4 BD8 M_ A _ D QS #5 M_ B _ D Q 34 B H1 1 S B _ D Q_ 3 3 S B _ D QS #_ 3 B G9 M_ B _ D QS #4
M_ A _ D Q 35 BA1 2 AU9 M_ A _ D QS #6 M_ B _ D Q 35 BG 8 B C2 M_ B _ D QS #5
M_ A _ D Q 36 AU1 3 S A _ D Q_ 3 5 S A_ DQ S #_ 6 A M8 M_ A _ D QS #7 M_ B _ D Q 36 B H1 2 S B _ D Q_ 3 5 S B _ D QS #_ 5 AT2 M_ B _ D QS #6
SYSTEM
M_ A _ D Q 37 AV1 3 M_ B _ D Q 37 BF1 1 A N5 M_ B _ D QS #7
SYSTEM
S A _ D Q_ 3 7 M _A _A [ 1 4 : 0 ] [1 0 ] S B _ D Q_ 3 7 S B _ D QS #_ 7
M_ A _ D Q 38 BD1 2 BA2 1 M_ A _ A 0 M_ B _ D Q 38 BF8
S A _ D Q_ 3 8 S A _ MA _ 0 S B _ D Q_ 3 8 M _B _A [ 1 4 : 0 ] [1 1 ]
M_ A _ D Q 39 BC1 2 BC2 4 M_ A _ A 1 M_ B _ D Q 39 BG 7 AV1 7 M_ B _ A 0
M_ A _ D Q 40 BB9 S A _ D Q_ 3 9 S A _ MA _ 1 B G2 4 M_ A _ A 2 M_ B _ D Q 40 BC 5 S B _ D Q_ 3 9 S B _ MA _ 0 BA2 5 M_ B _ A 1
M_ A _ D Q 41 BA9 S A _ D Q_ 4 0 S A _ MA _ 2 BH2 4 M_ A _ A 3 M_ B _ D Q 41 BC 6 S B _ D Q_ 4 0 S B _ MA _ 1 B C2 5 M_ B _ A 2
S A _ D Q_ 4 1 S A _ MA _ 3 S B _ D Q_ 4 1 S B _ MA _ 2
M_ A _ D Q 42 AU1 0 B G2 5 M_ A _ A 4 M_ B _ D Q 42 AY 3 A U2 5 M_ B _ A 3
M_ A _ D Q 43 AV9 S A _ D Q_ 4 2 S A _ MA _ 4 BA2 4 M_ A _ A 5 M_ B _ D Q 43 AY 1 S B _ D Q_ 4 2 S B _ MA _ 3 AW 2 5 M_ B _ A 4
M_ A _ D Q 44 BA1 1 BD2 4 M_ A _ A 6 M_ B _ D Q 44 BF6 BB2 8 M_ B _ A 5
M_ A _ D Q 45 B D9 S A _ D Q_ 4 4 S A _ MA _ 6 B G2 7 M_ A _ A 7 M_ B _ D Q 45 BF5 S B _ D Q_ 4 4 S B _ MA _ 5 A U2 8 M_ B _ A 6
M_ A _ D Q 46 A Y8 BF 2 5 M_ A _ A 8 M_ B _ D Q 46 BA1 AW 2 8 M_ B _ A 7
M_ A _ D Q 47 BA6 S A _ D Q_ 4 6 S A _ MA _ 8 AW 2 4 M_ A _ A 9 M_ B _ D Q 47 BD 3 S B _ D Q_ 4 6 S B _ MA _ 7 A T 33 M_ B _ A 8
M_ A _ D Q 48 AV5 BC2 1 M_ A _ A 10 M_ B _ D Q 48 AV2 B D3 3 M_ B _ A 9
S A _ D Q_ 4 8 S A _ M A _1 0 S B _ D Q_ 4 8 S B _ MA _ 9
DDR
M_ A _ D Q 49 AV7 B G2 6 M_ A _ A 11 M_ B _ D Q 49 AU 3 BB1 6 M_ B _ A 10
M_ A _ D Q 50 AT9 S A _ D Q_ 4 9 S A _ M A _1 1 BH2 6 M_ A _ A 12 M_ B _ D Q 50 AR 3 S B _ D Q_ 4 9 S B _ MA _1 0 AW 3 3 M_ B _ A 11
DDR
S A _ D Q_ 5 0 S A _ M A _1 2 S B _ D Q_ 5 0 S B _ MA _1 1
M_ A _ D Q 51 A N8 BH1 7 M_ A _ A 13 M_ B _ D Q 51 AN 2 AY3 3 M_ B _ A 12
M_ A _ D Q 52 A U5 S A _ D Q_ 5 1 S A _ M A _1 3 AY2 5 M_ A _ A 14 M_ B _ D Q 52 AY 2 S B _ D Q_ 5 1 S B _ MA _1 2 B H1 5 M_ B _ A 13
S A _ D Q_ 5 2 S A _ M A _1 4 S B _ D Q_ 5 2 S B _ MA _1 3
M_ A _ D Q 53 A U6 M_ B _ D Q 53 AV1 A U3 3 M_ B _ A 14
M_ A _ D Q 54 AT5 S A _ D Q_ 5 3 M_ B _ D Q 54 AP3 S B _ D Q_ 5 3 S B _ MA _1 4
S A _ D Q_ 5 4 S B _ D Q_ 5 4
M_ A _ D Q 55 AN1 0 M_ B _ D Q 55 AR 1
M_ A _ D Q 56 A M1 1 S A _ D Q_ 5 5 M_ B _ D Q 56 AL 1 S B _ D Q_ 5 5
S A _ D Q_ 5 6 S B _ D Q_ 5 6
M_ A _ D Q 57 A M5 M_ B _ D Q 57 AL 2
M_ A _ D Q 58 AJ 9 S A _ D Q_ 5 7 M_ B _ D Q 58 AJ 1 S B _ D Q_ 5 7
M_ A _ D Q 59 AJ 8 S A _ D Q_ 5 8 M_ B _ D Q 59 AH 1 S B _ D Q_ 5 8
S A _ D Q_ 5 9 S B _ D Q_ 5 9
M_ A _ D Q 60 AN1 2 M_ B _ D Q 60 AM 2
M_ A _ D Q 61 A M1 3 S A _ D Q_ 6 0 M_ B _ D Q 61 AM 3 S B _ D Q_ 6 0
S A _ D Q_ 6 1 S B _ D Q_ 6 1
M_ A _ D Q 62 AJ 1 1 M_ B _ D Q 62 AH 3
M_ A _ D Q 63 AJ 1 2 S A _ D Q_ 6 2 M_ B _ D Q 63 AJ 3 S B _ D Q_ 6 2
S A _ D Q_ 6 3 S B _ D Q_ 6 3
C A N T I GA -E B 8 8 C T GM C A N T I GA -E B 8 8 C T GM
M 12 M2 M6 M3 M4 M9 M8
M -MA R K 1 M-MA R K 1 M-M A R K 1 M-M A R K 1 M -MA R K 1 M-MA R K 1 M-M A R K 1
M H1 MH 2 MH 3 MH 4 H5 H 6
H24,H25,H27 H14 H16,H26,H18 H29 H 4_ 0 H 4 _0 H4 _ 0 H4 _ 0 C4 4 D4 4 C 44 D 4 4
? ? 6-34-M52GS-020 ? ? ? ? ? ?
02/26 M7 M5 M1 M1 0 M 11 M1 4 M1 3
6-34-M52NS-020 6-36-12181-20E 6-34-D90C0-021
For M720T M -MA R K 1 M-MA R K 1 M-M A R K 1 M-M A R K 1 M -MA R K 1 M-MA R K 1 M-M A R K 1
H 24 H 25 H 27 H1 4 H 26 H1 6 H 18 H 29
C 35 5 B 2 64 D 1 8 6 C 35 5 B 2 64 D 18 6 C 3 55 B 2 6 4D 18 6 C 2 1 7D 11 1 C 23 7 D 8 7 C 2 1 7D 8 7 C 2 17 D 8 7 C 2 37 D 1 4 6 S1
S MD 8 0 X 80
H7 H 3 H 4 H2 3 H2 8 H 8
1
C4 4 D4 4 C 44 D 4 4 C 4 4D 44 C 2 37 D 91 C 2 3 7D 9 1 C 44 D 4 4
H 19 H2 0
O 4 0X 1 0 2D 40 X 1 02 O4 0 X 10 2 D 4 0 X1 0 2
1
H1 H1 0 H1 2 H 22 H 13 H 15 H 9 H 21 H 17 H2 H1 1
2 9 2 9 2 4 2 9 2 4 2 4 2 9 2 9 2 9 2 9 2
3 8 3 8 3 3 8 3 8 3 8 3 8 3
4 1 7 4 1 7 1 4 1 1 1 4 1 7 4 1 7 4 1 7 4 1 7 4 1
5 6 5 6 3 5 5 6 3 5 3 5 5 6 5 6 5 6 5 6 5 6
M TH 31 5 D 1 1 1 M TH 3 15 D 1 1 1 M TH 3 15 D 1 1 1 B MT H 3 1 5D 11 1 A MT H 3 1 5D 11 1 B MT H 3 1 5D 11 1 B M T H 3 15 D 11 1 M T H 3 15 D 11 1 MT H 31 5 D 1 1 1-3 _ 4 MT H 3 1 5 D 1 11 M TH 5 _5 D 2 _ 8
Cantiga 3/6 - DDR B - 7

Schematic Diagrams
Cantiga 4/6 - Power
1.8V U15G 1.05VS

U1
5F
1
.05VS
AP33 W28
VCC_
SM_1 VCC_AX
G_NCTF_1
AN33 V28
BH32 VCC_
SM_2 VCC_AX
G_NCTF_2 W26 AG3
4
BG32 VCC_
SM_3 VCC_AX
G_NCTF_3 V26 AC3
4 VCC_1
VCC_
SM_4 VCC_AX
G_NCTF_4 VCC_2
3A BF32 W25 8.7A AB3
4
VCC_
SM_5 VCC_AX
G_NCTF_5 VCC_3
BD32 V25 AA3
4
BC32 VCC_
SM_6 VCC_AX
G_NCTF_6 W24 Y3
4 VCC_4
BB32 VCC_
SM_7 VCC_AX
G_NCTF_7 V24 1.05
VS CLOSE TO GMCH V3
4 VCC_5
VCC_
SM_8 VCC_AX
G_NCTF_8 VCC_6
BA32 W23 U3
4
VCC_
SM_9 VCC_AX
G_NCTF_9 VCC_7
AY32 V23 3A AM3
3
AW32 VCC_
SM_10 VCC_AXG_NCTF_10 AM21 AK3
3 VCC_8
AV32 VCC_
SM_11 VCC_AXG_NCTF_11 AL21 C11
2 C94 C85 C117 C420 AJ3
3 VCC_9
VCC_
SM_12 VCC_AXG_NCTF_12 VCC_10
AU32 AK21 AG3
3
VCC_
AT32 W21 10U_6.3V_X5R_0
8 0
.1U_10V_X7R_04 0.1U_
10V_X7R_04 0.1U_10V_X7R_04 *22
0U_4V_D AF3
3
AR32 VCC_
SM_14 VCC_AXG_NCTF_14 V21 VCC_12
AP32 VCC_
SM_15 VCC_AXG_NCTF_15 U21 AE3
3
POWER
VCC_
VCC CORE
AN32 AM20 AC3
3
VCC_
BH31 AK20 AA3
3
BG31 VCC_
SM_18 VCC_AXG_NCTF_18 W20 1.05
VS Y3
3 VCC_15
BF31 VCC_
SM_19 VCC_AXG_NCTF_19 U20 W3
3 VCC_16
VCC_
BG30 AM19 V3
3
VCC_
BH29 AL19 U3
3
BG29 VCC_
SM_22 VCC_AXG_NCTF_22 AK19 C76 C78 C59 C68 AH2
8 VCC_19
BF29 VCC_
SM_23 VCC_AXG_NCTF_23 AJ19 AF2
8 VCC_20
VCC_
BD29 AH19 0.47U_10V_04 1
U_6.3V_04 10U_6.3V_X5R_08 *330U_2.5V_D3 AC2
8
VCC_
VCC SM
BC29 AG19 AA2
8
BB29 VCC_
SM_26 VCC_AXG_NCTF_26 AF19 AJ2
6 VCC_23
BA29 VCC_
SM_27 VCC_AXG_NCTF_27 AE19 AG2
6 VCC_24
VCC_
AY29 AB19 AE2
6
VCC_
SM_29 VCC_AXG_NCTF_29 1.05
VS VCC_26
AW29 AA19 AC2
6
Sheet 7 of 40 AV29 VCC_

SM_30 VCC_AXG_NCTF_30 Y19 AH2
5 VCC_27
AU29 VCC_
SM_31 VCC_AXG_NCTF_31 W19 AG2
5 VCC_28
VCC_
AT29 V19 AF2
5
VCC_
Cantiga 4/6 - Power

AR29 U19 C77 C60 C62 C69 AG2
4
AP29 VCC_
SM_34 VCC_AXG_NCTF_34 AM17 AJ2
3 VCC_31 1.05VS
VCC_
SM_35 VCC_AXG_NCTF_35 AK17 10U_6.3V_X5R_0
8 0
.1U_10V_X7R_04 0.1U_
10V_X7R_04 1U_6.3V_X5R_06 AH2
3 VCC_32
VCC_SM_3
6 VCC_AXG_NCTF_36 VCC_33
BA36 AH17 AF2
3
POWER
VCC_SM_3
7 VCC_
SM_36/NC VCC_AXG_NCTF_37 VCC_34
BB24 AG17 AM32
VCC_SM_3
8 BD16 VCC_
SM_37/NC VCC_AXG_NCTF_38 AF17 T3
2 VCC_NCTF_1 AL32
BB21 VCC_
SM_38/NC VCC_AXG_NCTF_39 AE17 VCC_35 VCC_NCTF_2 AK32
VCC_SM_4
0 VCC_
SM_39/NC VCC_AXG_NCTF_40 1
.8V VCC_NCTF_3
AW16 AC17 AJ32
VCC_
SM_40/NC VCC_AXG_NCTF_41 VCC_NCTF_4
AW13 AB17 AH32
VCC_SM_4
2 AT13 VCC_
SM_41/NC VCC_AXG_NCTF_42 Y17 VCC_NCTF_5 AG32
VCC_
SM_42/NC VCC_AXG_NCTF_43 W17 VCC_NCTF_6 AE32
1.05VS VCC_AXG_NCTF_44 VCC_NCTF_7
V17 C40
7 C405 C40
6 C409 AC32
VCC_AXG_NCTF_45 VCC_NCTF_8
VCC GFX NCTF

AM16 AA32
Y26 VCC_AXG_NCTF_46 AL16 0.01U_16V_X7R_
04 1
0U_6.3V_X5R_08 10U_6.3V_X5R_08 15
0U_4V_B2 VCC_NCTF_9 Y32
AE25 VCC_
AXG_1 VCC_AXG_NCTF_47 AK16 VCC_NCTF_10 W32
VCC_
AXG_2 VCC_AXG_NCTF_48 VCC_NCTF_11
AB25 AJ16 U32
VCC_
AA25 AH16 AM30
AE24 VCC_
AXG_4 VCC_AXG_NCTF_50 AG16 VCC_NCTF_13 AL30
AC24 VCC_
AXG_5 VCC_AXG_NCTF_51 AF16 VCC_NCTF_14 AK30
VCC_
AA24 AE16 AH30
VCC_
Y24 AC16 AG30
AE23 VCC_
AXG_8 VCC_AXG_NCTF_54 AB16 VCC_NCTF_17 AF30
AC23 VCC_
AXG_9 VCC_AXG_NCTF_55 AA16 VCC_NCTF_18 AE30
VCC_
AB23 Y16 AC30
VCC_
AA23 W16 AB30
AJ21 VCC_
AXG_12 VCC_AXG_NCTF_58 V16 VCC_NCTF_21 AA30
AG21 VCC_
AXG_13 VCC_AXG_NCTF_59 U16 VCC_NCTF_22 Y30
VCC_
AE21 W30
VCC_
AXG_15 VCC_NCTF_24
AC21 V30
VCC NCTF
AA21 VCC_
AXG_16 VCC_NCTF_25 U30
VCC_
AXG_17
All trace width are 10mils VCC_NCTF_26
Y21 AL29
VCC_
AXG_18 VCC_NCTF_27
AH20 AK29
VCC_
AXG_19 VCC_SM_36 VCC_NCTF_28
AF20 C113 *0.1U_
10V_X7R_04 AJ29
AE20 VCC_
AXG_20 VCC_NCTF_29 AH29
AC20 VCC_
AXG_21 VCC_SM_37 C73 *0.1U_
10V_X7R_04 VCC_NCTF_30 AG29
VCC_
AXG_22 VCC_NCTF_31
AB20 AE29
VCC_
AA20 C65 *0.1U_
10V_X7R_04 AC29
T17 VCC_
AXG_24 VCC_NCTF_33 AA29
T16 VCC_
AXG_25 VCC_SM_40 C63 *0.1U_
10V_X7R_04 VCC_NCTF_34 Y29
VCC_
AXG_26 VCC_NCTF_35
AM15 W29
VCC_
AL15 C64 *0.1U_
10V_X7R_04 V29
AE15 VCC_
AXG_28 VCC_NCTF_37 AL28
AJ15 VCC_
AXG_29 VCC_NCTF_38 AK28
VCC_
AXG_30 VCC_NCTF_39
AH15 AL26
VCC_
AXG_31 VCC_NCTF_40
AG15 AK26
AF15 VCC_
AB15 VCC_
VCC_
AXG_34 VCC_NCTF_43
AA15 AK23
VCC_
AXG_35 VCC_NCTF_44
Y15
VCC GFX
V15 VCC_
AXG_36
U15 VCC_
AXG_37
VCC_
AXG_38 All trace width are 10mils
AN14
VCC_
AXG_39
AM14
U14 VCC_
AXG_40 AV44 SM_L
F1 C140 1U_6.3V_X5
R_06
T14 VCC_
AXG_41 VCC_SM_LF1 BA37 SM_L
F2 C114 1U_6.3V_X5
R_06 CANTIGA-EB88CTGM
VCC SM LF
VCC_
AXG_42 VCC_SM_LF2 SM_L
F3
AM40 C127 0.47U_1
0V_04
VCC_SM_LF3 SM_L
F4
AV21 C72 0.22U_1
0V_04
VCC_SM_LF4 AY5 SM_L
F5 C52 0.22U_1
0V_04
VCC_SM_LF5 AM10 SM_L
F6 C56 0.1U_10
V_X7R_04
VCC_SM_LF6 SM_L
F7
BB13 C58 0.1U_10
V_X7R_04
VCC_SM_LF7
VCC_AXG_SENSE AJ14
VSS_AXG_SENSE VCC_AXG _SENSE
AH14
VSS_AXG_SENSE
[5,8,10,11,30] 1.8V
CANTIGA-EB88CT
GM [2..5,8,13,16,29] 1.05 VS
B - 8 Cantiga 4/6 - Power

Schematic Diagrams
Cantiga 5/6 - Power
1. 0 5 V S
10mils
3 . 3V S _A T V D A C
L2 7
C 61 6 C3 9 4 C 39 3 U 1 5H
H C B 10 0 5K F -12 1 T 20 1A
4 . 7 U _ 6 . 3V _ X 5 R _ 0 6 0. 1U _1 0 V _ X7 R _ 0 4 0 . 0 1U _ 16 V _ X7 R _0 4 U 13
1 . 0 5V M_ D P L L A VTT_ 1 1. 0 5 V S
T13
C 41 7 B 27 VTT_ 2 U 12 C 3 44 C3 4 2 C3 5 0 C3 4 3 C 3 40 C 3 41
10mils V C C A _ C R T_ D A C _ 1 VTT_ 3
C4 1 5 A 26 T12
10 U _6 . 3 V _ X5 R _ 0 8 0 . 1 U _ 10 V _ X 7R _ 04 V C C A _ C R T_ D A C _ 2 VTT_ 4 U 11 *1 U _ 6. 3V _ X 5R _ 06 1 U _ 6 . 3V _ X 5 R _ 06 1 U _ 6 . 3V _ 0 4 2 . 2U _ 6. 3 V _ 0 6 1 0 U _ 6 . 3V _X 5 R _ 0 8 * 10 U _6 . 3 V _ X5 R _ 0 8
VTT_ 5
C 61 7 C3 8 9 C 39 0 T11
C RT
A 25 VTT_ 6 U 10
V C C A _ D A C _B G VTT_ 7
4 . 7 U _ 6 . 3V _ X 5 R _ 0 6 0. 1U _1 0 V _ X7 R _ 0 4 0 . 0 1U _ 16 V _ X7 R _0 4 B 25 T10
V S S A _ D A C_ B G VTT_ 8 U 9
1 . 0 5V S VTT_ 9 T9
V TT _ 1 0
10mils U 8
F 47 V TT _ 1 1 T8
1 . 0 5 V M_ D P L L A V C CA _ DP L L A V TT _ 1 2
10mils U 7
L3 0 L 48 V TT _ 1 3 T7
V TT
1 . 0 5V M _D P L LB V C CA _ DP L L B V TT _ 1 4
U 6 C 3 51 C5 5 C5 7 C3 5 2 C 54 C 3 49
P LL
10mils V TT _ 1 5
H C B 10 0 5K F -12 1 T 20 A D1 T6
1 . 0 5V M _ H P L L V C CA _ HP L L V TT _ 1 6 U 5 *0 . 1U _ 10 V _ X7 R _0 4 0 . 1U _ 10 V _ X 7R _0 4 0 . 1U _ 10 V _ X 7R _0 4 *0 . 1 U _ 1 0V _ X 7 R _ 04 0 . 1 U _ 1 0V _X 7 R _ 0 4 0 . 1 U _ 1 0V _X 7 R _ 0 4
1 . 0 5V M_ D P L L B 12mils
AE1 V TT _ 1 7 T5
C 42 9 1 . 0 5V M _ MP L L V C C A _ MP L L V TT _ 1 8 V3
V TT _ 1 9
C4 3 0 10mils U 3
10 U _6 . 3 V _ X5 R _ 0 8 0 . 1 U _ 10 V _ X 7R _ 04 J 48 V TT _ 2 0 V2
1. 8 V _ T XL V D S V C CA _ L V DS V TT _ 2 1
A P EG A L VD S
U 2
C1 4 3 J 47 V TT _ 2 2 T2
V S SA _ L V DS V TT _ 2 3
V1
10 0 0 P _5 0 V _ X7 R _0 4 V TT _ 2 4 U 1
1 . 0 5V S V TT _ 2 5
10mils
A D 48 1 . 0 5V M _ A XF R2 2 0
Sheet 8 of 40
V C C A _ P E G_ B G 0 _0 4
1 .5 V S 20mils
B2 2 1 . 0 5V S
V C C_ A X F _ 1
AX F
L2 4 C4 2 4 B2 1
V C C_ A X F _ 2
Cantiga 5/6 - Power

10mils A2 1 C 3 76 C 3 72
H C B 10 0 5K F -12 1 T 20 0. 1U _1 0 V _ X7 R _ 0 4 A A 48 V C C_ A X F _ 3
V C C A _ P E G_ P L L 1U _6 . 3 V _ X5 R _0 6 *1 0U _6 . 3 V _ X5 R _0 8
1 . 0 5V M_ H P L L
C3 3 8 C 34 7 A R 20
VC C A _ S M_ 1
A P 20
10 U _6 . 3 V _ X5 R _ 0 8 0 . 1 U _ 10 V _ X 7R _ 04 1. 0 5 V M_ P E G P LL A N 20 VC C A _ S M_ 2 1 . 8 V _ S MC K L 26
VC C A _ S M_ 3
A R 17 12mils H C B 1 00 5 K F -1 21 T 2 0
A P 17 VC C A _ S M_ 4 BF 21
50mils VC C A _ S M_ 5 V C C _ S M _C K _ 1 1 .8 V
A N 17 BH 20
SM CK
1. 0 5 V S VC C A _ S M_ 6 V C C _ S M _C K _ 2
A T 16
A SM
BG 20 C 3 83 C3 8 4
1 . 0 5V S C6 0 6 C6 0 7 C6 6 A R 16 VC C A _ S M_ 7 V C C _ S M _C K _ 3 BF 20
VC C A _ S M_ 8 V C C _ S M _C K _ 4
A P 16 0. 1 U _ 1 0 V _X 7 R _ 0 4 1 0U _ 6. 3 V _ X 5R _0 8
1U _ 6. 3 V _ 0 4 1U _ 6. 3 V _ 0 4 1U _ 6. 3 V _ X 5R _0 6 VC C A _ S M_ 9
L2 3
H C B 10 0 5K F -12 1 T 20
POWER 10mils
1 . 8 V _T X L V D S L9
H C B 1 00 5 K F -1 21 T 2 0
30mils K4 7
1 . 0 5V M_ MP L L V C C _ T X_ L V D S 1 .8 V
A P 28
C3 3 9 C 34 6 1. 0 5 V S A N 28 VC C A _ S M_ C K _1 C 1 38 C1 3 3
VC C A _ S M_ C K _2
C6 0 8 C8 1 A P 25
10 U _6 . 3 V _ X5 R _ 0 8 0 . 1 U _ 10 V _ X 7R _ 04 A N 25 VC C A _ S M_ C K _3 10 0 0P _ 5 0 V _X 7 R _ 0 4 1 0U _ 6. 3 V _ X 5R _0 8
VC C A _ S M_ C K _4
1U _ 6. 3 V _ 0 4 0. 1U _1 0 V _ X7 R _ 0 4 A N 24
A M 28 VC C A _ S M_ C K _5
VC C A _ S M_ C K _N CT F _ 1
02/12 A M 26
A M 25 VC C A _ S M_ C K _N CT F _ 2
A CK
A L 25 VC C A _ S M_ C K _N CT F _ 3 3. 3 V S D 17
L71 3. 3 V S _ A T V D A C A M 24 VC C A _ S M_ C K _N CT F _ 4 R B 5 5 1V -3 0
VC C A _ S M_ C K _N CT F _ 5 12mils
H C B 10 0 5 K F -12 1 T 20 10mils A L 24 C 35 R 2 35 1 0 _0 6 C A
VC C A _ S M_ C K _N CT F _ 6 V C C _H V _ 1 1 .0 5 V S
3 . 3V S A M 23 B3 5
VC C A _ S M_ C K _N CT F _ 7 V C C _H V _ 2
HV
A L 23 A3 5
VC C A _ S M_ C K _N CT F _ 8 V C C _H V _ 3
C3 8 1 C3 8 0 C 6 35 Close to U15
0. 1U _1 0 V _ X7 R _ 0 4 0. 01 U _ 1 6 V _X 7 R _ 0 4 0. 1 U _ 1 0 V _X 7 R _ 0 4
B 24
1. 5V S A 24 V C C A _ T V _D A C _ 1
TV
V C C A _ T V _D A C _ 2
R3 6 2 * 0 _0 4 V C C_ HD A
1 . 05 V M_ P E G L28
10mils
L7 R3 6 3 *1 0 m li _ sh o rt A 32 1.8A H C B 16 0 8 K F -1 21 T 25
V C C_ HD A
H DA
02/12 V4 8 1 .0 5 V S
H C B 10 0 5K F -12 1 T 20 V CC _P E G _1 U 48
02/12 V CC _P E G _2
PE G
V4 7 C 4 27 C4 2 8 C 4 33
1 . 5 V S _ QD A C V CC _P E G _3
10mils U 47
C8 3 C 82 M 25 V CC _P E G _4 U 46 0. 1 U _ 1 0 V _X 7 R _ 0 4 0 . 1U _ 10 V _ X 7R _0 4 1 0 U _ 6 . 3V _X 5 R _ 0 8
DT V/ CRT
1 . 5V S V C CD_ T V DA C V CC _P E G _5
10mils
0. 1 U _1 0 V _ X7 R _ 0 4 0 . 0 1U _1 6 V _ X7 R _0 4 C3 9 7 C3 9 6 L 28
V C CD_ Q DA C
12mils AH 48
0. 1U _1 0 V _ X7 R _ 0 4 0. 01 U _ 1 6 V _X 7 R _ 0 4 AF1 V C C_ DM I_ 1 AF 48 1 . 05 V M_ D MI L72
V C C D _ H P LL V C C_ DM I_ 2
AH 47 0 _0 4 02
DM I
10mils V C C_ DM I_ 3 0.5A
A A 47 AG 47
V C C D _ P E G _P LL V C C_ DM I_ 4
1 . 5V S _ Q D A C
C 4 32 C4 2 3 C 4 22 D03BCN? ? 0 OHM
1. 0 5 V S M 38
V C CD_ L V DS _ 1
L VD S
C3 4 5 L 37 A8 10 U _ 6 . 3 V _X 5 R _ 0 8 0 . 1U _ 10 V _ X 7R _0 4 0 . 1 U _ 1 0V _X 7 R _ 0 4
V C CD_ L V DS _ 2
VT TL F
V T T LF 1 L1
V T T LF 2
0. 1U _1 0 V _ X7 R _ 0 4 AB 2
1 . 0 5V S 1. 0 5 V M_ P E G P LL V T T LF 3
Within 10mils
L2 9 H C B 1 0 0 5K F -1 2 1 T2 0
C A N T I GA -E B 88 C TG M C 3 61 0. 47 U _ 1 0 V _0 4
C4 3 1 1 0U _ 6. 3 V _ X 5R _0 8 C4 8 0. 47 U _ 1 0 V _0 4
1 . 8 V _ LV D S C 3 48 0. 47 U _ 1 0 V _0 4
C4 2 6 0 . 1U _ 10 V _ X 7R _0 4 10mils
R 3 93 0 _ 04
1 . 8V
C4 2 5 0 . 1U _ 10 V _ X 7R _0 4
02/12 C1 0 9
Remove R360
1U _ 6. 3 V _ 0 4
[ 5 ] 1. 0 5 V M_ P E G
[ 5, 7 , 1 0 , 11 , 3 0 ] 1 . 8 V
[ 3 , 13 , 1 4 , 16 , 1 9 , 20 , 2 9 ] 1 . 5V S
[ 5 , 9 . . 16 , 1 8 . . 27 , 3 1 ] 3 . 3V S
[ 2 . . 5 , 7 , 13 , 1 6 , 29 ] 1. 0 5 V S
Cantiga 5/6 - Power B - 9

Schematic Diagrams
Cantiga 6/6 - GND
U 1 5I U1 5 J DMI X2 Select
A H8 R2 2 8 * 2. 2 K _ 1 %_ 0 4 MC H _ C F G 5 [5 ]
A U 48 A M3 6 BG 2 1 VS S _2 9 7 Y8
VSS_ 1 V S S _ 10 0 VS S _1 9 9 VS S _2 9 8 LOW : DMI=2
A R 48 AE3 6 L12 L8
A L 48 VSS_ 2 V S S _ 10 1 P3 6 AW 2 1 VS S _2 0 0 VS S _2 9 9 E8
VSS_ 3 V S S _ 10 2 VS S _2 0 1 VS S _3 0 0 HIGH: DMI=4 Default
B B 47 L 36 AU 2 1 B8
VSS_ 4 V S S _ 10 3 VS S _2 0 2 VS S _3 0 1
A W 47 J 36 AP2 1 AY7
A N 47 VSS_ 5 V S S _ 10 4 F36 AN 2 1 VS S _2 0 3 VS S _3 0 2 A U7
VSS_ 6 V S S _ 10 5 VS S _2 0 4 VS S _3 0 3
A J 47 B3 6 AH 2 1 A N7 iTPM Host Interface
A F 47 VSS_ 7 V S S _ 10 6 A H3 5 AF 2 1 VS S _2 0 5 VS S _3 0 4 A J7 R3 9 2 . 2 K _ 1% _ 0 4
VSS_ 8 V S S _ 10 7 VS S _2 0 6 VS S _3 0 5 MC H _ C F G 6 [5 ]
A D 47 AA3 5 AB2 1 AE7 LOW : Enable Default
A B 47 VSS_ 9 V S S _ 10 8 Y3 5 R 21 VS S _2 0 7 VS S _3 0 6 AA7
VSS_ 1 0 V S S _ 10 9 VS S _2 0 8 VS S _3 0 7
Y 47 U3 5 M 21 N7 HIGH: Disable
T 47 VSS_ 1 1 V S S _ 11 0 T 35 J21 VS S _2 0 9 VS S _3 0 8 J7
N 47 VSS_ 1 2 V S S _ 11 1 BF3 4 G 21 VS S _2 1 0 VS S _3 0 9 B G6
VSS_ 1 3 V S S _ 11 2 VS S _2 1 1 VS S _3 1 0
L 47 A M3 4 BC 2 0 B D6
G 47 VSS_ 1 4 V S S _ 11 3 A J 34 BA2 0 VS S _2 1 2 VS S _3 1 1 AV6
VSS_ 1 5 V S S _ 11 4 VS S _2 1 3 VS S _3 1 2 Intel Management Engine Crypto Strap
B D 46 AF3 4 AW 2 0 A T6
B A 46 VSS_ 1 6 V S S _ 11 5 AE3 4 AT 2 0 VS S _2 1 4 VS S _3 1 3 A M6
VSS_ 1 7 V S S _ 11 6 VS S _2 1 5 VS S _3 1 4 LOW : ATM Firmware use TLS cipher
A Y 46 W34 AJ 2 0 M6 R4 0 * 2. 2 K _ 1 %_ 0 4 MC H _ C F G 7 [5 ]
A V 46 VSS_ 1 8 V S S _ 11 7 B3 4 AG 2 0 VS S _2 1 6 VS S _3 1 5 C6 suite with no
VSS_ 1 9 V S S _ 11 8 VS S _2 1 7 VS S _3 1 6
A R 46 A3 4 Y 20 BA5 confidentiality
A M 46 VSS_ 2 0 V S S _ 11 9 B G3 3 N 20 VS S _2 1 8 VS S _3 1 7 A H5
VSS_ 2 1 V S S _ 12 0 VS S _2 1 9 VS S _3 1 8 HIGH: ATM Firmware use TLS cipher Default

V 46 B C3 3 K2 0 A D5
VSS_ 2 2 V S S _ 12 1 VS S _2 2 0 VS S _3 1 9 suite with confidentiality
R 46 BA3 3 F20 Y5
P 46 VSS_ 2 3 V S S _ 12 2 AV3 3 C 20 VS S _2 2 1 VS S _3 2 0 L5
VSS_ 2 4 V S S _ 12 3 VS S _2 2 2 VS S _3 2 1
H 46 A R3 3 A2 0 J5
F 46 VSS_ 2 5 V S S _ 12 4 A L 33 BG 1 9 VS S _2 2 3 VS S _3 2 2 H5
VSS_ 2 6 V S S _ 12 5 VS S _2 2 4 VS S _3 2 3 PCIE Graphics Lane
B F 44 A H3 3 A1 8 F5 R3 7 * 2. 2 K _ 1 %_ 0 4 MC H _ C F G 9 [5 ]
A H 44 VSS_ 2 7 V S S _ 12 6 AB3 3 BG 1 7 VS S _2 2 5 VS S _3 2 4 BE4
VSS_ 2 8 V S S _ 12 7 VS S _2 2 6 VS S _3 2 5 LOW : Reverse Lane Default
A D 44 P3 3 BC 1 7
Sheet 9 of 40 A A 44 VSS_ 2 9 V S S _ 12 8 L 33 AW 1 7 VS S _2 2 7 B C3 HIGH: Normal operation

Y 44
U 44
VSS_ 3 0
VSS_ 3 1
VSS_ 3 2
V S S _ 12 9
V S S _ 13 0
V S S _ 13 1
H3 3
N3 2
AT 1 7
R 17
VS
VS
VS
S _2 2 8
S _2 2 9
S _2 3 0
VSS VS
VS
VS
S _3 2 7
S _3 2 8
S _3 2 9
AV3
A L3
T 44 K3 2 M 17 R3
Cantiga 6/6 - GND VSS

VSS_ 3 3 V S S _ 13 2 VS S _2 3 1 VS S _3 3 0
M 44 F32 H 17 P3 PCIE Loopback Enable
F 44 VSS_ 3 4 V S S _ 13 3 C3 2 C 17 VS S _2 3 2 VS S _3 3 1 F3 R3 6 * 2. 2 K _ 1 %_ 0 4
VSS_ 3 5 V S S _ 13 4 VS S _2 3 3 VS S _3 3 2 MC H _ C F G 1 0 [ 5]
B C 43 A3 1 BA2 LOW : Enable
A V 43 VSS_ 3 6 V S S _ 13 5 A N2 9 BA1 6 VS S _3 3 3 AW 2
VSS_ 3 7 V S S _ 13 6 V S S _2 3 5 VS S _3 3 4
A U 43 T 29 A U2 HIGH: Disable Default
A M 43 VSS_ 3 8 V S S _ 13 7 N2 9 AU 1 6 VS S _3 3 5 A R2
J 43 VSS_ 3 9 V S S _ 13 8 K2 9 AN 1 6 VS S _2 3 7 VS S _3 3 6 AP2
VSS_ 4 0 V S S _ 13 9 VS S _2 3 8 VS S _3 3 7
C 43 H2 9 N 16 A J2
B G 42 VSS_ 4 1 V S S _ 14 0 F29 K1 6 VS S _2 3 9 VS S _3 3 8 A H2
VSS_ 4 2 V S S _ 14 1 VS S _2 4 0 VS S _3 3 9 MCH_CFG13 MCH_CFG12 Configuration
A Y 42 A2 9 G 16 AF2
A T 42 VSS_ 4 3 V S S _ 14 2 B G2 8 E1 6 VS S _2 4 1 VS S _3 4 0 AE2
VSS_ 4 4 V S S _ 14 3 VS S _2 4 2 VS S _3 4 1
A N 42 B D2 8 BG 1 5 A D2 R3 1 * 2. 2 K _ 1 %_ 0 4 MC H _ C F G 1 2 [ 5] LOW LOW Reserved
A J 42 VSS_ 4 5 V S S _ 14 4 BA2 8 AC 1 5 VS S _2 4 3 VS S _3 4 2 A C2
VSS_ 4 6 V S S _ 14 5 VS S _2 4 4 VS S _3 4 3
A E 42 AV2 8 W15 Y2
N 42 VSS_ 4 7 V S S _ 14 6 A T 28 A1 5 VS S _2 4 5 VS S _3 4 4 M2
VSS_ 4 8 V S S _ 14 7 VS S _2 4 6 VS S _3 4 5 HIGH LOW XOR Mode Enable
L 42 A R2 8 BG 1 4 K2
B D 41 VSS_ 4 9 V S S _ 14 8 A J 28 AA1 4 VS S _2 4 7 VS S _3 4 6 A M1 R3 4 * 2. 2 K _ 1 %_ 0 4
A U 41 VSS_ 5 0 V S S _ 14 9 A G2 8 C 14 VS S _2 4 8 VS S _3 4 7 AA1 MC H _ C F G 1 3 [ 5]
VSS_ 5 1 V S S _ 15 0 VS S _2 4 9 VS S _3 4 8 LOW HIGH All-Z Mode Enable
A M 41 AE2 8 BG 1 3 P1
A H 41 VSS_ 5 2 V S S _ 15 1 AB2 8 BC 1 3 VS S _2 5 0 VS S _3 4 9 H1
VSS_ 5 3 V S S _ 15 2 VS S _2 5 1 VS S _3 5 0
A D 41 Y2 8 BA1 3 HIGH HIGH Nomal Operation Default
A A 41 VSS_ 5 4 V S S _ 15 3 P2 8 VS S _2 5 2 U2 4 R3 8 * 1 0m i _l s h ort
VSS_ 5 5 V S S _ 15 4 VS S _3 5 1
Y 41 K2 8 U2 8 R4 6 * 1 0m i _l s h ort
U 41 VSS_ 5 6 V S S _ 15 5 H2 8 AN 1 3 VS S _3 5 2 U2 5 R4 1 * 1 0m i _l s h ort
T 41 VSS_ 5 7 V S S _ 15 6 F28 AJ 1 3 VS S _2 5 5 VS S _3 5 3 U2 9 R5 6 * 1 0m i _l s h ort FSB Dynamic ODT
M 41 VSS_ 5 8 V S S _ 15 7 C2 8 AE1 3 VS S _2 5 6 VS S _3 5 4 R3 3 * 2. 2 K _ 1 %_ 0 4
G 41 VSS_ 5 9 V S S _ 15 8 BF2 6 N 13 VS S _2 5 7 MC H _ C F G 1 6 [ 5]
VSS_ 6 0 V S S _ 15 9 VS S _2 5 8 LOW : Disable
B 41 A H2 6 L13 A F 32
B G 40 VSS_ 6 1 V S S _ 16 0 AF2 6 G 13 VS S _2 5 9 V S S _N C T F _ 1 A B 32
VSS_ 6 2 V S S _ 16 1 VS S _2 6 0 V S S _N C T F _ 2 HIGH: Enable Default
B B 40 AB2 6 E1 3 V 32
A V 40 VSS_ 6 3 V S S _ 16 2 AA2 6 BF 1 2 VS S _2 6 1 V S S _N C T F _ 3 A J3 0
VSS_ 6 4 V S S _ 16 3 VS S _2 6 2 V S S _N C T F _ 4
A N 40 C2 6 AV1 2 A M2 9
H 40 VSS_ 6 5 V S S _ 16 4 B2 6 AT 1 2 VS S _2 6 3 V S S _N C T F _ 5 A F 29
VSS_ 6 6 V S S _ 16 5 VS S _2 6 4 V S S _N C T F _ 6 DMI Lane Reversal
E 40 B H2 5 AM 1 2 A B 29 R5 0 * 4. 0 2 K _ 1% _ 0 4
VSS_ 6 7 V S S _ 16 6 VS S _2 6 5 V S S _N C T F _ 7 3 .3 VS MC H _ C F G 1 9 [ 5]
A T 39 B D2 5 AA1 2 U2 6
VS S NCT F
VSS_ 6 8 V S S _ 16 7 VS S _2 6 6 V S S _N C T F _ 8 LOW : Normal Default
A M 39 BB2 5 J12 U2 3
VSS_ 6 9 V S S _ 16 8 VS S _2 6 7 V S S _N C T F _ 9
A J 39 AV2 5 A1 2 A L2 0 HIGH: Lanes Reversed
A E 39 VSS_ 7 0 V S S _ 16 9 A R2 5 BD 1 1 VS S _2 6 8 V S S _ N C TF _ 1 0 V 20
VSS_ 7 1 V S S _ 17 0 VS S _2 6 9 V S S _ N C TF _ 1 1
N 39 A J 25 BB1 1 A C1 9
L 39 VSS_ 7 2 V S S _ 17 1 A C2 5 AY 1 1 VS S _2 7 0 V S S _ N C TF _ 1 2 A L1 7
VSS_ 7 3 V S S _ 17 2 VS S _2 7 1 V S S _ N C TF _ 1 3
B 39 Y2 5 AN 1 1 A J1 7 Digital Display Port
B H 38 VSS_ 7 4 V S S _ 17 3 N2 5 AH 1 1 VS S _2 7 2 V S S _ N C TF _ 1 4 A A 17
B C 38 VSS_ 7 5 V S S _ 17 4 L 25 VS S _2 7 3 V S S _ N C TF _ 1 5 U1 7 LOW : Only Digital Display Port Default
B A 38 VSS_ 7 6 V S S _ 17 5 J 25 Y 11 V S S _ N C TF _ 1 6
A U 38 VSS_ 7 7 V S S _ 17 6 G2 5 N 11 VS S _2 7 5 (SDVO/DP/iHDMI) or PCIE
VSS_ 7 8 V S S _ 17 7 VS S _2 7 6
A H 38 E2 5 G 11 B H4 8 R5 1 * 4. 0 2 K _ 1% _ 0 4 is operational
A D 38 VSS_ 7 9 V S S _ 17 8 BF2 4 C 11 VS S _2 7 7 V S S _S CB _ 1 B H1 MC H _ C F G 2 0 [ 5]
V SS S CB
VSS_ 8 0 V S S _ 17 9 VS S _2 7 8 V S S _S CB _ 2
A A 38 A D1 2 BG 1 0 A 48 HIGH: Digital Display Port
Y 38 VSS_ 8 1 V S S _ 18 0 AY2 4 AV1 0 VS S _2 7 9 V S S _S CB _ 3 C1
VSS_ 8 2 V S S _ 18 1 VS S _2 8 0 V S S _S CB _ 4 (SDVO/DP/iHDMI) and PCIE
U 38 A T 24 AT 1 0 A3
T 38 VSS_ 8 3 V S S _ 18 2 A J 24 AJ 1 0 VS S _2 8 1 V S S _S CB _ 5
VSS_ 8 4 V S S _ 18 3 VS S _2 8 2 are operational simultaneously
J 38 A H2 4 AE1 0 E1
F 38 VSS_ 8 5 V S S _ 18 4 AF2 4 AA1 0 VS S _2 8 3 N C_ 2 6 D2 via PEG port
C 38 VSS_ 8 6 V S S _ 18 5 AB2 4 M 10 VS S _2 8 4 N C_ 2 7 C3
VSS_ 8 7 V S S _ 18 6 VS S _2 8 5 N C_ 2 8
B F 37 R2 4 BF 9 B4
B B 37 VSS_ 8 8 V S S _ 18 7 L 24 BC 9 VS S _2 8 6 N C_ 2 9 A5
VSS_ 8 9 V S S _ 18 8 VS S _2 8 7 N C_ 3 0
A W 37 K2 4 AN 9 A6
A T 37 VSS_ 9 0 V S S _ 18 9 J 24 AM 9 VS S _2 8 8 N C_ 3 1 A 43
VSS_ 9 1 V S S _ 19 0 VS S _2 8 9 N C_ 3 2
A N 37 G2 4 AD 9 A 44
A J 37 VSS_ 9 2 V S S _ 19 1 F24 G 9 VS S _2 9 0 N C_ 3 3 B 45
H 37 VSS_ 9 3 V S S _ 19 2 E2 4 B 9 VS S _2 9 1 N C_ 3 4 C4 6
NC
C 37 VSS_ 9 4 V S S _ 19 3 B H2 3 BH 8 VS S _2 9 2 N C_ 3 5 D4 7
B G 36 VSS_ 9 5 V S S _ 19 4 A G2 3 BB 8 VS S _2 9 3 N C_ 3 6 B 47
VSS_ 9 6 V S S _ 19 5 VS S _2 9 4 N C_ 3 7
B D 36 Y2 3 AV 8 A 46
A K 15 VSS_ 9 7 V S S _ 19 6 B2 3 AT8 VS S _2 9 5 N C_ 3 8 F 48
VSS_ 9 8 V S S _ 19 7 VS S _2 9 6 N C_ 3 9
A U 36 A2 3 E 48
VSS_ 9 9 V S S _ 19 8 AJ 6 N C_ 4 0 C4 8
V S S _ 19 9 N C_ 4 1
B 48
N C_ 4 2
C A N T I G A -E B 8 8C TG M
C A N TI G A -E B 8 8C T GM
[ 5, 8 , 1 0 . . 16 , 1 8. . 27 , 3 1] 3 . 3V S
B - 10 Cantiga 6/6 - GND

Schematic Diagrams
DDRII CHANNEL A
SO-DIMM 1
JDIMM_1 Terminator
J D I MM_ 1 A
[6 ] M_ A _ A [ 1 4: 0 ] M _ A _A 0 1 02 5 M_ A _D Q0 M _A _ D Q [ 63 : 0 ] [6 ]
A0 DQ 0 0 .9 V S M
M _ A _A 1 1 01 7 M_ A _D Q1
M _ A _A 2 1 00 A1 DQ 1 17 M_ A _D Q2
M _ A _A 3 99 A2 DQ 2 19 M_ A _D Q3 M_ A _ R A S # 1 8 C1 0 3 0 . 1 U _ 10 V _ X7 R _0 4
M _ A _A 4 98 A3 DQ 3 4 M_ A _D Q4 M_ C S # 0 2 7 R N 16
M _ A _A 5 97 A4 DQ 4 6 M_ A _D Q5 M_ OD T 0 3 6 8 P 4R X5 6 _0 4 C9 7 0 . 1 U _ 10 V _ X7 R _0 4
A5 DQ 5
M _ A _A 6 94 14 M_ A _D Q6 M_ A _ A 1 3 4 5
M _ A _A 7 92 A6 DQ 6 16 M_ A _D Q7 1 .8 V
M _ A _A 8 93 A7 DQ 7 23 M_ A _D Q8 J D I MM_ 1 B M_ A _ A 4 1 8 C1 4 7 0 . 1 U _ 10 V _ X7 R _0 4
M _ A _A 9 91 A8 DQ 8 25 M_ A _D Q9 1 12 18 M_ A _ A 2 2 7 R N 17
M _ A _A 1 0 1 05 A9 DQ 9 35 M_ A _D Q1 0 1 11 VD D1 V S S 16 24 M_ A _ A 0 3 6 8 P 4R X5 6 _0 4 C1 1 5 0 . 1 U _ 10 V _ X7 R _0 4
A1 0 /AP DQ 1 0 VD D2 V S S 17
M _ A _A 1 1 90 37 M_ A _D Q1 1 1 17 41 M_ A B S 1 4 5
M _ A _A 1 2 89 A1 1 DQ 1 1 20 M_ A _D Q1 2 96 VD D3 V S S 18 53
M _ A _A 1 3 1 16 A1 2 DQ 1 2 22 M_ A _D Q1 3 95 VD D4 V S S 19 42 M_ C K E 1 1 8 C1 0 1 0 . 1 U _ 10 V _ X7 R _0 4
M _ A _A 1 4 86 A1 3 DQ 1 3 36 M_ A _D Q1 4 1 18 VD D5 V S S 20 54 M_ A _ A 1 1 2 7 R N 20
84 A1 4 DQ 1 4 38 M_ A _D Q1 5 81 VD D6 V S S 21 59 M_ A _ A 7 3 6 8 P 4R X5 6 _0 4 C8 9 0 . 1 U _ 10 V _ X7 R _0 4
A1 5 DQ 1 5 VD D7 V S S 22
[6 ] M_ A B S 2 M _ ABS2 85 43 M_ A _D Q1 6 82 65 M_ A _ A 6 4 5
A 1 6 _B A 2 DQ 1 6 45 M_ A _D Q1 7 87 VD D8 V S S 23 60
DQ 1 7 VD D9 V S S 24
[ 6 ] M_ A B S 0 M _ ABS0 1 07 55 M_ A _D Q1 8 1 03 66 1 8 C1 2 9 0 . 1 U _ 10 V _ X7 R _0 4
M _ ABS1 1 06 BA0 DQ 1 8 57 M_ A _D Q1 9 88 VD D1 0 V S S 25 127 M_ C K E 0 2 7 RN 7
[ 6 ] M_ A B S 1 M _ CS # 0 1 10 BA1 DQ 1 9 44 M_ A _D Q2 0 1 04 VD D1 1 V S S 26 139 M_ A _ A 1 4 3 6 8 P 4R X5 6 _0 4 C1 3 2 0 . 1 U _ 10 V _ X7 R _0 4
[ 5 ] M_ C S #0 S0 # DQ 2 0 VD D1 2 V S S 27
[ 5 ] M_ C S #1 M _ CS # 1 1 15 46 M_ A _D Q2 1 20mils 128 M_ A B S 2 4 5
Sheet 10 of 40
30 S1 # DQ 2 1 56 M_ A _D Q2 2 1 99 V S S 28 145
[ 5 ] M _C LK _ D D R 0 C K0 DQ 2 2 VDD SPD V D DS P D V S S 29
[ 5] M_ C L K _ D D R # 0 32 58 M_ A _D Q2 3 165 M_ A _ A 9 1 8 C1 2 5 0 . 1 U _ 10 V _ X7 R _0 4
1 64 C K 0# DQ 2 3 61 M_ A _D Q2 4 83 V S S 30 171 M_ A _ A 8 2 7 RN 5
[ 5 ] M _C LK _ D D R 1 1 66 C K1 DQ 2 4 63 M_ A _D Q2 5 1 20 N C1 V S S 31 172 M_ A _ A 1 2 3 6 8 P 4R X5 6 _0 4 C1 3 7 0 . 1 U _ 10 V _ X7 R _0 4
DDRII CHANNEL A
[ 5] M_ C L K _ D D R # 1 C K 1# DQ 2 5 N C2 V S S 32
[ 5 ] M_ C K E 0 M _ CK E 0 79 73 M_ A _D Q2 6 [ 5 , 1 1] P M_ E X TT S _ D D R # 50 177 M_ A _ A 5 4 5
M _ CK E 1 80 C KE0 DQ 2 6 75 M_ A _D Q2 7 69 N C3 V S S 33 187
[ 5 ] M_ C K E 1 C KE1 DQ 2 7 N C4 V S S 34
[ 6 ] M_ A _ C A S # M _ A _C A S # 1 13 62 M_ A _D Q2 8 1 63 178 M_ A _ A 1 1 8 C1 4 2 0 . 1 U _ 10 V _ X7 R _0 4
M _ A _R A S # 1 08 C AS# DQ 2 8 64 M_ A _D Q2 9 N CT E S T V S S 35 190 M_ A _ A 3 2 7 RN 3
[ 6 ] M_ A _ R A S # R AS# DQ 2 9 20mils V S S 36
M _ A _W E # 1 09 74 M_ A _D Q3 0 1 9 M_ A B S 0 3 6 8 P 4R X5 6 _0 4 C1 0 6 0 . 1 U _ 10 V _ X7 R _0 4
[ 6 ] M _A _ W E # W E# DQ 3 0 MV R E F _D I M0 VR EF V S S 37
S A 0_ D I M 0 1 98 76 M_ A _D Q3 1 21 M_ A _ A 1 0 4 5
S A 1_ D I M 0 2 00 SA0 DQ 3 1 123 M_ A _D Q3 2 2 01 V S S 38 33
SA1 DQ 3 2 G ND0 V S S 39
[ 1 1, 1 5 , 18 ] I C H _ S MB C L K 0 1 97 125 M_ A _D Q3 3 C1 6 7 C 17 4 2 02 155 M_ A _ C A S # 1 8 C9 3 0 . 1 U _ 10 V _ X7 R _0 4
1 95 SC L DQ 3 3 135 M_ A _D Q3 4 G ND1 V S S 40 34 M_ A _ W E # 2 7 RN 1
R 28 R2 7 [ 1 1, 1 5 , 18 ] I C H _ S MB D A T 0 SD A DQ 3 4 137 M_ A _D Q3 5 2 . 2U _6 . 3 V _ 06 0 . 1 U _ 10 V _ X 7R _0 4 V S S 41 132 M_ C S # 1 3 6 8 P 4R X5 6 _0 4 C1 2 1 0 . 1 U _ 10 V _ X7 R _0 4
DQ 3 5 V S S 42
[ 5 ] M_ O D T 0 M _ OD T 0 1 14 124 M_ A _D Q3 6 47 144 M_ OD T 1 4 5
1 0 K _ 04 10 K _ 04 M _ OD T 1 1 19 O DT 0 DQ 3 6 126 M_ A _D Q3 7 1 33 VSS1 V S S 43 156
[ 5 ] M_ O D T 1 O DT 1 DQ 3 7 VSS2 V S S 44
[6 ] M _A _ D M [ 7 : 0] 134 M_ A _D Q3 8 1 83 168 C9 8 0 . 1 U _ 10 V _ X7 R _0 4
M _ A _D M0 10 DQ 3 8 136 M_ A _D Q3 9 77 VSS3 V S S 45 2
M _ A _D M1 26 D M0 DQ 3 9 141 M_ A _D Q4 0 12 VSS4 V S S 46 3 C1 5 2 1 U _ 6 . 3V _ 0 4
D M1 DQ 4 0 VSS5 V S S 47
M _ A _D M2 52 143 M_ A _D Q4 1 48 15
M _ A _D M3 67 D M2 DQ 4 1 151 M_ A _D Q4 2 1 84 VSS6 V S S 48 27 C8 7 1 0 U _ 6. 3 V _ X5 R _0 8
D M3 DQ 4 2 VSS7 V S S 49
M _ A _D M4 1 30 153 M_ A _D Q4 3 78 39
M _ A _D M5 1 47 D M4 DQ 4 3 140 M_ A _D Q4 4 71 VSS8 V S S 50 149
M _ A _D M6 1 70 D M5 DQ 4 4 142 M_ A _D Q4 5 72 VSS9 V S S 51 161
D M6 DQ 4 5 VSS1 0 V S S 52 L a yo ut n o te :
M _ A _D M7 1 85 152 M_ A _D Q4 6 1 21 28
D M7 DQ 4 6 154 M_ A _D Q4 7 1 22 VSS1 1 V S S 53 40
[ 6] M_ A _ D QS [ 7 : 0 ] DQ 4 7 VSS1 2 V S S 54 Pl ac e o ne c ap clo se to ev ery 2 pu ll -u p resi sto rs
M _ A _D QS 0 13 157 M_ A _D Q4 8 1 96 138
M _ A _D QS 1 31 D QS 0 DQ 4 8 159 M_ A _D Q4 9 1 93 VSS1 3 V S S 55 150 t ermin a te d to + VT T _M EM
M _ A _D QS 2 51 D QS 1 DQ 4 9 173 M_ A _D Q5 0 8 VSS1 4 V S S 56 162
D QS 2 DQ 5 0 VSS1 5 V S S 57
M _ A _D QS 3 70 175 M_ A _D Q5 1
M _ A _D QS 4 1 31 D QS 3 DQ 5 1 158 M_ A _D Q5 2 A S 0A 4 2 1-N 2R N -4 F
D QS 4 DQ 5 2
M _ A _D QS 5 1 48 160 M_ A _D Q5 3 CLOSE TO JDIMM_1
M _ A _D QS 6 1 69 D QS 5 DQ 5 3 174 M_ A _D Q5 4
M _ A _D QS 7 1 88 D QS 6 DQ 5 4 176 M_ A _D Q5 5
D QS 7 DQ 5 5 MV R E F _D I M0
[ 6] M_ A _ D QS # [ 7 : 0 ] 179 M_ A _D Q5 6
M _ A _D QS # 0 11 DQ 5 6 181 M_ A _D Q5 7
D QS 0 # DQ 5 7
M _ A _D QS # 1 29 189 M_ A _D Q5 8 1 .8 V R8 0 1 K _ 1% _ 04
M _ A _D QS # 2 49 D QS 1 # DQ 5 8 191 M_ A _D Q5 9
M _ A _D QS # 3 68 D QS 2 # DQ 5 9 180 M_ A _D Q6 0
D QS 3 # DQ 6 0
M _ A _D QS # 4 1 29 182 M_ A _D Q6 1 R8 1 C 1 76 C 1 73
M _ A _D QS # 5 1 46 D QS 4 # DQ 6 1 192 M_ A _D Q6 2
D QS 5 # DQ 6 2
M _ A _D QS # 6 1 67 194 M_ A _D Q6 3 1 K _1 % _0 4 1U _6 . 3 V _ 04 0. 1 U _ 1 0V _ X 7 R _ 04
M _ A _D QS # 7 1 86 D QS 6 # DQ 6 3
D QS 7 #
A S 0A 4 2 1-N 2 R N -4 F
1 . 8V
CLOSE TO JDIMM_1
C1 6 1 C 38 2 C1 1 1 C1 3 5 C1 4 5 C1 3 9 C 1 49
*1 50 U _4 V _ B 2 22 0 U _ 4 V _D 1 U _ 6. 3 V _ 0 4 1 U _ 6. 3 V _ 0 4 1 U _ 6. 3 V _ 0 4 *0 . 2 2 U _ 16 V _ X7 R _0 6 * 0 . 22 U _ 1 6V _ X 7 R _ 06 3 . 3V S D8 VD DSPD 0 . 9V S M
R B 5 5 1 V -30
A C
1 .8 V C4 6 C 47 C 1 54 C1 4 8
*2 . 2 U _ 6. 3 V _ 0 6 0 . 1 U _ 16 V _ 0 4 1 0 U _ 1 0V _ 0 8 10 U _1 0 V _0 8
C1 6 3 C1 5 3 C1 3 0 C8 6 C1 0 0 C1 1 9
*1 50 U _4 V _ B 2 10 U _6 . 3 V _X 5 R _ 0 8 1 0U _6 . 3 V _ X5 R _ 0 8 1 0U _6 . 3 V _ X5 R _ 0 8 4 . 7U _6 . 3 V _ X5 R _ 0 6 4 . 7U _ 6. 3 V _ X5 R _ 0 6
1 .8 V
C1 2 4 C1 3 6 C1 2 3 C9 1 C3 9 1 C9 0 C1 1 0 C 14 4
0. 1 U _1 0 V _X 7 R _ 0 4 0. 1U _1 0 V _X 7 R _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4 0 . 1U _ 10 V _ X7 R _ 0 4 0 . 1U _ 10 V _ X7 R _0 4 0 . 1 U _ 10 V _ X7 R _0 4
[1 1 ] V D DS P D
[ 11 , 3 0 ] 0 . 9V S M
[ 5, 7 , 8 , 11 , 3 0 ] 1 . 8V
[ 5 , 8 , 9, 1 1 . . 1 6, 1 8 . . 27 , 3 1 ] 3 . 3V S
DDRII CHANNEL A B - 11
Schematic Diagrams
DDRII CHANNEL B
SO-DIMM 2 La yo ut no te :
JDIMM_2 is placed farther JDIMM_2 Terminator
from the GMCH than JDIMM_1 0 .9 V S M
16 -5 603 4-4 5A
JD I MM _2 A
[6 ] M_ B _ A [ 1 4: 0 ] M _B _ D Q[ 6 3: 0 ] [ 6]
M _ B _A 0 102 5 M _B _ D Q 0 M_ OD T 3 1 8 C4 0 8 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 1 101 A0 DQ 0 7 M _B _ D Q 1 M_ C S # 3 2 7 R N 15
M _ B _A 2 100 A1 DQ 1 17 M _B _ D Q 2 M_ B _ C A S # 3 6 8 P 4R X5 6 _0 4 C4 1 2 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 3 99 A2 DQ 2 19 M _B _ D Q 3 M_ B _ W E # 4 5
M _ B _A 4 98 A3 DQ 3 4 M _B _ D Q 4
A4 DQ 4
M _ B _A 5 97 6 M _B _ D Q 5 M_ B B S 0 1 8 C4 1 1 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 6 94 A5 DQ 5 14 M _B _ D Q 6 M_ B _ A 1 0 2 7 R N 18
M _ B _A 7 92 A6 DQ 6 16 M _B _ D Q 7 1. 8 V M_ B _ A 1 3 6 8 P 4R X5 6 _0 4 C4 0 2 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 8 93 A7 DQ 7 23 M _B _ D Q 8 J D I M M_ 2B M_ B _ A 3 4 5
M _ B _A 9 91 A8 DQ 8 25 M _B _ D Q 9 11 2 18
A9 DQ 9 VDD 1 VSS1 6
M _ B _A 1 0 105 35 M _B _ D Q 10 11 1 24 M_ B _ A 5 1 8 C4 0 4 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 1 1 90 A 1 0 /A P D Q1 0 37 M _B _ D Q 11 11 7 VDD 2 VSS1 7 41 M_ B _ A 8 2 7 R N 19
M _ B _A 1 2 89 A1 1 D Q1 1 20 M _B _ D Q 12 96 VDD 3 VSS1 8 53 M_ B _ A 9 3 6 8 P 4R X5 6 _0 4 C4 1 8 0 . 1 U _ 10 V _ X7 R _0 4
M _ B _A 1 3 116 A1 2 D Q1 2 22 M _B _ D Q 13 95 VDD 4 VSS1 9 42 M_ B _ A 1 2 4 5

M _ B _A 1 4 86 A1 3 D Q1 3 36 M _B _ D Q 14 11 8 VDD 5 VSS2 0 54
A1 4 D Q1 4 VDD 6 VSS2 1
84 38 M _B _ D Q 15 81 59 M_ B _ R A S # 1 8 C4 0 3 0 . 1 U _ 10 V _ X7 R _0 4
M_ B B S 2 85 A1 5 D Q1 5 43 M _B _ D Q 16 82 VDD 7 VSS2 2 65 M_ C S # 2 2 7 RN 2
[6 ] M_ B B S 2 A1 6 _ BA2 D Q1 6 VDD 8 VSS2 3
45 M _B _ D Q 17 87 60 M_ B _ A 1 3 3 6 8 P 4R X5 6 _0 4 C4 1 6 0 . 1 U _ 10 V _ X7 R _0 4
M_ B B S 0 107 D Q1 7 55 M _B _ D Q 18 10 3 VDD 9 VSS2 4 66 M_ OD T 2 4 5
[ 6 ] M_ B B S 0 M_ B B S 1 106 BA0 D Q1 8 57 M _B _ D Q 19 88 VDD 10 VSS2 5 1 27
[ 6 ] M_ B B S 1 BA1 D Q1 9 VDD 11 VSS2 6
[ 5 ] M_ C S #2 M_ C S # 2 110 44 M _B _ D Q 20 10 4 1 39 M_ B _ A 4 1 8 C4 0 0 0 . 1 U _ 10 V _ X7 R _0 4
M_ C S # 3 115 S0 # D Q2 0 46 M _B _ D Q 21 VDD 12 VSS2 7 1 28 M_ B _ A 2 2 7 RN 4
Sheet 11 of 40
[ 5 ] M_ C S #3 S1 # D Q2 1 20mils VSS2 8
[ 5 ] M _C LK _ D D R 2 30 56 M _B _ D Q 22 V DD S P D 19 9 1 45 M_ B _ A 0 3 6 8 P 4R X5 6 _0 4 C4 1 4 0 . 1 U _ 10 V _ X7 R _0 4
32 C K0 D Q2 2 58 M _B _ D Q 23 VDD SP D VSS2 9 1 65 M_ B B S 1 4 5
[ 5] M_ C L K _ D D R # 2 164 C K0 # D Q2 3 61 M _B _ D Q 24 83 VSS3 0 1 71
[ 5 ] M _C LK _ D D R 3 C K1 D Q2 4 NC1 VSS3 1
DDRII CHANNEL B
[ 5] M_ C L K _ D D R # 3 166 63 M _B _ D Q 25 12 0 1 72 M_ B _ A 1 1 1 8 C4 1 9 0 . 1 U _ 10 V _ X7 R _0 4
M_ C K E 2 79 C K1 # D Q2 5 73 M _B _ D Q 26 50 NC2 VSS3 2 1 77 M_ B _ A 1 4 2 7 RN 6
[ 5 ] M_ C K E 2 C KE0 D Q2 6 [ 5 , 10 ] P M _ E XT T S _D D R # NC3 VSS3 3
R 26 [ 5 ] M_ C K E 3 M_ C K E 3 80 75 M _B _ D Q 27 69 1 87 M_ B _ A 6 3 6 8 P 4R X5 6 _0 4 C1 0 7 0 . 1 U _ 10 V _ X7 R _0 4
M_ B _C A S # 113 C KE1 D Q2 7 62 M _B _ D Q 28 16 3 NC4 VSS3 4 1 78 M_ B _ A 7 4 5
1 0 K _0 4 [ 6 ] M_ B _ C A S # M_ B _R A S # 108 C AS# D Q2 8 64 M _B _ D Q 29 NCT E S T VSS3 5 1 90
[ 6 ] M_ B _ R A S # R AS# D Q2 9 20mils VSS3 6
[ 6 ] M _B _ W E # M_ B _W E # 109 74 M _B _ D Q 30 M V RE F _ DIM 1 1 9 1 8
S A 0_ D I M1 198 W E# D Q3 0 76 M _B _ D Q 31 VREF VSS3 7 21 2 7 RN 8
SA0 D Q3 1 VSS3 8
S A 1_ D I M1 200 12 3 M _B _ D Q 32 C 1 70 C1 7 9 20 1 33 M_ C K E 3 3 6 8 P 4R X5 6 _0 4 C1 0 5 0 . 1 U _ 10 V _ X7 R _0 4
197 SA1 D Q3 2 12 5 M _B _ D Q 33 20 2 GN D 0 VSS3 9 1 55 M_ B B S 2 4 5
[ 1 0, 1 5 , 18 ] I C H _ S MB C L K 0 195 SC L D Q3 3 13 5 M _B _ D Q 34 2 . 2 U _ 6 . 3V _ 0 6 0. 1 U _1 0 V _X 7 R _ 0 4 GN D 1 VSS4 0 34
[ 1 0, 1 5 , 18 ] I C H _ S MB D A T 0 SD A D Q3 4 VSS4 1
R 25 13 7 M _B _ D Q 35 1 32 M_ C K E 2 R2 3 7 5 6 _ 04 C4 1 3 0 . 1 U _ 10 V _ X7 R _0 4
M_ OD T 2 114 D Q3 5 12 4 M _B _ D Q 36 47 VSS4 2 1 44
[5 ] M_ O D T 2 O DT 0 D Q3 6 VSS1 VSS4 3
1 0 K _0 4 [5 ] M_ O D T 3 M_ OD T 3 119 12 6 M _B _ D Q 37 13 3 1 56
O DT 1 D Q3 7 13 4 M _B _ D Q 38 18 3 VSS2 VSS4 4 1 68 C1 5 1 0 . 1 U _ 10 V _ X7 R _0 4
M_ B _D M0 10 D Q3 8 13 6 M _B _ D Q 39 77 VSS3 VSS4 5 2
[6 ] M_ B _ D M 0 D M0 D Q3 9 VSS4 VSS4 6
[6 ] M_ B _ D M 1 M_ B _D M1 26 14 1 M _B _ D Q 40 12 3 C4 1 0 1 U _ 6 . 3V _ 0 4
3 .3 V S M_ B _D M2 52 D M1 D Q4 0 14 3 M _B _ D Q 41 48 VSS5 VSS4 7 15
[6 ] M_ B _ D M 2 D M2 D Q4 1 VSS6 VSS4 8
[6 ] M_ B _ D M 3 M_ B _D M3 67 15 1 M _B _ D Q 42 18 4 27 C3 6 9 *1 0 U _ 6 . 3V _ X 5 R _ 08
M_ B _D M4 130 D M3 D Q4 2 15 3 M _B _ D Q 43 78 VSS7 VSS4 9 39
[6 ] M_ B _ D M 4 M_ B _D M5 147 D M4 D Q4 3 14 0 M _B _ D Q 44 71 VSS8 VSS5 0 1 49
La y ou t no t e:
[6 ] M_ B _ D M 5 D M5 D Q4 4 VSS9 VSS5 1
[6 ] M_ B _ D M 6 M_ B _D M6 170 14 2 M _B _ D Q 45 72 1 61 Pla ce o n e ca p cl o se to e ve ry 2 p u ll- up re sist ors
M_ B _D M7 185 D M6 D Q4 5 15 2 M _B _ D Q 46 12 1 VSS1 0 VSS5 2 28
[6 ] M_ B _ D M 7 D M7 D Q4 6 VSS1 1 VSS5 3 te rmin at e d to + VT T_ MEM
15 4 M _B _ D Q 47 12 2 40
13 D Q4 7 15 7 M _B _ D Q 48 19 6 VSS1 2 VSS5 4 1 38
[6 ] M_ B _ D Q S0 31 D QS 0 D Q4 8 15 9 M _B _ D Q 49 19 3 VSS1 3 VSS5 5 1 50
[6 ] M_ B _ D Q S1 D QS 1 D Q4 9 VSS1 4 VSS5 6
[6 ] M_ B _ D Q S2 51 17 3 M _B _ D Q 50 8 1 62
70 D QS 2 D Q5 0 17 5 M _B _ D Q 51 VSS1 5 VSS5 7
[6 ] M_ B _ D Q S3 D QS 3 D Q5 1 CLOSE TO JDIMM_2
[6 ] M_ B _ D Q S4 131 15 8 M _B _ D Q 52 A S 0 A 4 21 -N 2 A N - 4F
148 D QS 4 D Q5 2 16 0 M _B _ D Q 53
[6 ] M_ B _ D Q S5 169 D QS 5 D Q5 3 17 4 M _B _ D Q 54 M V RE F _ DIM 1
[6 ] M_ B _ D Q S6 D QS 6 D Q5 4
[6 ] M_ B _ D Q S7 188 17 6 M _B _ D Q 55
D QS 7 D Q5 5 17 9 M _B _ D Q 56 R7 9 1 K _ 1% _ 04
D Q5 6 1 .8 V
[6 ] M_ B _ D Q S #0 11 18 1 M _B _ D Q 57
29 D QS 0 # D Q5 7 18 9 M _B _ D Q 58
[6 ] M_ B _ D Q S #1 49 D QS 1 # D Q5 8 19 1 M _B _ D Q 59 R 78 C1 7 1 C1 7 7
[6 ] M_ B _ D Q S #2 D QS 2 # D Q5 9
[6 ] M_ B _ D Q S #3 68 18 0 M _B _ D Q 60
129 D QS 3 # D Q6 0 18 2 M _B _ D Q 61 1 K _ 1% _ 0 4 1 U _ 6 . 3V _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4
[6 ] M_ B _ D Q S #4 D QS 4 # D Q6 1
[6 ] M_ B _ D Q S #5 146 19 2 M _B _ D Q 62
167 D QS 5 # D Q6 2 19 4 M _B _ D Q 63
[6 ] M_ B _ D Q S #6 186 D QS 6 # D Q6 3
[6 ] M_ B _ D Q S #7 D QS 7 #
A S 0A 42 1 -N 2 A N -4 F
1 .8 V
C 75 C 1 22 C 1 62 C9 6 C 1 08 C1 0 4 C1 3 4 C1 2 0 C1 1 6 C1 2 6
*1 5 0U _4 V _ B 2 10 U _ 6 . 3V _X 5 R _ 08 10 U _ 6 . 3 V _X 5 R _ 08 0. 1 U _ 1 0 V _X 7 R _ 0 4 0. 1 U _1 0 V _X 7 R _ 0 4 0. 1 U _1 0 V _X 7 R _ 0 4 0 . 1U _1 0 V _X 7 R _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4 4 . 7U _6 . 3 V _ X5 R _ 0 6 4 . 7U _ 6. 3 V _ X5 R _ 0 6
1 .8 V
C 92 C1 5 6 C 4 21 C9 9 C 1 02 C1 4 1 C1 2 8 C9 5 C1 5 0 C1 6 0
*2 2 0U _4 V _ D *1 50 U _ 4 V _ B 2 1U _6 . 3 V _ 04 1U _6 . 3 V _ 04 1U _6 . 3 V _ 04 0. 1 U _1 0 V _X 7 R _ 0 4 0 . 1U _1 0 V _X 7 R _ 0 4 0 . 1U _1 0 V _ X7 R _ 0 4 *0 . 2 2U _ 16 V _ X7 R _ 0 6 *0 . 2 2U _ 16 V _ X7 R _0 6
[ 10 , 3 0 ] 0 . 9V S M
[1 0 ] V D DS P D
[ 5, 7 , 8 , 10 , 3 0 ] 1 . 8V
[ 5, 8 . . 1 0, 1 2 . . 1 6, 1 8 . . 27 , 3 1 ] 3 . 3V S
B - 12 DDRII CHANNEL B
Schematic Diagrams
Panel, Inverter, CRT
CRT 5 VS 5V S Zo=55 Ohm

R1 8 8 2 . 2 K _0 4 L63 F C M1 0 05 K F -1 2 1T 0 3
3. 3 V S
Q1 6 C R T_ H S Y N C CRT _ HS Y NC_ R
G
Q2 6 2 N 7 00 2 W R1 9 0 2 . 2 K _0 4
2N 70 0 2W L64 F C M1 0 05 K F -1 2 1T 0 3
CRT _ HS Y N C D S D A C_ HS Y NC [5 ] C R T_ D D C A D A T D S D A C _ D D C A D A TA [5 ] C R T_ V S Y N C CRT _ V S Y N C_ R
G
Q2 7 Q1 7 L65 F C M1 0 05 K F -1 2 1T 0 3
2N 70 0 2W 2 N 7 00 2 W C R T_ D D C A C LK CRT _ DD CA CL K _ R
CRT _ V S Y N C D S C R T_ D D C A C LK D S
D A C_ V S Y N C [ 5] D A C _ D D C A C LK [5 ]
L66 F C M1 0 05 K F -1 2 1T 0 3
C R T_ D D C A D A T CRT _ DD CA DA T _ R
R3 9 8 1 K _ 04 R1 9 1 2 . 2 K _0 4
D3 1 A S D 75 1 V D1 4 A S D7 5 1 V
R3 9 9 1 K _ 04 C A R1 8 9 2 . 2 K _0 4 C A
3 . 3V S 5V S
3 .3 VS
Zo=50 Ohm Zo=55 Ohm
C
A
A
5V S
D 7 D6 D5 J_ C R T1
BAV9 9 B A V 99 BAV9 9 C 1 0 50 9 -91 5 0 5-L
AC
AC
AC
D1 3
C
A
A
L60 F C M1 0 05 K F -1 2 1T 0 3 D A C _ R E D _R 1 *A S D 7 5 1V C 2 97
[ 5] DA C_ R E D
9 Z 1 10 9 C A
L61 F C M1 0 05 K F -1 2 1T 0 3 D A C _ GR E E N _ R 2 *0 . 1U _ 16 V _ 04
[5 ] D A C _ GR E E N
10 D 4 D2 D1 D 3
A C
AC
AC
AC
L62 F C M1 0 05 K F -1 2 1T 0 3 D AC_ B L UE _ R 3 * B A V 99 *B A V 9 9 *B A V 9 9 * BAV9 9
[5 ] D A C_ B L UE
Sheet 12 of 40
11
4
R1 7 R1 5 R 14 C 31 7 C3 1 4 C 3 10 C3 4 C3 0 C 27 12 C R T _ D D C A D A T _R
5
Panel, Inverter,
1 50 _ 1% _ 0 4 15 0 _1 % _ 04 1 5 0 _1 % _0 4 2 2 P _5 0 V _0 4 2 2P _ 5 0V _0 4 22 P _ 5 0V _ 0 4 47 P _ 5 0V _ 0 4 47 P _ 50 V _ 0 4 4 7 P _5 0 V _ 04 13 C RT _ HS Y N C_ R
6
14 C R T _ V S Y N C _R
7
CRT
15 C R T _ D D C A C L K _R
8
GN D 1
GN D 2
1 2 3 4 5 C 28 C2 5 C1 9 C 18
6 11 7 12 8 13 9 14 10 15 1 0 00 P _ 5 0V _ X 7R _0 4 22 0 P _ 50 V _ 04 2 20 P _ 5 0V _ 0 4 1 0 00 P _ 5 0V _ X 7R _0 4
J_CRT1 Solder side
PANEL P LV D D INVERTER CONNECTOR

C1
C6 2 2 C6 2 3 C 6 24 C 62 5 For CCFL Panel only
2A 0. 1 U _1 6 V _0 4
J _ LC D 1 *1 0 P _ 50 V _ 04 *1 0 P _5 0 V _0 4 *1 0P _ 5 0V _ 0 4 * 10 P _ 50 V _ 0 4
1 2 L V D S -L 0N 3. 3V 3. 3 V V IN V IN_ INV
LV D S -L0 N [ 5 , 27 ] L21
L V D S -L0 N 3 4 L V D S -L 0P H C B 1 60 8 K F -1 21 T 25
L V D S -L0 P 5 6 3 . 3V S L V D S -L 2N LV D S -L0 P [ 5, 2 7 ]
7 8 L V D S -L 2P LV D S -L2 N [ 5 , 27 ]
P _ DD C_ CL K C2 7 3 LV D S -L2 P [ 5, 2 7 ]
L V D S -L2 N 9 10 P _ DD C_ DA T A L V D S -L 1N R1 8 7 *1 0 0 K _0 4 U 1 0A C3 0 6 C 30 0 C 2 93
14
1 1 12 L V D S -L 1P LV D S -L1 N [ 5 , 27 ]
L V D S -L2 P *0 . 1 U _ 16 V _ 0 4 LV D S -L1 P [ 5, 2 7 ] 74 L V C 0 8 P W U1 0 B
14
1 3 14 L V D S -LC LK N L V D S -L C L K N 1 7 4L V C 0 8 P W *0 . 1 U _ 1 6V _ 0 4 * 0. 1 U _5 0 V _0 6 0. 1 U _ 5 0V _ 0 6
L V D S -L1 N 1 5 16 L V D S -LC LK P L V D S -L C L K P LV D S -LC LK N [ 5 , 2 7] [ 1 5] S B _ B LO N 3 4
1 7 18 LV D S -LC LK P [ 5 , 27 ] 40 mil
L V D S -L1 P [ 2 6] B K L _E N 2 6
1 9 20 5
8 8 10 7 -20 0 0 1 C6 2 6 C6 2 7 C 6 28 C 62 9
U 1 0C J _ INV 1
14
*1 0 P _ 50 V _ 04 *1 0 P _5 0 V _0 4 *1 0P _ 5 0V _ 0 4 * 10 P _ 50 V _ 0 4 R5 7 1 00 K _ 0 4 74 L V C 0 8 P W
7
1
9
8 R 3 92 4 7K _ 0 4 2
[5 ] GM _ B LO N 3. 3V 10 3
3 .3 VS 4
5
6
14
R1 6 4 2 . 2 K _ 04 P _ DD C_ CL K P _ D D C _ C L K [ 5 , 27 ] R1 8 4 C 3 07
7
R1 6 3 2 . 2 K _ 04 P _ DD C_ DA T A 12 87 2 1 2-0 6 G0
P _ D D C _ D A T A [ 5 , 2 7] [ 1 9 , 26 ] L I D _S W # 11 *1 M_ 0 4 0. 1 U _ 1 6V _0 4
[ 5 , 15 , 1 7 , 26 ] C L_ P W R OK 13
U1 0 D 6-2 0-4 1A 10- 106
3 .3 V 7 4L V C 0 8 P W
7
S Y S 1 5V S Y S 1 5V
2A J_INV1
[ 27 ] I N V _ B LO N
1
Q2 2 C 61 8
[ 2 6, 2 7 ] B R I GH T N E S S
R3 7 7 R3 7 8 1 6
D D *0 . 1 U _ 1 6V _ 0 4 6
1 M_ 04 1 M_ 0 4 2 5
D D
3 4 2A
G S P L V DD
Q 23 Q2 4
C
D T C 1 1 4E U A 2 N 7 0 02 W S I 34 5 6B D V -T 1-E 3
B R 3 79 R 3 80
[5 ] E N A V DD
G C6 1 9 R3 8 1
20 0 _0 6 * 2 00 _ 06
R 38 2 0 . 02 2 U _ 25 V _ X 7R _0 6 *1 0 0K _ 0 4
S
E
* 10 0 K _0 4
D
Q2 5
[ 2 7 . . 29 ] S Y S 1 5V
G 2 N 7 0 02 W [ 2 , 13 . . 1 7, 1 9 , 2 0, 2 3 , 29 , 3 0] 3 . 3V
[ 5 , 8 . . 1 1, 1 3 . . 16 , 1 8 . . 27 , 3 1] 3 . 3V S
S
[ 1 3 , 16 , 1 9, 21 , 2 4, 2 5 , 27 ] 5V S
[ 2 7. . 3 2 ] V I N
[ 2 7] P L V D D
Panel, Inverter, CRT B - 13

Schematic Diagrams
ICH9-M 1/5 - SATA
R TC V C C
U2 3 A
RT C_ X 1 C 23 K5 LP C _ A D 0 [ 1 9 , 2 6]
R TC X1 F W H 0/ L A D 0
RT C_ X 2 C 24 K4
D 10 C 1 69 R TC X2 F W H 1/ L A D 1 L6 L P C _A D 1 [ 1 9 , 26 ]
F W H 2/ L A D 2 L P C _A D 2 [ 1 9 , 26 ]
A S D7 5 1 V RT CR S T # A 25 K2
A C 1U _6 . 3 V _ 04 SRT CR S T # F 20 R TC R S T # F W H 3/ L A D 3 LP C _ A D 3 [ 1 9 , 2 6]
V DD 3 S R TC R S T #
L PC
RTC
INT RU DE R # C 22 K3 L P C _F R A ME # [ 19 , 2 6 ]
I N TR U D E R # F W H4 /L F RA M E #
20mils D 9 I C H _ I N T V R ME N B 22 J3 L P C _D R Q 0#
JCBAT J CB A T 1 A S D7 5 1 V R 94 1M _0 4 A 22 I N TV R ME N L D R Q0 # J1 L D R Q1 #
R 24 5 1 K _ 04 A C INT RU DE R # L A N 1 0 0 _S L P L D R Q1 # / GP I O2 3
2 GL A N _ C LK E 25 N7 GA 20
1 R 96 33 2 K _ 1% _ 06 G LA N _ C L K A 20 G A TE A J2 7 G A 2 0 [ 2 6]
1 2 A 2 0M # H _ A 20 M# [ 2]
8 52 0 5 -02 0 0 1 I C H _I N T V R M E N LA N _ R S T S Y N C C 13
L A N _ R S TS Y N C A J2 5 I C H _ D P R S TP # R2 6 3 * 10 m li _ s ho rt H_ D PRS T P #
DP R S T P # H _ D P S LP # H _D P R S T P # [ 2, 5 , 3 1 ]
LA N _ R X D 0 F 14 A E 23 IC H_ DP S L P # R2 6 1 * 10 m li _ s ho rt H _D P S L P # [ 2 ]
L A N _ R XD 0 D PSL P#
LAN / G LA N
LA N _ R X D 1 G 13
L A N _ R XD 1 H_ F E R R#
LA N _ R X D 2 D 14 A J2 6 IC H_ F E RR # R2 6 2 56 _ 0 4 H _F E R R # [ 2]
1 .5 V S L A N _ R XD 2 F E RR #
LA N _ TX D 0 D 13 A D2 2 H _ PW RG D [ 2]
LA N _ TX D 1 D 12 L A N_ T X D0 C P U P W R GD
LA N _ TX D 2 E 13 L A N_ T X D1 A F 25
L A N_ T X D2 IG NN E # H _ I GN N E # [2 ]
C 45 3 R2 5 8
C PU
GP I O 56 B 10 A E 22 R9 3 * 10 m li _ s ho rt
G P I O5 6 I NIT # H _I N I T # [2 ]
0 . 1 U _ 1 6V _0 4 2 4 . 9_ 1 % _0 4 A G2 5
RT C V CC RT CV C C B 28 INT R L3 K B C _R S T # H _ I N T R [ 2]
G LA N _ C OM P I R CIN # K B C_ RS T # [2 6 ]
B 27
G LA N _ C OM P O A F 23
N MI H _ N MI [ 2 ]
A Z _ B I TC L K AF 6 A F 24 H _ S MI # [ 2 ]
R 95 R7 6 AZ _ SYN C AH4 H D A _ B I T _C L K SM I#
H DA _ S Y N C
A H2 7 H _ S TP C L K # [2 ]
S TP C L K #
Sheet 13 of 40
2 0 K _ 1% _ 0 4 2 0K _1 % _0 4 AZ _ RST # AE7
H DA _ RS T #
A G2 6 S B _ T H R MT R I P # P M_ TH R M TR I P # P M _ TH R M TR I P # [ 2 , 5 , 28 ]
S RT CR S T # RT CR ST # 35mil AF 4 T H R MT R I P #
[ 2 4] A Z _ SDIN 0 A G4 H DA _ S DIN 0 A G2 7 R2 5 7 54 . 9 _ 1% _ 0 4
[ 1 9] A Z _ SDIN 1
ICH9-M 1/5 - SATA

H DA _ S DIN 2 AH3 H DA _ S DIN 1 TP1 2
H DA _ S DIN 2
IHD A
C 2 13 C1 7 2 H DA _ S DIN 3 AE5
25mil H DA _ S DIN 3
JO P E N 1 A H1 1 R3 1 9 *1 0 K _0 4
1 U _6 . 3 V _ 04 1 U _ 6 . 3V _ 0 4 *O P E N _ 3 5m i l A Z _ S D OU T A G5 S AT A 4 RXN A J1 1 R3 1 8 *1 0 K _0 4
5mil H DA _ S DO UT S A TA 4 R XP
C lea r CM OS A G1 2
H DA _ DO CK _ E N # A G7 S A T A 4 TX N A F 12
H D A _ D O C K _ E N # / G P I O3 3 S A T A 4 T XP
[2 5 ] S B _ MU T E # S B _ M UT E # AE8
H D A _ D O C K _ R S T # / GP I O 3 4 A H9 R3 2 4 *1 0 K _0 4
S AT A 5 RXN
[ 19 ] S A T A _L E D # A G8 A J9 R3 2 5 *1 0 K _0 4
SA T A L E D# S A TA 5 R XP A E 10
S A T A _ RX N0 C 5 21 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A J 16 S A T A 5 TX N A F 10
S A T A _ RX P 0 C 5 31 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A H 16 SA T A 0 RX N S A T A 5 T XP
S A T A _ T XN 0 C 5 13 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A F 17 SA T A 0 RX P A H1 8
SAT A
S A T A 0 T XN S A T A _ CL K N C L K _S A T A # [ 18 ] 3 .3 V S
Zo= 55O? 5% S A T A _ T XP 0 C 5 10 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A G 17 A J1 8
S A T A 0 T XP S A TA _ C LK P C L K _S A T A [ 1 8]
Z diff= 10 0O? 0%
[ 1 9] S A T A _ RX N1 C 2 33 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A H 13 A J7 KB C _ RS T # R 3 48 1 0 K _ 04
C4 9 6 1 5 P _ 50 V _ 0 4 R T C_ X 1 C 2 34 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A J 13 SA T A 1 RX N SA T A RB IA S # A H7 R3 2 6 24 . 9 _ 1% _ 0 4 G A2 0 R 1 29 1 0 K _ 04
[ 1 9] S A T A _ RX P 1 SA T A 1 RX P S A T A RB IA S
[ 19 ] S A T A _T X N 1 C 2 31 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A G 14 A Z _ S D OU T R 1 35 * 1K _ 0 4
C 2 32 0 . 01 U _ 1 6 V _X 7 R _ 0 4 A F 14 S A T A 1 T XN SB _ M UT E# R 1 24 1 0 K _ 04
[ 19 ] S A T A _T X P 1 S A T A 1 T XP Within 500mil
2
1
X4 R 2 91 I C H 9 M- N H 8 2 8 01 I B M
3 2 . 7 68 K H z
1 0 M_ 0 4 1 .0 5 VS
3
4
H _F E R R # R 2 55 5 6 _0 4
C4 8 3 1 5 P _ 50 V _ 0 4 R T C_ X 2 H _D P R S T P # R 2 56 * 56 _ 0 4
H _D P S L P # R 2 54 * 56 _ 0 4
P M _ TH R M TR I P # R 2 50 5 6 _0 4
3 . 3V
G P I O5 6 R 1 20 1 0 K _ 04
Layout Note:
VERY CLOSE TO ICH9M
R 13 8 3 3 _0 4
[ 24 ] A U D _A Z _ S D OU T
A Z _S D OU T
SATA HDD [ 19 ] MD C _ A Z _ S D OU T
R 12 6
R 13 1
3 3 _0 4
3 3 _0 4
[ 24 ] A U D _A Z _ B I T C L K
A Z _B I T C LK
J _ HD D1 R 13 0 3 3 _0 4
S1 [ 19 ] MD C _ A Z _ B I TC L K
S2 S A T A _ T XP 0
S3 S A T A _ T XN 0 R 13 9 3 3 _0 4
[ 2 4] A U D_ AZ _ S YNC
S4 A Z _S Y N C
S5 SA T A _ RX N0 R 12 5 3 3 _0 4
[ 1 9] MD C _ A Z _ S Y N C
S6 SA T A _ RX P 0
S7
3. 3 V S R 13 3 3 3 _0 4
[ 2 4, 2 5 ] A U D_ A Z _ RS T # A Z _R S T #
1.5A
P1 R 12 3 3 3 _0 4
P2 [1 9 ] M D C _A Z _R S T #
P3 C1 4 C2 1
P4
P5 0 . 1U _1 6 V _ 0 4 10 U _ 1 0 V _0 8
P6
P7 5 VS
P8 1.0A
P9
P1 0
P1 1
P1 2 C1 1 C 6 C 12 C1 3 C 22 C2 9 4
P1 3
[ 2 , 1 2, 1 4 . . 1 7, 19 , 2 0, 23 , 2 9 , 30 ] 3. 3 V
P1 4 0 . 1U _1 6 V _ 0 4 0 . 1 U _ 1 6V _ 0 4 0 . 1 U _ 1 6 V _0 4 1U _ 10 V _ 0 6 1 0 U _ 1 0 V _0 8 *1 0 0U _6 . 3 V _ B 2 [ 2 1 , 26 . . 3 0 , 32 ] V D D 3
P1 5
[ 5 , 8 . . 1 2, 1 4 . . 1 6, 1 8 . . 2 7 , 31 ] 3. 3 V S
[ 1 2, 1 6 , 1 9, 2 1 , 2 4, 25 , 2 7] 5 V S
C 1 6 6 23 -1 22 A 4
P IN G ND 1 ~ 2 = G ND [ 3 , 8, 14 , 1 6, 19 , 2 0 , 29 ] 1. 5 V S
[1 6 ] RT C VCC
[ 2 . . 5, 7 , 8 , 1 6 , 29 ] 1. 0 5 V S
B - 14 ICH9-M 1/5 - SATA

Schematic Diagrams
ICH9-M 2/5 - PCIE, PCI, USB
Boot BIOS Strap

U 23 D
N2 9 V 27
[ 2 0] P C I E _ R XN 1_ W L A N N2 8 PERN 1 D MI 0 R XN V 26 D MI _ R XN 0 [ 5 ]
D ir ect M ed ia In te rfa ce
Strap PCI_GNT#0 SPI_CS1# [ 2 0] P C I E _ R XP 1 _ W LA N PERP1 D M I 0R X P D MI _ R XP 0 [ 5]
C4 6 3 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X N 1 _C P2 7 U2 9
[ 20 ] P C I E _ T XN 1_ W L A N P E T N1 D MI 0 T XN D MI _ T X N 0 [ 5 ]
C4 6 2 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X P 1_ C P2 6 U2 8 3 . 3V S
[ 20 ] P C I E _ T XP 1 _ W LA N PET P1 D MI 0 T X P D MI _ T X P 0 [ 5 ]
SPI 01 Stuff No stuff
L2 9 Y2 7 P C I _ R E Q #2 1 8
[2 0 ] P C I E _ R XN 2_ N E W _C A R D L2 8 PERN 2 D MI 1 R XN Y2 6 D MI _ R XN 1 [ 5 ] P C I _ TR D Y # 2 7 RN 1 1
[2 0 ] P C I E _ R XP 2 _ N E W _ C A R D PERP2 D M I 1R X P D MI _ R XP 1 [ 5]
PCI 10 No stuff Stuff C4 6 1 0 . 2 2U _1 6 V _ X7 R _ 0 6 P C I E _ T X N 2 _C M2 7 W29 P C I _ R E Q #3 3 6 8 P 4R X 8. 2 K _ 0 4
[ 20 ] P C I E _ T XN 2_ N E W _C A R D C4 6 0 0 . 2 2U _1 6 V _ X7 R _ 0 6 P C I E _ T X P 2_ C M2 6 P E T N2 D MI 1 T XN W28 D MI _ T X N 1 [ 5 ] P CI_ P E RR # 4 5
[ 20 ] P C I E _ T XP 2 _ N E W _ C A R D PET P2 D MI 1 T X P D MI _ T X P 1 [ 5 ]
P CI_ INT # B 1 8
LPC(default) 11 No stuff No stuff J2 9 AB2 7 Z diff= 100O? 5% P CI_ IRD Y # 2 7 RN 3 5
[ 19 ] P CIE _ RX N3 _ 3 G PERN 3 D MI 2 R XN D MI _ R XN 2 [ 5 ]
J2 8 AB2 6 P C I _ LO C K # 3 6 8 P 4R X 8. 2 K _ 0 4
P CI- Ex pre ss
[ 19 ] P C I E _ R X P 3 _3 G PERP3 D M I 2R X P D MI _ R XP 2 [ 5]
C4 5 9 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X N 3 _C K2 7 AA2 9 P C I _ S TO P # 4 5
[1 9 ] P C I E _ TX N 3 _ 3 G C4 5 8 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X P 3_ C K2 6 P E T N3 D MI 2 T XN AA2 8 D MI _ T X N 2 [ 5 ] P CI_ F RA M E # 1 8
[1 9 ] P C I E _ TX P 3 _3 G PET P3 D MI 2 T X P D MI _ T X P 2 [ 5 ]
P CI_ DE V S E L # 2 7 RN 1 2
R1 4 8 1 K_ 0 4 P C I _ G N T #0 G2 9 A D2 7 P CI_ INT # D 3 6 8 P 4R X 8. 2 K _ 0 4
[ 2 3 ] P C I E _ R X N 4 _L A N PERN 4 D MI 3 R XN D MI _ R XN 3 [ 5 ]
[ 2 3 ] P C I E _ R X P 4_ L A N G2 8 A D2 6 D MI _ R XP 3 [ 5] P C I _ R E Q #1 4 5
C4 5 7 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X N 4 _C H2 7 PERP4 D M I 3R X P A C2 9 P CI_ INT # C 1 8
[ 2 3 ] P C I E _T X N 4 _L A N C4 5 6 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X P 4_ C H2 6 P E T N4 D MI 3 T XN A C2 8 D MI _ T X N 3 [ 5 ] P CI_ INT # A 2 7 RN 1 3
[ 2 3 ] P C I E _T X P 4_ L A N PET P4 D MI 3 T X P D MI _ T X P 3 [ 5 ]
P CI_ S E RR # 3 6 8 P 4R X 8. 2 K _ 0 4
E2 9 T2 6 P CI_ INT # F 4 5
[ 2 2] P C I E _ R XN 5_ C A R D PERN 5 D MI _ C L K N C L K _ P C I E _ I C H # [ 18 ]
PC I_G NT# 3 A16 swap override Strap [ 22 ] P C I E _ R X P 5 _C A R D E2 8 T2 5 C L K _ P C I E _ I C H [ 1 8] P CI_ INT # E 1 8
PERP5 D M I _C L K P
C4 5 5 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X N 5 _C F27 P CI_ INT # H 2 7 RN 3 4
Enable [ 22 ] P C I E _ T XN 5_ C A R D C4 5 4 0 . 1 U _ 10 V _ X 7R _0 4 P C I E _ T X P 5_ C F26 P E T N5 AF2 9 P CI_ INT # G 3 6 8 P 4R X 8. 2 K _ 0 4
Stuff [ 2 2 ] P C I E _T X P 5 _C A R D PET P5 D M I _Z C OM P AF2 8 R2 6 0 2 4. 9 _ 1% _ 0 4 P C I _ R E Q #0 4 5
C2 9 D MI _ I R C OM P 1 . 5V S P C I _ GN T 2 #
No stuff Disable De fau lt P E R N 6/ G L A N _ R X N
C2 8 Within 500 mils R1 1 5 *8 . 2 K _ 04
D2 7 P E R P 6 / G LA N _R X P
P E T N 6 / GL A N _ T XN 3 . 3V
D2 6 A C5 US B _ P N0 [2 1 ]
P E T P 6/ G L A N _ TX P U S B P 0N A C4
Sheet 14 of 40
R1 3 2 * 1K _0 4 P C I _ G N T #3 S P I _S C L K D2 3 U SBP0 P A D3 US B _ P P 0 [2 1 ] U S B _ OC #8 1 8
S P I _C S 0 # S P I_ CL K U S B P 1N US B _ P N1 [2 1 ]
D2 4 A D2 US B _ P P 1 [2 1 ] U S B _ OC #5 2 7 RN 3 3
S P I _C S 1 # F23 S P I_ CS 0 # U SBP1 P A C1 U S B _ OC #9 3 6 8 P 4R X 10 K _ 04
Zo= 55O? 5% S P I _ C S 1 # / GP I O5 8 / C L GP I O6 U S B P 2N U S B _ P N 2 _ MI N I [ 2 0]
A C2 U S B _ OC #7 4 5
ICH9-M 2/5 - PCIE,

U SBP2 P U S B _ P P 2 _M I N I [ 20 ]
S P I _S I D2 5 AA5 U S B _ OC #4 1 8
S P I _S O E2 3 S P I _ MOS I U S B P 3N AA4 US B _ P N3 [1 9 ] U S B _ OC #6 2 7 RN 1 4
S P I _ MI S O S PI U SBP3 P US B _ P P 3 [1 9 ]
SPI_SI iTPM Enable AB2 U S B _ OC #1 0 3 6 8 P 4R X 10 K _ 04
N4 U S B P 4N AB3 US B _ P N4 _ NE W [ 20 ] U S B _ OC #2 4 5
PCI, USB
[ 21 ] U S B _ OC #0 1 OC 0# / GP I O5 9 U SBP4 P U S B _ P P 4 _N E W [ 2 0 ] Z diff= 90O? 5 %
Stuff Enable Default N5 AA1 U S B _ P N 5 _ 3G [ 1 9 ] U S B _ OC #1 1
US B _O C# 2 N6 OC 1# / GP I O4 0 U S B P 5N AA2 R3 5 1 1 0K _ 0 4
OC 2# / GP I O4 1 U SBP5 P U S B _ P P 5 _3 G [ 1 9]
No stuff Disable [1 9 ] US B _ O C# 3 US B _O C# 3 P6 USB W5
US B _O C# 4 M1 OC 3# / GP I O4 2 U S B P 6N W4
[2 0 ] US B _ O C# 4 US B _O C# 5 N2 OC 4# / GP I O4 3 U SBP6 P Y3
OC 5# / GP I O2 9 U S B P 7N US B _ P N7 _ CC D [1 9 ]
US B _O C# 6 M4 Y2 U S B _ P P 7 _C C D [ 1 9]
US B _O C# 7 M3 OC 6# / GP I O3 0 U SBP7 P W1
3 . 3V S OC 7# / GP I O3 1 U S B P 8N
US B _O C# 8 N3 W2
US B _O C# 9 N1 OC 8# / GP I O4 4 U SBP8 P V2
R8 6 * 1K _0 4 S P I_ S I US B _O C # 10 P5 OC 9# / GP I O4 5 U S B P 9N V3 US B _ P N9 _ B T [ 1 9]
OC 10 # / GP I O 46 U SBP9 P U S B _ P P 9 _B T [ 19 ]
US B _O C # 11 P3 U5
OC 11 # / GP I O 47 U S B P 1 0N U4
US B P 1 0 P
A G2 U1 U S B _ P N 1 1 _F P [ 2 1]
R3 4 6 2 2 . 6 _1 % _ 04 A G1 US B R B IA S U S B P 1 1N U2 3. 3 V
CLGPIO5 iTPM Enable US B R B IA S # US B P 1 1 P U S B _ P P 1 1_ F P [ 21 ] C 2 35
HIGH Enable Default Within 500 mils I C H 9 M-N H 8 28 0 1I B M *0 . 1U _ 16 V _ 04
LOW Disable U6
5
7 4A H C 1 G0 8 GW
P L T _ RS T # 1
4
U2 3 B 2 B U F _ P L T _R S T# [ 19 , 2 0, 22 , 2 3, 2 6 ]
3 . 3V 3 . 3V M_ S B S P I 1 P CI_ A D0 D1 1 F1 P C I _ R E Q# 0
J_SBSPI1 P CI_ A D1 C 8 A D0 R E Q0 # G4 P C I _ GN T # 0 R1 1 3
A D1 PC I GN T 0 #
R1 3 6 1 0 K _ 04 P CI_ A D2 D 9 B6 P C I _ R E Q# 1
3
D03 BCN P CI_ A D3 E1 2 A D2 R E Q 1 #/ G P I O5 0 A7 P C I _ G N T #1 *1 0 0 K _0 4
C L GP I O 5 [ 15 ] 1 2 A D3 G N T 1 #/ G P I O5 1
R1 2 8 * 10 0 K _ 04 P CI_ A D4 E9 F 13 P C I _ R E Q# 2
A D4 R E Q 2 #/ G P I O5 2
R 4 05 7 8 P CI_ A D5 C 9 F 12 P C I _ G N T 2#
P CI_ A D6 E1 0 A D5 G N T 2 #/ G P I O5 3 E6 P C I _ R E Q# 3
A D6 R E Q 3 #/ G P I O5 4
J S P I1 * 3 . 3K _ 1 %_ 0 4 J_ S B S P I 1 P CI_ A D7 B7 F6 P C I _ G N T #3
*O P E N _ 3 5m i l P CI_ A D8 C 7 A D7 G N T 3 #/ G P I O5 5
S P I _ C S 0# _ R 1 2 A D8
S P I _ C S # _ C ON S P I _S C L K _R P CI_ A D9 C 5 D8 P CI_ C / B E #0
3. 3 V S S P I _ S O_ R 3 4 S P I _S I _R P CI_ A D1 0 G1 1 A D9 C/B E 0 # B4 P CI_ C / B E #1
S P I _ C S 1# _ R 5 6 P CI_ A D1 1 F8 A D1 0 C/B E 1 # D6 P CI_ C / B E #2
7 8 A D1 1 C/B E 2 #
P CI_ A D1 2 F11 A5 P CI_ C / B E #3
J S P I2 *S P N Z -0 8S 3 -B -C - 0-P P CI_ A D1 3 E7 A D1 2 C/B E 3 #
A D1 3
R 3 76 *O P E N _ 3 5m i l P CI_ A D1 4 A3 D3 P CI_ IR DY #
P CI_ A D1 5 D 2 A D1 4 IRDY # E3 P CI_ P A R
0_ 0 4 3. 3 V M _S B S P I 1 P CI_ A D1 6 F10 A D1 5 PAR R1 P C I _ R S T#
A D1 6 P C IRS T #
U3 R8 9 33 _ 0 4 P CI_ A D1 7 D 5 C6 P C I _ D E V S E L#
8 5 S P I _ S I _R S P I_ S I C 1 75 *3 3P _ 5 0 V _0 4 P CI_ A D1 8 D1 0 A D1 7 DEVS EL # E4 P CI_ P E R R# P C L K _ I C H 33 R1 4 5 * 10 _ 0 4 C2 6 4 *1 0 P _ 50 V _ 04
VDD SI A D1 8 PERR #
R7 3 33 _ 0 4 P CI_ A D1 9 B3 C2 P C I _ L OC K #
R 75 2 S P I _ S O_ R S P I_ S O C 1 66 *3 3P _ 5 0 V _0 4 P CI_ A D2 0 F7 A D1 9 P L OC K # J4 P CI_ S E R R#
C 1 65 3 . 3K _ 1 % _0 4 SO R8 2 33 _ 0 4 P CI_ A D2 1 C 3 A D2 0 SERR # A4 P C I _ S T OP #
SBSPI_ W P# _ R 3 1 S P I _ C S 0 #_ R S P I_ CS 0 # P CI_ A D2 2 F3 A D2 1 S TO P # F5 P CI_ T RD Y #
0. 1 U _ 1 6 V _0 4 W P# CE# R7 7 33 _ 0 4 P CI_ A D2 3 F4 A D2 2 T RDY # D7 P C I _ F R A ME #
S P I_ S CL K A D2 3 F RA M E #
R 74 6 S P I _ S C L K _R C 1 68 *3 3P _ 5 0 V _0 4 P CI_ A D2 4 C 1
3 . 3K _ 1 % _0 4 S CK P CI_ A D2 5 G 7 A D2 4 C1 4 P L T_ R S T#
S B S P I_ HO L D# A D2 5 P L T RST # P L T_ R S T# [ 5 , 1 9 ]
7 4 P CI_ A D2 6 H 7 D4 P C L K _ I C H 33 P C L K _ I C H 33 [ 18 ]
H OL D # VSS P CI_ A D2 7 D 1 A D2 6 P CIC L K R2
02/20 A D2 7 PM E# P ME # [ 26 ]
MX 2 5L 1 6 05 A 1 6M P CI_ A D2 8 G 5
A D2 8
Remove C164 P CI_ A D2 9 H 6
P CI_ A D3 0 G 1 A D2 9
A D3 0
P CI_ A D3 1 H 3
SBSPI_ W P# _ R R3 7 5 * 0 _0 4 A D3 1
S B S P I _W P # [ 15 ]
I nt err up t I/F
P CI_ INT # A J5 H4 P C I _ I N T# E
3. 3 V M _S B S P I 1 P CI_ INT # B E1 P IRQ A# P I R QE # / GP I O 2 K6 P C I _ I N T# F
P IRQ B# P I R QF # / GP I O 3
U2 9 R 4 06 *3 3 _0 4 P CI_ INT # C J6 F2 P C I _ I N T# G
8 5 S P I 1 _S I _ R S P I_ S I P CI_ INT # D C 4 P IRQ C# P I R Q G# / GP I O 4 G2 P C I _ I N T# H
VDD SI P IRQ D# P I R Q H # / GP I O 5
R 4 07 *3 3 _0 4
R 40 8 2 S P I 1 _S O _R S P I_ S O I C H 9M -N H 82 8 0 1I B M
C 6 43 *3 . 3 K _ 1% _ 04 SO R 4 09 *3 3 _0 4
SBSPI_ W P# _ R 3 1 S P I _ C S 1 #_ R S P I_ CS 1 #
*0 . 1U _ 16 V _ 04 W P# CE# R 4 10 *3 3 _0 4
R 41 1 6 S P I 1 _S C LK _ R S P I_ S CL K
*3 . 3 K _ 1% _ 04 S CK
S B S P I_ HO L D# 7 4
H OL D # VSS
*M X2 5 L1 6 0 5A 1 6 M
[ 5 , 8 . . 13 , 1 5 , 16 , 1 8 . . 27 , 3 1] 3 . 3V S
[ 2, 1 2 , 1 3, 1 5 . . 1 7, 1 9 , 20 , 2 3 , 29 , 3 0] 3 . 3V
[ 3, 8 , 1 3 , 16 , 1 9 , 20 , 2 9] 1 . 5V S
ICH9-M 2/5 - PCIE, PCI, USB B - 15

Schematic Diagrams
ICH9-M 3/5 - GPIO, PWR Management
3. 3 V U 2 3C
I C H _S MB C L K 0 G1 6 A H2 3 S A T A 0 GP
[ 1 0 , 1 1, 1 8 ] I C H _ S MB C L K 0 S MB C LK S A T A 0 GP / G P I O2 1
8 1 G P I O1 3 DDR2, CLK GEN [ 1 0 , 1 1, 1 8 ] I C H _ S MB D A T 0 I C H _S MB D A T0 A1 3 AF1 9 S A T A 1 GP
R N9 7 2 SW I# GP I O 6 0 E1 7 S MB D A TA S A T A 1 GP / G P I O1 9 AE2 1 S A T A 4 GP
LI N K A L E R T # / GP I O 60 / C LG P I O4 S A T A 4 GP / G P I O3 6
SATA
GPIO
8 P 4 R X 1 0 K _0 4 6 3 P M _ S Y S R S T# I C H _S MB C L K 1 C1 7 A D2 0 S A T A 5 GP
S MB
[2 0 ] I C H _ S MB C L K 1 S ML I N K 0 S A T A 5 GP / G P I O3 7
5 4 L A N _P W R NEW CARD, MINI CARD I C H _S MB D A T1 B1 8
[2 0 ] I C H _ S MB D A T 1 S ML I N K 1 H1 C LK _ I C H 1 4
CL K 1 4 C L K _ I C H 14 [ 18 ]
8 1 G P I O6 0 SW I# F19 AF3 C LK _ I C H 4 8
R N3 6 7 2 S B _B A T L OW # [2 6 ] SW I# RI# CL K 4 8 C L K _ I C H 48 [ 18 ]
Clocks
8 P 4 R X 1 0 K _0 4 6 3 S B _B L O N R 4 P1 S U S CL K
5 4 A C _ P R E S E N T _R [ 1 9] L P CPD # P M_ S Y S R S T # G1 9 S U S _ S T A T #/ L P C P D # S U S C LK
S Y S _ R E S E T#
C1 6 S L P _ S 3# [ 17 ]
M6 SL P_ S3 # E1 6
[5 ] P M _S Y N C # P MS Y N C # / G P I O0 SL P_ S4 # S L P _ S 4# [ 17 ]
R 1 12 1 0 K _0 4 P C IE _ W A K E # G1 7 SL P_ S5 #
L A N_ P W R A1 7 SL P_ S5 #
[2 3 ] L A N _P W R S MB A L E R T # / GP I O1 1
R 3 45 * 10 K _ 0 4 P W R_ B T N# C1 0 S 4 _ S TA TE #
P M_ S T P P C I # A1 4 S 4 _ S TA TE # / G P I O2 6
R 3 03 1 0 K _0 4 IC H_ S M B DA T 1 [ 1 8] P M_ S T P P C I # P M_ S T P C P U # E1 9 S TP _ P C I # G2 0
S YS G PI O
[ 18 ] P M_ S T P C P U # S TP _ C P U # P W R OK S B _ P W RO K [1 7 ]
R 3 08 1 0 K _0 4 IC H_ S M B CL K 1 P M_ C LK R U N # L4 M2 R3 5 0 * 10 m i _l s h ort P M _D P R S L P V R
[ 1 9] P M_ C LK R U N # CL K RU N# D P R S L P V R / G P I O1 6 P M_ D P R S L P V R [ 5 , 31 ]
R 3 09 * 10 0 K _ 04 G P I O2 4 P CIE _ W A K E # E2 0 B1 3 S B _ B A T L OW #
P ow er M GT
[ 19 , 2 0 , 23 ] P C I E _ W A K E # W AKE# B A T LO W #
[ 1 9 , 2 6] S E R I R Q S E RIR Q M5
R 1 10 1 0 K _0 4 S U S _ P W R _ A C K _R P M_ T H R M# AJ 2 3 S E RIR Q R3 P W R _B TN #
[ 2 ] P M _T H R M# TH R M # P W R B TN # P W R _B T N # [ 26 ]
R 3 13 2 . 2 K _0 4 IC H_ S M B DA T 0 V RM _ P W RG D D2 1 D2 0 S B _ L A N R S T#
V RM P W RG D LA N _ R S T #
R 1 11 2 . 2 K _0 4 IC H_ S M B CL K 0 A2 0 D2 2 R9 1 1 0 0_ 0 4 R S MR S T#
TP 1 1 RS M RS T # RS M RS T # [ 1 7 , 2 6]
S MI # A G1 9 R5
[ 26 ] S MI # OD D _ D E T E C T# A H2 1 GP I O 1 C K _ P W R GD CL K _ P W RG D [ 1 8]
[ 1 9] OD D _ D E T E C T# GP I O 6
S CI# A G2 1 R6
3. 3 V S [ 26 ] S C I # A2 1 GP I O 7 C LP W R OK CL _ P W RO K [ 5 , 1 2 , 17 , 2 6 ]
GP I O 8 S L P _ M#
S B _ B L ON C1 2 B1 6
[ 1 2] S B _ B LO N GP I O 12 S L P _M #
Sheet 15 of 40
R 3 11 * 10 K _ 0 4 P M _ S TP P C I # GP I O 1 3 C2 1
GP I O 13
GP I O 1 7 AE1 8 F24 CL _ CL K 0 [5 ]
R 1 07 * 10 K _ 0 4 P M _ S TP C P U # GP I O 1 8 K1 GP I O 17 CL _ CL K 0 B1 9
GP I O 18 CL _ CL K 1 CL _ CL K 1 [2 0 ]
GP I O 2 0 AF8
Zo= 55 O? 5%
ICH9-M 3/5 - GPIO,
R 3 04 1 0 K _0 4 S A TA _ C LK R E Q# AJ 2 2 GP I O 20 F22
[1 4 ] S B S P I _W P # S C L OC K / GP I O 22 CL _ DA T A 0 CL _ DA T A 0 [5 ]
C on tr ol ler L in k
A9 C1 9 CL _ DA T A 1 [2 0 ]
G PI O
R 1 06 1 0 0K _ 0 4 G P I O1 7 D1 9 GP I O 27 CL _ DA T A 1
S A TA _ C LK R E Q# S A T A _ C L K R E Q #_ R L1 GP I O 28 C2 5
[ 1 8] S A T A _ CL K RE Q # S A TA C L K R E Q #/ G P I O3 5 C L_ V R E F 0 CL _ V RE F 0
PWR Mangement
R 1 46 8 . 2 K _0 4 S E RIRQ AE1 9 A1 9
R3 4 4 A G2 2 S LO A D / G P I O3 8 C L_ V R E F 1 CL _ V RE F 1
S D A T A OU T 0/ G P I O3 9
R 2 78 8 . 2 K _0 4 P M _ TH R M # *1 0m i l _s h or t AF2 1 F21
A H2 4 S D A T A OU T 1/ G P I O4 8 CL _ RS T 0 # D1 8 CL _ RS T # 0 [5 ]
R 3 49 8 . 2 K _0 4 P M _ CL K RU N# A8
GP I O 49 CL _ RS T 1 # CL _ RS T # 1 [ 2 0] Zo= 55 O? 5%
[1 4 ] C L G P I O5 GP I O 57 / C L G P I O5 A1 6 G P I O2 4 R 10 8 *1 0 mi l _s h o rt
M E M_ L E D / G P I O2 4 S US _ P W R_ A C K
R 2 77 * 10 K _ 0 4 M C H _I C H _ S Y N C # [2 4 ] IC H_ S P K R M7 C1 8 S U S _P W R _ A C K _ R S U S _ P W R _ A C K [ 2 6]
MC H _ I C H _S Y N C # AJ 2 4 SPKR GP I O 1 0/ S U S _ P W R _ A C K C1 1 A C _P R E S E N T_ R A C_ P RE S E N T
[5 ] M CH_ IC H_ S Y N C# MC H _ S Y N C # GP I O1 4/ A C _ P R E S E N T G P I O9 A C _ P R E S E N T [ 2 6]
R 3 01 1 0 0K _ 0 4 O D D _D E T E C T # B2 1 C2 0
A H2 0 TP 3 W O L _E N / GP I O 9 R 12 1 *1 0 mi l _s h o rt
M IS C
R 1 02 1 0 0K _ 0 4 S M I# AJ 2 0 TP 8
AJ 2 1 TP 9
R 97 1 0 0K _ 0 4 S C I# TP 1 0
I C H 9M -N H 8 28 0 1I B M
1 8 S A TA 0 G P 3 .3 V S
R N3 7 2 7 S A TA 4 G P
8 P 4 R X 1 0 K _0 4 3 6 S A TA 5 G P
4 5 S A TA 1 G P
R8 8
R 99 1 0 K _0 4 S B _L A N R S T # 3. 24 K _ 1 %_ 0 4
C L _V R E F 0
R 1 80 * 10 0 K _ 04 P M _ D P R S LP V R 12mils
R 1 01 1 M_ 0 4 V R M_ P W R GD
R 92 1 0 K _0 4 R S MR S T # C 19 7 R8 7
C 2 04 1 0 0P _ 5 0 V _0 4 0 . 1 U _ 1 0V _ X 7 R _ 04 45 3 _ 1% _ 0 6
R 2 97 1 0 0K _ 0 4 G P I O9
C L_VRET0/1 =0.405V
3 .3 V
R3 0 2
C L _V R E F 1 3. 24 K _ 1 %_ 0 4
POWER OK VCORE PWRGD 12mils
3 .3 V S
C 50 4 R2 9 8
0 . 1 U _ 1 0V _ X 7 R _ 04 45 3 _ 1% _ 0 6
3 .3 V S U 5 R1 0 4
2 P M _P W R OK
3 RS T # 1 0K _ 0 4
V CC 1
C 2 18 G ND R 11 4 V R M_ P W R GD
* G6 90 L 2 93 T 7 3
* 0 . 1U _1 6 V _ 04 ( IMP 80 9) * 10 0 K _ 04 D
C2 1 5
G 0 . 03 3 U _ 1 6 V _X 7 R _ 0 4
[ 31 ] CL K E N#
Q4
2 N 70 0 2W
S
[ 2 , 1 2 . . 14 , 1 6 , 17 , 1 9 , 20 , 2 3 , 29 , 3 0 ] 3 . 3 V
[ 5 , 8 . . 14 , 1 6 , 18 . . 2 7 , 3 1] 3. 3V S
B - 16 ICH9-M 3/5 - GPIO, PWR Management

Schematic Diagrams
ICH9-M 4/5 - Power

2 0m ils U23 F
A23 A15
RTCVCC VCCRTC VCC1_05[ 1] B15
C20 0 C201 C211 A6 VCC1_05[ 2] C15
V5REF VCC1_05[ 3] D15
0. 1U_10V_X7R_04 0.1U_10V_X7R_0 4 10U_10V_08 AE1 VCC1_05[ 4] E15
V5REF_SUS VCC1_05[ 5] F15
AA24 VCC1_05[ 6] L11
1.7 A
AA25 VCC1_5_B[1] VCC1_05[ 7] L12 1.05VS
AB24 VCC1_5_B[2] VCC1_05[ 8] L14 C241 C24 0 C224
CLOSE TO ICH9M VCC1_5_B[3] VCC1_05[ 9]
AB25 L16
AC24 VCC1_5_B[4] VCC1_05[1 0] L17 0.1 U_10V_X7R_04 1U_ 6.3V_04 100U_6.3 V_B2
AC25 VCC1_5_B[5] VCC1_05[1 1] L18
1 0m ils AD24 VCC1_5_B[6] VCC1_05[1 2] M11
V5REF AD25 VCC1_5_B[7] VCC1_05[1 3] M18
1 0m ils AE25 VCC1_5_B[8] VCC1_05[1 4] P11
V5REF_SUS AE26 VCC1_5_B[9] VCC1_05[1 5] P18
AE27 VCC1_5_B[10 ] VCC1_05[1 6] T11 VCCDMIPLL L3 3
L52 VCC1_5_ B AE28 VCC1_5_B[11 ] VCC1_05[1 7] T18 HCB1005 KF-121T2 0
HCB1608KF- 121T25 AE29 VCC1_5_B[12 ] VCC1_05[1 8] U11
10m il s
1A F25 VCC1_5_B[13 ] VCC1_05[1 9] U18 1.5VS
1.5VS
CORE
G25 VCC1_5_B[14 ] VCC1_05[2 0] V11 C448 C46 4
H24 VCC1_5_B[15 ] VCC1_05[2 1] V12
H25 VCC1_5_B[16 ] VCC1_05[2 2] V14 *10U_10V_08 0. 1U_10V_X7R_04
J24 VCC1_5_B[17 ] VCC1_05[2 3] V16
J25 VCC1_5_B[18 ] VCC1_05[2 4] V17
VCC1_5_B[19 ] VCC1_05[2 5]
K24 V18
C195 C19 0 C189 K25 VCC1_5_B[20 ] VCC1_05[2 6] VCCDMI L1 2
L23 VCC1_5_B[21 ] R29 HCB1005 KF-121T2 0
0.1 U_10V_ X7R_04 0. 1U_10V_X7R_04 0.1U_10V_X7R_0 4 L24 VCC1_5_B[22 ] VCCDMIPLL 10m il s
VCC1_5_B[23 ] 1.05VS
L25 W23
VCC1_5_B[24 ] VCC_DMI[ 1]
M24 VCC1_5_B[25 ] VCC_DMI[ 2] Y23 C212 4. 7U_6.3V_X5R_ 06
M25 10m il s
N23 VCC1_5_B[26 ] AB23
VCC1_5_B[27 ] V_CPU_IO[ 1] 1.05VS
N24 VCC1_5_B[28 ] V_CPU_IO[ 2] AC23
N25 VCC1_5_B[29 ] C229 C21 7 C225
P24 AG29
C206 C209 C21 0 C202 P25 VCC1_5_B[30 ] VCC3_3[ 1] 0.1 U_10V_X7R_04 0. 1U_10V_X7R_04 *4. 7U_6.3V_X5R_0 6
Sheet 16 of 40
5VS 3. 3VS VCC1_5_B[31 ]
R24 AJ6
VCCA 3GP
VCC1_5_B[32 ] VCC3_3[ 2]
100U_6. 3V_B2 10U_1 0V_08 10 U_10V_ 08 0.1U_10V_X7R_0 4 R25 VCC1_5_B[33 ]
R26
VCC1_5_B[34 ]
A
R27 C465 0. 1U_10V_X7R_04

R328
10_04
D29
ASD751V
T24
T27
T28
VCC1_5_B[35 ]
VCC1_5_B[36 ]
VCC1_5_B[37 ]
VCC3_3[ 7] AC10
AD19
C554 0. 1U_10V_X7R_04 ICH9-M 4/5 - Power
T29 VCC1_5_B[38 ] VCC3_3[ 3] AF20 C239 0. 1U_10V_X7R_04
VCCSATAPL L VCC1_5_B[39 ] VCC3_3[ 4]
C
L11 U24 VCC1_5_B[40 ] VCC3_3[ 5] AG24

HCB1005KF- 121T20 U25 AC20
VCCP _CORE
V5REF 10 mi ls V24
VCC1_5_B[41 ] VCC3_3[ 6]
C547 C546
1.5VS
V25 VCC1_5_B[42 ] B9
40m il s
VCC1_5_B[43 ] VCC3_3[ 8] 3.3VS
C59 7 C598 U23 VCC1_5_B[44 ] VCC3_3[ 9] F9
1U_16V_X5R_06 0.1 U_10V_ X7R_04 W24 VCC1_5_B[45 ] VCC3_3[1 0] G3 C244 C24 9 C250
10 U_10V_ 08 1U_6.3V_04 W25 G6
K23 VCC1_5_B[46 ] VCC3_3[1 1] J2 0.1 U_10V_X7R_04 0. 1U_10V_X7R_04 0.1U_10V_X7R_0 4
VCC1_5_B[47 ] VCC3_3[1 2]
C547 D 03 BCN? ? Y24 VCC1_5_B[48 ] VCC3_3[1 3] J7
Y25 K7
PCI
VCC1_5_B[49 ] VCC3_3[1 4]
1. 7A AJ19
5V 3 .3V VCCSATAPLL C55 9 0.1U_10V_X7R_0 4
AC16 AJ4
1 0m ils
1 .5VS VCC1_5_A[1] VCCHDA 3. 3VS
AD15 C56 4 0.1U_10V_X7R_0 4
VCC1_5_A[2]
A
C23 0 C243 AD16 AJ3 3. 3V

R347 D30 AE15 VCC1_5_A[3] VCCSUSHDA
ARX
1U_ 6.3V_04 0.1U_10V_X7R_0 4 AF15 VCC1_5_A[4] AC8 TP_VCCSUS1 05_ICH1
10_04 ASD751V AG15 VCC1_5_A[5] VCCSUS1_05[ 1] 1 0m ils
AH15 VCC1_5_A[6] F17 TP_VCCSUS1 05_ICH2
VCC1_5_A[7] VCCSUS1_05[ 2]
C
AJ15
VCC1_5_A[8] AD8 TP_VCCSUS1 5_ICH1
V5REF_ SUS AC11 VCCSUS1_5[ 1]
C586 C585 1 .5VS AD11 VCC1_5_A[9] F18 TP_VCCSUS1 5_ICH2 C599 0.1 U_10V_X7R_04
C22 6 C223 AE11 VCC1_5_A[10 ] VCCSUS1_5[ 2]
1U_16V_X5R_06 0.1 U_10V_ X7R_04 AF11 VCC1_5_A[11 ] 10m il s
ATX
1U_ 6.3V_04 0.1U_10V_X7R_0 4 AG10 VCC1_5_A[12 ]
AG11 VCC1_5_A[13 ] A18
AH10 VCC1_5_A[14 ] VCCSUS3_3[ 1] D16
VCC1_5_A[15 ] VCCSUS3_3[ 2]
VCCPSU S
C586 D 03 BCN? ? AJ10 D17 C600
VCC1_5_A[16 ] VCCSUS3_3[ 3] E22
AC9 VCCSUS3_3[ 4] 0.1 U_10V_X7R_04
1 .5VS VCC1_5_A[17 ]
1.5VS C60 1 C545 AC18 AF1
AC19 VCC1_5_A[18 ] VCCSUS3_3[ 5]
1U_ 6.3V_04 0.01U_16 V_X7R_ 04 VCC1_5_A[19 ] T1
VCCSUS3_3[ 6] 30m il s
AC21 T2
R259 VCC1_5_A[20 ] VCCSUS3_3[ 7] T3 3 .3V
*10mil_short G10 VCCSUS3_3[ 8] T4 C248 C584 C247
G9 VCC1_5_A[21 ] VCCSUS3_3[ 9] T5
1.5VS VCC1_5_A[22 ] VCCSUS3_3[1 0] T6 0.0 22U_16V_X7R_04 0.022U_1 6V_X7R_04 0.1 U_10V_X7R_04
VCCGLANPLL VCCSUS3_3[1 1]
C246 AC12 U6
C469 AC13 VCC1_5_A[23 ] VCCSUS3_3[1 2] U7
VCC1_5_A[24 ] VCCSUS3_3[1 3]
VCCPUS B
0.1U_10V_X7R_0 4 AC14 V6
0.1U_10V_X7R_0 4 VCC1_5_A[25 ] VCCSUS3_3[1 4] V7
VCCSUS3_3[1 5]
AJ5 VCCUSBPLL VCCSUS3_3[1 6] W6
1.5VS W7
AA7 VCCSUS3_3[1 7] Y6
C242 AB6 VCC1_5_A[26 ] VCCSUS3_3[1 8] Y7
VCC1_5_A[27 ] USB CORE VCCSUS3_3[1 9]
AB7 VCC1_5_A[28 ] VCCSUS3_3[2 0] T7 10m il s
0.1U_10V_X7R_0 4 AC6 VCC1_5_A[29 ]
C60 2 AC7 G22 TP_VCCCL_ 105 C214 0. 1U_10V_X7R_04
3.3VS 0.1U_1 0V_X7 R_04 VCC1_5_A[30 ] VCCCL1 _05
TP_VCCCL_ 15
1 0m ils
TP_VCCLAN105_ ICH1 A10 VCCLAN1_05[1] VCCCL 1_5 G23
10 mi ls TP_VCCLAN105_ ICH2 A11 VCCLAN1_05[2]
3.3VS A24 10m il s C208 C20 7
R270 A12 VCCCL3_3[ 1] B24
10m il s VCCLAN3_3[1] VCCCL3_3[ 2] 3 .3VS
*10mil_short C540 0.1 U_10V_ X7R_04 B12 VCCLAN3_3[2] *0.1U_10V_X7R_0 4 *1U_6. 3V_0 4
10m il s C603
VCCGLAN3_ 3 VCCGLANPLL A27
VCCGLANPLL 0.1 U_10V_X7R_04
VCC1_5 _B
C473 D28
GLAN POWER
VCCGLAN1_5[1] [ 19,21 ,28.. 31] 5 V

C184 C18 3 D29 VCCGLAN1_5[2] [12,1 3,19,2 1,24, 25,27] 5VS
0.1U_10V_X7R_0 4 E26 [2,12 ..15, 17,19, 20,23, 29,30] 3.3 V
0.1 U_10V_ X7R_04 0. 1U_10V_X7R_04 E27 VCCGLAN1_5[3]
VCCGLAN1_5[4] [ 5,8. .15,18 ..27, 31] 3 .3VS
10m il s A26
[ 3,8, 13,14, 19,20, 29] 1 .5VS
VCCGLAN3_3 VCCGLAN3_3 [ 2..5, 7,8,1 3,29] 1.05VS
[ 13] RTCVCC
I CH9M-NH82801I BM
ICH9-M 4/5 - Power B - 17

Schematic Diagrams
ICH9-M 5/5 - GND

U2 3E
AA2 6 H5
AA2 7 VSS[1] VSS[ 107 ] J23
VSS[2] VSS[ 108 ]
AA3 J26
VSS[3] VSS[ 109 ]
AA6 J27
VSS[4] VSS[ 110 ]
AB1 AC 22
VSS[5] VSS[ 111 ]
AA2 3 VSS[6] VSS[ 112 ] K2 8
AB2 8 K2 9 3. 3V
VSS[7] VSS[ 113 ]
AB2 9 L13
AB4 VSS[8] VSS[ 114 ] L15
VSS[9] VSS[ 115 ]
AB5 L2
VSS[10 ] VSS[ 116 ]
AC1 7 VSS[11 ] VSS[ 117 ] L26 C27 2
AC2 6 L27
VSS[12 ] VSS[ 118 ]
AC2 7 L5 *0.1 U_1 6V_04
AC3 VSS[13 ] VSS[ 119 ] L7
VSS[14 ] VSS[ 120 ]
AD1 M12 U 8A
14
VSS[15 ] VSS[ 121 ]
AD1 0 M13 7 4LVC08 PW
AD1 2 VSS[16 ] VSS[ 122 ] M14 1
VSS[17 ] VSS[ 123 ] [15 ,26 ] R SMRST#
AD1 3 M15 3
VSS[18 ] VSS[ 124 ] SUSB# [ 20, 23, 26, 27,2 9]
AD1 4 M16 2
VSS[19 ] VSS[ 125 ] [ 15] SLP_S3#
AD1 7 M17
AD1 8 VSS[20 ] VSS[ 126 ] M23
AD2 1 VSS[21 ] VSS[ 127 ] M28
7
VSS[22 ] VSS[ 128 ]
AD2 8 M29
VSS[23 ] VSS[ 129 ]
AD2 9 N11
AD4 VSS[24 ] VSS[ 130 ] N12 R10 9 *10mil_sh ort
VSS[25 ] VSS[ 131 ] [15 ] SL P_ S4# SU SC # [ 26]
AD5 N13
VSS[26 ] VSS[ 132 ]
AD6 N14
AD7 VSS[27 ] VSS[ 133 ] N15

VSS[28 ] VSS[ 134 ]
AD9 N16
AE1 2 VSS[29 ] VSS[ 135 ] N17
VSS[30 ] VSS[ 136 ]
AE1 3 N18
VSS[31 ] VSS[ 137 ]
AE1 4 N26
AE1 6 VSS[32 ] VSS[ 138 ] N27 3. 3V
VSS[33 ] VSS[ 139 ]
AE1 7 P1 2
AE2 VSS[34 ] VSS[ 140 ] P1 3
Sheet 17 of 40
VSS[35 ] VSS[ 141 ]
AE2 0 P1 4 U 8C
14
VSS[36 ] VSS[ 142 ]
AE2 4 P1 5 7 4LVC08 PW
AE3 VSS[37 ] VSS[ 143 ] P1 6 SYS_PWROK 9
VSS[38 ] VSS[ 144 ]
AE4 P1 7 8
ICH9-M 5/5 - GND

VSS[39 ] VSS[ 145 ] SB_ PW ROK [ 15]
AE6 P2 1. 8V_PWRGD 10
VSS[40 ] VSS[ 146 ]
AE9 P2 3
AF1 3 VSS[41 ] VSS[ 147 ] P2 8 R 154 C26 7
VSS[42 ] VSS[ 148 ]
AF1 6 P2 9
7
VSS[43 ] VSS[ 149 ]
AF1 8 P4 *1 0K_04 *0.1 U_1 6V_04
VSS[44 ] VSS[ 150 ]
AF2 2 P7
AH2 6 VSS[45 ] VSS[ 151 ] R11
AF2 6 VSS[46 ] VSS[ 152 ] R12
VSS[47 ] VSS[ 153 ]
AF2 7 R13
VSS[48 ] VSS[ 154 ]
AF5 R14
VSS[49 ] VSS[ 155 ]
AF7 R15
AF9 VSS[50 ] VSS[ 156 ] R16
VSS[51 ] VSS[ 157 ]
AG1 3 R17
VSS[52 ] VSS[ 158 ] 3. 3V
AG1 6 R18
AG1 8 VSS[53 ] VSS[ 159 ] R28
VSS[54 ] VSS[ 160 ]
AG2 0 T12
VSS[55 ] VSS[ 161 ]
AG2 3 T13 U 8B
14
VSS[56 ] VSS[ 162 ]
AG3 T14 7 4LVC08 PW
VSS[57 ] VSS[ 163 ]
AG6 T15 4
AG9 VSS[58 ] VSS[ 164 ] T16 [29] 1 .5VS_PWRG D 6 SY S_ PWR OK
VSS[59 ] VSS[ 165 ]
AH1 2 T17 5
VSS[60 ] VSS[ 166 ] [5 ,31 ] DELAY_PWRGD
AH1 4 T23
AH1 7 VSS[61 ] VSS[ 167 ] B2 6
VSS[62 ] VSS[ 168 ]
AH1 9 U12
7
VSS[63 ] VSS[ 169 ]
AH2 U13
VSS[64 ] VSS[ 170 ]
AH2 2 U14
AH2 5 VSS[65 ] VSS[ 171 ] U15
AH2 8 VSS[66 ] VSS[ 172 ] U16
AH5 VSS[67 ] VSS[ 173 ] U17
VSS[68 ] VSS[ 174 ]
AH8 AD 23
VSS[69 ] VSS[ 175 ]
AJ1 2 U26
VSS[70 ] VSS[ 176 ]
AJ1 4 U27
VSS[71 ] VSS[ 177 ]
AJ1 7 U3
AJ 8 VSS[72 ] VSS[ 178 ] V1
VSS[73 ] VSS[ 179 ]
B1 1 V1 3
B1 4 VSS[74 ] VSS[ 180 ] V1 5
VSS[75 ] VSS[ 181 ] 3. 3V
B1 7 V2 3
VSS[76 ] VSS[ 182 ]
B2 VSS[77 ] VSS[ 183 ] V2 8
B2 0 V2 9
VSS[78 ] VSS[ 184 ]
B2 3 V4 U 8D
14
B5 VSS[79 ] VSS[ 185 ] V5 7 4LVC08 PW
VSS[80 ] VSS[ 186 ]
B8 W26 1. 8V_PWRGD 12
VSS[81 ] VSS[ 187 ] [30 ] 1.8 V_ PW RGD
C2 6 W27 11
C2 7 VSS[82 ] VSS[ 188 ] W3 13 CL_ PW ROK [ 5,1 2,1 5,2 6]
VSS[83 ] VSS[ 189 ] [29 ] 1.0 5VM_PWRGD
E1 1 Y1
VSS[84 ] VSS[ 190 ]
E1 4 Y28 R 156
VSS[85 ] VSS[ 191 ]
E1 8 Y29
7
E2 VSS[86 ] VSS[ 192 ] Y4 *1 0K_04
E2 1 VSS[87 ] VSS[ 193 ] Y5
VSS[88 ] VSS[ 194 ]
E2 4 AG 28
VSS[89 ] VSS[ 195 ]
E5 AH 6
VSS[90 ] VSS[ 196 ]
E8 AF2
VSS[91 ] VSS[ 197 ]
F1 6 B2 5
VSS[92 ] VSS[ 198 ]
F2 8
F2 9 VSS[93 ] A1
VSS[94 ] VSS_ NCTF[1 ]
G1 2 A2
G1 4 VSS[95 ] VSS_ NCTF[2 ] A2 8
G1 8 A2 9
G2 1 AH 1
G2 4 VSS[98 ] VSS_ NCTF[5 ] AH 29
G2 6 AJ 1
VSS[10 0] VSS_ NCTF[7 ]
G2 7 VSS[10 1] VSS_ NCTF[8 ] AJ 2
G8 AJ 28
VSS[10 2] VSS_ NCTF[9 ]
H2 AJ 29
H2 3 VSS[10 3] VSS_N CTF[10 ] B1
VSS[10 4] VSS_N CTF[11 ]
H2 8 B2 9
H2 9 VSS[10 5] VSS_N CTF[12 ]
VSS[10 6]
I CH9M-NH8 2801 IBM
[2, 12. .16 ,19 ,20, 23, 29, 30] 3 .3V
B - 18 ICH9-M 5/5 - GND

Schematic Diagrams
Clock Generator
CLOCK GENERATOR
Layout note:
Insatlled: Differential clock
3 .3 VS 3 . 3 V M_ C L K
level is higher
L39 R 29 6 C L K _ MC H _ B C L K C 49 2 *1 0P _ 5 0 V _0 4
C L K _ MC H _ B C L K # C 49 7 *1 0P _ 5 0 V _0 4
H C B 1 60 8 K F -1 21 T 2 5 1 K _ 1% _ 0 4
40mils C L K _ C P U _B C L K C 48 4 *1 0P _ 5 0 V _0 4
R 2 95 3 0 0_ 1 % _0 4 3 . 3V M _ C L K C L K _ C P U _B C L K # C 48 8 *1 0P _ 5 0 V _0 4
Layout note:
30mils
C5 3 4 C 51 1 C 49 1 C 5 02 C 5 32 CL K_ P CIE _ IC H C 50 1 *1 0P _ 5 0 V _0 4
PLACE CRYSTAL WITHIN
CL K_ P CIE _ IC H# C 50 7 *1 0P _ 5 0 V _0 4
500 MILS OF 1 0 U _ 10 V _ 0 8 1 U _ 6 . 3 V _0 4 0 . 1 U _ 1 0V _ X 7 R _ 0 4 0 . 1 U _ 1 0V _X 7 R _ 0 4 0 . 1 U _ 10 V _ X 7R _0 4 C 4 82 C4 6 7 C 46 8 C 47 8
ICS9LPR363EGLF C L K _ P C I E _ J M3 8 0 C 54 1 *1 0P _ 5 0 V _0 4
0. 1 U _1 0 V _X 7 R _ 0 4 1U _ 6. 3 V _ 0 4 0 . 1 U _ 1 0V _ X 7 R _ 04 * 10 U _1 0 V _0 8 C L K _ P C I E _ J M3 8 0# C 54 2 *1 0P _ 5 0 V _0 4
3 . 3 V M_ C L K CL K_ P CIE _ M INI C 50 5 *1 0P _ 5 0 V _0 4
CL K_ P CIE _ M INI# C 50 9 *1 0P _ 5 0 V _0 4
X3 20mils
21
42
47
28
50
56
C L K _ P C I E _ G LA N
1
7
1 2 U2 2 C 54 4 *1 0P _ 5 0 V _0 4
C 5 35 C 5 00 C4 8 0 C L K _ P C I E _ G LA N # C 54 3 *1 0P _ 5 0 V _0 4
V D DP C I
V D DP C IE X
V D DP C IE X
VR EF
VDD PCI
V DD P CIE X
V DD RE F
V DD CP U
1 4 . 3 18 M H z 11 49 Z 17 1 0 1 4 R N2 4 C LK _ MC H _ B C LK C L K _ MC H _ B C L K [ 4 ]
1 0 U _ 1 0V _0 8 1 U _6 . 3 V _ 04 0 . 1 U _ 10 V _ X 7R _0 4 45 V D D4 8 C P U T _ L 1F 48 Z 17 1 1 2 3 4 P 2 R X 3 3 _0 4 C LK _ MC H _ B C LK # CL K_ S A T A C 52 8 *1 0P _ 5 0 V _0 4
C 4 72 C 4 71 V D DA C P U C _ L 1F C L K _ MC H _ B C L K # [ 4 ] CL K_ S A T A # C 53 3 *1 0P _ 5 0 V _0 4
Sheet 18 of 40
52 Z 17 1 2 1 4 R N2 2 C LK _ C P U _ B C L K
27 P _ 5 0V _ 0 4 27 P _ 5 0V _ 0 4 58 C P U T_ L 0 51 Z 17 1 3 2 3 4 P 2 R X 3 3 _0 4 C LK _ C P U _ B C L K # C L K _ C P U _ B C LK [ 2 ] C L K _ P C I E _ M I N I _ 3G C 51 2 *1 0P _ 5 0 V _0 4
X TA L _ I N X1 CP U C_ L 0 C L K _ C P U _ B C LK # [ 2] C L K _ P C I E _ M I N I _ 3G # C 51 9 *1 0P _ 5 0 V _0 4
Clock Generator
X TA L _ OU T 57 44 Z 17 1 4 3 2 R N2 6 C LK _ P C I E _I C H C L K _ P C I E _ N E W _C A R D C 53 7 *1 0P _ 5 0 V _0 4
X2 P C I e T _L 8 / C P U I TP T_ L 2 CL K _ P CIE _ ICH [1 4 ]
43 Z 17 1 5 4 1 4 P 2 R X 3 3 _0 4 C LK _ P C I E _I C H # C L K _ P C I E _ N E W _C A R D # C 53 6 *1 0P _ 5 0 V _0 4
P C I e C _ L8 / C P U I T P C _ L 2 C L K _ P C I E _ I C H # [ 1 4]
41 Z 17 3 8 R 30 6 4 75 _ 1 %_ 0 4 C L K _ P C I E _ 3 GP L L C 49 8 *1 0P _ 5 0 V _0 4
P C I e T _L 7 / P E R E Q1 # S A TA _C LK R E Q# [ 15 ] C L K _ P C I E _ 3 GP L L #
[2 ,4 ] C LK _ B S E L 0 R2 8 4 2. 2 K _ 0 4 40 Z 17 4 0 R 30 7 4 75 _ 1 %_ 0 4 MC H _ C L K R E Q # [5 ] C 49 9 *1 0P _ 5 0 V _0 4
P C I eC _L 7 / P E R E Q2 #
C L K _ I C H 48 R2 7 9 33 _ 0 4 FSL A 12 39 Z 17 1 8 1 4 R N3 0 C LK _ P C I E _N E W _ C A R D CL K_ DR E F S S C 49 0 *1 0P _ 5 0 V _0 4
[1 5 ] C LK _ I C H 4 8 F S L A / U S B _4 8 MH z P C I e T_ L 6 C L K _P C I E _ N E W _ C A R D [ 2 0]
38 Z 17 1 9 2 3 4 P 2 R X 3 3 _0 4 C LK _ P C I E _N E W _ C A R D # CL K_ DR E F S S # C 49 4 *1 0P _ 5 0 V _0 4
C L K _ I C H 14 R2 7 2 33 _ 0 4 R E F _ 1 4 . 31 8 M 60 P CIe C_ L 6 C L K _P C I E _ N E W _ C A R D # [ 20 ]
[1 5 ] C LK _ I C H 1 4 R E F 0_ 1 4 . 31 8 M CL K_ DR E F
36 Z 17 4 1 1 4 R N3 1 C LK _ P C I E _G L A N C L K _ P C I E _ GL A N [ 2 3] C 48 1 *1 0P _ 5 0 V _0 4
R2 6 9 10 K _ 0 4 FSL C 61 P C I e T_ L 5 35 Z 17 4 2 2 3 4 P 2 R X 3 3 _0 4 C LK _ P C I E _G L A N # CL K_ DR E F # C 48 7 *1 0P _ 5 0 V _0 4
[2 ,4 ] C LK _ B S E L 2 R E F 1/ F S LC / TE S T_ S E L P CIe C_ L 5 C L K _ P C I E _ GL A N # [ 23 ]
62 30 Z 17 2 2 2 3 R N3 2 C LK _ P C I E _J M 38 0
[ 15 ] P M_ S T P C P U # C P U _ S T OP # P C I e T_ L 4 C L K _ P C I E _ J M3 80 [ 22 ] C L K _ I C H 48
[ 1 5 ] P M _S T P P C I # 63 31 Z 17 2 3 1 4 4 P 2 R X 3 3 _0 4 C LK _ P C I E _J M 38 0 # C L K _ P C I E _ J M3 80 # [ 2 2 ] C 47 4 *1 0P _ 5 0 V _0 4
P C I / P C I E X _ S T OP # P CIe C_ L 4
R2 5 3 *1 0 K _0 4 S E L P C I E X 0 _ LC D # 5 26 Z 17 2 4 4 1 R N2 9 C LK _ S A T A P CL K _ K B C C 45 0 *1 0P _ 5 0 V _0 4
P C I C L K 3 / *S E L P C I E X 0 _ LC D # S A T A CL KT _ L C L K _ S A TA [ 1 3]
27 Z 17 2 5 3 2 4 P 2 R X 3 3 _0 4 C LK _ S A T A #
S A TA C L K C _ L C L K _ S A TA # [ 13 ] P C L K _ I C H 33 C 46 6 *1 0P _ 5 0 V _0 4
P CL K _ T P M R2 6 6 *3 3 _0 4 Z 1 70 3 4 24 Z 17 2 6 4 1 R N2 8 C LK _ P C I E _M I N I _ 3 G
[ 1 9] P C L K _ TP M P C ICL K 2 P C I e T_ L 3 25 Z 17 2 7 3 2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _M I N I _ 3 G# C L K _ P C I E _ MI N I _3 G [ 1 9 ] P CL K _ T P M C 44 9 *1 0P _ 5 0 V _0 4
P CIe C_ L 3 C L K _ P C I E _ MI N I _3 G # [ 1 9]
33 LA N _ C L K R E Q # [ 2 3]
P CL K _ K B C R2 6 7 33 _ 0 4 Z 1 70 4 3 *P E R E Q4 # C L K _ I C H 14 C 47 5 *1 0P _ 5 0 V _0 4
[ 2 6] P CL K _ K B C P C ICL K 1
22 Z 17 2 8 4 1 R N2 7 C LK _ P C I E _M I N I C L K _ P C I E _ MI N I [ 2 0 ]
P C I e T_ L 2 23 Z 17 2 9 3 2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _M I N I #
P CIe C_ L 2 C L K _ P C I E _ MI N I # [ 2 0] Layout note:
R2 6 8 10 K _ 0 4 RE Q _ SE L 64 32
3 .3 V S * *P C I C L K 0/ R E Q_ S E L *P E R E Q3 # W LA N _ C L K R E Q # [ 1 9, 2 0 ]
Place termination close
19 Z 17 3 0 4 1 R N2 5 C LK _ P C I E _3 G P LL
S E L L CD_ 2 7 # P C I e T_ L 1 C L K _ P C I E _ 3 GP L L [ 5 ] to ICS9LPR363DGLF
P C L K _ I C H 33 R2 7 1 33 _ 0 4 9 20 Z 17 3 1 3 2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _3 G P LL #
[1 4 ] P C LK _ I C H 3 3 * S E LL C D _ 27 # / P C I C L K _F 5 P CIe C_ L 1 34 C L K _ P C I E _ 3 GP L L # [ 5]
I T P _E N * P W RS AV E #
R2 6 5 10 K _ 0 4 8
P C I C L K _ F 4/ I T P _ E N 17 Z 17 3 2 4 1 R N2 3 C LK _ D R E F S S
2 7F I X/ L C D _ S S C G T/ P C I e T_ L 0 CL K _ DRE F SS [5 ]
[ 1 0 , 1 1, 1 5 ] I C H _ S MB C L K 0 54 18 Z 17 3 3 3 2 4 P 2 R X 3 3 _0 4 C LK _ D R E F S S # CL K _ DRE F SS # [5 ]
55 S C LK 2 7 S S / L C D _ S S C GC / P C I e C _ L 0 16 F S LB
[ 1 0 , 1 1, 1 5 ] I C H _ S MB D A T 0 S D A TA F S L B / T E S T_ M OD E
R2 9 3 *1 0 m li _ sh o rt CL K _ B S E L 1 [2 ,4 ]
10
[ 1 5] CL K _ P W RG D V T T _P W R _ GD / P D # 14 Z 17 3 5 4 1 R N2 1 C LK _ D R E F
P C I e T _ L9 / D O T T_ 9 6 MH z L CL K _ DRE F [5 ]
GN D A
3 .3 V S R2 8 2 *1 0 0K _ 0 4 15 Z 17 3 6 3 2 4 P 2 R X 3 3 _0 4 C LK _ D R E F #
G ND
GN D
G ND
GN D
G ND
GN D
P C I e C _ L 9/ D OT C _ 9 6 MH z L C L K _ D R E F # [ 5]
GN D
I C S 9 L P R 3 63 E G LF
13
37
46
53
59
29
2
6
Pin5 Pin9 Pin14/15 Pin17/18
SELPCIEX0_LCD#/ SELLCD_27#=0 PCIEX9 27FIX/SS

FS LC FS LB F SL A C K5 05 PCI3 = 0 (low) SELLCD_27#=1 DOT96 LCD(96MHz)
H os t Clo ck Red words must be controlled by BIOS
BS EL2 BS EL1 B SE L0 SELPCIEX0_LCD#/ SELLCD_27#=0 PCIEX9 PCIEX0
Fr eq uen cy
0 0 0 26 6 MHz 106 6 MHz SAT A_CL KREQ# PCI ECLK 6 (NEW CARD) M CH_CL KREQ # PCIECL K 1 ( 3GP LL ) PCI3 = 1 (high) SELLCD_27#=1 DOT96 PCIEX0 Default
0 1 0 20 0 MHz 800 M Hz (PEREQ1 #) SAT ACL K (PEREQ2 #) PCIECL K 8 ( ICH)
0 1 1 16 6 MHz 667 M Hz
WL AN_C LKREQ # PCI ECLK 2 (M INI ) L AN_CL KREQ # PCIECL K 3 ( MI NI_ 3G )

(PEREQ3 #) PCI ECLK 4 (J M3 85 ) (PEREQ4 #) PCIECL K 5 ( GL AN)
[ 5 , 8 . . 16 , 1 9. . 27 , 3 1] 3 . 3V S
Clock Generator B - 19
Schematic Diagrams
Multi I/O, ODD, CCD, BT, TPM
SATA ODD Layout Note TPM 1.2

SATA SINGAL FROM SB TO JODDB1
U7
END OF JODD1 26 10
[ 1 3 , 26 ] LP C _A D 0 LA D 0 V DD1 3. 3V S
[ 1 3 , 26 ] LP C _A D 1 23 19
20 LA D 1 V DD2 24 C5 8 7 C 26 6 C 26 9 C 2 65
FOR M720T FOR M730T [ 1 3 , 26 ]
[ 1 3 , 26 ]
LP C
LP C
_A D
_A D
2
3 17
LA D 2 V DD3
LA D 3 *0 . 1 U _ 1 6V _ 0 4 * 0. 1 U _ 1 6V _0 4 * 0. 1 U _1 6 V _0 4 *1 U _ 10 V _ 06
21 TPM
[ 1 8] P C L K _ TP M LC LK
J _O D D _ 7 2 J _O D D _ 7 3
S1 22 5
S2 S A T A _ TX P 1 1 S A T A _ TX P 1 [ 1 3 , 26 ] L P C _F R A ME # 16 LF R A ME # VSB 3 . 3V
S A T A _ TX P 1 [1 3 ] 2 [ 5 , 14 ] P LT _ R S T # LR E S E T #
S3 S A T A _ TX N 1 S A T A _ TX N 1 27 C5 8 1
S4 S A T A _ TX N 1 [ 13 ] 3 [ 15 , 2 6 ] S E R I R Q 15 SE RIR Q
4 [ 1 5] P M_ C L K R U N # CL K RU N#
S5 S A T A _ RX N1 S A T A _ RXN1 [1 3 ] S A T A _ RX N1 *0 . 1 U _ 1 6V _ 0 4
S6 S A T A _ RX P 1 5 S A T A _ RX P 1 28 6
S7 S A T A _ RXP 1 [ 1 3] 6 [ 1 5] L P CP D# LP C P D # G P IO 2
7 GP I O2
OD D _ D E T E C T # T P M_ B A D D 9
8 TE S T B I / B A D D 13
9 5V S X TA L I
TO SB GPIO 5 VS T P M_ P P 7 X2
P1 O D D _ D E T E C T# 10 PP * 3 2. 7 6 8K H z
O D D _ D E T E C T# [1 5 ] 1.6A 11
P2 14 4 1
12 XT A L O
P3 1 3 2
P4 *8 5 20 5 -1 2 3 NC_ 1 4
P5 C 20 5 C1 9 9 C 2 19 C1 9 8 C2 1 6 12 NC_ 2 GN D _1 11
NC_ 3 GN D _2
P6 18
0 . 1 U _ 16 V _ 04 0 . 1U _1 6 V _ 04 1U _1 0 V _ 06 1 0U _ 10 V _ 08 *1 0 0U _6 . 3 V _B 2 8 GN D _3 25 C2 7 1 C 27 0
TE S T I GN D _4
C 1 8 53 5 -11 3 0 5-L
*1 5 P _ 50 V _ 04 * 15 P _ 50 V _ 0 4
*S L B 9 6 35 T T
Sheet 19 of 40
Multi I/O, ODD,
CCD, BT, TPM Asserted before entering S3
LPC reset timing:
LPCPD# inactive to LRST# inactive 32~96us
Bluetooth HI : ACC ES S
TP M _P P
TP M _B A D D
R 1 47
R 1 52
*1 0 K _0 4
*1 0 K _0 4
3 .3 V S
TPM _P P
L OW : NOR MA L ( De fau lt ) R 1 51 *1 0 K _0 4
3. 3 V L2 0 3 VS_ BT
H C B 1 0 05 K F -1 2 1T 2 0 50m il HI : 4E / 4F h ( De fau lt )
TPM _B ADD P C L K _ TP M R 1 53 *3 3 _0 4 C 2 68 *1 0P _ 5 0V _ 0 4
L OW : 2E / 2F h
C2 8 9 C2 9 0
0 . 1 U _ 16 V _ 04 1 0U _1 0 V _0 8
J _B T 1
[ 14 ] US B _ PN9 _ B T
1
2
J_BT1 MULTI I/O CONN
3 1 6 R 13 2 0 0K _ 1 %_ 0 4
[ 14 ] U S B _ P P 9 _B T 4 [1 4 ] U S B _O C # 3
[ 2 6] B T_ D E T# B T _ E N# 5
R1 7 7 1 0 0K _ 0 4 R 11 1 0 0K _ 1 %_ 0 4
3 .3 V S 6 3 . 3V 1 .5 V S 3 .3 V S 5V US B V C C2
D
87 2 12 -0 6 G0 60 mil U1 60 mil
4 1
G C2 7 6 C 5 C2 8 8 V IN V OU T
[ 2 1, 2 6 ] BT_ EN
Q 15 C3 2 3 5 C 16 C 15 C2 0
2 N 7 0 02 W 0. 1 U _1 6 V _0 4 0 . 1 U _ 16 V _ 0 4 0 . 1U _1 6 V _0 4 V IN V OU T
S
1U _ 10 V _ 06 2 0 . 1 U _ 1 6V _ 0 4 0 . 1 U _ 16 V _ 04 *1 0 U _ 10 V _ 0 8
GN D
R T 9 70 1 -C P L
CCD 5V Q1 3 5 V _C C D J_ MF B 1
J _ MF B 2
A O3 40 9 [ 18 ] C LK _ P C I E _M I N I _ 3G # 1 2
48 mil 3 .3 VS= 1. 5A 3 . 3V S 1 2 U S B V CC 2 [ 18 ] C LK _ P C I E _M I N I _ 3 G 3 4
L18 H C B 1 00 5 K F -1 21 T 20 S D [ 1 4] P C I E _ R X N 3 _ 3 G
3 4 5 6
[ 2 6 ] L E D _ N U M# 5 6 3 .3 V [ 14 ] P C I E _ R X P 3_ 3 G 7 8
J_CCD1 [ 2 6] LE D _ C A P # 7 8 L E D _ T H R OT TL E # [ 2 6 ] [ 14 ] P C I E _ TX N 3 _ 3 G 9 10
C 4 C 2 77 R 1 65 C 27 4 C2 7 5
0 . 1 U _ 16 V _ 04 1 [ 1 3 ] S A T A _ LE D # 9 10 L E D _ S C R OL L # [ 26 ] [ 14 ] P C I E _ TX P 3 _ 3G 11 12
G
[ 3 0] M_ B T N # 11 12 1 .5 V S [ 1 5, 2 0 , 23 ] P C I E _ W A K E # 13 14
1 0 U _ 10 V _ 08 Z 1 9 07 Z 1 9 08 1 0 0 K _0 4 0 . 1 U _ 16 V _ 0 4 1 0U _1 0 V _ 08 [ 26 ] 3 G _D E T# [ 1 4 , 20 , 2 2 , 23 , 2 6] B U F _ P L T_ R S T#
13 14 15 16
5 [1 3 ] M DC_ A Z _ S DO UT 15 16 [ 1 8, 2 0 ] W L A N _ C L K R E Q# 17 18
[1 3 ] M DC_ A Z _ S Y N C 17 18 W L A N _ C L K R E Q# [ 1 8 , 20 ] [ 14 ] U S B _ P N 5 _ 3G 19 20
R1 6 8
[ 13 ] A Z _S D I N 1 19 20 3 G_ E N [ 2 1, 2 6 ] [ 1 4 ] U S B _P P 5 _ 3 G 21 22
[ 1 3] MD C _A Z _R S T# 21 22 A P K E Y # [ 3 0] 23 24
1 00 K _ 0 4 J _C C D 1 [1 3 ] M DC_ A Z _ B IT CL K W E B _ E MA I L# [ 2 6 ] [ 1 4] US B _ P N3
R1 6 9 33 0 K _ 04 23 24 25 26
Z 1 9 09 1 [2 5 ] S P K O UT R+ 25 26 W E B _ W W W # [2 6 ] [ 1 4] US B _ P P 3 27 28
[ 14 ] US B _ P N7 _ CCD 2 [ 2 5] S P K OU TR - 27 28 L I D _ S W # [ 1 2 , 26 ]
[ 14 ] U S B _ P P 7 _C C D 5 F 1 -23 3 A 1 -A 20 0 0-2 1 4
3
D
5 F 1 -2 33 A 1 -A 2 00 0 -21 4
[ 2 6] C C D _ D E T # 4
Q1 4
G 2 N 7 0 02 W 5
[ 26 ] C C D _E N 8 52 0 4 -05 0 01
S
From H8 default HI
[ 16 , 2 1, 2 8 . . 31 ] 5V
[ 1 2 , 13 , 1 6, 21 , 2 4, 2 5 , 27 ] 5V S
[ 2 , 1 2. . 1 7 , 2 0, 2 3 , 29 , 3 0] 3 . 3V
[ 5 , 8. . 1 6 , 18 , 2 0 . . 27 , 3 1] 3 . 3V S
[ 3 , 8, 1 3 , 14 , 1 6 , 20 , 2 9] 1 . 5V S
B - 20 Multi I/O, ODD, CCD, BT, TPM

Schematic Diagrams
New Card, Mini PCIE
3 .3 VS
NEW CARD C 4 46
*0 . 1 U _ 1 6V _ 0 4
5
B U F _ P L T_ R S T # 1
4
2
3 .3 V
U1 9 U1 8 J_ N E W 1
C4 4 0 0 . 1U _1 6 V _ 04 21 9 NC_ RS T # 74 A H C 1 G0 8G W N C _P E R S T # 13
3
A U XI N P E R S T# C 19 1 0 . 1 U _ 16 V _ 0 4 P E R S T#
NC_ 3 .3 V 20 mil
3 .3 VS 20 12 3 .3 V S
A U XO U T + 3 . 3V A U X
6- 01- 74 108 -Q6 1
C4 4 3 0 . 1U _1 6 V _ 04 6 40 mil C 19 6 0 . 1 U _ 16 V _ 0 4 W LA N _C L K R E Q# R 9 *1 0 K _ 04
3 .3 V IN NC_ 3 .3 V S
C4 4 2 0 . 1U _1 6 V _ 04 5 8 14
3 .3 V IN 3 . 3V O U T 7 C 19 3 0 . 1 U _ 16 V _ 0 4 15 + 3 . 3V
1 .5 VS 3 . 3V O U T + 3 . 3V
40 mil C 18 1 0 . 1 U _ 16 V _ 0 4
C4 4 1 0 . 1U _1 6 V _ 04 18 16 NC_ 1 .5 V S 9
1 .5 V IN 1 . 5V O U T + 1 . 5V
C4 4 5 0 . 1U _1 6 V _ 04 19 17 C 18 7 0 . 1 U _ 16 V _ 0 4 10
1 .5 V IN 1 . 5V O U T + 1 . 5V
15 N C _C P P E # 17
CP P E # C PPE#
[ 14 , 1 9, 2 2 , 2 3, 2 6 ] B U F _P L T _R S T# B U F _P L T _R S T# 2 14 N C _C P U S B # 4
23 S Y S RS T # C P US B # P CIE _ W A K E # 11 C P US B #
[ 14 ] U S B _ OC # 4 O C# [ 1 5 , 19 , 2 3] P CIE _ W A K E # W AKE#
R2 4 7 * 10 0 K _0 4 16
4 C LK R E Q#
[ 1 7 , 23 , 2 6, 2 7 , 2 9] SUSB# STBY# R2 4 9 * 10 0 K _0 4 19
3. 3 V [ 1 8] C L K _ P C I E _ N E W _ C A R D R EF CL K+
[ 1 8] C L K _ P C I E _ N E W _ C A R D # 18
1 22 R EF CL K- 5
10 N C R C LK E N 3 R2 4 2 * 10 K _ 04 22 R E S E RV E D 6
N C S HD N# [ 14 ] P C I E _ R X P 2 _N E W _C A R D P E R p0 R E S E R V E D
12 [ 14 ] P CIE _ RX N2 _ NE W _ CA R D 21
N C P E R n0
Sheet 20 of 40
13 11 25 1
N C GN D [ 1 4] P C I E _ T XP 2 _ N E W _ C A R D PET p 0 GN D
24 25 [ 1 4] P C I E _ T XN 2 _N E W _C A R D 24 20
N C GN D PET n 0 GN D 23
P 22 3 1T H LF C 1 GN D 26
GN D
New Card,
[ 1 4 ] U S B _P P 4 _ N E W 3 27
2 U S B _D + GN D 28
ENE P 223 1 p in 3,4 ,14 ,1 5,2 2 [ 14 ] U S B _ P N 4 _N E W U S B _D - GN D 29
has i nte rna ll y p ull ed hi gh GN D
[ 15 ] I C H _ S MB D A T 1 8 30
Mini PCIE
( 1 70 K o hmS ) 7 S M B _D A TA GN D
[ 15 ] I C H _ S MB C LK 1 S M B _C LK
13 0 80 1 -1
GN D 1 ~ 4 = G N D
MINI CARD
J_ MI N I 1 20 mil
P C I E _W A K E # 1 2
W AKE# 3. 3 V _ 0 W L A N3 .3 V
3 4
R 3 83 0 _0 4 5 BT _ DAT A GN D 5 6
W L A N_ CL K RE Q # 7 B T _ CHC L K 1. 5 V _ 0 8 W L A N1 .5 V S
W L A N3 .3 V [ 1 8, 1 9 ] W L A N_ CL K RE Q # C LK R E Q# U I M_ P W R
9 10
Q 3 * A O3 4 09 11 G ND0 U I M _D A TA 12
20mil 20mil [ 1 8 ] C L K _ P C I E _ MI N I # R E F CL K - U I M _C LK
S D 13 14
3 .3 V [ 1 8 ] C L K _ P C I E _ MI N I R E F CL K + U I M _R E S E T
15 16
C 33 G ND1 U I M _V P P
*0 . 1U _1 6 V _0 4 R 10 C 26
C2 9 KEY
G
* 10 0 K _ 04 *0 . 1 U _ 1 6V _ 0 4
*1 0 U _ 10 V _ 0 8 17 18
R 16 19 N C3 GN D 6 20
21 N C4 W _D I S A B L E # 22 B U F _ P L T_ R S T # W L A N_ E N [ 2 1, 2 6 ]
R1 2 * 10 0 K _ 04 23 G ND2 P E RS E T # 24
*3 3 0K _ 0 4 [ 14 ] P C I E _R X N 1 _W L A N 25 PETn 0 3. 3 V _ 2 26 W L A N 3 . 3V
[ 1 4 ] P C I E _ R XP 1 _ W LA N PETp 0 GN D 7 20 mil
27 28 W L A N 1 . 5V S
29 G ND3 1. 5 V _ 1 30 R 21 *0 _0 4
G ND4 N C (S M B _C LK ) I C H _ S MB C LK 1 [1 5 ]
D
31 32 R 20 *0 _0 4
[1 4 ] P C I E _ T X N 1 _W L A N P E R n0 N C (S M B _D A TA ) I C H _ S MB D A T1 [1 5 ]
Q2 [ 1 4] P C I E _ T XP 1 _ W LA N 33 34
G *2 N 7 0 02 W 35 P E R p0 GN D 8 36
[ 26 ] W L A N _P W R [ 2 6] W L A N _ D E T # G ND1 1 N C (U S B _ D -) U S B _P N 2_ M I N I [1 4 ]
37 38 U S B _P P 2 _ MI N I [ 1 4]
39 N C6 N C (U S B _D +) 40
S
W L A N 3. 3 V 41 3 . 3 V _3 GN D 9 42
3 . 3 V _4 N C (L E D _ W W A N #)
43 44
R2 4 *1 0m i l _s h ort 45 N C9 LE D _ W LA N # 46
[ 1 5] CL _ CL K 1 47 N C1 0 N C (L E D _W P A N #) 48
N C1 1 1. 5 V _ 2 W L A N1 .5 V S
[ 1 5] CL _ DA T A 1 R2 3 *1 0m i l _s h ort 49 50 20 mil
51 N C1 2 GN D 1 0 52
N C1 3 3. 3 V _ 1 W L A N3 .3 V
[ 1 5] C L _ R S T #1 R2 2 *1 0m i l _s h ort
88 9 08 -5 2 04
For Kedron WLAN Device
W L A N3 .3 V W LA N 1. 5 V S R1 8 1 . 5V S
0 _0 4
C 23 C4 4 C4 5 C2 4 C 40 C4 2 C4 1 C 43
0 . 1 U _ 16 V _ 0 4 1 0U _1 0 V _ 08 0. 1 U _1 6 V _0 4 10 U _ 1 0V _ 0 8 0 . 1 U _ 16 V _ 0 4 0. 1 U _1 6 V _0 4 0. 1 U _ 1 6V _ 0 4 0 . 1 U _ 16 V _ 0 4
[ 3 , 8, 1 3 , 14 , 1 6 , 19 , 2 9] 1 . 5V S
[ 2 , 1 2. . 1 7 , 1 9, 2 3 , 29 , 3 0] 3 . 3V
[ 5 , 8 . . 1 6, 1 8 , 19 , 2 1 . . 27 , 3 1] 3 . 3V S
New Card, Mini PCIE B - 21

Schematic Diagrams
LED, FAN, TP, FP, USB
LED V D D3 V DD3 3. 3 V S 3 .3 V S
FAN CONTROL
5V S
R 15 8 R 1 57 R 1 60 R 1 61
2 20 _ 04 22 0 _0 4 2 20 _ 0 4 22 0 _0 4 5
C 4 37
+ 7 5 VS L3 1 5 VS_ FAN
Z 21 0 1 Z 2 1 02 Z 21 0 9 Z 2 1 10 6 H C B 1 0 05 K F -1 2 1T 2 0
*0 . 1U _1 6 V _ 04
- U1 6 B
3
L M3 58 L
1 3 D1 8 1 3 D1 9 C4 3 8
SG
SG
Y
Y
2 4 R Y -S P 15 5 H Y Y G4 2 4 R Y -S P 1 55 H Y Y G4 10 U _1 0 V _0 8
30mils
R 2 43
8
POWER ON LED WLAN/BT LED Z 21 1 1 Z 2 1 12 4 . 9 9K _ 1 %_ 0 4
C
F A N _D C _ V OL F A N _ D C _ V OL _R 3 +
S
1 Z 21 1 5 G
B B R 2 44 2 D2 0
[ 26 ] L E D_ A C IN# L E D_ P W R # [ 26 ] [ 1 9, 2 6 ] BT_ EN W LA N _E N [ 2 0 , 26 ]
1 0 K _1 % _0 4
- U 1 6A Q 20 R B 5 5 1V - 30
Q8 Q 7 LM 35 8 L A O3 4 09
D T C 1 1 4E U A DT C1 1 4 E UA
A
4
30mils J_ F A N 1
E
F A N _ D C _ V OL 1
C4 3 9 2
3
1 00 U _ 6 . 3V _ B 2 8 5 20 5 -03 0 01
[ 26 ] CP U_ F A N
V D D3 V DD3 3 .3 V S
Sheet 21 of 40
J_FAN1
[ 2 6] C P U _F A N S E N 3
R 15 9 R 1 55 R 1 62 R2 4 6 4 . 7 K _ 04
LED, FAN, TP, FP,

3 . 3V S 1
2 20 _ 04 22 0 _0 4 22 0 _0 4 C A
D 21 R B 5 51 V -3 0
Z 21 0 5 Z 2 1 06 Z 2 1 13
USB
A
1
3
1 3 D2 2 D2 3
SG
R Y -S P 1 72 Y G 34
Y
2 4 R Y -S P 15 5 H Y Y G4
FP CONN
4
Z 2 1 14
BAT LED 3G LED
C
Q 9
C
B 3. 3 V S _ F P L8 3 .3 V S
[ 26 ] LE D _B A T _ C H G# L E D _ B A T _ F U L L# [ 26 ] 3 G _E N [ 1 9, 2 6 ] J _ FP1 H C B 1 0 05 K F -1 2 1T 2 0
DT C1 1 4 E UA 1
2 U S B _ P P 11 _ F P [1 4 ] C 88
E
3 U S B _ P N 1 1 _F P [ 14 ]
4 0 . 1 U _ 16 V _ 0 4
85 2 01 -0 40 5 1
J_FP1
4 1
USB PORT US B V C C0 1 US B _ V CC0 1 _ 1

5V U S B V CC0 1
60 mil
60mil U2 1 60mil L3 6 H C B 16 0 8K F -1 2 1T 2 5
4 1
V IN V OU T C5 0 8 C5 2 9
C 49 3
1 U _ 1 0V _ 0 6
3
V IN V OU T
5
2
C 4 86
0. 1 U _ 1 6V _ 0 4
C 50 3
0 . 1 U _ 16 V _ 0 4
C4 9 5
*1 0 U _ 1 0V _ 0 8
1 00 U _ 6 . 3V _B 2 0 . 1U _ 16 V _ 04 CLICK CONN
GN D
R T 9 70 1 -C P L J _ US B 2
L4 1 1
V+
*W C M 20 1 2F 2S -1 6 1T 0 3
1 2 US B _ P N1 _ R 2
[ 1 4] US B _ P N1 D A TA _ L
4 3 U S B _ P P 1 _R 3 5 VS
[ 1 4] US B _ P P 1 D A TA _ H
G ND 1
G ND2
4
GN D
C 1 07 7 7-1 0 4 A 3-L R7 0 R 71
6
R2 9 9 US B V C C0 1 US B _ V CC0 1 _ 0 J _ TP 1 10 K _ 04 1 0 K _ 04
L ay out n ote : 1 00 K _ 1 %_ 0 4 60 mil J_TP1
L3 5 H C B 16 0 8K F -1 2 1T 2 5 1
Place under the common [1 4 ] U S B _O C # 0 1 2 T P _D A T A [ 2 6]
4
bead body and same as 3 T P _C L K [ 2 6]
R3 0 0 C4 4 4 C4 4 7
2 00 K _ 1 %_ 0 4 4 C1 4 6 C 1 58 C 15 9 C 15 7
USB trace requirment
1
1 00 U _ 6 . 3V _B 2 0 . 1U _ 16 V _ 04 8 5 20 1 -0 40 5 1
1 U _ 10 V _ 06 47 P _ 50 V _ 0 4 4 7 P _ 50 V _ 04 * 10 U _ 1 0V _ 0 8
J _ US B 1
L3 4 1
V+
*W C M 20 1 2F 2S -1 6 1T 0 3
1 2 US B _ P N0 _ R 2
[ 1 4] US B _ P N0 D A TA _ L
4 3 U S B _ P P 0 _R 3
[ 1 4] US B _ P P 0 D A TA _ H
G ND 1
G ND2
4
GN D
C 1 07 7 7-1 0 4 A 3-L
6
[ 13 , 2 6 . . 30 , 3 2] V D D 3
[ 1 2 , 13 , 1 6, 19 , 2 4, 2 5 , 27 ] 5V S
[ 16 , 1 9, 2 8 . . 31 ] 5V
[ 5 , 8 . . 1 6, 1 8 . . 20 , 2 2 . . 27 , 3 1] 3 . 3V S
B - 22 LED, FAN, TP, FP, USB

Schematic Diagrams
JMB385 Card Reader
JMB385 CARD READER

3. 3V S
02/12 3 .3 V S _ CA R D
3 .3 V S _ CA R D
R4 0 3 0 _0 6
R3 3 2 4 . 7K _ 0 4 S D _ CD# 40mil 40mil
R3 1 0 4 . 7K _ 0 4 M S _ INS# 3 .3 V S_ CAR D
V C C_ CA R D
DV1 .8 V
M D I O 12
R3 3 1 1 0K _ 0 4 SD W P#
R3 4 3 1 0K _ 0 4 M D I O 13
C5 7 3
0 . 1U _ 16 V _ 0 4
36
35
34
33
32
31
30
29
28
27
26
25
3 .3 V S _ CA R D U 27
M D I O8
M DIO 9
M D I O1 0
M D I O1 2
N C
G ND
GN D
G ND
T AV3 3
M D I O 11
NC
NC
R3 3 5 1 0K _ 0 4 M DIO 7
R3 5 3 2 00 K _ 0 4 M D I O 12 37 24
38 DV 18 GN D 23 M D I O 13
3 .3 V S _ CA R D PC IE S _ E N M D I O 13
R3 3 9 2 00 K _ 0 4 M D I O 14 39 22 M D I O 14
M DIO 7 40 PC IE S M D I O 14 21
MD I O7 C R _L E D N
SD W P# 41 20 3 . 3 V S _C A R D
S D / MS C L K R 38 4 2 2 _ 04 S D / MS C L K _R 4 2 MD I O6 D V 33 19
MD I O5 RE G _ CT RL
S D CM D/M S B S 4 3 18 D V1 .8 V
44 MD I O4 JMB385 D V 18 17
Sheet 22 of 40
3 .3 VS _ CA R D DV 33 C R1 _ P CT L N V C C_ CA R D
S D / MS _ D 3 45 16 S D _ CD# C5 8 3
S D / MS _ D 2 46 MD I O3 CR1 _ CD 0 N 15 M S _ INS # C 59 2
HIGH LOW C5 6 1 S D / MS _ D 1 47
MD I O2 CR1 _ CD 1 N
14 0 . 1U _ 16 V _ 0 4
S D / MS _ D 0 48 MD I O1 S E ECL K 13 0 . 1 U _ 1 6 V _0 4
JMB385 Card Reader

MD I O0 S E EDA T
A P CL K P
APR EXT
0 . 1U _ 16 V _ 0 4
A P C LK N
MDIO7 On Borad Add-in Card
X RS T N
APVD D
A P GN D
APR XN
A P RX P
AP TXP
XT EST
APT XN
A P V 18
CR1_PCTLN CR1_PCTLN Layout Note:
J MB 38 5 -L GE Z 0 B
High Low
10
11
12
MDIO1 2 Must > 30mil
1
2
3
4
5
6
7
8
9
Active Active
CR1_LEDN CR1_LEDN C 54 9 0 . 1U _ 10 V _ X 7R _ 04
[ 1 4 , 19 , 2 0 , 23 , 2 6 ] B U F _ P L T_ R S T# P C I E _R X P 5_ C A R D [1 4 ]
C 55 0 0 . 1U _ 10 V _ X 7R _ 04
High Low P C I E _R X N 5 _C A R D [1 4 ]
MDIO1 4
Active Active [ 1 8 ] C L K _P C I E _ J M3 8 0# D V1 .8 V
[ 18 ] C L K _ P C I E _J M3 8 0
P C I E _ TX N 5_ C A R D [1 4 ]
DV 1 .8 V P C I E _ TX P 5 _ C A R D [ 1 4]
R 32 7 8 . 2K _ 1 % _0 4
3. 3 V S _ C A R D V C C_ CA R D
S D / MS C L K
C 59 0 C 59 1 C5 2 2 C5 1 7 C5 2 4
1 0 U _ 1 0V _0 8 0 . 1 U _ 1 6 V _0 4 1 0P _ 5 0 V _0 4 0 . 1U _ 16 V _ 0 4 0 . 1U _ 16 V _ 0 4
Near Cardreader CONN
Layout note: Layout note: Layout note:

M720T Card Reader M730T Card Reader Ve ry cl os ed b et wee n
pi n 19 an d pi n 20
V er y clo se d to pi n 5( Tr ac e w id th /l eng th :
2 0m il / < 12 0m il )
Ve ry c los ed b et wee n
p in 1 0
Connector Connector 3 .3 V S _ CA R D DV 1 .8 V
J _ C A R D -R _7 3
J _ C A R D -R _7 2 S D_ C D# P1
S D_ C D# P1 S D/M S _ D2 P2 CD _ S D
S D/M S _ D2 P2 CD _ S D D A T2 _ S D
D A T2 _ S D S D/M S _ D3 P3 C5 5 7 C6 0 5 C6 0 4 C5 5 2 C5 5 3 C5 5 1
S D/M S _ D3 P3 S D C MD / MS B S P4 C D / D A T3 _ S D
S D C MD / MS B S P4 C D / D A T3 _ S D CM D_ SD
CM D_ S D P5 0 . 1U _ 16 V _ 0 4 0 . 1U _ 16 V _ 0 4 0 . 1U _ 16 V _ 0 4 1 00 0 P _ 50 V _ X 7R _ 04 1 0U _1 0 V _ 0 8 0 . 1U _ 16 V _ 0 4
P5 P6 VSS_ SD
P6 VSS_ SD V CC _ CA R D V D D_ SD
V CC _ CA R D V D D_ S D S D/M S CL K P7
S D/M S CL K P7 P8 CL K_ SD
P8 CL K _ S D VSS_ SD
VSS_ SD S D/M S _ D0 P9
S D/M S _ D0 P9 S D/M S _ D1 P1 0 D A T0 _ S D
S D/M S _ D1 P1 0 D A T0 _ S D D A T1 _ S D
D A T1 _ S D S DW P # P1 1
S DW P # P1 1 P1 2 W P_ SD
P1 2 W P_ SD VSS_ M S
VSS_ M S V CC _ CA R D P1 3
P1 3 S D/M S CL K P1 4 V C C _ MS
V CC _ CA R D V C C _ MS S C LK _ M S
S D/M S CL K P1 4 S D/M S _ D3 P1 5
S D/M S _ D3 P1 5 S C LK _ M S D A T3 _ MS
MS _ I N S # P1 6
MS _ I N S # P1 6 D A T3 _ MS I N S _M S
I N S _M S S D/M S _ D2 P1 7
S D/M S _ D2 P1 7 S D/M S _ D0 P1 8 D A T2 _ MS
S D/M S _ D0 P1 8 D A T2 _ MS S D I O/ D A T0 _ MS
S D I O/ D A T0 _ MS S D/M S _ D1 P1 9
S D/M S _ D1 P1 9 S D C MD / MS B S P2 0 D A T1 _ MS P2 2
S D C MD / MS B S P2 0 D A T1 _ MS P2 2 B S _ MS GN D
B S _ MS GN D P 2 3 P2 1 P2 3
P2 1 VSS_ M S GN D
VSS_ M S GN D
* MD R 0 1 9-C 0 -00 1 0 (R e v e rse )
M D R 01 9 -C 0 -0 0 10 (R ev ers e )
[ 5 , 8. . 16 , 1 8 . . 21 , 2 3 . . 2 7, 3 1 ] 3 .3 VS
JMB385 Card Reader B - 23

Schematic Diagrams
PCI-E LAN RTL8111C

LA N _ V D D 3
R4 0 0 0_ 0 4
60mil M A 1 /E E DI R4 5 3. 6 K _ 0 6
60mil Q2 8 *A O 3 40 9
S D E N _ LA N 1 2 R2 1 7 0_ 0 4
3. 3V LA N _ V D D 3
R4 1 2 C 64 4 R 4 13 R 21 7
[1 5 ] L A N _P W R
G
G
Q2 9 *3 3 0K _0 4 * 0. 1 U _1 6 V _ 04 * 10 0 K _ 0 4 RTL 81 11 C S tu ff
*2 N 70 0 2 W
S D RTL 81 02 E U ns tu ff
R4 1 4
* 10 0 K _ 04 L A N_ V D D3
L1 9 U 2
EEC S 1 8
MA 2 / E E S K 2 CS VCC 7
RTL 81 11 C G ST 50 09L F / LG -24 13 S- 1 SK NC
LA N _ V D D 3 MA 1 / E E D I 3 6
DI OR G
20mils 20mils RTL 81 02 E L F- H6 442 S- 1 MA 0 / E E D O 4 5
DO GN D C3 7 3
1. 2V _ L A N
H T9 3 L C 4 6 -A 18 P B
C 50 C3 5 4 C3 8 5 C 84 C3 8 8 C3 8 6 C3 7 8 C5 1 0 . 1U _ 16 V _ 0 4
* 10 U _1 0 V _ 08 0. 1 U _1 6 V _ 04 0 . 1 U _ 16 V _ 0 4 0 . 1 U _ 1 6 V _0 4 0. 1 U _1 6 V _ 04 0 . 1U _ 16 V _ 0 4 0. 1U _1 6 V _ 04 0. 1 U _1 6 V _ 04 L19
V _D A C 1 24 MC T 1
T CT 1 MC T 1
MD I O 0 + 2 23 MX 1 +
MD I O 0 - 3 T D1 + M X1 + 22 MX 1 -
L A N _V D D 3 V _D A C T D1 - MX 1 -
L3 L A N_ A V D D3 4 21 MC T 2
0_ 0 4 MD I O 1 + 5 T CT 2 MC T 2 20 MX 2 + J_ R J-4 5
15mils T D2 + M X2 +
C3 7 9 C3 8 7 C 3 64 C 3 75 MD I O 1 - 6 19 MX 2 - L MX 1+ 1 G ND 1
V _D A C 7 T D2 - MX 2 - 18 MC T 3 L MX 1- 2 D A+ s hi e l d G ND 2
C3 7 0 C3 5 9 0 . 1U _ 16 V _ 0 4 0. 1U _1 6 V _ 04 0. 1 U _1 6 V _ 04 0 . 1 U _ 1 6 V _0 4 MD I O 2 + 8 T CT 3 MC T 3 17 MX 3 + L MX 2+ 3 D A- s hi e l d
T D3 + M X3 + D B+
Sheet 23 of 40
MD I O 2 - 9 16 MX 3 - L MX 2- 6
0 . 1 U _ 16 V _ 0 4 0 . 1U _ 16 V _ 0 4 V _D A C 10 T D3 - MX 3 - 15 MC T 4 D B-
1 . 2 V _ LA N MD I O 3 + 11 T CT 4 MC T 4 14 MX 4 +
MD I O 3 - 12 T D4 + M X4 + 13 MX 4 - L MX 3+ 4
T D4 - MX 4 - D C+
PCI-E LAN
L MX 3- 5
L MX 4+ 7 D C-
D D+
L53 G S T 50 0 9 LF L MX 4- 8
53
37
52
49
43
38
32
21
59
46
16
D D-
2
0 _ 04 U1 4
RTL8111C
C 1 0 09 1 -1 08 A 4
D V DD 1 2
20mils
A VD D3 3
VD D3 3
VD D3 3
DVD D1 2
DV DD1 2
A V D D 3 3/ N C
D V DD1 2 /NC
D V D D 1 2/ N C
DV DD1 2 /NC
V D D 33
V D D 33
C5 3 C 6 45 C3 5 5 C 35 6 C 3 57
V _D A C C2 8 4 0 . 0 1 U _ 16 V _ X 7R _ 04
*1 0 U _ 1 0 V _0 8 0 . 1 U _ 1 6 V _0 4 0. 1U _1 6 V _ 04 0 . 1 U _ 1 6V _ 0 4 0 . 1 U _ 1 6 V _0 4 44 EEC S L67
E ECS V _D A C
8 48 M A 2/ E E S K C2 8 5 0 . 0 1 U _ 16 V _ X 7R _ 04 *W C M2 0 12 F 2 S -1 61 T 0 3
11 AV D D1 2 EESK 47 M A 1/ E E D I M X1 + 4 3 L MX 1 +
A V D D 1 2/ N C E E DI/A U X
14 45 M A 0/ E E D O
58 A V D D 1 2/ N C E EDO M X1 - 1 2 L MX 1 -
A V D D 1 2/ D V D D 1 2 50 V _D A C C2 8 6 0 . 0 1 U _ 16 V _ X 7R _ 04
22 GP I 51
L A N_ E V DD 1 2 28 EV D D1 2
EV D D1 2
P CI -E LA N GP O V _D A C C2 8 7 0 . 0 1 U _ 16 V _ X 7R _ 04
23 3 M D I O 0+ L68
[ 1 4 ] P C I E _T X P 4 _L A N HS I P MD I P 0
24 4 M D I O 0- *W C M2 0 12 F 2 S -1 61 T 0 3
[ 1 4 ] P C I E _ TX N 4_ L A N HS I N M DIN 0 M X2 + 4 3 L MX 2 +
[1 4 ] P C I E _ R X P 4 _L A N C3 7 4 0 . 1 U _ 1 0V _ X 7 R _ 0 4 P C I E _ R X P 4 _ LA N _ C 29 6 M D I O 1+ C2 86 ,C 28 7
C3 7 7 0 . 1 U _ 1 0V _ X 7 R _ 0 4 P CIE _ RX N4 _ L A N_ C 30 HS O P MD I P 1 7 M D I O 1- M X2 - 1 2 L MX 2 -
[ 14 ] P C I E _ R X N 4_ L A N HS O N M DIN 1
R TL8 11 1C S tu ff
26 9 M D I O 2+
[ 18 ] C L K _ P C I E _ G LA N RE F CL K _ P MD I P 2 / N C
[ 1 8 ] C L K _P C I E _ GL A N # 27 10 M D I O 2- R TL8 10 2E U ns tu ff
RE F CL K _ N GND MD I N 2 / N C
02/22
[1 8 ] L A N _ C LK R E Q# 33 12 M D I O 3+ L69
20 C L K R E Q# MD I P 3 / N C 13 M D I O 3- *W C M2 0 12 F 2 S -1 61 T 0 3
[ 1 4 , 1 9, 2 0 , 2 2, 26 ] B U F _ P L T_ R S T# P E R S T# MD I N 3 / N C M X3 + L MX 3 +
6 0mi ls a nd le ng th < 20 0m il 4 3
57 3 .3 V S
L4 LE D 0 56 M X3 - 1 2 L MX 3 -
60 mi ls a nd le ng th < 20 0mi l
S W F 2 52 0 C F -4 R 7M -M LE D 1 55 R2 2 3 * 1K _0 4
1. 2V _ L A N
1
S RO UT 1 2 /V CT RL 1 2 A
LE D 2
LE D 3
54 La yo ut n ot e:
R2 2 4 * 1 0m i _l s h ort Place under the common
5 SUS B# [ 1 7, 2 0 , 2 6, 2 7 , 2 9]
1 . 2 V _L A N F B 1 2 / A V D D 12 bead body and same as
C 49 C6 4 0 R2 2 5 * 15 K _ 0 4 L70
C3 5 8 36 I S OL A T E # LAN trace requirment *W C M2 0 12 F 2 S -1 61 T 0 3
2 2 U _ 6 . 3 V _X 5 R _ 0 8 0. 1U _1 6 V _ 04
RT L8 111 C/ I S OL A T E # M X4 + 4 3 L MX 4 +
0 . 1U _ 16 V _ 0 4 RT L8 102 E L ANW AK E#
19
P CIE _ W A K E # [ 15 , 1 9 , 20 ] M X4 - L MX 4 -
1 2
61
CK T A L 2
C4 9 L4
1
63
V D D S R / V C T R L 1 2D
RT L81 11 C Stu ff SW F2 520 CF -4 R7 M-M X1
E N _ LA N 1 2 62
N C/DV DD1 2
E NS R/NC 2 5 MH z
RT L81 02 E Uns tu ff 0_ 08 05 R17 8, R1 79
64 60
2
RS E T CK T A L 1 M CT 1 R 17 5 7 5_ 0 4
EG ND
4 0m il s and l en gth < 2 00m il RT L81 11 C St uf f
E GN D
C3 6 8 C 3 65
N C
N C
N C
N C
NC
NC
NC
NC
R 40 1 0 _0 4 R 2 15 RT L81 02 E Un st uf f M CT 2 R 17 6 7 5_ 0 4
LA N _ V D D 3
R T L8 1 11 C -V B -GR 22 P _ 5 0V _ 0 4 2 2 P _ 50 V _ 0 4
R 40 4 *0 _ 0 4 2 . 4 9 K _ 1% _ 0 4
42
40
35
18
15
31
25
41
39
34
17
1 . 2V _ L A N
L5 C3 67 C 61 M CT 3 R 17 8 7 5_ 0 4
C6 7 C3 6 0
R TL 81 11C HC B1 005 KF -1 21T 20 S tu ff Un st uff M CT 4 R 17 9 7 5_ 0 4
2 2U _ 6. 3 V _ X 5R _ 08 0. 1 U _1 6 V _ 04 Layout note:
R TL 81 02E 0_ 04 02 U ns tu ff St uf f
C358 must close C 2 92
RT L81 11 C R4 01
to U14 pin5 R 4 02 * 0_ 0 4 10 0 0P _2 K V _ 1 2
1 . 2 V _ LA N 1 . 2 V _ LA N L5 L A N_ E V D D1 2
RT L81 02 E R4 04 R 40 2, C6 41 C6 4 1 H C B 1 0 0 5K F - 12 1 T2 0 15mils
RT L8 11 1C Un stu ff *0 . 1 U _ 1 6 V _0 4
C 37 1 C3 6 7 C6 1
RT L8 10 2E St uff
0 . 1 U _ 1 6V _ 0 4 0 . 1 U _ 16 V _ 0 4 *4 . 7 U _ 6 . 3V _X 5 R _ 0 6
[ 5, 8 . . 1 6 , 1 8. . 2 2 , 2 4. . 2 7 , 3 1] 3 . 3V S
[ 2, 1 2 . . 1 7, 1 9 , 2 0, 29 , 3 0 ] 3 . 3 V
B - 24 PCI-E LAN RTL8111C

Schematic Diagrams
Audio Codec ALC662
Layout Note: Layout Note:

Clo se to co dec p in 25 C los e t o cod ec pi n 3 8
3 . 3V S 3. 3 V S _ A U D 5 V S _A U D 5V S _ A U D L45 5 VS
H C B 1 00 5 K F -1 21 T 20
L 38 H C B 10 0 5 K F -12 1 T2 0
C2 5 9 C 5 75 C 56 7 C5 7 0 C 5 76
L16
C 5 06 C5 1 4 C 2 36 C 23 7 0. 1 U _1 6 V _0 4 1 0 U _ 1 0V _ 0 8 0 . 1 U _ 1 6V _ 0 4 1 0U _ 10 V _ 08 H C B 1 60 8 K F -1 21 T 25 1 U _1 0 V _0 6
0. 1 U _ 1 6 V _0 4 1 0U _1 0 V _0 8 0. 1 U _ 1 6V _0 4 0 . 1 U _ 1 6V _ 0 4
A UDG A U DG A U DG A UD G
A U DG
Layout Note:
25
38
4
7
1
9
U 25
C5 6 6 Close to codec
D VSS2
D VDD1
DV DD 2
A V D D1
DV SS 1
A V DD2
2 1 0 U _ 1 0V _ 0 8
[2 5 ] C O D E C _E A P D #
3
GP I O 0
GP I O 1 VR EF
27 Z2412 F OR M7 20 T
C 5 30 2 2 P _5 0 V _ 04
5 28 M I C 1 -V R E F O -L A UDG J _ S PDIF _ 7 2
[ 1 3] A U D _A Z _ S D O U T 6 S D A T A -OU T MI C 1 -V R E F O -L 32 M I C 1 -V R E F O -R Z2424 5
[ 1 3] A U D _A Z _ B I T C L K A Z _ S DIN0 _ R B I T -C L K MI C 1-V R E F O-R
[1 3 ] A Z _ S DIN 0 R3 1 2 3 3 _0 4 8 R 38 5 *0 _0 4 S P D I F O _7 3 Z2425 4
10 S D A T A -I N 39 3 R
[ 1 3] A U D _A Z _ S Y N C 11 SYN C DIG ITA L S U R R -O U T -L 41
[ 1 3 , 25 ] A U D _ A Z _ R S T # RE S E T # S U R R -OU T -R
S P DIF O L5 4 F C M1 0 05 K F -1 02 T 02 Z2426 2
E A P D _ MO D E 47 30 M I C 2 -V R E F O Z2427 6 L
EAPD M I C 2 -V R E F O
31 C5 7 4 1
L I N E 2 -V R E F O
Sheet 24 of 40
S P DIF O 48 0. 0 1 U _ 1 6V _ X 7R _0 4 R3 3 7 C5 8 0 C 1 2 10 3 -1 06 0 9-L
S P DIF O 35
BEEP Z 2 4 04 1 2 F R ON T-O U T -L F R ON T-L [2 5 ]
R 1 17 4 7K _ 0 4 Z 2 40 3
PCBE EP F R O N T -OU T -R
36 F R ON T-R [ 2 5] 2 20 _ 04 10 0 0 P _5 0 V _X 7 R _ 0 4 SPDIF O UT
Audio Codec
R 1 16 4 . 7K _ 0 4 C 5 23 1 U _ 10 V _ 06 14
A UDG L I N E 2 -L 15
H P _O U T -L [ 2 5] BLACK
C 23 8 1 0 0P _ 5 0V _ 0 4 JD _S E N S E 1 13 L I N E 2 -R H P _O U T -R [ 25 ]
S e ns e A (JD 1 )
JD _S E N S E 2 34 43
ALC662
MI C _S E N S E R 3 23 2 0K _ 1 % _0 4 S e ns e B (JD 2 ) CEN 44 MI C _ S E N S E
37 LFE
N.C .
HP _ S E NS E R 3 20 3 9. 2 K _ 1 %_ 0 4 29 45 R 38 6 *0 _0 4 MI C 1-R _7 3 J _ MI C _7 2
N.C . ANALOG N.C .
N.C .
46 5
C5 5 6 4 . 7U _6 . 3 V _ X5 R _ 0 6 Z 2 40 8 16 4
I N T _ MI C C5 6 0 4 . 7U _6 . 3 V _ X5 R _ 0 6 Z 2 40 9 17 MI C 2-L 33 MI C 1 -R L48 F C M1 00 5 K F -1 21 T 03 Z2428 3 R
MI C 2-R N.C .
18 40 Z2421 R1 4 2 2 0 K _1 % _ 04 MI C 1 -L L47 F C M1 00 5 K F -1 21 T 03 Z2429 2
19 C D -L J DR E F Z2430 6 L
C 56 3 20 C D -GN D 23 1
C D -R L I N E 1 -L
4 . 7 U _ 6. 3 V _ X5 R _0 6 24 AUD G R 38 7 *0 _0 4 MI C 1-L _ 73 C5 7 8 C5 7 9 C 1 2 10 3 -D 0 6 09 -L
L I N E 1 -R
AVSS1
AVSS2
MI C 1-L R 3 29 1 K _0 4 Z 2 41 0 21
Z 2 41 1 MI C 1-L
MI C 1-R R 3 30 1 K _0 4 22
MI C 1-R
6 80 P _ 50 V _ X 7R _0 4 68 0 P _ 50 V _ X7 R _ 0 4 MIC IN
C 56 5 A L C 6 6 2-G R
PINK
26
4 . 7 U _ 6. 3 V _ X5 R _0 6
42
HP_ SENSE
A UD G
R 38 8 *0 _0 4 H P -R _7 3 J _ HP_ 7 2
Lay ou t N ot e: 5
4
Cod ec pi n 1 ~ 11 an d p in 47 ~ 48 H P -R L46 F C M1 00 5 K F -1 21 T 03 3 R
[ 2 5] H P -R
are D igi tal s ign als . H P -L L50 F C M1 00 5 K F -1 21 T 03 2
[ 25 ] H P -L 6 L
The o the rs ar e a nal og si gna ls.
[2 5 ] HP _ P L UG H P _P L U G 1
C 1 2 10 3 -6 06 0 9-L
R 38 9 *0 _0 4 H P -L _ 73
C5 8 8 C5 7 7 HEADPHO NE
For M730T 6 80 P _ 50 V _ X 7R _0 4 68 0 P _ 50 V _ X7 R _ 0 4
GREEN
R385,R386,R387,R388,
R389
C2 2 7 1 U _ 10 V _ 0 6 B EEP
[2 6 ] K B C _B E E P
C2 2 8 1 U _ 10 V _ 0 6
[1 5 ] IC H_ S PK R
2 3
4
FO R M7 30T Layout Note: M I C 1 -V R E F O -L MI C 1-V R E F O-R MI C 2 -V R E F O J_I NT MIC 1
1
Ve ry clo se to Au dio C ode c 2 1

6 5
J_ A U D _7 3 R3 3 3 R 33 4 R7 2
1 S P D I F O_ 7 3 2 . 2K _ 0 4 2 . 2 K _0 4 4 . 7K _ 0 4
2
J _I N T MI C 1
3 MI C _ S E N S E Z 24 0 8 C5 4 8 0. 1U _1 6 V _0 4 MI C 1 -L MI C 1 -R I N T _ MI C
4 MI C 1 -R _ 7 3 Z 24 0 9 C5 5 5 0. 1U _1 6 V _0 4 1
5 2
MI C 1 -L _7 3 C5 6 8 C 56 9 C1 5 5
6 Z 24 1 0 C5 5 8 0. 1U _1 6 V _0 4 8 82 6 6 -02 0 01
7
HP _ S E NS E Z 24 1 1 C5 6 2 0. 1U _1 6 V _0 4 6 80 P _ 50 V _ X7 R _0 4 6 8 0P _ 5 0V _ X 7 R _ 04 6 80 P _ 50 V _ X7 R _0 4 P C B F o o t pri n t = 8 8 26 6 -2 L
8 H P -R _ 7 3
9 H P -L _7 3
10
H P _ P LU G A UD G AUD G AU DG
11
12
*8 7 15 1 -12 0 71 G
[ 12 , 1 3, 1 6 , 19 , 2 1 , 25 , 2 7] 5V S
[ 5 , 8. . 1 6 , 18 . . 2 3, 2 5 . . 2 7, 3 1 ] 3 . 3V S
Audio Codec ALC662 B - 25

Schematic Diagrams
Audio AMP2056
5 VS
C 642
*0 . 1 U _ 1 6 V _ 0 4
5
5V S
[2 4 ] CO DE C_ E A P D # 1
4
2
U2 8 C 518 5 VS_ AM P
*7 4 A H C 1 G0 8 G W
* 0 . 1 U _ 1 6 V _ 04 R 13 7
30mils
3
Low mute!
5
1 0 0K _0 4
R3 1 4 0_ 0 4 S Y S M U T E A MP # 1 C 245 C2 5 6 C2 5 8 C5 2 0
[ 2 6] K B C _ MU T E #
4 MU T E A M P #
R3 1 5 *0 _ 04 2 * 0 . 1 U _ 1 6 V _ 04 0. 1 U _ 16 V _ 0 4 0. 1 U _ 16 V _ 0 4 0. 1U _ 1 6V _0 4
[1 3 ] S B _ MU T E # U 24
7 4 A H C 1 G 0 8G W C5 3 9 0 .1 U_ 1 6 V _ 0 4 Z 25 2 0
[1 3 ,2 4 ] A U D _ A Z _R S T #
3
A UD G AU DG
28
26
10
20
1
U2 6
R1 4 4 3. 0 1 K _ 1 % _ 04 C 2 62 4 . 7 U _ 6. 3 V _ X 5 R _ 0 6 Z2505 3
[2 4 ] F R O N T -R R _ I N _ A MP
VD D
BE EP
SD #
PVD D
P VDD
22 S PKO UT R +
R _ OU T + S P K O U TR + [1 9 ]
[2 4 ] F R O N T -L R1 4 1 3. 0 1 K _ 1 % _ 04 C 2 57 4 . 7 U _ 6. 3 V _ X 5 R _ 0 6 Z2506 5
L _I N _ A M P 21 S PKO UT R -
R _ OU T- S P K O U TR - [ 1 9]
C 2 51 4 . 7 U _ 6. 3 V _ X 5 R _ 0 6 R 13 4 3 9 K _ 04 Z2509 4
[2 4 ] H P _ O U T -R R_ IN _ HP 8 S PKO UT L +
C 2 55 4 . 7 U _ 6. 3 V _ X 5 R _ 0 6 R 14 0 3 9 K _ 04 Z2510 6 L _ OU T +
[2 4 ] H P _ O U T -L L _I N _ H P
9 S PKO UT L -
L _ OU T-
AP A205 6A
Sheet 25 of 40
M720T M730T 5V S R3 2 1 10 0 K _ 0 4 Z 2 5 12 R 3 22 1 0 K_ 0 4 Z2513 27
A MP _E N # 17 R_ H P_ O R3 9 0 270_04
R_ O UT _ HP H P -R [2 4 ]
C6 3 6 24
R144 3.01K_1%_04 6.2K_1%_04 HP_ E N
Audio AMP2056
R1 2 7 18 L _ HP _ O R3 9 1 270_04
L _ O UT _ HP H P -L [2 4 ]
0. 01 U _ 16 V _ X 7 R _ 0 4 Near CP+ and CP-
1 0K _0 4 12
R141 3.01K_1%_04 5.6K_04 CP+
C
C5 7 1 11
CVD D 5V S _ A MP
B D03
[ 2 4] H P _ P L UG
BCN 2 . 2 U _ 1 6 V _ X5 R _ 06 14 19 C 2 61 C6 3 7
Q 5 CP- HVD D
D T C 11 4 E U A 15 0 .1 U_ 1 6 V _ 0 4 1U _ 1 0V _0 6
16 CVS S
P GN D
CG ND
PG ND
E
B IAS
HVS S
GN D
G ND
C5 7 2 A UD G AU DG
D3 2 A S D7 5 1 V A P A 2 0 5 6A
3 .3 VS _ AM P L 5 5
29
13
23
25
MU T E A M P # C A 2 . 2 U _ 1 6 V _ X5 R _ 06
7
H C B 1 0 0 5 K F -1 2 1 T2 0
Z 2 5 19
3 .3 VS
D03 D03 BCN
C 252 C2 5 3 C2 6 0
BCN ? ? APA2057A
A U DG 1 U _ 10 V _ 0 6 0 . 1 U _ 1 6 V _ 04 0 . 1 U _ 1 6 V _ 04
A U DG A U DG A U DG
Z 2 5 09 C6 2 0 6 8P _5 0 V _ 0 4 R _ HP _ O
Z 2 5 10 C6 2 1 6 8P _5 0 V _ 0 4 L _ H P _O
For M720T For M730T 5 VS L37

H C B 1 0 0 5 K F -1 2 1T 2 0
5V S _ A MP
L1 J_SPK*_* L56 C 538 C 51 5 C 51 6 C 25 4 C2 6 3

F C M 1 00 5 K F - 12 1 T 0 3 J _S P K L _ 72 * F C M 1 0 05 K F -1 21 T 0 3 J_ S P K R _ 7 3
SPKO UT L + S P K O U TL + _ R 2 1 S P K O UT R+ S P K O U T R +_ R 1 0 . 1 U _1 0 V _ X 7 R _ 0 4 *1 0 U _1 0 V _ 0 8 *1 0 U _1 0 V _ 0 8 1 U_ 1 0 V_ 0 6 *0 . 1 U _ 1 6 V _ 0 4
SPKO UT L - S P K O U TL -_ R 1 S P K O UT R- S P K O U T R -_ R 1 1
2 2
L2 C1 0 C9 8 8 2 66 -0 2 0 0 1_ R L57 C 6 12 C 613 *8 8 2 6 6- 02 0 0 1 _R
F C M 1 00 5 K F - 12 1 T 0 3 * F C M 1 0 05 K F -1 21 T 0 3 AU DG
18 0 P _ 5 0 V _ 04 18 0 P _ 5 0 V _ 0 4 P C B F o o t p ri nt = 88 2 6 6 -02 R * 1 80 P _ 5 0 V _ 0 4 * 1 80 P _ 5 0 V _ 0 4 P C B F o o t p rin t = 8 8 2 6 6-0 2 R
L58
* F C M 1 0 05 K F -1 21 T 0 3 J_ S P K L _7 3
S P K OU T L+ S P K O UT L + _ R1
S P K OU T L- S P K O U T L -_ R 1 1
2
L59 C 6 14 C 615 *8 8 2 6 6- 02 0 0 1 _R
* F C M 1 0 05 K F -1 21 T 0 3
* 1 80 P _ 5 0 V _ 0 4 * 1 80 P _ 5 0 V _ 0 4 P C B F o o t p rin t = 8 8 2 6 6-0 2 R
[ 5, 8 . . 1 6 , 1 8 . . 2 4 , 2 6, 2 7 , 3 1 ] 3. 3 V S
[ 1 2, 1 3 , 1 6 , 1 9 , 21 , 2 4 , 2 7 ] 5 V S
B - 26 Audio AMP2056
Schematic Diagrams
KBC-ITE IT8512E
K B C_ A V DD L 10 R2 9 4 10 K _ 04 W D T _E N
V D D3
H C B 1 0 0 5K F -1 2 1 T2 0
VDD 3 V DD 3 V DD3
R2 9 2 R 67 W D _D I S A B L E
C4 7 0 C 1 86 C 1 78 C 2 20 C1 8 8 C1 8 5 C 18 0
1 0K _ 0 4 1 0 0 K _0 4 J1
10 U _1 0 V _0 8 0. 1 U _ 1 6 V _0 4 0. 1 U _ 1 6 V _0 4 0 . 1 U _ 1 6V _ 0 4 0. 1 U _1 6 V _0 4 *0 . 1 U _ 1 6V _ 0 4 * 0. 1 U _1 6 V _0 4 *OP E N _ 35 m li
R2 8 8 10 K _ 04 W D _D I S A B L E R 2 90
G
K B C _ A GN D K B C _ A GN D U 20 1 0 0 K _0 4
Z 2 60 8 3
3 . 3V S M R# 1 Z2609S D K B C_ W RE S E T # 35mil
R E S E T#
C2 0 3
0. 1 U _1 6 V _0 4
FOR M720T FOR M730T C4 7 6
5
2
VC C
W DI
4 Q2 1
2 N 7 0 02 W
C 4 89
G ND 25mil
121
11 4
12 7
J_ K B _ 7 2 J _ K B _7 3 1 U _1 0 V _0 6
11
26
50
92
74
3
U4 8 5 20 2 -24 0 5 1 *8 52 0 2 -24 0 51 0 . 1 U _ 16 V _ 0 4 A T 35 1 0 I GV -2 . 9 3-C -C -T 1 5mil
3 IN1
VST B Y
VC C
VST BY
VST BY
VST BY
VST BY
VST BY
VBAT
A V CC
[ 1 3 , 19 ] L P C _A D 0 10 58 K B -S I 0 4 K B -S I 0 4
9 L AD 0 K S I 0 / S TB # 59 K B -S I 1 5 K B -S I 1 5
[ 1 3 , 19 ] L P C _A D 1 L AD 1 K S I1 /A F D #
[ 1 3 , 19 ] L P C _A D 2 8 60 K B -S I 2 6 K B -S I 2 6
7 L AD 2 K S I 2/ I N I T # 61 K B -S I 3 8 K B -S I 3 8
[ 1 3 , 19 ] L P C _A D 3 P C LK _ K B C 13 L AD 3 K S I 3/ S L I N # 62 K B -S I 4 11 K B -S I 4 11
[ 1 8] P C L K _ K B C L PC CL K KS I4 MODEL ID SELECTOR
[ 1 3, 1 9 ] L P C _ F R A ME # 6 63 K B -S I 5 12 K B -S I 5 12
5 L F R A ME # KS I5 64 K B -S I 6 14 K B -S I 6 14
[ 15 , 1 9] S E R I R Q S E RIRQ LPC K/B MATRIX KS I6
[ 1 4, 1 9 , 2 0, 2 2 , 23 ] B U F _ P L T_ R S T # 22 65 K B -S I 7 15 K B -S I 7 15 R 276 R2 85 VO LTA GE M ODE L_ ID
L P C R S T #/ W U I 4 / GP D 2( P U ) KS I7
K B C _W R E S E T # 14 36 K B -S O0 1 K B -S O0 1 1 0K X 3 .3V M7 20T /M7 30 T
W RS T # K S O0 / P D 0
37 K B -S O1 2 K B -S O1 2
126 K S O1 / P D 1 38 K B -S O2 3 K B -S O2 3
[ 1 3] GA 2 0 G A 2 0/ G P B 5 K S O2 / P D 2 X 10 K 0V M73 5T
[ 3 2] A C _ I N # 4 39 K B -S O3 7 K B -S O3 7
16 K B R S T #/ G P B 6 ( P U ) K S O3 / P D 3 40 K B -S O4 9 K B -S O4 9
[ 2 1] LE D _ A C I N # 20 P W U R E Q #/ GP C 7 ( P U ) K S O4 / P D 4 41 K B -S O5 10 K B -S O5 10
[ 2] T H E R M _ A LE R T# L 8 0 LL A T / GP E 7 ( P U ) K S O5 / P D 5
42 K B -S O6 13 K B -S O6 13
Sheet 26 of 40
23 K S O6 / P D 6 43 K B -S O7 16 K B -S O7 16
[ 30 ] A P _K E Y # E C S C I # / GP D 3 ( P U ) K S O7 / P D 7
[1 9 ] W E B _ E MA I L # 15 44 K B -S O8 17 K B -S O8 17
E C S MI # / GP D 4 ( P U ) K S O8 / A C K # 45 K B -S O9 18 K B -S O9 18
K S O 9/ B U S Y 46 K B -S O1 0 19 K B -S O1 0 19
DAC
KBC-ITE IT8512E
C P U_ F AN_ R 76 K S O 10 / P E 51 K B -S O1 1 20 K B -S O1 1 20 MO D E L _I D R 27 6 10 K _ 0 4
77 D A C 0 / GP J 0 K S O1 1 / E R R # 52 K B -S O1 2 21 K B -S O1 2 21 VD D3
D A C 1 / GP J 1 K S O1 2/ S L C T
[ 2 0 ] W L A N _P W R 78 53 K B -S O1 3 22 K B -S O1 3 22 R 28 5 *1 0 K _0 4
79 D A C 2 / GP J 2 KSO 1 3 54 K B -S O1 4 23 K B -S O1 4 23 V D D3
[ 20 , 2 1 ] W L A N _ E N D A C 3 / GP J 3 KSO 1 4
80 55 K B -S O1 5 24 K B -S O1 5 24
[2 5 ] K B C _ MU T E #
81 D
D
A C 4 / GP J 4
A C 5 / GP J 5
IT 85 12 E KSO 1 5 R2 8 1
R2 7 3
10 K _ 04
4. 7 K _ 0 4
ADC FLASH R2 7 4 4. 7 K _ 0 4
BA T _ DET 66 100
AD C 0 / GP I 0 F L F R A ME # / GP G 2
B A T _ V OL T _R 67 101 K B C_ S P I_ CE # C V D D3
C U R _ S E N S E _R 68 AD C 1 / GP I 1 F L A D0 /S CE # 102 K B C_ S P I_ S I 1 J_KB1 24 S M C_ B A T AC
T OT A L _C U R _R 69 AD C 2 / GP I 2 F L A D1 /S I 103 K B C_ S P I_ S O D 11 A 3 G_ D E T # R 26 4 10 K _ 0 4
AD C 3 / GP I 3 F L AD2 /SO
[ 2] C P U TE M P C P U T E MP 70 104 BAV9 9
3 G_ D E T # 71 AD C 4 / GP I 4 F L A D 3 / GP G 6 105 K B C_ S P I_ S CL K C CC D_ DE T # R 27 5 10 K _ 0 4
[ 1 9 ] 3 G_ D E T # AD C 5 / GP I 5 F L CL K /S CK S M D_ B A T
[ 1 9] C C D _ D E T # C CD_ DET # 72 106 CC D_ EN [ 19 ] AC
M OD E L _ I D 73 AD C 6 / GP I 6 ( P D )F LR S T #/ W U I 7 / TM / GP G 0 D 12 A S MC _C P U _ T H E R M R 20 1 4. 7 K _ 0 4
AD C 7 / GP I 7 BAV9 9
GPIO
SMBUS 56 C S MD _C P U _ T H E R M R 19 9 4. 7 K _ 0 4
S MC _ B A T 110 ( P D )K S O1 6 / GP C 3 57 S US B # [ 17 , 2 0, 2 3 , 2 7, 2 9 ] B A T _ DE T AC
[3 2 ] S M C_ BA T SM C L K 0 / GP B 3 ( P D )K S O1 7 / GP C 5 S US C # [ 1 7] [3 2 ] B A T _ DE T
[3 2 ] S M D_ BA T S MD _ B A T 111 D 25 A C P U TE M P R 37 0 *1 K _ 1% _ 04
S M C _ C P U _T H E R M 1 1 5 SM D A T 0 / GP B 4 93 CL K RU N# BAV9 9
[2 ] S M C _ C P U _ TH E R M S M D _ C P U _T H E R M 1 1 6 SM C L K 1 / GP C 1 ( PD )I D 0 / GP H 0 94 C
[2 ] S M D _ C P U _ TH E R M SM D A T 1 / GP C 2 ( PD )I D 1 / GP H 1 L E D _ TH R O TT L E # [ 1 9]
117 95 B A T _ V OL T AC
118 SM C L K 2 / GP F 6 ( P U ) ( PD )I D 2 / GP H 2 96 W DT _ E N A C_ P RE S E NT [1 5 ] [ 3 2] B A T _V O LT D 24 A R9 0 * 10 _ 04 C1 9 4 *1 0 P _ 50 V _ 04
SM D A T 2 / GP F 7 ( P U ) ( PD )I D 3 / GP H 3
97 W L A N_ DE T # [2 0 ] BAV9 9 P C LK _ K B C
( PD )I D 4 / GP H 4 98 C R2 8 0 1 0 0_ 0 4 C4 7 7 1 U _ 1 0V _ 0 6
PWM ( PD )I D 5 / GP H 5 B T _D E T# [ 19 ]
L C D _B R I GH TN E S S 24 99 C H G_ C U R AC B A T _ V OL T B A T_ V OL T _R
PW M0 / GP A 0 ( PU ) ( PD )I D 6 / GP H 6 D D _O N [ 28 ] [ 3 2] C H G_ C U R
25 D 26 A R2 8 6 1 0 0_ 0 4 C4 7 9 1 U _ 1 0V _ 0 6
[ 24 ] K B C _ B E E P 28 PW M1 / GP A 1 ( PU ) 107 BAV9 9 C H G_ C U R C U R _S E N S E _ R
[ 1 9 ] L E D _ S C R OL L # PW M2 / GP A 2 ( PU ) ( P D )I D 7 / GP G 1 3 G_ E N [ 19 , 2 1]
[ 19 ] L E D _N U M# 29 C R2 8 9 1 0 0_ 0 4 C4 8 5 1 U _ 1 0V _ 0 6
30 PW M3 / GP A 3 ( PU ) T OT A L _C U R AC T OT A L _C U R T O TA L _ C U R _ R
[ 19 ] L E D _C A P # PW M4 / GP A 4 ( PU ) EXT GPIO [ 32 ] T OT A L _ C U R
LOW ACTIVE [ 2 1] L E D _ B A T _C H G# 31 82 S MI # [ 1 5 ] D 27 A
32 PW M5 / GP A 5 ( PU ) ( P D )E G A D / GP E 1 83 BAV9 9
[ 2 1 ] L E D _ B A T _ F U L L# 34 PW M6 / GP A 6 ( PU ) ( P D )E G C S # / GP E 2 84 S CI# [1 5 ]
[2 1 ] L E D_ P W R# PW M7 / GP A 7 ( PU ) ( P D )E G C L K / GP E 3 P W R_ B T N# [1 5 ]
PS/2 WAKE UP
8 0 CL K 85 35 R S M R S T # [ 1 5, 1 7 ]
3 IN1 86 PS 2C LK 0 / G P F 0( PU ) ( P D )W U I 5 / GP E 5 17
PS 2D A T0 / G P F 1( PU ) ( P D ) LP C P D # / W U I 6 / GP E 6 K B C _ R S T# [ 1 3 ] KBC_SPI_*_R = 0.1"~0.5"
8 0 DE T # 87 V DD3
PS 2C LK 1 / G P F 2( PU )
88 PWM/COUNTER C 4 34 0 . 1 U _ 16 V _ 0 4
[ 14 ] P ME # 89 PS 2D A T1 / G P F 3( PU ) 47
[2 1 ] T P _ CL K PS 2C LK 2 / G P F 4( PU ) ( P D )T A C H 0 / GP D 6 C P U _F A N S E N [ 2 1]
[2 1 ] T P_ DAT A 90 48 U 17 R2 5 1 1 5 _1 % _0 4
PS 2D A T2 / G P F 5( PU ) ( P D )T A C H 1 / GP D 7 8 5 K B C _S P I _ S I _ R K B C _ S P I _S I
120 VD D SI R2 4 0 1 5 _1 % _0 4 C4 5 1 *3 3 P _ 50 V _ 04
WAKE UP ( P D )T MR I 0/ W U I 2 / GP C 4 V C O R E _ ON [3 1 ]
125 124 2 K B C _S P I _ S O _R K B C _ S P I _S O
[2 ] T H E R M_ R S T # P W R S W / GP E 4( P U ) ( P D )T MR I 1/ W U I 3 / GP C 6 CL _ PW RO K [ 5 , 1 2, 1 5 , 17 ] R 2 39 3. 3 K _ 1 %_ 0 4 SO R2 4 1 1 5 _1 % _0 4 C4 3 5 *3 3 P _ 50 V _ 04
CIR
[ 30 ] P W R _ S W # 18 119 K B C _ F LA S H 3 1 K B C _S P I _ C E #_ R K B C _ S P I _C E #
21 R I 1 #/ W U I 0/ GP D 0 ( P U ) ( P D )C R X / GP C 0 123 W P# C E# R2 5 2 1 5 _1 % _0 4 C4 3 6 *3 3 P _ 50 V _ 04
[ 1 2, 1 9 ] L I D _ S W # R I 2 #/ W U I 1/ GP D 1 ( P U ) ( P D )C TX / GP B 2 S U S _ P W R _A C K [1 5 ] 6 K B C _S P I _ S C LK _ R K B C _ S P I _S C L K
R 2 48 3. 3 K _ 1 %_ 0 4 SC K C4 5 2 *3 3 P _ 50 V _ 04
GP INTERRUPT LPC/WAKE UP
33 19 Z 2 61 2 7 4
[1 9 ] W EB_ W W W # G I N T / GP D 5 ( P U ) ( P D )L 80 H LA T / GP E 0 SW I# [1 5 ] H OL D # V SS
112 E N 2 5P 0 5 -50 G C P
( P D )R I N G# / P W R F A I L# / L P C R S T# / GP B 7 C H G_ E N [ 32 ]
UART
108 CLOCK
[ 1 9 , 21 ] B T_ E N 109 R X D / GP B 0 ( P U ) 2
AVSS
[ 12 ] B K L_ E N T X D / G P B 1( P U ) C K 32 K E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
128
C K 32 K R1 0 5 * 10 M _0 4 MP ? ? ?
I T8 5 1 2E / E X
11 3
1 22
12
27
91
75
J_ECDBG1 J _ E C D B G1
49
1
X5 3 2. 7 6 8 K H z W D T _E N
2 1 V DD3
R8 5 1 20 K _ 1% _ 0 4 4 1 2 1
C P U_ F AN_ R 3 2 4 3
[2 1 ] CP U _ F A N 9 6 5
C2 2 1 C 2 22 10 3 IN1 8 0 CL K
R 41 5 8 7 8 0 DE T #
C1 8 2 0 . 1U _1 6 V _ 04 1 5P _ 5 0V _0 4 1 5 P _ 50 V _ 0 4 10 9
D 03 A
B OM ? ? 0_04 S P U F Z -1 0S 3-V B -0 -B
R8 4 *1 0 mi l _s h o rt
[ 1 2 , 27 ] B R I GH T N E S S L C D _ B R I GH TN E S S N C1 *N C _0 4
R 41 5
I T8 512 E/ EX -- -0 _0 4 O HM
C1 9 2 *0 . 1 U _ 1 6V _ 0 4
K B C _ A GN D [ 1 3, 2 1 , 27 . . 3 0 , 32 ] V DD3
I T8 502 E- J-- - -0. 1U _16 V_0 4 [ 5 , 8 . . 1 6, 1 8 . . 25 , 2 7 , 31 ] 3. 3 V S
KBC-ITE IT8512E B - 27
Schematic Diagrams
System Power, LED BKLT
5VS,3.3VS S Y S 15 V VD D3
P Q2 9
A O4 4 68 3 . 3V S
V D D5 8
6A 7 3 6A
P Q 27 6 2
SYS1 5 V V DD5 A O 44 6 8 5 VS P R 1 54 5 1
P R9 8 8 P C9 8 P C 1 05 PR9 1
3A 7 3 3A 1 M_ 0 4
1 00 K _ 04 6 2 0 . 1 U _ 1 6V _ 0 4 *1 0U _1 0 V _ 08 10 0 K _ 04
4
PR9 7 5 1
SU SB PC1 0 1 PC1 0 4 P R9 5
1 M_ 04
D
0 . 1U _1 6 V _ 04 *1 0 U _ 10 V _ 08 10 0 K _0 4
4
P Q2 4 PQ 2 5 P C 10 0
G 2 N 7 00 2 W SUSB G 2 N 7 0 0 2W
[ 1 7 , 2 0, 2 3 , 26 , 2 9 ] S US B #
1 0 0P _ 5 0 V _0 4
D
S
S
P R 14 7 P Q3 2 P C1 0 3 P R 20 0
S US B G 2 N 7 00 2 W
* 10 0 K _0 4 *1 0 0P _ 5 0V _ 0 4 *1 0 _ 06
S
P Q 64
D
* 2N 7 00 2 W
S
Sheet 27 of 40 M735T LED PANEL BACKLIGHT DRIVER
System Power,
SEL1 SEL2 SEL3 LEDx Output
0 0 0 Only LED1 on
LED BKLT V IN
P D2 3 *F M2 6 0
L E D_ P W R+
1 0 0 LED1 throgh LED2 on
P L1 0 *4 . 7u H A C 0 1 0 LED1 throgh LED3 on

V DD5
OV P=3 5V
P C 20 1 P C 20 2 P C2 0 3 P C2 0 4 1 1 0 LED1 throgh LED4 on
P R1 8 5
* 10 U _ 2 5V _ 1 2 * 10 U _ 2 5 V _1 2 *1 U _ 5 0 V _1 2 *1 U _ 5 0V _ 1 2
P C 20 5 *9 0 . 9K _ 1 % _0 4 0 0 0 LED1 throgh LED5 on
[ 12 , 2 6 ] B RIG HT NE S S
* 1U _1 0 V _ 06
R.OVP = (V.OVP-30)/54.9uA 1 0 1 LED1 throgh LED6 on
25
22
24
23
V DD 5 PU 9
0 1 1 LED1 throgh LED7 on
O VP
SW
SW
V IN
S GN D
19
EN
26 1 1 1 LED1 throgh LED8 on
P R 1 86 1 0 0 - 4 0 0H z 20 A GN D
PW M 27
EP
*1 00 K _ 04 P Q5 9 2 0 K -2 MH z 6
APW M
D
*2 N 7 0 02 W 1
P GN D
2
G S K IP 21
3 P GN D S GN D V DD5
C O MP
30mil J _ LE D 1 _7 3
S
D
18 S E L 3 = H P R1 8 7 *1 0K _ 0 4
F s w = 2 MH z 4 S E L3 L E D_ P W R+ 1
S G ND
G P R 1 88 FSET 17 S E L 2 = L P R1 8 9 *0 _0 4 L E D1 - 2
[ 12 ] I N V _B LO N P Q6 0 S E L2 L E D3 - 3
4
*2 N 7 00 2 W P C 2 06 *1 . 05 K _ 1 %_ 0 4 L E D = 20 m A 5 16 S E L 1 = H P R1 9 0 *1 0K L E D5 -
S
IS E T S E L1 L E D6 - 5
* 0 . 1U _1 6 V _0 4 L E D4 - 6
7
P C 2 07 P R 19 1 PR1 9 2 7 15 L E D 2- L E D2 -
L E D1 L E D2 8
9
L ED 7
*0 . 1U _1 6 V _ 04 * 13 K _ 1% _ 04 *1 2 K _0 4
LG N D
L E D3
L E D5
L E D8
L E D6
L E D4
[ 5, 1 2 ] L V D S -L 0 N 10
[ 5, 1 2 ] L V D S -L 0 P 11
2A 12
*A 8 5 00 P L V DD 13
10
13
14
S GN D S G ND S G ND
11
12
8
9
14
3 .3 V S 15
L E D 4- 16
Fsw = 26.03/R.FSET ID = [ 5, 1 2 ] L V D S -L 2 N 17
1.23/I.SET * 210 [ 5, 1 2 ] L V D S -L 2 P 18
L E D 6-
(mA/LED) 19
[ 5 , 1 2] P _ D D C _C LK 20
L E D 5- [ 5 , 12 ] P _ D D C _ D A T A 21
P R 1 93 *0 _ 06 L E D 3- 22
23
L E D 1- 24
[ 5, 1 2 ] L V D S -L 1 N 25
[ 5, 1 2 ] L V D S -L 1 P 26
S GN D
27
[ 5 , 1 2] L V D S -L C L K N 28
[ 5 , 1 2] L V D S -L C L K P 29
30
* 20 3 7 4-0 3 0E -3 1
[ 12 , 2 8. . 3 2 ] V I N
[ 1 2] P L V D D
[ 1 2, 2 8 , 29 ] S Y S 1 5V
[ 28 , 2 9] V D D 5
[ 1 3, 2 1 , 26 , 2 8 . . 30 , 3 2] V D D 3
[ 12 , 1 3, 1 6 , 1 9, 2 1 , 24 , 2 5] 5 V S
[ 5 , 8 . . 16 , 1 8 . . 26 , 3 1] 3 . 3V S
B - 28 System Power, LED BKLT

Schematic Diagrams
Power VDD3, VDD5
VDD3,VDD5
35mil V IN
SYS5 V
E
25mil P C1 8 8
5mil V IN1 P R1 6 9 1 0 _0 4 V IN 2
B PQ 2 1 PC2 1 0 P C2 1 1
[ 2 9, 3 0 ] D D _ ON # + +
D T A 11 4 E U A 6 -06 -0 054 0- 021 0 . 1 U _ 25 V _ X 7R _0 6
15 U _2 5 V _D 2 LD O5 V *1 5 U _ 2 5V _ D 2
P Q 18
C
D
2 N 7 0 02 W D D _O N H [ 3 0]
A
[ 26 ] DD_ O N G
P D2 1 P C1 9 4 P D2 2 P C1 9 3 P R 17 1
PJ 9 P C 1 48 PR1 4 1
S
P R 85 F M0 5 4 0-N 4 . 7U _ 6. 3 V _ X5 R _0 6 F M0 54 0 -N 0 . 1U _ 10 V _ X7 R _0 4 * 1M _0 4
* OP E N _3 5 m li 0 . 1 U _ 1 6V _ 0 4 20 0 K _ 1% _ 0 4
1 00 K _ 0 4
21
18
19
15
P C1 8 5 P C1 9 7
P C1 8 0 P R 16 5 P R1 5 7 P C 1 76
B O OS T 1
B OO S T 2
IN T V CC
V IN
*1 00 0 P _ 50 V _ X 7R _0 4 * 10 _ 0 6 0 . 1U _ 10 V _ X7 R _0 4 0 . 1U _ 10 V _ X7 R _0 4 *1 0 _0 6 *1 00 0 P _ 50 V _ X7 R _0 4
Sheet 28 of 40
8
7
6
5
5
6
7
8
P Q5 3 4 22 14 4 P Q 55
T G1 T G2
A O 44 6 8 A O 44 6 8
Power VDD3, VDD5
3
2
1
1
2
3
VDD 5 PJ 1 2 S Y S 5V P R 1 56 PL 8 PL 9 P R 1 58 SY S3 V V DD 3
*O P E N _ 5 mm 10 m _1 2 4 . 7 U H _6 . 8 *7 . 3 *3 . 5 2. 5 U H _ 6. 8 *7 . 3 *3 . 5 8m _ 25 PJ 1 3
5A 5A 23 13 7A 7A
SW 1 SW 2
C
P Q5 2 *O P E N _ 5 mm
1
8
7
6
5
5
6
7
8
1
P D1 5 A O4 46 8 P D 16
P C 1 63 P C1 6 2 +P C 1 7 1 +P C 17 7 P C 17 4
F M5 82 2 4 L GA T E 1 20 17 LG A TE 2 4 P Q 54 F M 58 2 2
0. 1 U _ 1 0 V _X 7 R _ 0 4 0. 1U _1 0 V _ X7 R _ 0 4 1 50 U _6 . 3 V _V B G1 B G2 A O 44 6 8 1 5 0U _ 6. 3 V _ V 0 . 1 U _ 10 V _ X 7R _0 4
25 mo hm_ NE C A
2 5m ohm _NE C
A
2
3
2
1
1
2
3
2
P R 1 61 1 0_ 0 4 27 8 P R 1 82 1 0_ 0 4
S E NS E 1 + SENSE2 +
P C1 8 4 P C1 9 8
1 00 0 P _5 0 V _ X7 R _0 4 1 00 0 P _ 50 V _ X 7R _0 4
P R 1 60 1 0_ 0 4 28 7 P R 1 81 1 0_ 0 4
S E NS E 1 - S E NS E 2 -
P C 1 87 P R1 6 8 P R1 6 4 47 K _ 04 P C 18 1 22 0 P _ 50 V _ 0 4 P R 17 6 0 _0 6
S GN D 4 2 11 5V
* 2 2P _ 5 0V _ 0 4 1 05 K _ 1% _ 0 6 IT H1 E X T V CC
P C1 8 6 * 10 0 P _ 50 V _ 0 4 P C 19 5 2 20 P _ 5 0V _ 0 4 P R1 7 3 47 K _ 0 4 P R 17 2 P C 1 92
3 5
VF B1 IT H2 6 3 . 4K _ 1 %_ 0 6 * 1 00 P _ 50 V _ 0 4
12 P C1 9 6 1 0 0 P _5 0 V _ 04
P R1 6 7 P GO OD
S G ND 4
P R 16 2 * 10 m li _ s ho rt 24
L D O5 V MO D E / P L L I N
2 0K _ 1 %_ 0 6 P R1 5 9 1 0 K _ 04 4
25 VFB2
L D O5 V F R E Q / P L LF L T R
T K/SS2
T K/SS1
P R1 6 6 16 P R 17 0
R UN2
RU N1
P GN D
S GN D 4 P R 1 63
I LI M
*0 _ 04 2 0 K _1 % _0 4
3. 3 2 K _ 1% _ 06 PU 8
26
10
L T C 3 85 0
1
PIN 29 = SGND4
S G ND4
S GN D 4 S GN D 4
P C 19 9 10 0 0P _5 0 V _X 7 R _ 0 4 E N_ 3 V
P R1 8 4
P C 18 3 10 0 0P _5 0 V _X 7 R _ 0 4 E N_ 5 V * 10 m i _l s ho rt P C 1 89 C A S Y S 5V
0. 0 1 U _ 5 0V _ X 7 R _ 04
P R 1 74 * 0_ 0 4 T K/SS2 L D O5 V L GA T E 1 P D 17 F M0 54 0 -N
SYS5 V
S G ND 4 02/22
A C
S Y S 10 V
P R1 7 5 P C2 0 0 P C 18 2 P R 1 83
E N _3 V E N _ 5V P D 18 F M0 54 0 -N P C1 7 8
35mil *0 _0 4 0. 0 2 2 U _ 16 V _ X 7R _0 4 0 . 0 1U _ 50 V _ X7 R _0 4 *1 0K _ 0 4
2 20 0 P _ 50 V _ X7 R _0 4
P C 1 90 C A
5V LD O5 V 0. 0 1 U _ 5 0V _ X 7 R _ 04
D
P Q5 6 P Q 57 25mil S G ND 4 S GN D 4 P D 19 F M0 54 0 -N
S GN D 4
*2 N 7 0 02 W * 2N 70 0 2 W 5mil
G G A C
P R1 7 7 P R 17 9 S Y S 15 V
P D 20 F M0 54 0 -N P C1 7 9
S
*1 0 K _0 4 * 10 K _ 04
2 20 0 P _ 50 V _ X7 R _0 4
S GN D 4 S GN D 4
D
P Q 58 P R1 8 0
PR1 7 8 PJ 1 4 P C 1 91 * 2N 70 0 2 W *0 _ 0 4
G P M _T H R MT R I P # [ 2, 5 , 1 3]
*1 00 K _ 0 4 *O P E N _ 3 5m i l * 0 . 1U _1 6 V _ 04 P NC 1 *N C _0 4
[ 1 2, 2 7 , 2 9. . 3 2 ] V I N
S
[ 1 3 , 21 , 2 6 , 27 , 2 9 , 30 , 3 2] V D D 3
S GN D 4 [ 27 , 2 9] V D D 5
[ 32 ] S Y S 5 V
[ 12 , 2 7 , 29 ] S Y S 1 5V
[ 1 6, 1 9 , 2 1, 2 9 . . 31 ] 5V
Power VDD3, VDD5 B - 29

Schematic Diagrams
Power 1.5VS, 1.05VS, 3.3V, 5V
1.05VS 5V V IN
A
P C 2 12
PD2 4 +
P R7 8 1 00 K _ 04 E N _ 1. 0 5 V S PR2 0 1 5 . 1K _1 % _0 4 15 U _ 2 5 V _D
5V
5
6
7
8
F M0 54 0 -N
D
P C 90 4 P Q6 5
C
I R F 7 4 13 Z P B F
S US B L G P Q 23 0 . 0 33 U _ 1 6 V _X 7 R _ 04
2
3
1
2 N 7 00 2 W
P U1 0 P C 2 13
S
S C4 1 2 A
13
15
16
14
0. 1 U _ 5 0V _ 0 6 PL 1 1 V 1 .0 5 P J 28 1 . 05 V S
2. 5 U H + / -20 % _B C I H P 1 0 40 15A
D H
IL IM
N.C
N.C
P R 2 02 1 0K _ 0 4 12 1 1 2 1 2
3 . 3V EN LX
11 2 1 0m m
[ 1 7] 1. 05 V M_ P W R G D P GD BST P Q6 6
C
5
6
7
8
10 3 I R F 7 8 32 Z T R P B F
V OU T VC C P D 25 P C 2 14 P C 2 15 P C2 1 6
+ +
9 4 4
FB DL F M5 82 2 2 2 0U _ 4V _ D *2 20 U _ 4 V _D 0 . 1U _ 16 V _ 04
G ND
RT N
17
N.C
N.C
2
3
1
PAD
A
P R 20 3 P R 20 4 P C 2 17
7
6
5
0 _ 04 1 0 . 7K _ 1 % _0 4 1U _1 0 V _ 06
Sheet 29 of 40 P C 21 8
0 . 0 1U _ 16 V _ X7 R _ 0 4
P C 21 9
2 0 P _5 0 V _ 04
P R 2 05
2 4 . 9 K _1 % _0 6
Power 1.5VS,
1.05VS, 3.3V, 5V
1.5V 5V
PC1 5 4
V1 .8
PU 7 1 U _ 10 V _ 06
P R1 5 1 1 0 K _0 4 2. 5A 5 6 V 1 .5 PJ 1 0 1 . 5V S
3 .3 V VIN V CNT L
35mil 9 * OP E N _3 m m
7 VIN 4 2. 5A 1 2
[ 1 7] 1. 5 V S _ P W R G D P OK VO UT
3 PC1 5 1
25mil P R1 4 8 1 0 0K _ 0 4 8 VO UT P R1 5 0 P C 1 53 P C 15 8 PC1 5 6
5V EN
5mil 8 2P _ 5 0V _ 0 4 17 . 4 K _1 % _ 04
1 2 10 U _ 1 0V _ 0 8 1 0 U _ 10 V _ 0 8 0 . 1U _ 16 V _ 04
GN D VF B
D
P R1 4 9 P C 1 52 P C 1 59 P C 16 0 A P L 5 9 13
G P Q4 7 PR1 5 2
1 00 K _ 0 4 2 N 7 0 02 W 10 0 0P _5 0 V _X 7 R _ 04 0. 1 U _ 1 6V _0 4 1 0 U _ 1 0V _ 0 8
1 9. 6 K _ 1% _ 06
S
SUS BL
[ 30 ] SU SBL
D
P J 27
G P Q 46 * OP E N _3 5 mi l
[ 17 , 2 0, 2 3 , 2 6, 2 7 ] S USB # 2 N 7 00 2 W
P Q2 6
3.3V,5V S Y S1 5 V VDD 3 8
P Q2 8
A O4 4 6 8
3 .3 V
S Y S 15 V V D D 5
3A
8
7
A O4 46 8
3
3A
5V
7 3 6 2
3A 6 2 3A 5 1
5 1 PR9 4
P R 96 P R 93
P R9 0 1M _0 4
4
1 M_ 0 4 1 00 K _ 0 4
4
1 00 K _ 0 4
P Q3 0
D
P Q3 1 PC9 9 2N 70 0 2W
D
P C 10 2 2N 70 0 2 W
*1 00 P _ 5 0V _ 0 4 G D D _O N #
4 7 0P _ 5 0V _ X 7R _ 04 G D D _ ON #
D D _ ON # [ 2 8 , 30 ]
S
S
[ 27 , 2 8] V D D 5
[ 1 3, 2 1 , 26 . . 2 8 , 30 , 3 2] V D D 3
[ 1 2, 2 7 , 28 ] S Y S 1 5V
[ 16 , 1 9 , 21 , 2 8, 3 0 , 31 ] 5V
[ 2 , 1 2. . 1 7 , 1 9, 2 0 , 23 , 3 0] 3 . 3V
[ 2. . 5 , 7 , 8 , 13 , 1 6] 1. 05 V S
[ 3 , 8, 1 3 , 14 , 1 6 , 19 , 2 0] 1 . 5V S
[3 0 ] V 1 .8
[ 12 , 2 7 , 28 , 3 0. . 3 2 ] V I N
B - 30 Power 1.5VS, 1.05VS, 3.3V, 5V

Schematic Diagrams
Power 1.8V, 0.9VSM

1.8V,0.9VSM
V IN 5V 3 .3 V
A
P R 39 P R4 7 PR 5 0
PD 1 2
1 M_ 0 4 10 _ 0 6 F M 0 5 40 -N 1 0 0 K _ 04
V 1 .8
P U3
P R1 3 3 1 0 _0 6 3 7
C
V D DQ S PG D 1 . 8 V _ P W R GD [ 17 ]
Ra
PC 5 0 P R6 2 PC 1 3 9 P C1 3 6 P R2 6
2 0_06
T ON
1 0 0 P _5 0 V _ 0 4 2 . 2K _1 % _ 0 4 1 U _1 0 V _ 0 6 1U _ 10 V _ 0 6 24
BST
V IN
6
8 FB P C3 6 P C1 4 2 PC 5 6 P C 14 0
RE F
P R 5 1 1 0 _ 06
9 0 . 1U _ 25 V _ X 7 R _ 0 6 *4 . 7 U _ 2 5 V _X 5 R _0 8 * 4 . 7U _ 25 V _ X 5 R _ 0 8 0 . 1 U _ 5 0 V _0 6
C O MP
5
6
7
8
Rb P R5 7
P C 51 0_06 PQ 4 3
PR 5 4 P R1 3 2 23 4 I R F 7 41 3 Z P B F
D H
*0 . 1 U _1 6 V _ 0 4
1 0 _ 06 1 0K _ 1 % _ 04 10 P R2 5
VTTS
1
2
3
4 .7 K_ 0 4
5 21 PL 5 V 1 .8
V C CA IL IM 2 . 5 U H _ 6 . 8 *7 . 3 *3 . 5 P J4
PC 5 3 P C 48 P R 42 PC 4 2 P C4 4
LX
22 1 2 7A 1 2 1. 8 V
1 U_ 1 0 V _ 0 6 *0 . 0 6 8 U _ 1 0V _0 4 0 _ 06 1 0 00 P _ 5 0 V _ X7 R _0 4 1U _ 1 0V _ 0 6
DL
19 * OP E N _ 8 m m
Sheet 30 of 40
C
5
6
7
8
VS SA 4 P D7 P C1 4 6 PC 7 7 PC7 4
VSSA +
0 .9 VS M 2
PJ 2
1 1.5A 14
15
VTT
VTT
V D DP 1
20
P C3 5
5V
4 F M5 8 22 22 0 U _ 4 V _ D 0 . 1 U _ 1 6 V _ 04 0 . 01 U _5 0 V _ X 7R _ 0 4
Power 1.8V,
A
1
2
3
0.9VSM
* OP E N _ 3m m V 1 .8 12
PR 4 0 P C5 5 P C6 7 13 V D DP 2 1 U _1 0 V _ 0 6 PQ 4 2 P R5 6
V D DP 2
PC 4 9 PC5 2 A O 4 45 6 0 _0 6
2 0 K _ 1% _ 0 4 4 . 7U _ 6. 3V _ X 5 R _ 0 6 1 0 U _1 0 V _ 0 8 1 18 VSSA
1 0 U _ 1 0 V _ 08 1 U _ 1 0V _0 6 E N /P S V P GN D 1 16
11 P GN D 1 17
VTTEN P GN D 2
S C 4 86
P R3 0 2 20 K _ 1 % _ 04 1 .8 V EN
5V V D D3 V IN VA 500mA V IN1
PD 8 F M0 5 40 -N
D
PC 3 8 A C
P Q1 5
G PQ 4 0 0 . 1 U _ 1 6 V _ 04 P R1 4 5 N D S 3 5 2A P _N L PD 9 F M0 5 40 -N
[ 2 8, 29 ] D D _ ON # 2N 7 0 02 W S D A C
1 0 K_ 0 4
S
[2 6 ] P W R_ S W #
P Q 17 P R 14 3 1 0 0 K _0 4 PR 1 4 2 20 K _ 1 % _ 04
G
D
2 N 7 0 0 2W
AP_ KEY # [2 6 ]
G
P Q 14 PQ 1 3 P Q 61 P Q6 2
D
2 N 7 0 0 2W 2 N 70 0 2 W 2 N 7 0 0 2W 2 N 70 0 2 W
P R4 1 4 7 K _ 04 VTTEN P R 14 0 1 0 0 K _0 4
5V
E C G G G G
V IN
S
P C 1 49 PQ 1 6 P R1 4 6 P C 15 0
PC 4 6 0. 1 U _5 0 V _ 0 6 D TA 11 4 E U A
D
10 0 K _ 0 4 0 . 1 U _ 5 0 V _0 6
B
[2 9 ] S US B L G PQ 9 0 . 1 U _ 1 6 V _ 04
2N 7 0 02 W P R 14 4 1 0 K_ 0 4
S
[1 9 ] M_ B T N #
[2 8 ] D D_ O NH
VIN E C PR 1 9 4 1 00 K _ 0 4
P C 20 9 PQ 6 3 P R 1 95 P C2 0 8
0 . 1 U _5 0 V _ 0 6 D TA 11 4 E U A
1 0 0 K _0 4 0. 1 U _5 0 V _ 0 6
B
P R 19 6 1 0 K _ 04
[ 1 9] APKE Y#
[ 10 , 1 1 ] 0 . 9 V S M
[ 5 , 7 , 8 , 1 0, 11 ] 1 . 8V
[ 29 ] V 1 . 8
[ 1 6 , 1 9, 2 1 , 2 8 , 2 9, 3 1 ] 5V
[ 2 , 1 2 . . 1 7 , 19 , 2 0 , 2 3, 29 ] 3 . 3V
[ 1 3, 2 1 , 2 6 . . 2 9, 3 2 ] V D D 3
[ 1 2 , 2 7 . . 29 , 3 1 , 3 2 ] V I N
Power 1.8V, 0.9VSM B - 31

Schematic Diagrams
Power VCORE
VCORE VI N 5V
V -R C 1
A
P C 24
P C1 2 8 P D1 1
1 U _ 1 0V _ 0 6
1 00 0 P _ 50 V _ X 7R _ 04 F M0 5 4 0-N P R2 4
P R1 2 3 V IN
1 0_ 0 6
C
1 00 _ 1 %_ 0 4 BST1
P Q3 6 P C2 1 P C 19 P C 22 P C 1 32
+
5
6
7
8
P R 16 * 0_ 0 4 I R F 7 4 13 Z P B F
P C2 3 0 . 1U _ 50 V _ 06 0 . 1 U _ 50 V _ 0 6 0 . 1 U _ 5 0V _ 0 6 1 5 U _ 2 5V _D 2
P R1 5 0_ 0 6 4
S GN D 3 PR 1 4 1 U _ 25 V _ 0 8
7 . 5K _ 1 % _0 4
2
3
1
P R1 0 0_04 D P R S L_ S T P
[ 2 , 5 , 13 ] H _ D P R S TP # E N_ V CO RE P C2 7
P R1 2 2 4 9 9 _1 % _0 4 DP RS L T G1 0 . 01 5 U _ 5 0V _ 0 6 PL 3 V C OR E
[ 5 , 15 ] P M_ D P R S L P V R 0. 5 U H _ 10 *1 0 *4 . 1
close to IMVP6
20A 40A
VPN 1
D RN1
3 . 3V S BG 1
DR N1
C
5
6
7
8
5
6
7
8
IS H
P C 11 6 P C1 2 9 P C 13 0
44
43
41
39
37
36
35
34
[ 1 5] CL K E N#
42
40
38
P R1 9 P U2 4 4 + + +
PD3 3 30 U _2 . 5 V _ D 3 33 0 U _ 2 . 5V _D 3 * 33 0 U _ 2 . 5V _D 3
VPN 1
V5 _ 1
IS H
DP R S L
V IN1
BST 1
T G1
D RN1
B G1
EN
NC
P C2 8 1 0 0P _ 5 0V _0 4 6 80 _ 0 4 F M5 8 22
2
3
1
2
3
1
A
Sheet 31 of 40
P R1 7 3 3 K _1 % _ 04 P R 18 1 33
13 0 K _ 1% _ 0 4 V C OR E _ V R E F 2 C LK E N # C S1 + 3 2 CS 1 N PQ 7
V C OR E _ H Y S VR EF C S 1-
3 3 1 CS 2 N * I R F 7 8 32 Z T R P B F PQ 3 9
C S 1N
P R2 3 2 2 0K _ 1 % _0 4 V C OR E _ C LS E T 4 H YS C S 2- 30 I R F 7 83 2 Z T R P B F P R3 8 0_06
Power VCORE
C LS E T C S2 +
[ 3] H_ V ID6 5 29
P R 22 6 V ID 6 TRERMAL PAD E R R OU T 2 8 VCC A
[ 3] H_ V ID5 V ID 5 V C CA
13 0 K _ 1% _ 0 4 [ 3] H_ V ID4 7 27
P C3 4 1 0 0P _ 5 0V _0 4 8 V ID 4 A GN D 2 6 DA C
0 . 1 U _ 25 V _ X 7 R _ 0 6
[ 3] H_ V ID3 9 V ID 3 D AC 2 5 V C _S S P R4 8 0_06
0 . 0 22 U _1 6 V _ X 7R _0 4
10 0 0P _5 0 V _ X 7R _0 4
1K _1 % _0 4
[ 3] H_ V ID2 V ID 2 SS
PR 2 1
10 24
1 00 P _ 5 0V _0 4
P C3 3 1 0 00 P _ 50 V _ X 7R _ 04 [ 3] H_ V ID1 11 V ID 1 DR P + 23
[ 3] H_ V ID0 V ID 0 D RP-
C S 2N
1 U _ 1 0V _ 0 6
P W RG D
VPN 2
D RN2
BST2
V5 _ 2
3 . 3V S
GN D
V IN2
P S I#
FB -
F B+
T G2
B G2
S GN D 3
P C 12 3 P C1 3 1 P C 12 4
E -R C
P R 29 P R1 3 0 SC4 5 2 V IN + + +
45
12
13
15
17
19
20
21
22
*3 3 0 U _ 2. 5 V _ D 3 33 0 U _ 2 . 5V _D 3 3 3 0U _ 2. 5 V _ D 3
14
16
18
R 17 0 1 00 _ 1 %_ 0 4 1 K _ 04 *6 8 0_ 0 4
15 0 0 P _5 0 V _ 04
V C OR E
P C 25
PC3 0
PR 3 1 *1 0m i l _s h or t Z 2 8 01 P C5 8 PC5 9 P C2 0 P C1 3 8
P C 13 4
PC 3 1
P C3 7
P C3 2
[ 5 , 1 7] D E L A Y _P W R GD FB+ +
5
6
7
8
P R 1 31 1 0_ 0 4
[3 ] CP U_ V C CS E N S E PR 3 3 1 0_ 0 4 FB- 0 . 1 U _ 5 0 V _0 6 0. 1 U _5 0 V _0 6 0 . 1U _5 0 V _ 06 1 5U _ 25 V _ D 2
[3 ] C P U_ V S S S E N S E Z 2 8 02
[2 ] P S I# 4
D RP - V C OR E _ V R E F
P R 1 28 * 10 m li _ s ho rt D RP + S GN D 3 P C 29 P Q4 4
2
3
1
0 . 0 15 U _5 0 V _ 06 I R F 7 4 13 Z P B F
P R2 0 7. 5 K _ 1 %_ 0 4 C S 2P
P C 13 7 R1 7 2 P C1 3 5 P C 1 33
DR N2
T G2 PR 3 2 0 _ 06 P Q4 1 PL 4
* 10 0 P _5 0 V _ 04 10 0 _ 1% _ 0 4 *1 0 0P _5 0 V _ 04 *1 00 P _ 5 0V _ 0 4 BG 2 I R F 7 8 32 Z T R P B F 0. 5 U H _ 10 *1 0 *4 . 1
20A
V P N2
5V
C
5
6
7
8
5
6
7
8
A
S G ND3 S GN D 3 S GN D 3 P C4 3 P C4 5 PD4
P R4 9 P D1 3 P C4 1 4 4
1 00 0 P _ 50 V _ X 7R _ 04 1U _2 5 V _ 08 F M5 8 22
1 00 _ 1 %_ 0 4 F M0 5 40 -N 1 U _ 10 V _ 0 6
V -R C 2
2
3
1
2
3
1
A
PR1 2 9 0_06 VC _ SS P R 13 *0 _ 04
C
5V
V IN B S T2 P Q8 S GN D 3 P C1 8 P C 26
*I R F 7 83 2 Z T R P B F * 0 . 1U _1 6 V _ 04
*0 . 0 2 2U _ 16 V _ X 7R _0 4
P U1
D
5
S G ND3 *7 4A H C T 1 G0 2 GW
C L KEN# 1 PQ 6
P R 11 *0 _ 0 4 4 G
P RT 2 D P RS L 2 *2 N 7 0 02 W
5V P R 35 D RP _ L 1 2 1 C S1 N
S
2 8K _ 1 % _0 4 P R 12 *0 _ 0 4
P R 1 26 1 0 K _0 4 E N _ V C OR E 1 0 0K _N TC _ 06 D P RS L _ S T P
3
P C3 9
DRN 1 P R 27 P R3 6
P R 12 5 P R 12 4 47 K _ 0 4 S GN D 3
1 7. 4 K _ 1 %_ 0 4 0 . 0 33 U _ 1 6 V _X 7 R _ 0 4 DRP +
D
1 00 K _ 0 4 *1 0 K _ 04 DCR _ DR1 P R4 3 4 7 K _ 04
G DCR _ DR2 P R4 4 4 7 K _ 04 P C4 0 P R2 8
P Q3 8
D
2 N 7 00 2 W P C4 7 6 80 P _ 5 0V _ X 7 R _ 0 4 9. 1 K _ 1 %_ 0 6
S
PJ 6 35mil DRN 2 P R 46 P R3 7
P R1 2 7 *1 0 m li _ sh o rt G *O P E N _ 3 5m i l DRP -
[ 26 ] V C OR E _ ON 47 K _ 0 4
1 7. 4 K _ 1 %_ 0 4 0 . 0 33 U _ 1 6 V _X 7 R _ 0 4
PQ 3 7
S
25mil P RT 1
2 N 7 0 0 2W
P R 45 D RP _ L 2 2 1 C S2 N
5mil
2 8K _ 1 % _0 4
10 0 K _ N T C _ 0 6
[ 1 6 , 19 , 2 1 , 28 . . 3 0 ] 5 V
[3 ] V CO RE
[ 5 , 8. . 1 6 , 1 8. . 2 7 ] 3 . 3 V S
[ 1 2 , 2 7. . 3 0 , 3 2] V I N
B - 32 Power VCORE
Schematic Diagrams
Power AC-IN, Charger
AC IN & CHARGER P R1 0 5
* 10 m i _l s ho rt
VA
Ch arg e Cur re nt 2.0 A
P Q 34
VIN
4
A M 48 3 5P Ch arg e Vol ta ge 16. 8V
1 5
2 6 To tal P owe r 60W
3 7
J_ D C -J A C K 1 PL 1 VA P Q3 3 8
2D C -G2 1 3 -B 20 0 H C B 4 5 3 2K F -8 0 0 T6 0 A M4 8 35 P P Q 35 A
8 P R9 S P 8K 10 S F D 5 T B PL 2 P R 10 4 BAT V _B A T
1
7 3 30 m _ 20 2 10 U H _6 . 8 *7 . 3 *3 . 5 3 0 m_ 2 0 PF2
2 6 2 1 7 1 2
G ND1 P R1 0 0 5 1
G ND2
5A
G ND3
5
6
4 . 7 U _ 2 5V _ X 5 R _ 0 8
4 . 7 U _ 2 5V _ X 5 R _ 0 8
1 30 K _ 1 %_ 0 4 P C 17
4. 7 U _ 2 5 V _X 5 R _0 8
4 . 7U _2 5 V _ X 5R _0 8
4 . 7 U _ 25 V _ X 5 R _ 08
4. 7 U _2 5 V _X 5 R _0 8
G ND4
P C 10 7 P C 1 06 P C 10 8 PR 9 9 P R7 P C1 1 5
8
4 . 7 U _ 25 V _ X 5R _0 8 0 _0 4
0 . 1 U _ 50 V _ 0 6 0. 1 U _ 5 0 V _0 6 0 . 1U _ 50 V _ 06 1 0 K _ 08 PR 5 3 0 . 1U _ 50 V _ 06
P R 1 17
P R1 0 1 0 _0 4 P Q 35 B
P C1 0 9
P C 11 0
P C 1 11
P C1 1 2
P C1 1 3
P C 11 4
2 0 0 K _1 % _0 4 P C1 4 S P 8 K 1 0S F D 5 TB
4
1 0K _ 1 % _0 4
4. 7 U _ 2 5 V _X 5 R _ 0 8
P C1 2 5
0 . 1 U _ 25 V _ X 7R _0 6
BA T
PD 2 P C1 6
P R 1 16 F M0 5 40 -N 1 U _ 2 5V _0 8
PC 6 P C7 P C8 C A
0 . 1 U _ 5 0V _ 0 6 0. 1 U _ 5 0 V _0 6 0 . 1U _ 50 V _ 06
1 0 0 K _1 % _0 4
Sheet 32 of 40
P C 12 2
Power AC-IN,
VA
0 . 1 U _ 1 6V _ 0 4
PC 5 P C4 Charger
32
31
29
28
27
26
30
25
V IN P U6 VA S G ND 5 0 . 1 U _ 5 0V _ 0 6 0. 1 U _5 0 V _0 6
C B
LX
VB
CEL L S
CT L 2
OU T -1
OU T -2
P G ND
1 24 P C1 1 7 0 . 1 U _ 5 0V _ 0 6
2 VC C VIN 23 C TL 1
-I N C 1 C T L1
P C 13 P C1 2 P C1 1 PC 1 0 3 22
4 + INC 1 GN D 21
A C IN V RE F
0 . 1U _5 0 V _ 06 0. 1 U _ 5 0 V _0 6 0 . 1U _ 50 V _ 06 0 . 1 U _ 5 0V _ 0 6 5 TRERMAL PAD 20 P R 1 08
6 A C OK RT 19 *1 0 m li _ sh o rt
-I N E 3 CS
C OM P 2
7 18 S GN D 5
O UT C 1
OU T C 2
C O MP 3
+ INC 2
AD J 1 A D J3
A DJ 2
8 17
-I N E 1
-I N C 2
S GN D 5 P R 1 15 C OMP 1 B A TT 33
S GN D
02/22
1 0 K _ 1% _ 04 P R1 1 3 MB 3 9 A 13 2 P R 1 19
P C 11 8
P R1 0 7
10
12
13
14
15
11
16
9
10 K _ 1 %_ 0 4 1 K _ 1 %_ 0 4
TOTAL
4 9 . 9K _ 1 % _0 4
0 . 1 U _ 16 V _ 0 4
3 9. 2 K _ 1 %_ 0 4
POWER CHARGE
P R 1 20 P C1 2 6 P R 1 10
P R1 0 6
P R 1 14 0 _0 6 ADJ P C 1 27 CURRENT
1 0 . 2 K _1 % _ 04 22 0 0 P _5 0 V _ X7 R _ 0 4 10 K _ 1 %_ 0 4 ADJ
1 0 0 P _5 0 V _ 04
S G ND5
S GN D 5
S Y S 5V S GN D 5 S GN D 5
P C 12 1 *2 2 P _5 0 V _ 04
P R 10 9 2 2 K _1 % _ 04
P R1 1 8
P C 1 19 1 00 0 P _ 50 V _ X 7R _0 4 P C 12 0 P R 10 3 P R 1 02
10 0 K _ 04 22 K _ 1 %_ 0 4 1 K _ 1% _ 04
1 0 00 P _ 5 0V _ X 7R _ 04
CT L 1
P R 11 2 0 _ 04
0 .7 5V/ 1A
D
[ 26 ] T OT A L _ C U R S G ND 5 S G ND 5
SY S5 V P R 12 1 1 00 K _ 0 4 Z 3 22 8 G PQ 4 P R 11 1 0 _ 04
2N 70 0 2 W [ 2 6] C H G_ C U R
0 .7 5V/ 1A
D
P Q3 35mil
G PJ 1
[2 6 ] C H G_ E N V_ BAT
2 N 7 0 02 W *O P E N _ 3 5 mi l
S
25mil P MB A T 1
5mil 5
P R3 1 0 0 _0 4 Z 32 2 5
[ 26 ] S MC _ B A T P R2 1 0 0 _0 4 Z 32 2 6 4
[ 26 ] S MD _ B A T 3
V D D3 [2 6 ] B A T _ DE T P R1 1 0 0 _0 4 Z 32 2 7
2
PQ 2 P R8 PC 1 PC 2 PC 3 1
PR 4 D TA 1 1 4 E U A 3 0 K _ 1% _ 0 4 B T D -0 5 T I 1G
BAT E C Z 3 22 9
B A T _ V OL T [2 6 ]
B tt er y Vol ta ge : 3 0 P _ 50 V _ 04 3 0 P _ 50 V _ 04 3 0 P _5 0 V _ 04
1 0 K _0 4
A C_ IN# [2 6 ]
1 2V ~1 6. 8V
P D1
C
C A Z 3 23 1 B PQ 1 Z 3 2 30 P R6 P C1 5
VA
D
U D Z 1 6B D TD 11 4 E K 6 . 04 K _ 1 %_ 0 4 0 . 1U _ 16 V _ 04
PC 9
G P Q5
E
S Y S 5V
* 0. 1 U _1 6 V _0 4 2N 70 0 2W
S
[ 13 , 2 1, 26 . . 3 0] V D D 3
[ 1 2 , 2 7. . 3 1 ] V I N
[ 28 ] S Y S 5 V
Power AC-IN, Charger B - 33

Schematic Diagrams
Multi I/O Board 1/2
SPEAKER For M720T LID SWITCH HOT KEY & POWER SWITCH
SW8
SW6
M J_S PK R_7 2 MS W 1
MS W 2 T JG -5 33 -S -V -T / R
2 1 T JG -5 33 -S -V -T / R 1 2
1 2 MW E B _W W W # 3 4 MM_ B T N #
M 3. 3 V 3 4
MC 22
ML 6 M R1 10 0 K _ 04
5
6
F C M 10 0 5K F - 12 1 T0 3 MJ _ S P K R _ 7 2 0 . 1U _1 6 V _ 04
5
6
MS P K R - M S P K R -_ R M U1
MS P K R + M S P K R + _R 1 1 3 M LI D _S W #
2 VCC O UT
MG N D
GN D
ML 7 8 82 6 6-0 2 00 1 MG N D MG N D MSW 1~ 4
F C M 10 0 5K F - 12 1 T0 3 M C1 7 MC 16 P C B F o o t p rin t = 88 2 66 -2 L M C1
MH -2 4 8 MU 1 SW4 3 1 SW2
1 8 0P _ 5 0V _ 0 4 1 80 P _ 50 V _ 0 4 0 . 1 U _ 16 V _ 04 2 4 2
2
MS W 3 MS W 4
T JG -5 33 -S -V -T / R T JG -5 33 -S -V -T / R
MG N D MGN D 1 3 1 2 MW E B _E M A I L# 1 2 MA P K E Y #
FO R E MI 3 4 3 4
MG N D MC 19 MC 18
0 . 1U _1 6 V _ 04 0 . 1U _1 6 V _ 04
5
6
5
6
MG N D MG N D MG N D MG N D
Sheet 33 of 40 LED M3 . 3 V S POWER SWITCH

LED
M3 . 3 V S HDD/ODD
LED
M 3 . 3V S NUM LOCK
LED
M3 . 3V S CAPS LOCK
LED
M 3 . 3V S SCROLL LOCK
LED
M 3. 3 V S THROTTLE
LED
Multi I/O Board 1/2
E
MS 2 M S1
S MD 80 X 80 S M D 8 0 X8 0
MR 2 B M S A T A _L E D # MR 6 MR 5 MR 4 MR 3
1
22 0 _0 4 MQ 1 2 20 _ 04 2 20 _ 0 4 2 20 _ 04 22 0 _ 04
D T A 11 4 E U A
1
M 73 0T/ M73 5T D0 3 M R7
B CN ? ? 470
2 2 0 _0 4 MG N D M GN D
A
M D1 M D2 M D3 M D4
A
A
3/31 MS1? ? 180?
MD 5 MD 6 R Y -S P 1 7 2Y G3 4 R Y -S P 1 7 2Y G3 4 R Y -S P 1 7 2Y G3 4 R Y -S P 1 72 Y G 3 4 BY? ? ? ?
R Y -S P 1 50 D N B 84 -5 / 1 X R Y -S P 17 2 Y G 34
C
C
C
MN U M_ L E D # MC A P _ LE D # MS C R OL L _ LE D # MT H R OT TL E _ L E D #
M GN D M GN D
FOR M720T 3.3 VS= 2A M J _M F B 1_ 7 2

MC LK _ P C I E _M I N I _ 3G #
MJ _ MF B 2 _7 2
M3 . 3V S 1 2 MU S B V C C 2 [ 3 4] MC L K _ P C I E _ MI N I _ 3G # 1 2
MC LK _ P C I E _M I N I _ 3G
MN U M_ LE D # 3 4 [ 3 4] MC LK _ P C I E _ MI N I _ 3G MP C I E _R X N 3 _3 G 3 4
5 6 M3 . 3 V [ 3 4] MP C I E _R XN 3 _3 G 5 6 M US B V CC 2 M3 . 3 V S M1 . 5 V S
MC A P _ L E D # M TH R OT T LE _L E D # [ 34 ] MP C I E _ R X P 3 _ 3G MP C I E _R X P 3_ 3 G
MS A T A _L E D # 7 8 M S C R O LL _ L E D # MP C I E _T X N 3 _ 3G 7 8
MM_ B T N # 9 10 [ 34 ] MP C I E _ T XN 3 _3 G MP C I E _T X P 3 _3 G 9 10
11 12 M1 . 5 V S [ 3 4 ] M P C I E _ TX P 3 _ 3G 11 12
[ 3 4 ] M3 G_ D E T# M3 G_ D E T # [3 4 ] M P CIE _ W A K E # MP C I E _W A K E # M C9 MC 11 MC 8
MA Z _ S D OU T 13 14 MB U F _P L T _ R S T # 13 14
[ 3 4 ] M A Z _S D OU T 15 16 [ 3 4] MB U F _P L T _ R S T # 15 16
[ 34 ] MA Z _ S Y N C MA Z _ S Y N C MW L A N _C LK R E Q# MW L A N _C LK R E Q# [3 4 ] [ 3 4] MW L A N _ C L K R E Q# MW L A N _ C LK R E Q# * 0 . 1U _1 6 V _0 4 *0 . 1 U _ 1 6V _ 0 4 0. 1 U _ 1 6V _ 0 4
MA Z _ S D I N 1 17 18 M3 G_ E N MU S B _P N 5 _3 G 17 18
[ 34 ] MA Z _ S D I N 1 MA Z _ R S T # 19 20 MA P K E Y # M3 G_ E N [ 3 4] [ 3 4 ] M U S B _ P N 5 _ 3G MU S B _P P 5_ 3 G 19 20
[ 3 4 ] MA Z _ R S T# 21 22 [ 3 4 ] M U S B _ P P 5 _3 G 21 22
[ 3 4 ] M A Z _B I T C LK MA Z _ B I TC LK MW E B _ E M A I L# M GN D MG N D M GN D
MS P K R + 23 24 MW E B _ W W W # MU S B _P N 3 23 24
MS P K R - 25 26 ML I D _ S W # [ 3 4] MU S B _P N 3 MU S B _P P 3 25 26
27 28 [ 34 ] M US B _ P P 3 27 28
5P 1 -2 51 A 4 -1 3V 0 0 -21 4 5 P 1- 25 1 A 4-1 3 V 00 -2 1 4
M GN D MG N D MG N D
FOR M730T
M P C I E _ R X N 3 _ 3G 2 3 MR N 2 MP C I E _ R XN 3_ 3 G_ 13
M P C I E _ R X P 3 _3 G 1 4 *4 P 2 R X 0_ 0 4 MP C I E _ R XP 3 _ 3G _1 3
3. 3V S=2 A M J_ MF B 1_ 7 3 MJ _ MF B 2 _ 73
MC LK _ P C I E _M I N I _ 3G # _1 3 M P C I E _ TX N 3 _ 3 G 2 3 MR N 3 MP C I E _ T X N 3 _3 G_ 1 3
M 3. 3 V S 1 2 MU S B V C C 2 1 2 MP C I E _ T X P 3_ 3 G_ 13
MC LK _ P C I E _M I N I _ 3G _ 13 M P C I E _ TX P 3 _ 3G 1 4 *4 P 2 R X 0_ 0 4
M N U M_ LE D # 3 4 MP C I E _R X N 3 _3 G_ 1 3 3 4
M CA P _ L E D# 5 6 MT H R OT T LE _ L E D # M3 . 3 V MP C I E _R X P 3_ 3 G_ 13 5 6 M USB _ PN3 2 3 MR N 5 MU S B _ P N 3_ 1 3
7 8 7 8 MU S B _ P P 3 _ 13
M S A T A _L E D # MS C R O LL _ LE D # MP C I E _T X N 3 _ 3G _1 3 M USB _ PP 3 1 4 *4 P 2 R X 0_ 0 4
M M_ B T N # 9 10 MP C I E _T X P 3 _3 G_ 1 3 9 10
11 12 M1 . 5 V S 11 12 MU S B _ P N 5_ 3 G_ 13
M 3G _ D E T # MP C I E _W A K E # M U S B _ P N 5 _3 G 2 3 MR N 4
M A Z _ S D OU T 13 14 MB U F _P LT _ R S T # 13 14 M U S B _ P P 5_ 3 G 1 4 *4 P 2 R X 0_ 0 4 MU S B _ P P 5 _ 3G _1 3
M A Z _ S Y NC 15 16 MW L A N _ C L K R E Q# MW L A N _ C LK R E Q# 15 16
17 18 17 18 MC L K _ P C I E _ MI N I _3 G #_ 1 3
M A Z _ S DIN1 M3 G_ E N MU S B _P N 5 _3 G_ 1 3 M C L K _P C I E _ MI N I _ 3 G# 2 3 MR N 1
M AZ _ RST # 19 20 MA P K E Y # MU S B _P P 5_ 3 G_ 13 19 20 M C L K _P C I E _ MI N I _ 3 G 1 4 *4 P 2 R X 0_ 0 4 MC L K _ P C I E _ MI N I _3 G _1 3
M A Z _ B I TC LK 21 22 MW E B _ E MA I L# 21 22
23 24 23 24
M SP KR+ MW E B _ W W W # MU S B _P N 3 _1 3
M SP KR- 25 26 ML I D _ S W # MU S B _P P 3_ 1 3 25 26
27 28 27 28
*5 P 1-2 5 1A 4 -1 3 V 00 -2 14 * 5P 1 -2 51 A 4 -1 3V 0 0 -21 4
[3 4 ] MU S B V C C 2
[ 3 4] M3 . 3 V
MG N D MG N D M GN D [ 3 4] M3 . 3 V S
[ 3 4] M1 . 5 V S
B - 34 Multi I/O Board 1/2

Schematic Diagrams
Multi I/O Board 2/2
3G/Raboson 20 mil
M C2 1
1 50 U _ 6 . 3V _V MU I M_ P W R MR 1 2 *4 . 7 K _ 04
M J_ S I M 1
M GN D
M R1 3 LOC K
*1 0m i l _s h ort (TO P VIE W)
MJ _3 G1 MC 3 0 . 1 U _ 16 V _ 04 M U I M _C LK MU I M_ C L K _ R C3 C 7 MU I M_ D A T A _ R MR 1 4 *1 0m i _l s h ort MU I M_ D A T A
1 2 MU I M_ R S T C2 U I M_ C L K U I M_ D A TA C 6 MU I M_ V P P
[3 3 ] M P CIE _ W A K E # W AKE # 3. 3 V _ 0 M3 . 3 V S U I M_ R S T U I M_ V P P
3 4 MU I M_ P W R C1 C 5
5 B T _ DA T A GN D 5 6 U I M_ P W R U I M_ GN D MC 2 5 M C2 6 MC 27
M R8 *0 _0 4 7 B T _ CH CL K 1. 5 V _ 0 8 MU I M _P W R M1 . 5 V S M C2 8
[3 3 ] MW L A N _ C LK R E Q# C LK R E Q# U I M_ P W R MU I M _D A TA MGN D
9 10 OP EN *2 2 P _ 50 V _ 04 * 22 P _ 50 V _ 0 4 *2 2 P _5 0 V _0 4
11 G ND0 U I M _D A TA 12 MU I M _C LK MC 24 * 2 2P _ 5 0V _ 0 4 S I M L OC K 1 7 70 6 6 1-1
[ 3 3 ] M C L K _P C I E _ MI N I _ 3 G# R E F CL K - U I M _C LK MU I M _R S T
[ 3 3 ] M C L K _P C I E _ MI N I _ 3 G 13 14 0 . 1 U _ 1 6V _ 0 4
15 R E F CL K + U I M _R E S E T 16 MU I M _V P P M GN D MG N D MG N D MGN D
G ND1 U I M _V P P M GN D
KEY
17 18 La you t?
N C3 GN D 6
[3 3 ] MP C I E _ R X N 3 _3 G
19
21
23
25
N C4
G ND2
PET n 0
W _ DIS A B L E #
P E RS E T #
3 . 3V A U X
20
22
24
26
M 3G _ E N [ 3 3 ]
M B U F _ P L T_ R S T #
M3 . 3 V S
[3 3 ]
1. SI M? ? ? ? ? ? ? ? (1 0m il)
2. ? ? ? ? ? ? ? ? GN D
USB PORT
[ 3 3] MP C I E _R XP 3 _ 3G PET p 0 GN D 7 3. SI M h ol d ? ? ? ? ? GN D? ?
27 28 M1 . 5 V S
29 G ND3 1. 5 V _ 1 30 MU S B V C C 2 M L5 MU S B V C C
G ND4 N C (S M B _C LK )
4. SIM CO NN ? ? MI NI CAR D CON N
31 32 H C B 1 60 8 K F -1 21 T 25 60 mil
[ 3 3] MP C I E _T X N 3 _3 G P E R n0 N C (S M B _D A TA )
33 34
[ 33 ] M P C I E _ T XP 3 _ 3G 35 P E R p0 GN D 8 36
[ 3 3] M3 G_ D E T # G ND1 1 N C (U S B _ D -) M U S B _ P N 5 _ 3G [3 3 ]
37 38 M U S B _ P P 5 _3 G [ 3 3] MC 1 4 MC 13
39 N C6 N C (U S B _D +) 40
M3 . 3 V S 41 N C7 GN D 9 42 10 0 U _ 6 . 3V _ B 2 0 . 1U _1 6 V _0 4
N C8 N C (L E D _W W A N #)
M C2 MC 23 43 44
45 N C9 L E D _ W LA N # 46
Sheet 34 of 40
0 . 1 U _ 16 V _ 04 1 0U _1 0 V _ 08 47 N C1 0 N C (L E D _W P A N #) 48
N C1 1 1. 5 V _ 2 M1 . 5 V S
49 50 MJ _ U S B 1
51 N C1 2 GN D 1 0 52 ML 4 1
N C1 3 3. 3 V _ 1 M3 . 3 V S V +
Multi I/O Board 2/2

MG N D MG N D *W C M 20 1 2F 2 S -1 6 1T 0 3
M C2 0 1 2 M US B _ P N3 _ R 2
88 9 10 -5 2 04 [3 3 ] MU S B _P N 3 D A T A _L
1 5 0 U _ 6. 3 V _ V 4 3 M U S B _ P P 3 _R 3
[ 33 ] MU S B _ P P 3 D A T A _H
MG N D M GN D
4
s h ei l d
s h ei l d
G N D 2s hi e dl
G N D 4sh i e dl
M GN D G ND
GN D 1
GN D 3
C 10 7 B 3 -10 4 03 -Y
M1 . 5V S M3 . 3 V S
MC 4 M C5
La you t not e:
0 . 1U _1 6 V _0 4 0 . 1 U _ 1 6V _ 0 4 Place under the common M GN D MG N D
bead body and same as
MGN D M GN D USB trace requirment
RJ-11 MDC MODULE MJ_MDC1
? ? ? ? ? ? ? ? ? 12 11
2 1
? ? 2.5mm ? ?
MR 1 5 *1 0 mi l _ sh o rt M3 . 3 V
M J_ MD C 1
1 2 ML 1
GN D R E S E RV E D
MJ_MODEM1 3 4 H C B 1 00 5 K F -1 21 T 20
MODEM 3 /3 1 D EL RJ -11
[3 3 ] M A Z _S D OU T MR 11 5 A za l ai _ S D O
GN D
R E S E RV E D
3. 3 V Ma i n/ au x
6 10mil M3 . 3 V
1 2 2 2_ 0 4 7 8
[ 33 ] MA Z _ S Y N C A za l ai _ S Y N C G ND
* MC 12 FO R [ 33 ] MA Z _ S D I N 1
MA Z _ S D I N 1_ R 9
A za l ai _ S D I G ND
10
11 12
MJ _ MOD E M1
E MI MJ _ R J -1 1
[ 3 3 ] MA Z _ R S T# A za l ai _ R S T # A za il a _B C L K M A Z _B I T C LK [ 33 ]
Z 3 50 1 ML 2 B K 16 0 8H S 12 1 Z 3 5 03 1 8 8 01 8 -12 0 G MC 6 MC 7
1 Z 3 50 2 ML 3 B K 16 0 8H S 12 1 Z 3 5 04 2 TI P
2 RING 0 . 1U _1 6 V _0 4 22 P _ 50 V _ 0 4
85 2 0 5-0 2 00 1
P J S -02 F B 3 G
P I N GN D 1 ~ 2= MG N D MG N D MG N D MGN D M GN D
3/ 31 DE L
*M C1 5 F OR EM I
IH1 IH2 IH 6 IH 3
2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
? ? 6-34-D90T0-010-1 ? ? 6-34-M56AS-011 ? ? 6-34-M72SS-020 ? ? 6-34M72SS-010 M TH 3 15 D 1 1 1 MT H 3 1 5D 1 11 M T H 3 15 D 1 1 1 MT H 2 37 D 11 1
M GN D MG N D M GN D MG N D MG N D
FOR M720T FOR M720T FOR M730T
IH 7 IH 8 IH4 IH5 IH9 IH1 0 IH1 1
C 23 7 D 1 4 6 C 23 7 D 1 4 6 C 2 56 D 1 4 6 C 2 56 D 14 6 C 2 76 D 1 8 6 C 2 37 D 14 6 C 2 3 7D 14 6
[3 3 ] MU S B V C C 2
[ 3 3] M1 . 5 V S
MGN D MG N D MG N D MG N D MG N D MG N D M GN D
[ 3 3] M3 . 3 V
[ 3 3] M3 . 3 V S
Multi I/O Board 2/2 B - 35

Schematic Diagrams
Finger Printer Board
Finger Printer
F 3 .3 V
FJ _ FP1 F G P I O0 / I N T FR 19 1 . 5 K _ 04 F T C_ VD D
1
F US B _ P P 1 F U S B _ P P 1 _R FR 21 2 7 . 4 _1 % _ 04 FU SB_ PP1 F DAT A2 F R1 3 4 7K _ 0 4
FJ_FP1
1
2 F U S B _ P N1
3
F DAT A1 F R1 1 4 7K _ 0 4
4
4 F C2 0
8 52 0 1 -04 0 5 1 F DAT A0 F R1 2 4 7K _ 0 4
F GN D 4 7P _ 5 0 V _0 4
3/31 ? ? FUSB_PN1 BOT? ? -? Case ? ? F GP I O 1 F R7 3 30 K _ 0 4
F MI S O / MO D E 3 F R9 4 7K _ 0 4
F G ND
F GN D
F U4 TC S4 B 3 3P _5 0V_ 04
F U S B _ P N1 _ R FR 20 2 7 . 4 _1 % _ 04 F U S B _ P N1
A1 F E S D_ RIN G TC S4 C 2 2P _5 0V_ 04
E X T _R I N G 2 F TC _ V D D
B1 F G RID 0 /S E NS E F R1 8 F C1 9 F U3
CR IDO F MI S O / MO D E 3 5 8
S VD D
C1 F E S D _G N D 1 00 K _ 0 4 4 7P _ 5 0 V _0 4 F MO S I 2
R ING F MC S 1 Q
CS #
Sheet 35 of 40
D1 Z3701 FC 12 3 3 P _ 50 V _ 0 4 F G ND F MC L K 6
M U X OU T SCK 3 FC 8
W P#
E1 F A V DD F G ND F G ND
A V DD 0 . 1 U _ 1 6 V _0 4
Finger Printer
F1 F M CS
MC S FC 15 1 U _ 1 0 V _ 06 4 7
F G ND VSS H OL D #
G1
P A D _ V D D 1B M9 5 12 8 W M N 6 T P
Board
H1 F M I S O/ M OD E 3 F T C_ V D D F GN D F GN D
M ISO FC 16 0 . 1 U _ 1 6 V _0 4
J1 F G ND
D V DD F 3 .3 V
A2 F G P I O1 F D V DD 1
GP I O 1
B2
A G ND FC 21 FC 22
C2 FD ATA0 FL1
D AT A0
H C B 1 60 8 K F -1 2 1T 2 5 1 U _ 1 0 V _ 06 0 . 1 U _ 1 6 V _0 4
D2 FD ATA1 FC 9 F R1 0
D AT A1
0 . 1U _ 25 V _ X 7R _ 06 1 00 _ 0 6 F U2
E2 F G P I O0 / I N T F GR I D 0 / S E N S E Z3706 F E S D _R I N G 10mil 1
GP I O 0
F E S D _G N D F GN D 3
F2 F M CL K 2
MC LK
F R8 FC 7
G2 F U S B _ P N1 _ R R C al m p 05 0 2 B
U S B _ DN
3 30 K _ 0 6 * 47 P _ 5 0 V _0 6
H2 F U S B _ P P 1 _R
US B _ DP
J2 F M OS I
M OS I
A3 F P D _ RE G F G ND
P D _ RE G F 3 .3 V
T CS 4B Un st uf f
B3 F N RESE T FR 14 4 7 K _ 04
NRE S E T F T C_ VD D
T CS 4C 47 P_ 50 V_0 6
C3 FC 13 1 U _ 6 . 3 V _ 04 F Q1
DG ND F G ND
N D S 3 52 A P _ N L
S
D3 FD ATA2 F G _ F ET G F R1 6
D AT A2
E3 F E S D_ RIN G *0 _ 06
E X T _R I N G 1
F T C_ VD D F C1
F3
D
P V DD F A V DD
FC 14 1 U _ 1 0 V _ 06 F G ND 0 . 02 2 U _ 1 6 V _X 7 R _ 0 4
G3 F X IN T CS 4B Un st uf f
XT A L I N
F T C_ V D D FR 15 1 5 _ 06
H3 F 3 . 3V
P G ND F G ND 2 1 T CS 4C 1U _6 .3 V_0 4
FC 10 F C1 1
J3 F X O UT F R4 TC S4 B U ns tu ff
XT A L OU T 3 4 F GN D
1 U _ 1 0 V _ 06 0 . 1U _ 16 V _ 0 4
T CS 4 B F X1 3 3_ 0 6 TC S4 C 3 30 K_ 04
E
H S X 5 3 1S _ 1 2 MH z
F GN D B F Q2 F R6 F C6
F D VDD 1 2 S B 1 19 8 K R / T 1 4 6
F R1 7 *1 M_ 0 4 F G ND
*3 3 0K _0 4 *1 U _ 6 . 3 V _ 04
F C1 8 F C1 7 F C5 F 3 .3 V
C
FC 4
1 8P _ 5 0 V _0 6 1 8P _ 5 0 V _0 6 1 U _ 10 V _ 0 6 0 . 1U _ 16 V _ 0 4 F P D _ REG
F GN D
C
F G ND F G ND
F G ND F U1 FR 1 F R5
1 8 FD 1
A# VC C 3 3 0 K _0 4 0 _0 4 *R B 5 51 V -3 0
Z 3 70 2 2
B 7 Z 3 70 3
A
Rx /Cx
FR 3 FC 3 3 6 Z 3 70 4
F 3. 3 V CL R# Cx
FC 2 2 . 2U _ 6. 3 V _ 0 6 F E S D _G N D F GN D
1 0 0 K _0 4 1 U _ 1 0 V _ 06
4 5 Z 3 70 5 F R 2 1 0K _ 0 4 F G_ F E T
GN D Q
S N 7 4 L V C 1 G1 2 3 D C T
F GN D F GN D
B - 36 Finger Printer Board

Schematic Diagrams
Click Board
CLICK BOARD
C J_TP1
CC1 CTPBTN_ L_73
0 .1U_ 16V_04 1 CTPBTN_ R_72
CJ_T P1 2 CTPBTN_ L_72
C5V 3
CTPBTN_ R_73
4
1 5
CGND CJ_ TP2
CJ _TP2 6
1 7 CGND
CTP_DATA
2 4 8 CTP_C LK
CTP_CL K
3 1 9 CTP_D ATA
4 12 10
11 C5V
8520 1-04 051_ R
12
Sheet 36 of 40
CG ND 6-2 0-94A2 0-112 CC2
8 7151 -12 071G
0.1U _16V_0 4
CGND
Click Board
CSW 1~2
LIFT 2 4 RIGHT
KEY 1 3 KEY
CSW1 CSW2
TJG-5 33-S- V- T/R TJG-5 33-S- V- T/R
1 2 1 2
3 4 CTPBU TTON_ L 3 4 C TPBU TTON_ R
5
6
5
6
C GND C GND
CH1 CH4 C H3 CH2

2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH2 37D9 1 MTH23 7D91 MTH237 D91 MTH2 37D9 1
CG ND CGND CGND CGND CG ND CGND
For M720T For M730T

CR 1 0 _04 CR2 *0_04
CTPBU TTON_ L CTPBTN_L _72 CTPBUTTON_L C TPBTN _L_7 3
CR 3 0 _04 CR4 *0_04

CTPBU TTON_ R CTPBTN_R _72 CTPBUTTON_R C TPBTN _R_7 3
Click Board B - 37
Schematic Diagrams
M730T ODD Bridge Board
M730T ODD BRIDGE BOARD

Sheet 37 of 40
M730T ODD Bridge
Board
BJ_SATA1
S1
S2 BSATA_TXP1 BJ ODD 2
S3 BSATA_TXN 1
S4 12 BSATA_TXP1
S5 BSATA_R XN 1 11 BSATA_TXN1
S6 BSATA_R XP1 10
S7 9 BSATA_RXN1
8 BSATA_RXP1
7
6 BOD D_DETECT#
BGND 5
P1 BODD _D ETEC T# B5VS
P2 4
B5VS 3
P3 1.6A
P4 2
P5 1
P6 *88266-12
BGN D
*C18535-11305-L
BGND
BH1 BH 4 BH 2 BH 3
C236D110 C 236D 110 C 45D45N C 45D45N
BGN D BGND
B - 38 M730T ODD Bridge Board

Schematic Diagrams
M730T Audio Board
M730T AUDIO BRIDGE BOARD
AJSPDIF1
5
4
3 R
ASPDIFO AL4 *FCM1005KF- 102T02 2

6 L
AC1 1
*0.01U_16V_X7R_04 AR2 AC5 *C12103-10609
-L
*220_04 *100
0P_50V_X
7R_04
SP DIF OUT
Sheet 38 of 40
BLA CK
AAGND AAGND M730T Audio Board
3/31 ? ? ? NET? ? ? ? ? ,? ? ? ?
AJ_AUD2 AJMIC1
AMIC_
SENSE 5
1
ASPDIFO 4
2
AMIC1
-R AL1 *FCM1005KF-121T03 3 R
3
AMIC_SENSE
4 AMIC1-R AMIC1
-L AL2 *FCM1005KF-121T03 2
5 AMIC1-L 6 L
6
1
7
AHP_SENSE AC3 AC4 *C12103-D0609-L
8
AHP-R
9 AHP-L *680
P_50
V_X7
R_04 *680
P_50V_X7R_04
10 AHP_PLUG
MIC IN
11
12 PIN K 2 3
*871
51-12071G
AAGND AAGND 4
1
6 5
AJHP1
AHP_SENSE 5
4
AHP-R AL3 *FCM1005KF-121T03 3 R
AHP-L AL5 *FCM1005KF-121T03 2

6 L
AHP_PLUG 1
*C12103-606
09-L
AC2 AC6
HE AD PHON E
*680
P_50
V_X7
R_04 *680
P_50V_X7R_04
GREE N
AAGND
AH2 AH1 AH4 AH3

C315D110 C315D110 C45D45N C45D45N
AAGND AAGND
M730T Audio Board B - 39

Schematic Diagrams
Power Sequence Diagram
M720T V0.0 BOOT BLOCK DIAGRAM

9 CL _P WR OK
7 G FX _V RE N
PW R_ SW # 1 M ULT I I/ O BO AR D 13
DE LA Y_ PW RG D
NORTH BRIDGE GFX VR
? ? ? ? ? ? 8 V GF X_ CO RE S C4 72 B
Cantiga 17 H _C PU RS T#
V DD 3/ VD D5 3 .3 V 3
VR 5V 3
LT C3 85 0
Other
16 P LT _R ST #
Platform
EC DD _O N 2
1 .8 V 3 Devices
DR AM V R
Sheet 39 of 40
I TE 85 12 E 0 .9 VS M 6
S C4 86
SOUTH BRIDGE
Power Sequence PW R_ BT N# 4a
Diagram DE LAY
PM _R SM RS T# 4b
DD _ON
75 ms 15 Processor
SU SC # 5a H_P WR GD
Penryn
SU SB # 5b
D EL AY
C L_ PW RO K
CL _P WR OK 9 9 C L_ PW RO K
ICH9-M 16 PCI _R ST #
Other
PCI
1 50 m s
Devices
VC OR E_ ON 10 CL KE N# 12 V RM _P WR GD
VCORE VR
1 2- 1 CLK _P WR GD C lo ck G en era to r
VC OR E 11 SC 45 2 14 S B_ PW RO K
IC S9 LP R3 63E GL F
DE LA Y_ PW RGD 13
1. 5V S_ PW RGD 1. 8V _P WR GD
5b S US B# SL P_ M# 5b
9 CL _P WRO K
1. 5V S 6
A PL 59 13 6 1.0 5V S 1. 05 VM _P WR GD
6 3.3 VS SC 41 1 MOS FE T
M OS FE T
6 5VS FO R ME FOR M E
6 1 .0 5V M
6 3 .3 VM
B - 40 Power Sequence Diagram

Schematic Diagrams
Power Sequence v3.0
M720T V3.0 POWER ON SEQUENCE

560ms
1 PWR_SW#
164.7ms
2 DD_ON
370us
3 5V
515.4us
3 V5REF_SUS
568.0us
3 3.3V
6.215ms
3 1.8V
76.4ms
4a RSMRST# 206.4ms
120.8ms
Sheet 40 of 40
4b PWR_BTN# 85.6ms
174.4ms
5a SUSC#
Power Sequence
5b SUSB#
61.10us
365.6us
v3.0
6 5VS
371.5us
6 V5REF
482.8us
6 3.3VS
690.8us
6 1.05VS
1.5912ms
6 0.9VSM
3.932ms
6 1.5VS
7
8
920us
9 CL_PWROK ms
107.6ms
10 VCORE_ON 1.17V
2.64ms (950mV)
11 VCORE
3.32ms
12 VRM_PWRGD
2.981ms
12-1 CLK_PWRGD
9.36ms
13 DELAY_PWRGD
9.4ms
14 SB_PWROK
9.36ms
15 H_PWRGD
10.44ms
16 PLT_RST#
(1.05V)
17 H_CPURST# 105.6ms
(440mV)
12ms
Power Sequence v3.0 B - 41

Schematic Diagrams
B - 42

Clevo m720t m730t m728t m729t

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Clevo m720t m730t m728t m729t

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Preface

About this Manual

The following information is included:

Appendix A, Part Lists

the manufacturer for

IMPORTANT SAFETY INSTRUCTIONS

TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

This Computer’s Optical Device is a Laser Class 1 Product

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

ICH9-M 3/5 - GPIO, PWR Management .................................... B-16

The M720T/M728T/M729T/M730T series notebook is designed to be upgradeable. See “Disassembly” on page 2 - 1

Intel® Core™2 Duo Processor 45nm (45 Nanometer) Process Technology

Core Logic Intel GM45 + ICH9M Chipset

LCD M720T/M728T/M729T: M730T:

Memory 64-bit Wide DDRII (DDR2) Data Channel

Video Adapter Intel GM45 Integrated Video

Security Security (Kensington® Type) Lock Slot BIOS Password

BIOS One 32Mb SPI Flash ROM Phoenix™ BIOS

Audio High Definition Audio (HDA) Direct Sound 3D™ Compatible

Keyboard & Winkey Keyboard Built-In TouchPad with Scrolling Function

ExpressCard Slot One ExpressCard/34(54) Slot

Communication 10M/ 100/ 1000Mb Base-TX Ethernet LAN

Power Supports ACPI 3.0 Supports Wake on LAN

Battery 4 Cell Smart Lithium-Ion Battery Pack, 14.8V/2.4AH

Dimensions M720T/M728T/M729T: M730T:

cannot coexist. There LAN Mini-Card Module

8 Cell Smart Lithium-Ion Battery Pack

External Locator - Top View with LCD Panel Open Figure 1

External Locator - Top View with LCD Panel Open 1 - 5

Figure 2 External Locator - Front & Right side Views

1 - 6 External Locator - Front & Right side Views

External Locator - Left Side & Rear View

External Locator - Left Side & Rear View 1 - 7

External Locator - Bottom View

To prevent your com-

1 - 8 External Locator - Bottom View

Mainboard Overview - Top (Key Parts) Figure 7

Mainboard Overview - Top (Key Parts) 1 - 9

Figure 8 Mainboard Overview - Bottom (Key Parts)

1. CPU Socket (no

1 - 10 Mainboard Overview - Bottom (Key Parts)

Mainboard Overview - Top (Connectors) Figure 9

Mainboard Overview - Top (Connectors) 1 - 11

Figure 10 Mainboard Overview - Bottom (Connectors)

6. CPU Fan Cable

1 - 12 Mainboard Overview - Bottom (Connectors)

An example of these types of boxes are shown in the sidebar.

To remove the Battery: To remove the Wireless LAN Module:

To remove the Optical Device:

Removing the Battery

Removing the Battery 2 - 5

Removing the Hard Disk Drive

a. Locate the HDD bay Hard Disk Upgrade Process

New HDD’s are blank. Before you begin make sure:

2 - 6 Removing the Hard Disk Drive

3. Remove the hard disk bay cover 63 .

Removing the Hard Disk Drive 2 - 7

Figure 4 Removing the Optical (CD/DVD) Device

2 - 8 Removing the Optical (CD/DVD) Device

Removing the Optical (CD/DVD) Device 2 - 9

Memory Upgrade Process

Be careful not to touch a.

2 - 10 Removing the System Memory (RAM)