Sơ đồ chân kit basys 3

Câu 1: Thiết kế bộ đếm tiến thập phân, kết quả hiển thị LED 7 thanh bằng phương
pháp máy trạng thái
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau1 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau1;

architecture Behavioral of cau1 is

type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s: state;
----chia tan--
signal clk: std_logic;
begin
process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:=not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
----dem---
process(clk, rst)
begin
if rst='1' then s<=s0;
else
if clk'event and clk='1' then
case s is
when s0 => s <= s1;
when s1 => s <= s2;
when s2 => s <= s3;
when s3 => s <= s4;
when s4 => s <= s5;
when s5 => s <= s6;
when s6 => s <= s7;
when s7 => s <= s8;
when s8 => s <= s9;
 when others => s <= s0;
end case;
end if;
end if;
end process;
----giai ma----
process(s)
begin
case s is
when s0 => Q <= x"c0";
when s1 => Q <= x"f9";
when s2 => Q <= x"a4";
when s3 => Q <= x"b0";
when s4 => Q <= x"99";
when s5 => Q <= x"92";
when s6 => Q <= x"82";
when s7 => Q <= x"f8";
when s8 => Q <= x"80";
when others => Q <= x"90";
end case;
end process;
end Behavioral;
Câu 2: Thiết kế bộ đếm lùi thập phân, kết quả hiển thị LED 7 thanh bằng cách sử
dụng nhiều proccess
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau2 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau2;

architecture Behavioral of cau2 is

signal d: integer range 0 to 9;
signal clk: std_logic;
begin
chiatan: process(clock, rst)
variable dem2: integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst)
variable d_tam: integer range 0 to 9;
begin
if rst='1' then d_tam := 0;
else
if clk'event and clk='1' then
if d_tam=0 then d_tam:=9;
else d_tam:= d_tam-1;
end if;
end if;
end if;
d<= d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= X"C0";
when 1 => Q <= X"F9";
when 2 => Q <= X"A4";
when 3 => Q <= X"B0";
 when 4 => Q <= X"99";
when 5 => Q <= X"92";
when 6 => Q <= X"82";
when 7 => Q <= X"F8";
when 8 => Q <= X"80";
when 9 => Q <= X"90";
when others => Q <= "XXXXXXXX";
end case;
end process;
end Behavioral;
Câu 3: Thiết kế bộ đếm cho phép chọn đếm tiến hoặc đếm lùi theo mã thập phân,
kết quả hiển thị LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau3 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
A : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau3;

architecture Behavioral of cau3 is

signal d: integer range 0 to 9;
begin
dem: process(clk,rst,A)
variable d_tam: integer range 0 to 9;
begin
if rst='1' then d_tam := 0;
else
if clk'event and clk='1' then
if A ='1' then
if d_tam = 9 then d_tam := 0;
else d_tam:=d_tam + 1;
end if;
else
 if d_tam = 0 then d_tam := 9;
else d_tam:=d_tam - 1;
end if;
end if;
end if;
end if;
d <= d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= X"C0";
when 1 => Q <= X"F9";
when 2 => Q <= X"A4";
when 3 => Q <= X"B0";
when 4 => Q <= X"99";
when 5 => Q <= X"92";
when 6 => Q <= X"82";
when 7 => Q <= X"F8";
when 8 => Q <= X"80";
when 9 => Q <= X"90";
when others => Q <= "XXXXXXXX";
end case;
end process;
end Behavioral;
Câu 4: Thiết kế bộ đếm tiến nhị phân Kđ = 255, kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau4 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (7 downto 0));
end cau4;
architecture Behavioral of cau4 is
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b: std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst)
variable d_tam: integer range 0 to 254:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam =254 then d_tam:=0;
else d_tam:=d_tam + 1;
end if;
end if;
end if;
A <= conv_std_logic_vector(d_tam,8);
end process;
end Behavioral;
Câu 5: Thiết kế bộ đếm lùi nhị phân Kđ = 255, kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau5 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau5;

architecture Behavioral of cau5 is

signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst)
variable d_tam: integer range 0 to 254:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam = 254 then d_tam:=0;
else d_tam:= d_tam -1;
end if;
end if;
 end if;
Q <= conv_std_logic_vector(d_tam,8);
end process;
end Behavioral;
Câu 6: Thiết kế bộ đếm cho phép chọn đếm tiến hoặc đếm lùi theo mã nhị phân
Kđ=128, kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau6 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
A : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (6 downto 0));
end cau6;

architecture Behavioral of cau6 is

signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst,A)
variable d_tam: integer range 0 to 127:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if A='1' then
if d_tam=127 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
else
if d_tam=0 then d_tam:=127;
else d_tam:=d_tam-1;
end if;
end if;
end if;
end if;
Q <= conv_std_logic_vector(d_tam,7);
end process;
end Behavioral;
Câu 7: Thiết kế mạch đếm theo mã vòng 16 bit , kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cau7 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0));
end cau7;

architecture Behavioral of cau7 is

signal d: integer range 0 to 15;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

dem:process(clk,rst)
variable d_tam: integer range 0 to 15:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam=15 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
end if;
end if;
d <= d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= "0000000000000001";
when 1 => Q <= "0000000000000010";
when 2 => Q <= "0000000000000100";
when 3 => Q <= "0000000000001000";
when 4 => Q <= "0000000000010000";
 when 5 => Q <= "0000000000100000";
when 6 => Q <= "0000000001000000";
when 7 => Q <= "0000000010000000";
when 8 => Q <= "0000000100000000";
when 9 => Q <= "0000001000000000";
when 10 => Q <= "0000010000000000";
when 11 => Q <= "0000100000000000";
when 12 => Q <= "0001000000000000";
when 13 => Q <= "0010000000000000";
when 14 => Q <= "0100000000000000";
when 15 => Q <= "1000000000000000";
when others => Q <= "XXXXXXXXXXXXXXXX";
end case;
end process;
Câu 8: Thiết kế mạch đếm theo mã Johnson 8 bit , kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau8 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau8;

architecture Behavioral of cau8 is

signal d: integer range 0 to 15;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
 b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

dem:process(clk,rst)
variable d_tam: integer range 0 to 15:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam = 15 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
end if;
end if;
d<=d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= "00000000";
when 1 => Q <= "00000001";
when 2 => Q <= "00000011";
when 3 => Q <= "00000111";
when 4 => Q <= "00001111";
when 5 => Q <= "00011111";
when 6 => Q <= "00111111";
when 7 => Q <= "01111111";
when 8 => Q <= "11111111";
when 9 => Q <= "11111110";
when 10 => Q <= "11111100";
 when 11 => Q <= "11111000";
when 12 => Q <= "11110000";
when 13 => Q <= "11100000";
when 14 => Q <= "11000000";
when 15 => Q <= "10000000";
when others => Q <= "XXXXXXXX";
end case;
end process;
end Behavioral;
Câu 9: Thiết kế bộ đếm tiến các số chẵn từ 0  100 theo mã nhị phân, kết quả hiển
thị LED đơn

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity cau9 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (6 downto 0));
end cau9;

architecture Behavioral of cau9 is

signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
 dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

dem:process(clk,rst)
variable d_tam: integer range 0 to 100:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam rem 2 = 0 then
if d_tam =100 then d_tam:=0;
else d_tam:=d_tam+2;
end if;
end if;
end if;
end if;
Q<= conv_std_logic_vector(d_tam,7);
end process;
end Behavioral;
Câu 10: Thiết kế bộ đếm lùi các số lẻ từ 99  1 theo mã nhị phân, kết quả hiển thị
LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau10 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (6 downto 0));
end cau10;

architecture Behavioral of cau10 is

signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

dem:process(clk,rst)
variable d_tam: integer range 1 to 99;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam rem 2 /= 0 then
if d_tam =1 then d_tam:=99;
else d_tam:= d_tam-2;
end if;
end if;
end if;
end if;
Q<=conv_std_logic_vector(d_tam,7);
end process;
end Behavioral;
Câu 11: Thiết kế bộ đếm tiến, thập phân cho phép chọn đếm chẵn hoặc đếm lẻ, kết
quả hiển thị LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau11 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
A : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau11;

architecture Behavioral of cau11 is

signal d: integer range 0 to 9;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst,A)
variable d_tam: integer range 0 to 9:=0;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
 if A='1' then
if d_tam rem 2 =0 then
if d_tam=8 then d_tam:=0;
else d_tam:=d_tam+2;
end if;
else
d_tam:=d_tam+1;
end if;
else
if d_tam rem 2/=0 then
if d_tam=9 then d_tam:=1;
else d_tam:=d_tam+2;
end if;
else
d_tam:=d_tam+1;
end if;
end if;
end if;
end if;
d<=d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= x"C0";
when 1 => Q <= x"F9";
when 2 => Q <= x"A4";
when 3 => Q <= x"B0";
when 4 => Q <= x"99";
when 5 => Q <= x"92";
when 6 => Q <= x"82";
when 7 => Q <= x"F8";
when 8 => Q <= x"80";
when 9 => Q <= x"90";
when others => Q <= "XXXXXXXX";
 end case;
end process;
end Behavioral;
Câu 12: Thiết kế mạch quét LED 7 thanh để hiển thị số 1234 trên kit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau12 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau12;

architecture Behavioral of cau12 is

type state is (s0,s1,s2,s3);
signal s:state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem:integer range 0 to 50000;
begin
if rst='1' then dem:=0;
elsif clock'event and clock='1' then
if dem=50000 then
dem:=0;
clk<='0';
else
dem:=dem+1;
if dem=25000 then
clk<='1';
end if;
end if;
end if;
end process;
c2:process(clk,s)
begin
if clk'event and clk='1' then
case s is
when s0=>s<=s1; led7<=x"a4"; Q<="1011";
when s1=>s<=s2; led7<=x"b0"; Q<="1101";
when s2=>s<=s3; led7<=x"99"; Q<="1110";
when others=>s<=s0; led7<=x"f9"; Q<="0111";
end case;
end if;
end process;
end Behavioral;
Câu 13: Thiết kế mạch kiểm tra chuỗi dữ liệu vào nối tiếp. Đầu ra bằng 1 khi có 3
bit 1 vào liên tiếp. Đầu ra bằng 0 trong các trường hợp còn lại.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau13 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
D : in STD_LOGIC;
Y : out STD_LOGIC);
end cau13;

architecture Behavioral of cau13 is

type state is (s0,s1,s2,s3);
signal s: state;
begin
c1:process(clk,rst,D)
begin
if rst = '1' then s <= s0;
else
if clk'event and clk = '1' then
case s is
when s0 => if D='0' then s <= s0;
else s <= s1;end if;
when s1 => if D='0' then s<= s2;
 else s <= s3;end if;
when s2 => if D='0' then s <= s0;
else s <= s1;end if;
when others => if D='0' then s <= s2;
else s <= s3;end if;
end case;
end if;
end if;
end process;
c2:process(s,D,rst,clk)
begin
if clk'event and clk = '1' then
if D = '1' and s = s3 and rst = '0' then
y <= '1';
else
y <= '0';
end if;
end if;
end process;
end Behavioral;
Câu 14: Thiết kế mạch điều khiển 16 LED đơn sáng lan từ giữa sang 2 bên
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau14 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0));
end cau14;

architecture Behavioral of cau14 is

signal d: integer range 0 to 8;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

c1:process(clk,rst)
variable d_tam: integer range 0 to 8;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam = 8 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
end if;
end if;
d<=d_tam;
end process;
c2:process(d)
begin
case d is
when 0 => Q <= "0000000000000000";
when 1 => Q <= "0000000110000000";
when 2 => Q <= "0000001111000000";
when 3 => Q <= "0000011111100000";
when 4 => Q <= "0000111111110000";
 when 5 => Q <= "0001111111111000";
when 6 => Q <= "0011111111111100";
when 7 => Q <= "0111111111111110";
when 8 => Q <= "1111111111111111";
when others => Q <= "XXXXXXXXXXXXXXXX";
end case;
end process;
end Behavioral;
Câu 15: Thiết kế mạch điều khiển 16 LED đơn sáng lan từ 2 bên về giữa theo
phương pháp máy trạng thái
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau15 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0));
end cau15;

architecture Behavioral of cau15 is

type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal s: state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
 end if;
clk<=b;
end process;

c1:process(clk,rst)
begin
if rst='1' then s<=s0;
else
if clk'event and clk='1' then
case s is
when s0=>s<=s1;
when s1=>s<=s2;
when s2=>s<=s3;
when s3=>s<=s4;
when s4=>s<=s5;
when s5=>s<=s6;
when s6=>s<=s7;
when s7=>s<=s8;
when others =>s<=s0;
end case;
end if;
end if;
end process;
c2:process(s)
begin
case s is
when s0 => Q <= "0000000000000000";
when s1 => Q <= "1000000000000001";
when s2 => Q <= "1100000000000011";
when s3 => Q <= "1110000000000111";
when s4 => Q <= "1111000000001111";
when s5 => Q <= "1111100000011111";
when s6 => Q <= "1111110000111111";
when s7 => Q <= "1111111001111111";
when others => Q <= "1111111111111111";
 end case;
end process;
end Behavioral;
Câu 16: Thiết kế bộ đếm theo mã Gray 4 bit, kết quả hiển thị LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau16 is
Port ( rst : in STD_LOGIC;
clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end cau16;

architecture Behavioral of cau16 is

signal d: integer range 0 to 15;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

dem:process(rst,clk)
variable d_tam: integer range 0 to 15;
begin
 if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
if d_tam=15 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
end if;
end if;
d<=d_tam;
end process;
mahoa:process(d)
begin
case d is
when 0 => Q <= "0000";
when 1 => Q <= "0001";
when 2 => Q <= "0011";
when 3 => Q <= "0010";
when 4 => Q <= "0110";
when 5 => Q <= "0111";
when 6 => Q <= "0101";
when 7 => Q <= "0100";
when 8 => Q <= "1100";
when 9 => Q <= "1101";
when 10 => Q <= "1111";
when 11 => Q <= "1110";
when 12 => Q <= "1010";
when 13 => Q <= "1011";
when 14 => Q <= "1001";
when others => Q <= "1000";
end case;
end process;
end Behavioral;
Câu 17: Thiết kế mạch điều khiển đèn giao thông. Yêu cầu đèn đỏ sáng 10s, đèn
xanh sáng 7s, đèn vàng sáng 3s, số giây được đếm ngược về 0 và hiển thị trên LED
7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau17 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (2 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau17;

architecture Behavioral of cau17 is

signal d: integer range 0 to 19;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;

c1:process(clk,rst)
variable d_tam: integer range 0 to 19;
begin
if rst='1' then d_tam:=0;
else
if clk'event and clk='1' then
 if d_tam=19 then d_tam:=0;
else d_tam:=d_tam+1;
end if;
end if;
end if;
d<=d_tam;
end process;
c2:process(d)
begin
case d is
when 0 =>led7<= x"90";Q<="100";
when 1 =>led7<= x"80";Q<="100";
when 2 =>led7<= x"f8";Q<="100";
when 3 =>led7<= x"82";Q<="100";
when 4 =>led7<= x"92";Q<="100";
when 5 =>led7<= x"99";Q<="100";
when 6 =>led7<= x"b0";Q<="100";
when 7 =>led7<= x"a4";Q<="100";
when 8 =>led7<= x"f9";Q<="100";
when 9 =>led7<= x"c0";Q<="100";
when 10 =>led7<= x"82";Q<="010";
when 11 =>led7<= x"92";Q<="010";
when 12 =>led7<= x"99";Q<="010";
when 13 =>led7<= x"b0";Q<="010";
when 14 =>led7<= x"a4";Q<="010";
when 15 =>led7<= x"f9";Q<="010";
when 16 =>led7<= x"c0";Q<="010";
when 17 =>led7<= x"a4";Q<="001";
when 18 =>led7<= x"f9";Q<="001";
when others =>led7<= x"c0";Q<="001";
end case;
end process;
end Behavioral;
Câu 18: Thiết kế thanh ghi dịch vào nối tiếp, ra song song 8 bít bằng phương pháp
sử dụng proccess
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau18 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end cau18;

architecture Behavioral of cau18 is

signal tam: std_logic_vector(7 downto 0);
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dich:process(D,clk,rst)
begin
if rst='1' then tam<=x"00";
else
if clk'event and clk='1' then
tam(0)<=D;
tam(1)<=tam(0);
 tam(2)<=tam(1);
tam(3)<=tam(2);
tam(4)<=tam(3);
tam(5)<=tam(4);
tam(6)<=tam(5);
tam(7)<=tam(6);
end if;
end if;
Q <= tam;
end process;
end Behavioral;
Câu 19: Thiết kế mạch cộng 2 số nhị phân 2 bít, kết quả hiển thị LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau19 is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0));
end cau19;

architecture Behavioral of cau19 is

signal C :std_logic;
signal tam :std_logic_vector(1 downto 0);
begin
c1:process(A,B,Cin)
begin
tam(0)<=A(0) xor B(0) xor Cin;
C<= (B(0) and Cin) or (A(0) and (B(0) xor Cin));
end process;
c2:process(A,B,C)
begin
tam(1)<=A(1) xor B(1) xor C;
Cout<= (B(1) and C) or (A(1) and (B(1) xor C));
end process;
c3:process(tam)
begin
case tam is
when "00" =>led<=x"c0";
when "01" =>led<=x"f9";
when "10" =>led<=x"a4";
when others =>led<=x"b0";
end case;
end process;
end Behavioral;
Câu 20: Thiết kế mạch trừ 2 số nhị phân 3 bít, kết quả hiển thị LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau20 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0));
end cau20;

architecture Behavioral of cau20 is

signal C:std_logic_vector(1 downto 0);
signal tam:std_logic_vector(2 downto 0);

begin
c1:process(A,B,Cin)
begin
tam(0) <= A(0)xor B(0) xor Cin;
c(0) <= (B(0) and Cin) or ((not A(0)) and (B(0) xor Cin));
end process;
c2:process(A,B,C)
begin
tam(1) <= A(1)xor B(1) xor C(0);
c(1) <= (B(1) and C(0)) or ((not A(1)) and (B(1) xor C(0)));
end process;
c3:process(A,B,C)
begin
tam(2) <= A(2)xor B(2) xor C(1);
Cout <= (B(2) and C(1)) or ((not A(2)) and (B(2) xor C(1)));
end process;
c4:process(tam)
begin
case tam is
when "000" =>led<=x"c0";
when "001" =>led<=x"f9";
when "010" =>led<=x"a4";
when "011" =>led<=x"b0";
when "100" =>led<=x"99";
when "101" =>led<=x"92";
when "110" =>led<=x"82";
when others =>led<=x"f8";
end case;
end process;
end Behavioral;
Câu 21: Thiết kế và mô phỏng mạch cộng đầy đủ 3 bit sử dụng component là bộ
cộng đầy đủ 1 bit. Kết quả hiển thị dạng nhị phân trên LED đơn.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau21 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
led : out STD_LOGIC_VECTOR (2 downto 0));
end cau21;

architecture Behavioral of cau21 is

signal C: std_logic_vector(1 downto 0);
component cong1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
out1 : out STD_LOGIC );
end component;
begin
c1: cong1 port map (A(0),B(0),Cin,C(0),led(0));
c2: cong1 port map (A(1),B(1),C(0),C(1),led(1));
c3: cong1 port map (A(2),B(2),C(1),Cout,led(2));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cong1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
out1 : out STD_LOGIC );
end cong1;

architecture Behavioral of cong1 is

begin
process(A,B,Cin)
begin
out1 <= A xor B xor Cin;
Cout <= ((B and Cin) or(A and (B xor Cin)));
end process;
end Behavioral;
Câu 22: Cho hai số đầu vào A, B (3 bit). Thiết kế mạch điện thực hiện một trong
các chức năng: A+B; A+1; B+1 tùy theo giá trị của đầu vào lựa chọn chức năng.
Kết quả hiển thị trên LED đơn và LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity cau22 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
C : in STD_LOGIC_VECTOR (1 downto 0);
led : out STD_LOGIC_VECTOR (3 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau22;

architecture Behavioral of cau22 is

signal d_tam:std_logic_vector(3 downto 0);
begin
c1:process(A,B,C)
begin
if C="01" then
d_tam <= ('0'&A) + ('0'&B);
elsif C="10" then
d_tam <= ('0'&A) + '1';
elsif C="11" then
d_tam <= ('0'&B) + '1';
end if;
end process;
c2:process(d_tam)
begin
case d_tam is
when "0000" =>led7<=x"c0"; led<="0000";
when "0001" =>led7<=x"f9"; led<="0001";
when "0010" =>led7<=x"a4"; led<="0010";
 when "0011" =>led7<=x"b0"; led<="0011";
when "0100" =>led7<=x"99"; led<="0100";
when "0101" =>led7<=x"92"; led<="0101";
when "0110" =>led7<=x"82"; led<="0110";
when "0111" =>led7<=x"f8"; led<="0111";
when "1000" =>led7<=x"80"; led<="1000";
when "1001" =>led7<=x"90"; led<="1001";
when "1010" =>led7<=x"88"; led<="1010";
when "1011" =>led7<=x"83"; led<="1011";
when "1100" =>led7<=x"c6"; led<="1100";
when "1101" =>led7<=x"a1"; led<="1101";
when "1110" =>led7<=x"86"; led<="1110";
when others =>led7<=x"8e"; led<="1111";
end case;
end process;
end Behavioral;
Câu 23 : Thiết kế và mô phỏng mạch cộng đầy đủ 3 bit sử dụng nhiều Process (mỗi
proces là bộ cộng đầy đủ 1 bit). Kết quả hiển thị dạng nhị phân trên LED đơn và
trên LED 7 thanh.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau23 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
led : out STD_LOGIC_VECTOR (2 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau23;

architecture Behavioral of cau23 is

signal c:std_logic_vector(1 downto 0);
signal tam:std_logic_vector(2 downto 0);
begin
c1:process(A,B,Cin)
begin
tam(0)<= A(0) xor B(0) xor Cin;
c(0)<= ((B(0) and Cin) or (A(0) and (B(0) xor Cin)));
end process;
c2:process(A,B,c)
begin
tam(1)<= A(1) xor B(1) xor c(0);
c(1)<= ((B(1) and c(0)) or (A(1) and (B(1) xor c(0))));
end process;
c3:process(A,B,c)
begin
tam(2)<= A(2) xor B(2) xor c(1);
Cout<= ((B(2) and c(1)) or (A(2) and (B(2) xor c(1))));
end process;
c4:process(tam)
begin
case tam is
when "000" =>led7<=x"c0"; led<="000";
when "001" =>led7<=x"f9"; led<="001";
when "010" =>led7<=x"a4"; led<="010";
when "011" =>led7<=x"b0"; led<="011";
when "100" =>led7<=x"99"; led<="100";
when "101" =>led7<=x"92"; led<="101";
when "110" =>led7<=x"82"; led<="110";
when others =>led7<=x"88"; led<="111";
end case;
end process;
end Behavioral;
Câu 24: Hãy thiết kế bộ đếm tiến BCD và quả hiển thị dạng nhị phân trên LED đơn
và dạng thập phân trên LED 7 thanh. Mạch thiết kế theo máy trạng thái và được
thực thi trên KIT BASYS 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau24 is
Port ( clock : in STD_LOGIC;
 rst : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau24;

architecture Behavioral of cau24 is

type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst)
begin
if rst='1' then s<=s0;
elsif clk'event and clk='1' then
case s is
when s0=>s<=s1;
when s1=>s<=s2;
when s2=>s<=s3;
when s3=>s<=s4;
when s4=>s<=s5;
 when s5=>s<=s6;
when s6=>s<=s7;
when s7=>s<=s8;
when s8=>s<=s9;
when others =>s<=s0;
end case;
end if;
end process;
mahoa:process(s)
begin
case s is
when s0=>led7<=x"c0"; led<="0000";
when s1=>led7<=x"f9"; led<="0001";
when s2=>led7<=x"a4"; led<="0010";
when s3=>led7<=x"b0"; led<="0011";
when s4=>led7<=x"99"; led<="0100";
when s5=>led7<=x"92"; led<="0101";
when s6=>led7<=x"82"; led<="0110";
when s7=>led7<=x"f8"; led<="0111";
when s8=>led7<=x"80"; led<="1000";
when others=>led7<=x"90"; led<="1001";
end case;
end process;
end Behavioral;
Câu 25: Cho hai số đầu vào A, B (3 bit). Thiết kế mạch điện thực hiện một trong
các chức năng: A+1; B+1; A and B; và A or B tùy theo giá trị của đầu vào lựa
chọn chức năng . Kết quả hiển thị trên LED đơn và LED 7 thanh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity cau25 is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
C : in STD_LOGIC_VECTOR (1 downto 0);
 led : out STD_LOGIC_VECTOR (3 downto 0);
led7 : out STD_LOGIC_VECTOR (7 downto 0));
end cau25;

architecture Behavioral of cau25 is

signal tam:std_logic_vector(3 downto 0);
begin
c1:process(A,B,C)
begin
if C="00" then
tam <= ('0'&A) or ('0'&B);
elsif C="01" then
tam <= ('0'&A) and ('0'&B);
elsif C="10" then
tam <= ('0'&A) + 1;
elsif C="11" then
tam <= ('0'&B) + 1;
end if;
end process;
c2:process(tam)
begin
case tam is
when "0000" =>led7<=x"c0"; led<="0000";
when "0001" =>led7<=x"f9"; led<="0001";
when "0010" =>led7<=x"a4"; led<="0010";
when "0011" =>led7<=x"b0"; led<="0011";
when "0100" =>led7<=x"99"; led<="0100";
when "0101" =>led7<=x"92"; led<="0101";
when "0110" =>led7<=x"82"; led<="0110";
when "0111" =>led7<=x"f8"; led<="0111";
when "1000" =>led7<=x"80"; led<="1000";
when "1001" =>led7<=x"90"; led<="1001";
when "1010" =>led7<=x"88"; led<="1010";
when "1011" =>led7<=x"83"; led<="1011";
when "1100" =>led7<=x"c6"; led<="1100";
 when "1101" =>led7<=x"a1"; led<="1101";
when "1110" =>led7<=x"86"; led<="1110";
when others =>led7<=x"8e"; led<="1111";
end case;
end process;
end Behavioral;
Câu 26: Thiết kế bộ đếm tiến các số chẵn từ 0 --> 20 theo mã nhị phân bằng
phương pháp máy trạng thái. Kết quả đếm hiển thị trên LED đơn
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau26 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (4 downto 0));
end cau26;

architecture Behavioral of cau26 is

type state is (s0,s2,s4,s6,s8,s10,s12,s14,s16,s18,s20);
signal s:state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst)
begin
if rst='1' then s<=s0;
elsif clk'event and clk='1' then
case s is
when s0=>s<=s2;
when s2=>s<=s4;
when s4=>s<=s6;
when s6=>s<=s8;
when s8=>s<=s10;
when s10=>s<=s12;
when s12=>s<=s14;
when s14=>s<=s16;
when s16=>s<=s18;
when s18=>s<=s20;
when others=>s<=s0;
end case;
end if;

end process;
mahoa:process(s)
begin
case s is
when s0=>Q<="00000";
when s2=>Q<="00010";
when s4=>Q<="00100";
when s6=>Q<="00110";
when s8=>Q<="01000";
when s10=>Q<="01010";
when s12=>Q<="01100";
when s14=>Q<="01110";
when s16=>Q<="10000";
when s18=>Q<="10010";
when others =>Q<="10100";
 end case;
end process;
end Behavioral;
Câu 27: Thiết kế DFF. Sử dụng DFF như component để thiết kế thanh ghi dịch vào
nối tiếp, ra song song
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity main is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
D : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0));
end main;

architecture Behavioral of main is

component DFF is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
out1 : out STD_LOGIC);
end component;
signal tg: STD_LOGIC_VECTOR (7 downto 0);
begin
c1: DFF port map (clk,rst,D,tg(0));
c2: DFF port map (clk,rst,tg(0),tg(1));
c3: DFF port map (clk,rst,tg(1),tg(2));
c4: DFF port map (clk,rst,tg(2),tg(3));
c5: DFF port map (clk,rst,tg(3),tg(4));
c6: DFF port map (clk,rst,tg(4),tg(5));
c7: DFF port map (clk,rst,tg(5),tg(6));
c8: DFF port map (clk,rst,tg(6),tg(7));
led <= tg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity DFF is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
out1 : out STD_LOGIC);
end DFF;

architecture Behavioral of DFF is

begin
process(clk,rst,d)
begin
if rst = '1' then out1<= '0';
elsif clk'event and clk='1' then
out1<= d;
end if;
end process;
end Behavioral;
Câu 28: Thiết kế JKFF. Sử dụng JKFF như component để thiết kế bộ đếm tiến nhị
phân 4 bít
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity main is
Port ( clk : in STD_LOGIC;
 rst : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 downto 0));
end main;

architecture Behavioral of main is

component JK is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
out1 : out STD_LOGIC);
end component;
signal temp :STD_LOGIC_VECTOR (3 downto 0);
begin
c1: JK port map (clk,rst,J,K,temp(0));
c2: JK port map (clk,rst,temp(0),temp(0),temp(1));
c3: JK port map (clk,rst,temp(0)and temp(1),temp(0)and temp(1),temp(2));
c4: JK port map (clk,rst,temp(0)and temp(1)and temp(2),temp(0)and temp(1)and
temp(2),temp(3));
led <= temp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity JK is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
j : in STD_LOGIC;
 k : in STD_LOGIC;
out1 : out STD_LOGIC);
end JK;

architecture Behavioral of JK is
signal tg : STD_LOGIC:='0';
begin
process(clk,rst,j,k)
begin
if rst ='1' then tg <= '0';
elsif clk'event and clk='1' then
tg <= (j and not(tg)) or (tg and not(k));
end if;
out1<=tg;
end process;
end Behavioral;

Câu 29: Thiết kế mạch điều khiển máy pha café tự động: chờ khởi động( 1đèn
xanh sáng)  trộn café và sữa trong 2s ( 2 đèn xanh sáng)  hòa tan café+ sữa+
nước trong 5s (3 đèn xanh sáng)  kết thúc (đèn đỏ sáng 1s)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau29 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
X : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end cau29;

architecture Behavioral of cau29 is

type state is (s0,s1,s2,s3);
signal s: state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst,X)
variable d: integer range 0 to 4:=0;
begin
if rst='1' then s<=s0;
else
if clk'event and clk='1' then
if d=0 then
case s is
when s0=>if X='1' then
s<=s1; d:=1;
end if;
when s1=>s<=s2; d:=4;
when s2=>s<=s3; d:=0;
when others =>s<= s0;
end case;
else
d:=d-1;
end if;
end if;
end if;
end process;
mahoa:process(s)
begin
case s is
when s0=>Q<="1000";
when s1=>Q<="1100";
when s2=>Q<="1110";
when s3=>Q<="0001";
when others =>Q<="XXXX";
end case;
end process;
end Behavioral;
Câu 30: Thiết kế mạch điều khiển máy giặt quần áo tự động : chờ khởi động 
bơm nước trong 5 phút (1 đèn xanh sáng)  giặt trong 7 phút (2 đèn xanh sáng) 
tháo nước trong 2 phút ( 1đèn vàng sáng)  bơm nước trong 5 phút (1 đèn xanh
sáng)  xả trong 10 phút (3 đèn xanh sáng)  tháo nước trong 2 phút (1 vàng
sáng)  vắt trong 5 phút (2 đèn vàng sáng)  kết thúc (1 đèn đỏ sáng trong 1
phút)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cau30 is
Port ( clock : in STD_LOGIC;
rst : in STD_LOGIC;
kd : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (5 downto 0));
end cau30;

architecture Behavioral of cau30 is

type state is (ckd,bom1,giat,thao1,bom2,xa,thao2,vat,ketthuc);
signal s:state;
signal clk:std_logic;
begin
chiatan:process(clock,rst)
variable dem2:integer range 0 to 300000000;
variable b:std_logic;
begin
 if rst='1' then dem2:=0;
elsif clock'event and clock='1' then
if dem2=25000000 then
dem2:=0;
b:= not b;
else
dem2:=dem2+1;
end if;
end if;
clk<=b;
end process;
dem:process(clk,rst,kd)
variable d:integer range 0 to 9:=0;
begin
if rst='1' then s<=ckd;
elsif clk'event and clk='1' then
if d=0 then
case s is
when ckd => if kd='1' then
s<=bom1; d:=4;
end if;
when bom1 =>s<=giat;d:=6;
when giat =>s<=thao1;d:=1;
when thao1 =>s<=bom2;d:=4;
when bom2 =>s<=xa;d:=9;
when xa =>s<=thao2;d:=1;
when thao2 =>s<=vat;d:=4;
when vat =>s<=ketthuc;d:=0;
when others =>s<=ckd;
end case;
else
d:=d-1;
end if;
end if;
end process;
mahoa:process(s)
begin
case s is
when ckd =>Q<="000000";
when bom1 =>Q<="000001";
when bom2 =>Q<="000001";
when giat =>Q<="000011";
when thao1 =>Q<="001000";
when thao2 =>Q<="001000";
when xa =>Q<="000111";
when vat =>Q<="011000";
when others =>Q<="100000";
end case;
end process;
end Behavioral;