Bài 2: Viết chương trình mô tả bộ đếm lùi Mod 9 (có CLK, CLR,

Pause)
Nguyên lí hoạt động của mạch
Code VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bai2 is
port (CLK: in std_logic;
CLR: in std_logic;
PAUSE: in std_logic;
count: out std_logic_vector(3 downto 0));
end hai;

architecture Behavioral of bai2 is

Signal counter: std_logic_vector(3 downto 0) := "1000";
begin

process (CLK, CLR, PAUSE)

begin
if CLR = '1' then counter <= "0000";
end if;
 if rising_edge(CLK) and CLR = '0' and PAUSE = '0' then
if (counter = "0000") then
counter <= "1000";
else counter <= counter - 1;
end if;
end if;
end process;
count <= counter;
end Behavioral;
Test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mot is
end mot;

architecture Behavioral of mot is

component bai2 is
port ( CLK : in std_logic;
CLR : in std_logic;
 PAUSE : in std_logic;
count : out std_logic_vector(3 downto 0));
end component;

signal CLK,CLR,PAUSE: std_logic := '0';

signal count: std_logic_vector(3 downto 0);
begin
uut: hai port map(
CLK => CLK,
CLR => CLR,
PAUSE => PAUSE,
count => count
);
CLK <= not CLK after 10ns ;
pausess: process
begin
PAUSE <= '0'; wait for 500ns;
PAUSE <= '1'; wait for 80ns;
end process;

clearr: process
begin
CLR <= '0'; wait for 700ns;
CLR <= '1'; wait for 10ns;
 end process;

end Behavioral;

Bài 4: Viết chương trình mô tả bộ phân kênh 1:16 (Enable hoạt

động ở mức thấp)
Nguyên lý hoạt động
Bộ phân kênh 1 đầu vào 16 đầu ra, sử dụng Sel 4 bit thay đổi liên tục 16
trạng thái. Khi enable = 0 ứng với mỗi trạng thái Sel tại mỗi thời điểm sẽ
làm thay đổi đầu ra tương ứng. Khi enable = 1 toàn bộ đầu ra bằng 0.
Code VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
Port (
Enable : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR(3 downto 0);
Din : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (15 downto 0));
end main;

architecture Behavioral of main is

 Signal OutPut: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
begin
process(Sel, Enable, Din)
begin
OutPut <= "0000000000000000";
if Enable = '0' then
Case Sel is
when "0000" => OutPut(0) <= Din;
when "0001" => OutPut(1) <= Din;
when "0010" => OutPut(2) <= Din;
when "0011" => OutPut(3) <= Din;
when "0100" => OutPut(4) <= Din;
when "0101" => OutPut(5) <= Din;
when "0110" => OutPut(6) <= Din;
when "0111" => OutPut(7) <= Din;
when "1000" => OutPut(8) <= Din;
when "1001" => OutPut(9) <= Din;
when "1010" => OutPut(10) <= Din;
when "1011" => OutPut(11) <= Din;
when "1100" => OutPut(12) <= Din;
when "1101" => OutPut(13) <= Din;
when "1110" => OutPut(14) <= Din;
when others => OutPut(15) <= Din;
end case;
end if;
end process;
OutData <= OutPut;
end Behavioral;
 Test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp is
end comp;

architecture Behavioral of comp is

component main is
Port (
Enable : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR(3 downto 0);
Din : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Signal Enable, Din : STD_LOGIC :='0';
Signal Sel : STD_LOGIC_VECTOR(3 downto 0) := "0000";
Signal OutData : STD_LOGIC_VECTOR(15 downto 0);
begin
uut: main port map(
Enable => Enable,
Sel => Sel,
Din => Din,
OutData => OutData
);
 Enable <= not Enable after 200ns;
Din <= not Din after 50ns;
process
begin
Sel <= "0000";
for i in 0 to 15 loop
wait for 10ns;
Sel <= Sel + 1;
end loop;
end process;
end Behavioral;
Bài 5: Viết mô tả VHDL (Entity và Architecture) cho mạch đó. Viết testbench để kiểm
tra hoạt động của mạch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Bai5 is
Port
(
CLK : in STD_LOGIC;
X : in STD_LOGIC;
Z : out STD_LOGIC
);
end Bai5;

architecture Behavioral of Bai5 is

----------------------------------------
component JKFF is
Port
(
CLK: in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC
);
end component;
----------------------------------------
signal j0_data : std_logic;
signal k0_data : std_logic;
signal q0_data : std_logic;
signal q0n_data : std_logic;

signal k1_data : std_logic;

signal q1_data : std_logic;
signal q1n_data : std_logic;

begin
j0_data <= q1n_data and X;
k0_data <= q1_data xor X;
k1_data <= q0n_data nand X;
Z <= q0_data and q1_data and X;

JKFF_INST0: JKFF
Port map
(
 CLK => CLK,
J => j0_data,
K => k0_data,
Q => q0_data,
QN => q0n_data
);

JKFF_INST1: JKFF
Port map
(
CLK => CLK,
J => q0_data,
K => k1_data,
Q => q1_data,
QN => q1n_data
);

end Behavioral;

Test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Test_bench IS
END Test_bench;

ARCHITECTURE behavior OF Test_bench IS

 -- Component Declaration for the Unit Under Test (UUT)

COMPONENT Bai5
PORT(
CLK : IN std_logic;
X : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;

--Inputs
signal CLK : std_logic := '0';
signal X : std_logic := '0';

--Outputs
signal Z : std_logic;

-- Clock period definitions

-- constant CLK_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Bai5
PORT MAP
(
CLK => CLK,
 X => X,
Z => Z
);

-- Clock process definitions

CLK_process :process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '0';
--000
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '0';
 wait until rising_edge(CLK);
X <= '1';
--001
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '1';
--010
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '0';
-- 011
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '1';
--100
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
 X <= '0';
--101
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '0';
wait until rising_edge(CLK);
X <= '1';
--110
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '1';
wait until rising_edge(CLK);
X <= '1';
-- insert stimulus here
end process;

END;