19/09/2013

thiet ke 8051 Intel su dung VHDL

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GAL - PAL - CPLD - FPGA

thiet ke 8051 Intel su dung VHDL

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#1

21-05-09 13:36
hungthientu
Thnh vin tch cc

Tham gia: Mar 2009

thiet ke 8051 Intel su dung VHDL

i8051_lib.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

Ni C Ng: Reverse
Engineering Academy

-------------------------------------------------------------------------------

Bi vit:

package I8051_LIB is

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constant
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CD_16 : UNSIGNED (15 downto 0) := "----------------";

CD_12 : UNSIGNED (11 downto 0) := "------------";
CD_11 : UNSIGNED (10 downto 0) := "-----------";
CD_8 : UNSIGNED ( 7 downto 0) := "--------";
C0_8 : UNSIGNED ( 7 downto 0) := "00000000";
C1_8 : UNSIGNED ( 7 downto 0) := "00000001";
C7_8 : UNSIGNED ( 7 downto 0) := "00000111";
CM_8 : UNSIGNED ( 7 downto 0) := "11111111";
CD_7 : UNSIGNED ( 6 downto 0) := "-------";
C0_7 : UNSIGNED ( 6 downto 0) := "0000000";
C9_4 : UNSIGNED ( 3 downto 0) := "1001";

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R_B : UNSIGNED (7 downto 0) := "11110000";

R_ACC : UNSIGNED (7 downto 0) := "11100000";
R_PSW : UNSIGNED (7 downto 0) := "11010000";
R_IP : UNSIGNED (7 downto 0) := "10111000";
R_IE : UNSIGNED (7 downto 0) := "10101000";
R_SP : UNSIGNED (7 downto 0) := "10000001";
R_P0 : UNSIGNED (7 downto 0) := "10000000";
R_P1 : UNSIGNED (7 downto 0) := "10010000";
R_P2 : UNSIGNED (7 downto 0) := "10100000";
R_P3 : UNSIGNED (7 downto 0) := "10110000";
R_DPL : UNSIGNED (7 downto 0) := "10000010";
R_DPH : UNSIGNED (7 downto 0) := "10000011";
R_PCON : UNSIGNED (7 downto 0) := "10000111";
R_SCON : UNSIGNED (7 downto 0) := "10011000";
R_SBUF : UNSIGNED (7 downto 0) := "10011001";
R_TCON : UNSIGNED (7 downto 0) := "10001000";
R_TMOD : UNSIGNED (7 downto 0) := "10001001";
R_TL0 : UNSIGNED (7 downto 0) := "10001010";
R_TL1 : UNSIGNED (7 downto 0) := "10001011";
R_TH0 : UNSIGNED (7 downto 0) := "10001100";
R_TH1 : UNSIGNED (7 downto 0) := "10001101";

constant
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ACALL : UNSIGNED (4 downto 0) := "10001";

ADD_1 : UNSIGNED (4 downto 0) := "00101";
ADD_2 : UNSIGNED (7 downto 0) := "00100101";
ADD_3 : UNSIGNED (6 downto 0) := "0010011";
ADD_4 : UNSIGNED (7 downto 0) := "00100100";
ADDC_1 : UNSIGNED (4 downto 0) := "00111";
ADDC_2 : UNSIGNED (7 downto 0) := "00110101";
ADDC_3 : UNSIGNED (6 downto 0) := "0011011";
ADDC_4 : UNSIGNED (7 downto 0) := "00110100";
AJMP : UNSIGNED (4 downto 0) := "00001";
ANL_1 : UNSIGNED (4 downto 0) := "01011";
ANL_2 : UNSIGNED (7 downto 0) := "01010101";

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thiet ke 8051 Intel su dung VHDL

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ANL_2 : UNSIGNED (7 downto 0) := "01010101";

ANL_3 : UNSIGNED (6 downto 0) := "0101011";
ANL_4 : UNSIGNED (7 downto 0) := "01010100";
ANL_5 : UNSIGNED (7 downto 0) := "01010010";
ANL_6 : UNSIGNED (7 downto 0) := "01010011";
ANL_7 : UNSIGNED (7 downto 0) := "10000010";
ANL_8 : UNSIGNED (7 downto 0) := "10110000";
CJNE_1 : UNSIGNED (7 downto 0) := "10110101";
CJNE_2 : UNSIGNED (7 downto 0) := "10110100";
CJNE_3 : UNSIGNED (4 downto 0) := "10111";
CJNE_4 : UNSIGNED (6 downto 0) := "1011011";
CLR_1 : UNSIGNED (7 downto 0) := "11100100";
CLR_2 : UNSIGNED (7 downto 0) := "11000011";
CLR_3 : UNSIGNED (7 downto 0) := "11000010";
CPL_1 : UNSIGNED (7 downto 0) := "11110100";
CPL_2 : UNSIGNED (7 downto 0) := "10110011";
CPL_3 : UNSIGNED (7 downto 0) := "10110010";
DA : UNSIGNED (7 downto 0) := "11010100";
DEC_1 : UNSIGNED (7 downto 0) := "00010100";
DEC_2 : UNSIGNED (4 downto 0) := "00011";
DEC_3 : UNSIGNED (7 downto 0) := "00010101";
DEC_4 : UNSIGNED (6 downto 0) := "0001011";
DIV : UNSIGNED (7 downto 0) := "10000100";
DJNZ_1 : UNSIGNED (4 downto 0) := "11011";
DJNZ_2 : UNSIGNED (7 downto 0) := "11010101";
INC_1 : UNSIGNED (7 downto 0) := "00000100";
INC_2 : UNSIGNED (4 downto 0) := "00001";
INC_3 : UNSIGNED (7 downto 0) := "00000101";
INC_4 : UNSIGNED (6 downto 0) := "0000011";
INC_5 : UNSIGNED (7 downto 0) := "10100011";
JB : UNSIGNED (7 downto 0) := "00100000";
JBC : UNSIGNED (7 downto 0) := "00010000";
JC : UNSIGNED (7 downto 0) := "01000000";
JMP : UNSIGNED (7 downto 0) := "01110011";
JNB : UNSIGNED (7 downto 0) := "00110000";
JNC : UNSIGNED (7 downto 0) := "01010000";
JNZ : UNSIGNED (7 downto 0) := "01110000";
JZ : UNSIGNED (7 downto 0) := "01100000";
LCALL : UNSIGNED (7 downto 0) := "00010010";
LJMP : UNSIGNED (7 downto 0) := "00000010";
MOV_1 : UNSIGNED (4 downto 0) := "11101";
MOV_2 : UNSIGNED (7 downto 0) := "11100101";
MOV_3 : UNSIGNED (6 downto 0) := "1110011";
MOV_4 : UNSIGNED (7 downto 0) := "01110100";
MOV_5 : UNSIGNED (4 downto 0) := "11111";
MOV_6 : UNSIGNED (4 downto 0) := "10101";
MOV_7 : UNSIGNED (4 downto 0) := "01111";
MOV_8 : UNSIGNED (7 downto 0) := "11110101";
MOV_9 : UNSIGNED (4 downto 0) := "10001";
MOV_10 : UNSIGNED (7 downto 0) := "10000101";
MOV_11 : UNSIGNED (6 downto 0) := "1000011";
MOV_12 : UNSIGNED (7 downto 0) := "01110101";
MOV_13 : UNSIGNED (6 downto 0) := "1111011";
MOV_14 : UNSIGNED (6 downto 0) := "1010011";
MOV_15 : UNSIGNED (6 downto 0) := "0111011";
MOV_16 : UNSIGNED (7 downto 0) := "10100010";
MOV_17 : UNSIGNED (7 downto 0) := "10010010";
MOV_18 : UNSIGNED (7 downto 0) := "10010000";
MOVC_1 : UNSIGNED (7 downto 0) := "10010011";
MOVC_2 : UNSIGNED (7 downto 0) := "10000011";
MOVX_1 : UNSIGNED (6 downto 0) := "1110001";
MOVX_2 : UNSIGNED (7 downto 0) := "11100000";
MOVX_3 : UNSIGNED (6 downto 0) := "1111001";
MOVX_4 : UNSIGNED (7 downto 0) := "11110000";
MUL : UNSIGNED (7 downto 0) := "10100100";
NOP : UNSIGNED (7 downto 0) := "00000000";
ORL_1 : UNSIGNED (4 downto 0) := "01001";
ORL_2 : UNSIGNED (7 downto 0) := "01000101";
ORL_3 : UNSIGNED (6 downto 0) := "0100011";
ORL_4 : UNSIGNED (7 downto 0) := "01000100";
ORL_5 : UNSIGNED (7 downto 0) := "01000010";
ORL_6 : UNSIGNED (7 downto 0) := "01000011";
ORL_7 : UNSIGNED (7 downto 0) := "01110010";
ORL_8 : UNSIGNED (7 downto 0) := "10100000";
POP : UNSIGNED (7 downto 0) := "11010000";
PUSH : UNSIGNED (7 downto 0) := "11000000";
RET : UNSIGNED (7 downto 0) := "00100010";
RETI : UNSIGNED (7 downto 0) := "00110010";
RL : UNSIGNED (7 downto 0) := "00100011";
RLC : UNSIGNED (7 downto 0) := "00110011";
RR : UNSIGNED (7 downto 0) := "00000011";
RRC : UNSIGNED (7 downto 0) := "00010011";
SETB_1 : UNSIGNED (7 downto 0) := "11010011";
SETB_2 : UNSIGNED (7 downto 0) := "11010010";
SJMP : UNSIGNED (7 downto 0) := "10000000";
SUBB_1 : UNSIGNED (4 downto 0) := "10011";
SUBB_2 : UNSIGNED (7 downto 0) := "10010101";

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SUBB_3 : UNSIGNED (6 downto 0) := "1001011";

SUBB_4 : UNSIGNED (7 downto 0) := "10010100";
SWAP : UNSIGNED (7 downto 0) := "11000100";
XCH_1 : UNSIGNED (4 downto 0) := "11001";
XCH_2 : UNSIGNED (7 downto 0) := "11000101";
XCH_3 : UNSIGNED (6 downto 0) := "1100011";
XCHD : UNSIGNED (6 downto 0) := "1101011";
XRL_1 : UNSIGNED (4 downto 0) := "01101";
XRL_2 : UNSIGNED (7 downto 0) := "01100101";
XRL_3 : UNSIGNED (6 downto 0) := "0110011";
XRL_4 : UNSIGNED (7 downto 0) := "01100100";
XRL_5 : UNSIGNED (7 downto 0) := "01100010";
XRL_6 : UNSIGNED (7 downto 0) := "01100011";

constant
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ALU_OPC_NONE : UNSIGNED (3 downto 0) := "0000";

ALU_OPC_ADD : UNSIGNED (3 downto 0) := "0001";
ALU_OPC_SUB : UNSIGNED (3 downto 0) := "0010";
ALU_OPC_MUL : UNSIGNED (3 downto 0) := "0011";
ALU_OPC_DIV : UNSIGNED (3 downto 0) := "0100";
ALU_OPC_DA : UNSIGNED (3 downto 0) := "0101";
ALU_OPC_NOT : UNSIGNED (3 downto 0) := "0110";
ALU_OPC_AND : UNSIGNED (3 downto 0) := "0111";
ALU_OPC_XOR : UNSIGNED (3 downto 0) := "1000";
ALU_OPC_OR : UNSIGNED (3 downto 0) := "1001";
ALU_OPC_RL : UNSIGNED (3 downto 0) := "1010";
ALU_OPC_RLC : UNSIGNED (3 downto 0) := "1011";
ALU_OPC_RR : UNSIGNED (3 downto 0) := "1100";
ALU_OPC_RRC : UNSIGNED (3 downto 0) := "1101";
ALU_OPC_PCSADD : UNSIGNED (3 downto 0) := "1110";
ALU_OPC_PCUADD : UNSIGNED (3 downto 0) := "1111";

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OPC_ACALL : UNSIGNED (6 downto 0) := "0000000";

OPC_ADD_1 : UNSIGNED (6 downto 0) := "0000001";
OPC_ADD_2 : UNSIGNED (6 downto 0) := "0000010";
OPC_ADD_3 : UNSIGNED (6 downto 0) := "0000011";
OPC_ADD_4 : UNSIGNED (6 downto 0) := "0000100";
OPC_ADDC_1 : UNSIGNED (6 downto 0) := "0000101";
OPC_ADDC_2 : UNSIGNED (6 downto 0) := "0000110";
OPC_ADDC_3 : UNSIGNED (6 downto 0) := "0000111";
OPC_ADDC_4 : UNSIGNED (6 downto 0) := "0001000";
OPC_AJMP : UNSIGNED (6 downto 0) := "0001001";
OPC_ANL_1 : UNSIGNED (6 downto 0) := "0001010";
OPC_ANL_2 : UNSIGNED (6 downto 0) := "0001011";
OPC_ANL_3 : UNSIGNED (6 downto 0) := "0001100";
OPC_ANL_4 : UNSIGNED (6 downto 0) := "0001101";
OPC_ANL_5 : UNSIGNED (6 downto 0) := "0001110";
OPC_ANL_6 : UNSIGNED (6 downto 0) := "0001111";
OPC_ANL_7 : UNSIGNED (6 downto 0) := "0010000";
OPC_ANL_8 : UNSIGNED (6 downto 0) := "0010001";
OPC_CJNE_1 : UNSIGNED (6 downto 0) := "0010010";
OPC_CJNE_2 : UNSIGNED (6 downto 0) := "0010011";
OPC_CJNE_3 : UNSIGNED (6 downto 0) := "0010100";
OPC_CJNE_4 : UNSIGNED (6 downto 0) := "0010101";
OPC_CLR_1 : UNSIGNED (6 downto 0) := "0010110";
OPC_CLR_2 : UNSIGNED (6 downto 0) := "0010111";
OPC_CLR_3 : UNSIGNED (6 downto 0) := "0011000";
OPC_CPL_1 : UNSIGNED (6 downto 0) := "0011001";
OPC_CPL_2 : UNSIGNED (6 downto 0) := "0011010";
OPC_CPL_3 : UNSIGNED (6 downto 0) := "0011011";
OPC_DA : UNSIGNED (6 downto 0) := "0011100";
OPC_DEC_1 : UNSIGNED (6 downto 0) := "0011101";
OPC_DEC_2 : UNSIGNED (6 downto 0) := "0011110";
OPC_DEC_3 : UNSIGNED (6 downto 0) := "0011111";
OPC_DEC_4 : UNSIGNED (6 downto 0) := "0100000";
OPC_DIV : UNSIGNED (6 downto 0) := "0100001";
OPC_DJNZ_1 : UNSIGNED (6 downto 0) := "0100010";
OPC_DJNZ_2 : UNSIGNED (6 downto 0) := "0100011";
OPC_INC_1 : UNSIGNED (6 downto 0) := "0100100";
OPC_INC_2 : UNSIGNED (6 downto 0) := "0100101";
OPC_INC_3 : UNSIGNED (6 downto 0) := "0100110";
OPC_INC_4 : UNSIGNED (6 downto 0) := "0100111";
OPC_INC_5 : UNSIGNED (6 downto 0) := "0101000";
OPC_JB : UNSIGNED (6 downto 0) := "0101001";
OPC_JBC : UNSIGNED (6 downto 0) := "0101010";
OPC_JC : UNSIGNED (6 downto 0) := "0101011";
OPC_JMP : UNSIGNED (6 downto 0) := "0101100";
OPC_JNB : UNSIGNED (6 downto 0) := "0101101";
OPC_JNC : UNSIGNED (6 downto 0) := "0101110";
OPC_JNZ : UNSIGNED (6 downto 0) := "0101111";
OPC_JZ : UNSIGNED (6 downto 0) := "0110000";
OPC_LCALL : UNSIGNED (6 downto 0) := "0110001";
OPC_LJMP : UNSIGNED (6 downto 0) := "0110010";
OPC_MOV_1 : UNSIGNED (6 downto 0) := "0110011";
OPC_MOV_2 : UNSIGNED (6 downto 0) := "0110100";
OPC_MOV_3 : UNSIGNED (6 downto 0) := "0110101";
OPC_MOV_4 : UNSIGNED (6 downto 0) := "0110110";
OPC_MOV_5 : UNSIGNED (6 downto 0) := "0110111";

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constant OPC_MOV_5 : UNSIGNED (6 downto 0) := "0110111";

constant OPC_MOV_6 : UNSIGNED (6 downto 0) := "0111000";
constant OPC_MOV_7 : UNSIGNED (6 downto 0) := "0111001";
constant OPC_MOV_8 : UNSIGNED (6 downto 0) := "0111010";
constant OPC_MOV_9 : UNSIGNED (6 downto 0) := "0111011";
constant OPC_MOV_10 : UNSIGNED (6 downto 0) := "0111100";
constant OPC_MOV_11 : UNSIGNED (6 downto 0) := "0111101";
constant OPC_MOV_12 : UNSIGNED (6 downto 0) := "0111110";
constant OPC_MOV_13 : UNSIGNED (6 downto 0) := "0111111";
constant OPC_MOV_14 : UNSIGNED (6 downto 0) := "1000000";
constant OPC_MOV_15 : UNSIGNED (6 downto 0) := "1000001";
constant OPC_MOV_16 : UNSIGNED (6 downto 0) := "1000010";
constant OPC_MOV_17 : UNSIGNED (6 downto 0) := "1000011";
constant OPC_MOV_18 : UNSIGNED (6 downto 0) := "1000100";
constant OPC_MOVC_1 : UNSIGNED (6 downto 0) := "1000101";
constant OPC_MOVC_2 : UNSIGNED (6 downto 0) := "1000110";
constant OPC_MOVX_1 : UNSIGNED (6 downto 0) := "1000111";
constant OPC_MOVX_2 : UNSIGNED (6 downto 0) := "1001000";
constant OPC_MOVX_3 : UNSIGNED (6 downto 0) := "1001001";
constant OPC_MOVX_4 : UNSIGNED (6 downto 0) := "1001010";
constant OPC_MUL : UNSIGNED (6 downto 0) := "1001011";
constant OPC_NOP : UNSIGNED (6 downto 0) := "1001100";
constant OPC_ORL_1 : UNSIGNED (6 downto 0) := "1001101";
constant OPC_ORL_2 : UNSIGNED (6 downto 0) := "1001110";
constant OPC_ORL_3 : UNSIGNED (6 downto 0) := "1001111";
constant OPC_ORL_4 : UNSIGNED (6 downto 0) := "1010000";
constant OPC_ORL_5 : UNSIGNED (6 downto 0) := "1010001";
constant OPC_ORL_6 : UNSIGNED (6 downto 0) := "1010010";
constant OPC_ORL_7 : UNSIGNED (6 downto 0) := "1010011";
constant OPC_ORL_8 : UNSIGNED (6 downto 0) := "1010100";
constant OPC_POP : UNSIGNED (6 downto 0) := "1010101";
constant OPC_PUSH : UNSIGNED (6 downto 0) := "1010110";
constant OPC_RET : UNSIGNED (6 downto 0) := "1010111";
constant OPC_RETI : UNSIGNED (6 downto 0) := "1011000";
constant OPC_RL : UNSIGNED (6 downto 0) := "1011001";
constant OPC_RLC : UNSIGNED (6 downto 0) := "1011010";
constant OPC_RR : UNSIGNED (6 downto 0) := "1011011";
constant OPC_RRC : UNSIGNED (6 downto 0) := "1011100";
constant OPC_SETB_1 : UNSIGNED (6 downto 0) := "1011101";
constant OPC_SETB_2 : UNSIGNED (6 downto 0) := "1011110";
constant OPC_SJMP : UNSIGNED (6 downto 0) := "1011111";
constant OPC_SUBB_1 : UNSIGNED (6 downto 0) := "1100000";
constant OPC_SUBB_2 : UNSIGNED (6 downto 0) := "1100001";
constant OPC_SUBB_3 : UNSIGNED (6 downto 0) := "1100010";
constant OPC_SUBB_4 : UNSIGNED (6 downto 0) := "1100011";
constant OPC_SWAP : UNSIGNED (6 downto 0) := "1100100";
constant OPC_XCH_1 : UNSIGNED (6 downto 0) := "1100101";
constant OPC_XCH_2 : UNSIGNED (6 downto 0) := "1100110";
constant OPC_XCH_3 : UNSIGNED (6 downto 0) := "1100111";
constant OPC_XCHD : UNSIGNED (6 downto 0) := "1101000";
constant OPC_XRL_1 : UNSIGNED (6 downto 0) := "1101001";
constant OPC_XRL_2 : UNSIGNED (6 downto 0) := "1101010";
constant OPC_XRL_3 : UNSIGNED (6 downto 0) := "1101011";
constant OPC_XRL_4 : UNSIGNED (6 downto 0) := "1101100";
constant OPC_XRL_5 : UNSIGNED (6 downto 0) := "1101101";
constant OPC_XRL_6 : UNSIGNED (6 downto 0) := "1101110";
constant OPC_ERROR : UNSIGNED (6 downto 0) := "1101111";
constant OPC_NU1 : UNSIGNED (6 downto 0) := "1110000";
constant OPC_NU2 : UNSIGNED (6 downto 0) := "1110001";
constant OPC_NU3 : UNSIGNED (6 downto 0) := "1110010";
constant OPC_NU4 : UNSIGNED (6 downto 0) := "1110011";
constant OPC_NU5 : UNSIGNED (6 downto 0) := "1111100";
constant OPC_NU6 : UNSIGNED (6 downto 0) := "1111101";
constant OPC_NU7 : UNSIGNED (6 downto 0) := "1111110";
constant OPC_NU8 : UNSIGNED (6 downto 0) := "1111111";
end I8051_LIB;
-------------------------------------------------------------------------------- end of file -i8051_alu.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
-----------------------------------------------------------------------------------------

rst (active hi) : alu outputs don't car values during reset
op_code : defines the alu operation (see I8051_LIB)
src_1 : first source operand of the alu
src_2 : second source operand of the alu
src_3 : third source operand of the alu
src_cy : carry into the 7th bit of the alu
src_ac : carry into the 4th bit of the alu
des_1 : first destination operand of the alu
des_2 : second destination operand of the alu

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-- des_2 : second destination operand of the alu

-- des_cy : carry out of the 7th bit of the alu
-- des_ac : carry out of the 4th bit of the alu
-- des_ov : overflow out of the alu
-entity I8051_ALU is
port(rst : in STD_LOGIC;
op_code : in UNSIGNED (3 downto 0);
src_1 : in UNSIGNED (7 downto 0);
src_2 : in UNSIGNED (7 downto 0);
src_3 : in UNSIGNED (7 downto 0);
src_cy : in STD_LOGIC;
src_ac : in STD_LOGIC;
des_1 : out UNSIGNED (7 downto 0);
des_2 : out UNSIGNED (7 downto 0);
des_cy : out STD_LOGIC;
des_ac : out STD_LOGIC;
des_ov : out STD_LOGIC);
end I8051_ALU;

------------------------------------------------------------------------------architecture BHV of I8051_ALU is

------------------------------------------------------------------------------procedure PCSADD (a : UNSIGNED (15 downto 0);
b : UNSIGNED (7 downto 0);
r : out UNSIGNED (15 downto 0)) is
variable v1, v2 : SIGNED (15 downto 0);
begin
v1 := SIGNED(a);
if( b(7) = '1' ) then
v2 := SIGNED(CM_8 & b);
else
v2 := SIGNED(C0_8 & b);
end if;
v1 := v1 + v2;
r := UNSIGNED(v1);
end PCSADD;
------------------------------------------------------------------------------procedure PCUADD (a : UNSIGNED (15 downto 0);
b : UNSIGNED (7 downto 0);
r : out UNSIGNED (15 downto 0)) is
begin
r := a + b;
end PCUADD;
------------------------------------------------------------------------------procedure DO_ADD (a, b : in UNSIGNED (7 downto 0);
c : in STD_LOGIC;
r : out UNSIGNED (7 downto 0);
cy, ac, ov : out STD_LOGIC) is
variable v1, v2, v3, v4 : UNSIGNED (4 downto 0);
variable v5, v6, v7, v8 : UNSIGNED (3 downto 0);
variable v9, vA, vB, vC : UNSIGNED (1 downto 0);
begin
v1
v2
v3
v4

:= "0" & a(3 downto 0);

:= "0" & b(3 downto 0);
:= "0" & "000" & c;
:= v1 + v2 + v3;

v5
v6
v7
v8

:= "0" & a(6 downto 4);

:= "0" & b(6 downto 4);
:= "0" & "00" & v4(4);
:= v5 + v6 + v7;

v9
vA
vB
vC

:= "0" & a(7);

:= "0" & b(7);
:= "0" & v8(3);
:= v9 + vA + vB;

r(7)
r(6)
r(5)
r(4)
r(3)
r(2)
r(1)
r(0)

:= vC(0);
:= v8(2);
:= v8(1);
:= v8(0);
:= v4(3);
:= v4(2);
:= v4(1);
:= v4(0);

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r(0) := v4(0);
cy := vC(1);
ac := v4(4);
ov := vC(1) xor v8(3);
end DO_ADD;

thiet ke 8051 Intel su dung VHDL

------------------------------------------------------------------------------procedure DO_SUB (a, b : in UNSIGNED (7 downto 0);

c : in STD_LOGIC;
r : out UNSIGNED (7 downto 0);
cy, ac, ov : out STD_LOGIC) is
variable v1, v2, v3, v4 : UNSIGNED (4 downto 0);
variable v5, v6, v7, v8 : UNSIGNED (3 downto 0);
variable v9, vA, vB, vC : UNSIGNED (1 downto 0);
begin
v1
v2
v3
v4

:= "1" & a(3 downto 0);

:= "0" & b(3 downto 0);
:= "0" & "000" & c;
:= v1 - v2 - v3;

v5
v6
v7
v8

:= "1" & a(6 downto 4);

:= "0" & b(6 downto 4);
:= "0" & "00" & (not v4(4));
:= v5 - v6 - v7;

v9
vA
vB
vC

:= "1" & a(7);

:= "0" & b(7);
:= "0" & (not v8(3));
:= v9 - vA - vB;

r(7) := vC(0);
r(6) := v8(2);
r(5) := v8(1);
r(4) := v8(0);
r(3) := v4(3);
r(2) := v4(2);
r(1) := v4(1);
r(0) := v4(0);
cy := not vC(1);
ac := not v4(4);
ov := (not vC(1)) xor (not v8(3));
end DO_SUB;
------------------------------------------------------------------------------procedure DO_MUL(a, b : in UNSIGNED (7 downto 0);
r : out UNSIGNED (15 downto 0);
ov : out STD_LOGIC) is
variable v1 : UNSIGNED (15 downto 0);
begin
v1 := a * b;
r := v1;
if( v1(15 downto 8) /= C0_8 ) then
ov := '1';
else
ov := '0';
end if;
end DO_MUL;
------------------------------------------------------------------------------procedure DO_DIV(a, b : in UNSIGNED (7 downto 0);
r : out UNSIGNED (15 downto 0);
ov : out STD_LOGIC) is
variable v1 : UNSIGNED (15 downto 0);
variable v2, v3 : UNSIGNED (8 downto 0);
begin
if( b = C0_8 ) then
r(7 downto 0) := CD_8;
r(15 downto 8) := CD_8;
ov := '1';
elsif( a = b ) then
r(7 downto 0) := C1_8;
r(15 downto 8) := C0_8;
ov := '0';
elsif( a < b ) then
r(7 downto 0) := C0_8;
r(15 downto 8) := src_1;

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r(15 downto 8) := src_1;
ov := '0';
else
v1(7 downto 0) := a;
v1(15 downto 8) := C0_8;
v3 := "0" & b;
for i in 0 to 7 loop
v1(15 downto 1) := v1(14 downto 0);
v1(0) := '0';
v2 := "1" & v1(15 downto 8);
v2 := v2 - v3;
if( v2(8) = '1' ) then
v1(0) := '1';
v1(15 downto 8) := v2(7 downto 0);
end if;
end loop;
r := v1;
ov := '0';
end if;
end DO_DIV;
------------------------------------------------------------------------------procedure DO_DA(a : in UNSIGNED (7 downto 0);
c1, c2 : in STD_LOGIC;
r : out UNSIGNED (7 downto 0);
cy : out STD_LOGIC) is
variable v : UNSIGNED (8 downto 0);
begin
v := "0" & a;
if( (c2 = '1') or (v(3 downto 0) > C9_4) ) then
v := v + "000000110";
end if;
v(8) := v(8) or c1;
if( v(8) = '1' or (v(7 downto 4) > C9_4) )then
v := v + "001100000";
end if;
r := v(7 downto 0);
cy := v(8);
end DO_DA;
------------------------------------------------------------------------------begin
process(rst, op_code, src_1, src_2, src_3, src_cy, src_ac)
variable v16 : UNSIGNED (15 downto 0);
variable v8 : UNSIGNED (7 downto 0);
variable v_cy, v_ac, v_ov : STD_LOGIC;
begin
if( rst = '1' ) then
des_1 <= CD_8;
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
else
case op_code is
when ALU_OPC_ADD =>
DO_ADD(src_1, src_2, src_cy, v8, v_cy, v_ac, v_ov);
des_1 <= v8;
des_2 <= CD_8;
des_cy <= v_cy;
des_ac <= v_ac;
des_ov <= v_ov;
when ALU_OPC_SUB =>
DO_SUB(src_1, src_2, src_cy, v8, v_cy, v_ac, v_ov);
des_1 <= v8;
des_2 <= CD_8;
des_cy <= v_cy;
des_ac <= v_ac;
des_ov <= v_ov;
when ALU_OPC_MUL =>

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when ALU_OPC_MUL =>
DO_MUL(src_1, src_2, v16, v_ov);
des_1 <= v16(7 downto 0);
des_2 <= v16(15 downto 8);
des_cy <= '-';
des_ac <= '-';
des_ov <= v_ov;
when ALU_OPC_DIV =>
DO_DIV(src_1, src_2, v16, v_ov);
des_1 <= v16(7 downto 0);
des_2 <= v16(15 downto 8);
des_cy <= '-';
des_ac <= '-';
des_ov <= v_ov;
when ALU_OPC_DA =>
DO_DA(src_1, src_cy, src_ac, v8, v_cy);
des_1 <= v8;
des_2 <= CD_8;
des_cy <= v_cy;
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_NOT =>
des_1(7) <= not src_1(7);
des_1(6) <= not src_1(6);
des_1(5) <= not src_1(5);
des_1(4) <= not src_1(4);
des_1(3) <= not src_1(3);
des_1(2) <= not src_1(2);
des_1(1) <= not src_1(1);
des_1(0) <= not src_1(0);
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_AND =>
des_1(7) <= src_1(7) and
des_1(6) <= src_1(6) and
des_1(5) <= src_1(5) and
des_1(4) <= src_1(4) and
des_1(3) <= src_1(3) and
des_1(2) <= src_1(2) and
des_1(1) <= src_1(1) and
des_1(0) <= src_1(0) and
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_XOR =>
des_1(7) <= src_1(7) xor
des_1(6) <= src_1(6) xor
des_1(5) <= src_1(5) xor
des_1(4) <= src_1(4) xor
des_1(3) <= src_1(3) xor
des_1(2) <= src_1(2) xor
des_1(1) <= src_1(1) xor
des_1(0) <= src_1(0) xor
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_OR =>
des_1(7) <= src_1(7) or
des_1(6) <= src_1(6) or
des_1(5) <= src_1(5) or
des_1(4) <= src_1(4) or
des_1(3) <= src_1(3) or
des_1(2) <= src_1(2) or
des_1(1) <= src_1(1) or
des_1(0) <= src_1(0) or
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';

src_2(7);
src_2(6);
src_2(5);
src_2(4);
src_2(3);
src_2(2);
src_2(1);
src_2(0);

src_2(7);
src_2(6);
src_2(5);
src_2(4);
src_2(3);
src_2(2);
src_2(1);
src_2(0);

src_2(7);
src_2(6);
src_2(5);
src_2(4);
src_2(3);
src_2(2);
src_2(1);
src_2(0);

when ALU_OPC_RL =>

des_1(0) <= src_1(7);
des_1(7 downto 1) <= src_1(6 downto 0);
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';

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when ALU_OPC_RLC =>
des_1(0) <= src_cy;
des_1(7 downto 1) <= src_1(6 downto 0);
des_2 <= CD_8;
des_cy <= src_1(7);
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_RR =>
des_1(7) <= src_1(0);
des_1(6 downto 0) <= src_1(7 downto 1);
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov<= '-';
when ALU_OPC_RRC =>
des_1(7) <= src_cy;
des_1(6 downto 0) <= src_1(7 downto 1);
des_2 <= CD_8;
des_cy <= src_1(0);
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_PCSADD =>
PCSADD(src_2 & src_1, src_3, v16);
des_1 <= v16(7 downto 0);
des_2 <= v16(15 downto 8);
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
when ALU_OPC_PCUADD =>
PCUADD(src_2 & src_1, src_3, v16);
des_1 <= v16(7 downto 0);
des_2 <= v16(15 downto 8);
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
when others =>
des_1 <= CD_8;
des_2 <= CD_8;
des_cy <= '-';
des_ac <= '-';
des_ov <= '-';
end case;
end if;
end process;
end BHV;
-------------------------------------------------------------------------------- end of file -i8051_dec.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
--------------------------------------------------------------------------------- rst (active hi) : OPC_ERROR returned when this is asserted
-- op_in : actual variable length opcode (see 8051 specs)
-- op_out(6 downto 0) : cracked (fixed length) opcode (see I8051_LIB)
-- op_out(7) : set if this instruction uses a second byte of data
-- op_out(8) : set if this instruction uses a third byte of data
-entity I8051_DEC is
port(rst : in STD_LOGIC;
op_in : in UNSIGNED (7 downto 0);
op_out : out UNSIGNED (8 downto 0));
end I8051_DEC;
------------------------------------------------------------------------------architecture DFL of I8051_DEC is
begin
op_out <= ("00" & OPC_ERROR ) when rst = '1' else
("01" & OPC_ACALL ) when op_in(4 downto 0) = ACALL else
("00" & OPC_ADD_1 ) when op_in(7 downto 3) = ADD_1 else
("01" & OPC_ADD_2 ) when op_in(7 downto 0) = ADD_2 else
("00" & OPC_ADD_3 ) when op_in(7 downto 1) = ADD_3 else
("01" & OPC_ADD_4 ) when op_in(7 downto 0) = ADD_4 else
("00" & OPC_ADDC_1) when op_in(7 downto 3) = ADDC_1 else
("01" & OPC_ADDC_2) when op_in(7 downto 0) = ADDC_2 else

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("01"
("00"
("01"
("01"
("00"
("01"
("00"
("01"
("01"
("11"
("01"
("01"
("11"
("11"
("11"
("11"
("00"
("00"
("01"
("00"
("00"
("01"
("00"
("00"
("00"
("01"
("00"
("00"
("01"
("11"
("00"
("00"
("01"
("00"
("00"
("11"
("11"
("01"
("00"
("11"
("01"
("01"
("01"
("11"
("11"
("00"
("01"
("00"
("01"
("00"
("01"
("01"
("01"
("01"
("11"
("01"
("11"
("00"
("01"
("01"
("01"
("01"
("11"
("00"
("00"
("00"
("00"
("00"
("00"
("00"
("00"
("00"
("01"
("00"
("01"
("01"
("11"
("01"
("01"
("01"
("01"
("00"
("00"
("00"
("00"
("00"
("00"

&
&
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&

OPC_ADDC_2) when op_in(7 downto 0) = ADDC_2 else

OPC_ADDC_3) when op_in(7 downto 1) = ADDC_3 else
OPC_ADDC_4) when op_in(7 downto 0) = ADDC_4 else
OPC_AJMP ) when op_in(4 downto 0) = AJMP else
OPC_ANL_1 ) when op_in(7 downto 3) = ANL_1 else
OPC_ANL_2 ) when op_in(7 downto 0) = ANL_2 else
OPC_ANL_3 ) when op_in(7 downto 1) = ANL_3 else
OPC_ANL_4 ) when op_in(7 downto 0) = ANL_4 else
OPC_ANL_5 ) when op_in(7 downto 0) = ANL_5 else
OPC_ANL_6 ) when op_in(7 downto 0) = ANL_6 else
OPC_ANL_7 ) when op_in(7 downto 0) = ANL_7 else
OPC_ANL_8 ) when op_in(7 downto 0) = ANL_8 else
OPC_CJNE_1) when op_in(7 downto 0) = CJNE_1 else
OPC_CJNE_2) when op_in(7 downto 0) = CJNE_2 else
OPC_CJNE_3) when op_in(7 downto 3) = CJNE_3 else
OPC_CJNE_4) when op_in(7 downto 1) = CJNE_4 else
OPC_CLR_1 ) when op_in(7 downto 0) = CLR_1 else
OPC_CLR_2 ) when op_in(7 downto 0) = CLR_2 else
OPC_CLR_3 ) when op_in(7 downto 0) = CLR_3 else
OPC_CPL_1 ) when op_in(7 downto 0) = CPL_1 else
OPC_CPL_2 ) when op_in(7 downto 0) = CPL_2 else
OPC_CPL_3 ) when op_in(7 downto 0) = CPL_3 else
OPC_DA ) when op_in(7 downto 0) = DA else
OPC_DEC_1 ) when op_in(7 downto 0) = DEC_1 else
OPC_DEC_2 ) when op_in(7 downto 3) = DEC_2 else
OPC_DEC_3 ) when op_in(7 downto 0) = DEC_3 else
OPC_DEC_4 ) when op_in(7 downto 1) = DEC_4 else
OPC_DIV ) when op_in(7 downto 0) = DIV else
OPC_DJNZ_1) when op_in(7 downto 3) = DJNZ_1 else
OPC_DJNZ_2) when op_in(7 downto 0) = DJNZ_2 else
OPC_INC_1 ) when op_in(7 downto 0) = INC_1 else
OPC_INC_2 ) when op_in(7 downto 3) = INC_2 else
OPC_INC_3 ) when op_in(7 downto 0) = INC_3 else
OPC_INC_4 ) when op_in(7 downto 1) = INC_4 else
OPC_INC_5 ) when op_in(7 downto 0) = INC_5 else
OPC_JB ) when op_in(7 downto 0) = JB else
OPC_JBC ) when op_in(7 downto 0) = JBC else
OPC_JC ) when op_in(7 downto 0) = JC else
OPC_JMP ) when op_in(7 downto 0) = JMP else
OPC_JNB ) when op_in(7 downto 0) = JNB else
OPC_JNC ) when op_in(7 downto 0) = JNC else
OPC_JNZ ) when op_in(7 downto 0) = JNZ else
OPC_JZ ) when op_in(7 downto 0) = JZ else
OPC_LCALL ) when op_in(7 downto 0) = LCALL else
OPC_LJMP ) when op_in(7 downto 0) = LJMP else
OPC_MOV_1 ) when op_in(7 downto 3) = MOV_1 else
OPC_MOV_2 ) when op_in(7 downto 0) = MOV_2 else
OPC_MOV_3 ) when op_in(7 downto 1) = MOV_3 else
OPC_MOV_4 ) when op_in(7 downto 0) = MOV_4 else
OPC_MOV_5 ) when op_in(7 downto 3) = MOV_5 else
OPC_MOV_6 ) when op_in(7 downto 3) = MOV_6 else
OPC_MOV_7 ) when op_in(7 downto 3) = MOV_7 else
OPC_MOV_8 ) when op_in(7 downto 0) = MOV_8 else
OPC_MOV_9 ) when op_in(7 downto 3) = MOV_9 else
OPC_MOV_10) when op_in(7 downto 0) = MOV_10 else
OPC_MOV_11) when op_in(7 downto 1) = MOV_11 else
OPC_MOV_12) when op_in(7 downto 0) = MOV_12 else
OPC_MOV_13) when op_in(7 downto 1) = MOV_13 else
OPC_MOV_14) when op_in(7 downto 1) = MOV_14 else
OPC_MOV_15) when op_in(7 downto 1) = MOV_15 else
OPC_MOV_16) when op_in(7 downto 0) = MOV_16 else
OPC_MOV_17) when op_in(7 downto 0) = MOV_17 else
OPC_MOV_18) when op_in(7 downto 0) = MOV_18 else
OPC_MOVC_1) when op_in(7 downto 0) = MOVC_1 else
OPC_MOVC_2) when op_in(7 downto 0) = MOVC_2 else
OPC_MOVX_1) when op_in(7 downto 1) = MOVX_1 else
OPC_MOVX_2) when op_in(7 downto 0) = MOVX_2 else
OPC_MOVX_3) when op_in(7 downto 1) = MOVX_3 else
OPC_MOVX_4) when op_in(7 downto 0) = MOVX_4 else
OPC_MUL ) when op_in(7 downto 0) = MUL else
OPC_NOP ) when op_in(7 downto 0) = NOP else
OPC_ORL_1 ) when op_in(7 downto 3) = ORL_1 else
OPC_ORL_2 ) when op_in(7 downto 0) = ORL_2 else
OPC_ORL_3 ) when op_in(7 downto 1) = ORL_3 else
OPC_ORL_4 ) when op_in(7 downto 0) = ORL_4 else
OPC_ORL_5 ) when op_in(7 downto 0) = ORL_5 else
OPC_ORL_6 ) when op_in(7 downto 0) = ORL_6 else
OPC_ORL_7 ) when op_in(7 downto 0) = ORL_7 else
OPC_ORL_8 ) when op_in(7 downto 0) = ORL_8 else
OPC_POP ) when op_in(7 downto 0) = POP else
OPC_PUSH ) when op_in(7 downto 0) = PUSH else
OPC_RET ) when op_in(7 downto 0) = RET else
OPC_RETI ) when op_in(7 downto 0) = RETI else
OPC_RL ) when op_in(7 downto 0) = RL else
OPC_RLC ) when op_in(7 downto 0) = RLC else
OPC_RR ) when op_in(7 downto 0) = RR else
OPC_RRC ) when op_in(7 downto 0) = RRC else

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("00" & OPC_SETB_1) when op_in(7 downto 0) = SETB_1 else
("01" & OPC_SETB_2) when op_in(7 downto 0) = SETB_2 else
("01" & OPC_SJMP ) when op_in(7 downto 0) = SJMP else
("00" & OPC_SUBB_1) when op_in(7 downto 3) = SUBB_1 else
("01" & OPC_SUBB_2) when op_in(7 downto 0) = SUBB_2 else
("00" & OPC_SUBB_3) when op_in(7 downto 1) = SUBB_3 else
("01" & OPC_SUBB_4) when op_in(7 downto 0) = SUBB_4 else
("00" & OPC_SWAP ) when op_in(7 downto 0) = SWAP else
("00" & OPC_XCH_1 ) when op_in(7 downto 3) = XCH_1 else
("01" & OPC_XCH_2 ) when op_in(7 downto 0) = XCH_2 else
("00" & OPC_XCH_3 ) when op_in(7 downto 1) = XCH_3 else
("00" & OPC_XCHD ) when op_in(7 downto 1) = XCHD else
("00" & OPC_XRL_1 ) when op_in(7 downto 3) = XRL_1 else
("01" & OPC_XRL_2 ) when op_in(7 downto 0) = XRL_2 else
("00" & OPC_XRL_3 ) when op_in(7 downto 1) = XRL_3 else
("01" & OPC_XRL_4 ) when op_in(7 downto 0) = XRL_4 else
("01" & OPC_XRL_5 ) when op_in(7 downto 0) = XRL_5 else
("11" & OPC_XRL_6 ) when op_in(7 downto 0) = XRL_6 else
("00" & OPC_ERROR );
end DFL;
-------------------------------------------------------------------------------- end of file -CH TNG T:
thiet ke mach do nhiet do dung IC8051 hien thi len led 7doan
thiet ke 8051 hoan chinh dung veriog
thiet ke dong ho do nhiet do dung 8051

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21-05-09 13:38
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i8051_ram.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
--------------------------------------------------------------------------------- rst (active hi) : when asserted, the registers are set to default values
-- clk (rising edge) : clock signal - all ram i/o is synchronous
-- addr : this is the address of ram/reg being requested
-- in_data : this is the data being writen into the ram/reg
-- out_data : this is the data being read from the ram/reg
-- in_bit_data : this is the bit-data being writen into the ram/reg
-- out_bit_data : this is the bit-data being read from the ram/reg
-- rd (active lo) : asserted to signal a ram/reg read
-- wr (active lo) : asserted to signal a ram/reg write
-- is_bit_addr (active hi) : asserted if requesting a ram/reg bit-data
-- p0_in : write access to the 8051's port 0
-- p0_out : read access to the 8051's port 0
-- p1_in : write access to the 8051's port 0
-- p1_out : read access to the 8051's port 0
-- p2_in : write access to the 8051's port 0
-- p2_out : read access to the 8051's port 0
-- p3_in : write access to the 8051's port 0
-- p3_out : read access to the 8051's port 0
-entity I8051_RAM is
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (7 downto 0);
in_data : in UNSIGNED (7 downto 0);
out_data : out UNSIGNED (7 downto 0);
in_bit_data : in STD_LOGIC;
out_bit_data : out STD_LOGIC;
rd : in STD_LOGIC;
wr : in STD_LOGIC;
is_bit_addr : in STD_LOGIC;
p0_in : in UNSIGNED (7 downto 0);
p0_out : out UNSIGNED (7 downto 0);
p1_in : in UNSIGNED (7 downto 0);
p1_out : out UNSIGNED (7 downto 0);
p2_in : in UNSIGNED (7 downto 0);
p2_out : out UNSIGNED (7 downto 0);
p3_in : in UNSIGNED (7 downto 0);
p3_out : out UNSIGNED (7 downto 0));
end I8051_RAM;

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end I8051_RAM;
------------------------------------------------------------------------------architecture BHV of I8051_RAM is
type IRAM_TYPE is array (0 to 127) of UNSIGNED (7 downto 0);
signal iram : IRAM_TYPE;
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

sfr_b : UNSIGNED (7 downto 0);

sfr_acc : UNSIGNED (7 downto 0);
sfr_psw : UNSIGNED (7 downto 0);
sfr_ie : UNSIGNED (7 downto 0);
sfr_ip : UNSIGNED (7 downto 0);
sfr_sp : UNSIGNED (7 downto 0);
sfr_dpl : UNSIGNED (7 downto 0);
sfr_dph : UNSIGNED (7 downto 0);
sfr_pcon : UNSIGNED (7 downto 0);
sfr_scon : UNSIGNED (7 downto 0);
sfr_sbuf : UNSIGNED (7 downto 0);
sfr_tcon : UNSIGNED (7 downto 0);
sfr_tmod : UNSIGNED (7 downto 0);
sfr_tl0 : UNSIGNED (7 downto 0);
sfr_th0 : UNSIGNED (7 downto 0);
sfr_tl1 : UNSIGNED (7 downto 0);
sfr_th1 : UNSIGNED (7 downto 0);

begin
process(rst, clk)
------------------------------------------------------------------------------procedure GET_BYTE (a : UNSIGNED (7 downto 0);
v : out UNSIGNED (7 downto 0)) is
begin
case a is
when R_B => v := sfr_b;
when R_ACC => v := sfr_acc;
when R_PSW => v := sfr_psw;
when R_IP => v := sfr_ip;
when R_IE => v := sfr_ie;
when R_SP => v := sfr_sp;
when R_P0 => v := p0_in;
when R_P1 => v := p1_in;
when R_P2 => v := p2_in;
when R_P3 => v := p3_in;
when R_DPL => v := sfr_dpl;
when R_DPH => v := sfr_dph;
when R_PCON => v := sfr_pcon;
when R_SCON => v := sfr_scon;
when R_SBUF => v := sfr_sbuf;
when R_TCON => v := sfr_tcon;
when R_TMOD => v := sfr_tmod;
when R_TL0 => v := sfr_tl0;
when R_TL1 => v := sfr_tl1;
when R_TH0 => v := sfr_th0;
when R_TH1 => v := sfr_th1;
when others => v := iram(conv_integer(a(6 downto 0)));
end case;
end GET_BYTE;
------------------------------------------------------------------------------procedure SET_BYTE (a : UNSIGNED (7 downto 0);
v : UNSIGNED (7 downto 0)) is
begin
case a is
when R_B => sfr_b <= v;
when R_ACC => sfr_acc <= v;
when R_PSW => sfr_psw <= v;
when R_IP => sfr_ip <= v;
when R_IE => sfr_ie <= v;
when R_SP => sfr_sp <= v;
when R_P0 => p0_out <= v;
when R_P1 => p1_out <= v;
when R_P2 => p2_out <= v;
when R_P3 => p3_out <= v;
when R_DPL => sfr_dpl <= v;
when R_DPH => sfr_dph <= v;
when R_PCON => sfr_pcon <= v;
when R_SCON => sfr_scon <= v;
when R_SBUF => sfr_sbuf <= v;
when R_TCON => sfr_tcon <= v;
when R_TMOD => sfr_tmod <= v;
when R_TL0 => sfr_tl0 <= v;

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when R_TL1 => sfr_tl1 <= v;
when R_TH0 => sfr_th0 <= v;
when R_TH1 => sfr_th1 <= v;
when others => iram(conv_integer(a(6 downto 0))) <= v;
end case;
end SET_BYTE;
------------------------------------------------------------------------------procedure GET_BIT (a : UNSIGNED (7 downto 0); v : out STD_LOGIC) is
variable vu : UNSIGNED (7 downto 0);
variable vi : INTEGER;
begin
vu := a(7 downto 3) & "000";
vi := conv_integer(a(2 downto 0));
case vu is
when R_B => v := sfr_b(vi);
when R_ACC => v := sfr_acc(vi);
when R_PSW => v := sfr_psw(vi);
when R_IP => v := sfr_ip(vi);
when R_IE => v := sfr_ie(vi);
when R_SP => v := sfr_sp(vi);
when R_P0 => v := p0_in(vi);
when R_P1 => v := p1_in(vi);
when R_P2 => v := p2_in(vi);
when R_P3 => v := p3_in(vi);
when R_SCON => v := sfr_scon(vi);
when R_TCON => v := sfr_tcon(vi);
when others =>
vu := "0010" & a(6 downto 3);
v := iram(conv_integer(vu))(vi);
end case;
end GET_BIT;
------------------------------------------------------------------------------procedure SET_BIT (a : UNSIGNED (7 downto 0); v : STD_LOGIC) is
variable vu : UNSIGNED (7 downto 0);
variable vi : INTEGER;
begin
vu := a(7 downto 3) & "000";
vi := conv_integer(a(2 downto 0));
case vu is
when R_B => sfr_b(vi) <= v;
when R_ACC => sfr_acc(vi) <= v;
when R_PSW => sfr_psw(vi) <= v;
when R_IP => sfr_ip(vi) <= v;
when R_IE => sfr_ie(vi) <= v;
when R_SP => sfr_sp(vi) <= v;
when R_P0 => p0_out(vi) <= v;
when R_P1 => p1_out(vi) <= v;
when R_P2 => p2_out(vi) <= v;
when R_P3 => p3_out(vi) <= v;
when R_SCON => sfr_scon(vi) <= v;
when R_TCON => sfr_tcon(vi) <= v;
when others =>
vu := "0010" & a(6 downto 3);
iram(conv_integer(vu))(vi) <= v;
end case;
end SET_BIT;
------------------------------------------------------------------------------variable v8 : UNSIGNED (7 downto 0);
variable v1 : STD_LOGIC;
begin
if( rst = '1' ) then
for i in 0 to 127 loop
iram(i) <= CD_8;
end loop;
sfr_b <= C0_8;
sfr_acc <= C0_8;
sfr_psw <= C0_8;
sfr_ie <= C0_8;
sfr_ip <= C0_8;
sfr_sp <= CD_8;
sfr_dpl <= C0_8;
sfr_dph <= C0_8;
sfr_pcon <= C0_8;
sfr_scon <= C0_8;
sfr_sbuf <= C0_8;
sfr_tcon <= C0_8;
sfr_tmod <= C0_8;

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sfr_tmod <= C0_8;

sfr_tl0 <= C0_8;
sfr_th0 <= C0_8;
sfr_tl1 <= C0_8;
sfr_th1 <= C0_8;

thiet ke 8051 Intel su dung VHDL

out_data <= CD_8;

out_bit_data <= '-';
p0_out <= CD_8;
p1_out <= CD_8;
p2_out <= CD_8;
p3_out <= CD_8;
elsif( clk'event and clk = '1' ) then
if( rd = '1' ) then
if( is_bit_addr = '1' ) then
GET_BIT(addr, v1);
out_bit_data <= v1;
else
GET_BYTE(addr, v8);
out_data <= v8;
end if;
elsif( wr = '1' ) then
if( is_bit_addr = '1' ) then
SET_BIT(addr, in_bit_data);
else
SET_BYTE(addr, in_data);
end if;
end if;
end if;
end process;
end BHV;
-------------------------------------------------------------------------------- end of file -i8051_rom.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
entity I8051_ROM is
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (11 downto 0);
data : out UNSIGNED (7 downto 0);
rd : in STD_LOGIC);
end I8051_ROM;
architecture BHV of I8051_ROM is
type ROM_TYPE is array (0 to 541) of UNSIGNED (7 downto 0);
constant PROGRAM : ROM_TYPE := (
"00000010",
"00000000",
"11001010",
"10001011",
"00010010",
"10001010",
"00010011",
"10001001",
"00010100",
"10001101",
"00010101",
"11100100",
"11111111",
"11101111",
"11000011",
"10010101",
"00010101",
"01010000",
"01000110",
"10101110",
"00000111",
"11101110",
"11000011",
"10010101",
"00010101",

-- LJMP
-- MOV_9
-- MOV_9
-- MOV_9
-- MOV_9
------

CLR_1
MOV_5
MOV_1
CLR_2
SUBB_2

-- JNC
-- MOV_6
-- MOV_1
-- CLR_2
-- SUBB_2

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19/09/2013

"00010101",
"01010000",
"00111011",
"10101011",
"00010010",
"10101010",
"00010011",
"10101001",
"00010100",
"10001110",
"10000010",
"01110101",
"10000011",
"00000000",
"00010010",
"00000001",
"11001111",
"11111101",
"10001111",
"10000010",
"01110101",
"10000011",
"00000000",
"00010010",
"00000001",
"11001111",
"11111100",
"11010011",
"10011101",
"01000000",
"00011100",
"10001100",
"00010110",
"10001110",
"10000010",
"01110101",
"10000011",
"00000000",
"00010010",
"00000001",
"11001111",
"10001111",
"10000010",
"01110101",
"10000011",
"00000000",
"00010010",
"00000001",
"11111100",
"10001110",
"10000010",
"01110101",
"10000011",
"00000000",
"11100101",
"00010110",
"00010010",
"00000001",
"11111100",
"00001110",
"10000000",
"10111111",
"00001111",
"10000000",
"10110100",
"11100100",
"11110101",
"10000000",
"00100010",
"10001011",
"00010010",
"10001010",
"00010011",
"10001001",
"00010100",
"10001101",
"00010101",
"11100100",
"11110101",
"00010110",
"10101101",
"00010110",
"11101101",
"00110011",
"10010101",
"11100000",
"11111100",
"11000011",

thiet ke 8051 Intel su dung VHDL

-- JNC
-- MOV_6
-- MOV_6
-- MOV_6
-- MOV_9
-- MOV_12
-- LCALL
-- MOV_5
-- MOV_9
-- MOV_12
-- LCALL
-----

MOV_5
SETB_1
SUBB_1
JC

-- MOV_9
-- MOV_9
-- MOV_12
-- LCALL
-- MOV_9
-- MOV_12
-- LCALL
-- MOV_9
-- MOV_12
-- MOV_2
-- LCALL
-- INC_2
-- SJMP
-- INC_2
-- SJMP
-- CLR_1
-- MOV_8
-- RET
-- MOV_9
-- MOV_9
-- MOV_9
-- MOV_9
-- CLR_1
-- MOV_8
-- MOV_6
-- MOV_1
-- RLC
-- SUBB_2
-- MOV_5
-- CLR_2

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19/09/2013

"11000011",
"11101101",
"10010101",
"00010101",
"01110100",
"10000000",
"11111000",
"01101100",
"10011000",
"01010000",
"00011001",
"10101011",
"00010010",
"10101010",
"00010011",
"10101001",
"00010100",
"10101111",
"00010110",
"11101111",
"00110011",
"10010101",
"11100000",
"10001111",
"10000010",
"11110101",
"10000011",
"00010010",
"00000001",
"11001111",
"11110101",
"10000000",
"00000101",
"00010110",
"10000000",
"11010101",
"00100010",
"01111000",
"00001000",
"01111100",
"00000000",
"01111101",
"00000000",
"01111011",
"11111111",
"01111010",
"00000000",
"01111001",
"11000000",
"01111110",
"00000000",
"01111111",
"00001010",
"00010010",
"00000001",
"10100110",
"01111011",
"00000000",
"01111010",
"00000000",
"01111001",
"00001000",
"01111101",
"00001010",
"00010010",
"00000000",
"00000011",
"01111011",
"00000000",
"01111010",
"00000000",
"01111001",
"00001000",
"01111101",
"00001010",
"00010010",
"00000000",
"01011101",
"10000000",
"11111110",
"00100010",
"00010011",
"00010010",
"00010001",
"00010000",
"00001111",
"00001110",
"00001101",

-- CLR_2
-- MOV_1
-- SUBB_2

thiet ke 8051 Intel su dung VHDL

-- MOV_4
-----

MOV_5
XRL_1
SUBB_1
JNC

-- MOV_6
-- MOV_6
-- MOV_6
-- MOV_6
-- MOV_1
-- RLC
-- SUBB_2
-- MOV_9
-- MOV_8
-- LCALL
-- MOV_8
-- INC_3
-- SJMP
-- RET
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- LCALL
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- LCALL
-- MOV_7
-- MOV_7
-- MOV_7
-- MOV_7
-- LCALL
-- SJMP
-- RET
-- RRC
-- LCALL
-- INC_2
-- INC_2
-- INC_2

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thiet ke 8051 Intel su dung VHDL

"00001101",
"00001100",
"00001011",
"00001010",
"01111000",
"01111111",
"11100100",
"11110110",
"11011000",
"11111101",
"01110101",
"10000001",
"00010110",
"00000010",
"00000000",
"10010100",
"11100111",
"00001001",
"11110110",
"00001000",
"11011111",
"11111010",
"10000000",
"01000110",
"11100111",
"00001001",
"11110010",
"00001000",
"11011111",
"11111010",
"10000000",
"00111110",
"10001000",
"10000010",
"10001100",
"10000011",
"11100111",
"00001001",
"11110000",
"10100011",
"11011111",
"11111010",
"10000000",
"00110010",
"11100011",
"00001001",
"11110110",
"00001000",
"11011111",
"11111010",
"10000000",
"01111000",
"11100011",
"00001001",
"11110010",
"00001000",
"11011111",
"11111010",
"10000000",
"01110000",
"10001000",
"10000010",
"10001100",
"10000011",
"11100011",
"00001001",
"11110000",
"10100011",
"11011111",
"11111010",
"10000000",
"01100100",
"10001001",
"10000010",
"10001010",
"10000011",
"11100000",
"10100011",
"11110110",
"00001000",
"11011111",
"11111010",
"10000000",
"01011000",
"10001001",
"10000010",
"10001010",
"10000011",

------

INC_2
INC_2
INC_2
INC_2
MOV_7

-- CLR_1
-- MOV_13
-- DJNZ_1
-- MOV_12
-- LJMP
------

MOV_3
INC_2
MOV_13
INC_2
DJNZ_1

-- SJMP
------

MOV_3
INC_2
MOVX_3
INC_2
DJNZ_1

-- SJMP
-- MOV_9
-- MOV_9
------

MOV_3
INC_2
MOVX_4
INC_5
DJNZ_1

-- SJMP
------

MOVX_1
INC_2
MOV_13
INC_2
DJNZ_1

-- SJMP
------

MOVX_1
INC_2
MOVX_3
INC_2
DJNZ_1

-- SJMP
-- MOV_9
-- MOV_9
------

MOVX_1
INC_2
MOVX_4
INC_5
DJNZ_1

-- SJMP
-- MOV_9
-- MOV_9
------

MOVX_2
INC_5
MOV_13
INC_2
DJNZ_1

-- SJMP
-- MOV_9
-- MOV_9

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thiet ke 8051 Intel su dung VHDL

"10000011",
"11100000",
"10100011",
"11110010",
"00001000",
"11011111",
"11111010",
"10000000",
"01001100",
"10000000",
"11010010",
"10000000",
"11111010",
"10000000",
"11000110",
"10000000",
"11010100",
"10000000",
"01101001",
"10000000",
"11110010",
"10000000",
"00110011",
"10000000",
"00010000",
"10000000",
"10100110",
"10000000",
"11101010",
"10000000",
"10011010",
"10000000",
"10101000",
"10000000",
"11011010",
"10000000",
"11100010",
"10000000",
"11001010",
"10000000",
"00110011",
"10001001",
"10000010",
"10001010",
"10000011",
"11101100",
"11111010",
"11100100",
"10010011",
"10100011",
"11001000",
"11000101",
"10000010",
"11001000",
"11001100",
"11000101",
"10000011",
"11001100",
"11110000",
"10100011",
"11001000",
"11000101",
"10000010",
"11001000",
"11001100",
"11000101",
"10000011",
"11001100",
"11011111",
"11101001",
"11011110",
"11100111",
"10000000",
"00001101",
"10001001",
"10000010",
"10001010",
"10000011",
"11100100",
"10010011",
"10100011",
"11110110",
"00001000",
"11011111",
"11111001",
"11101100",
"11111010",
"10101001",

------

MOVX_2
INC_5
MOVX_3
INC_2
DJNZ_1

-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- SJMP
-- MOV_9
-- MOV_9
--------

MOV_1
MOV_5
CLR_1
MOVC_1
INC_5
XCH_1
XCH_2

-- XCH_1
-- XCH_1
-- XCH_2
------

XCH_1
MOVX_4
INC_5
XCH_1
XCH_2

-- XCH_1
-- XCH_1
-- XCH_2
-- XCH_1
-- DJNZ_1
-- DJNZ_1
-- SJMP
-- MOV_9
-- MOV_9
-------

CLR_1
MOVC_1
INC_5
MOV_13
INC_2
DJNZ_1

-- MOV_1
-- MOV_5
-- MOV_6

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thiet ke 8051 Intel su dung VHDL

"10101001",
"11110000",
"11101101",
"11111011",
"00100010",
"10001001",
"10000010",
"10001010",
"10000011",
"11101100",
"11111010",
"11100000",
"10100011",
"11001000",
"11000101",
"10000010",
"11001000",
"11001100",
"11000101",
"10000011",
"11001100",
"11110000",
"10100011",
"11001000",
"11000101",
"10000010",
"11001000",
"11001100",
"11000101",
"10000011",
"11001100",
"11011111",
"11101010",
"11011110",
"11101000",
"10000000",
"11011011",
"10001001",
"10000010",
"10001010",
"10000011",
"11100100",
"10010011",
"10100011",
"11110010",
"00001000",
"11011111",
"11111001",
"10000000",
"11001100",
"10001000",
"11110000",
"11101101",
"00100100",
"00000010",
"10110100",
"00000100",
"00000000",
"01010000",
"11000010",
"11110101",
"10000010",
"11101011",
"00100100",
"00000010",
"10110100",
"00000100",
"00000000",
"01010000",
"10111000",
"00100011",
"00100011",
"01000101",
"10000010",
"11110101",
"10000010",
"11101111",
"01001110",
"01100000",
"10101110",
"11101111",
"01100000",
"00000001",
"00001110",
"11100101",
"10000010",
"00100011",
"10010000",

-- MOV_6
-----

MOV_1
MOV_5
RET
MOV_9

-- MOV_9
-------

MOV_1
MOV_5
MOVX_2
INC_5
XCH_1
XCH_2

-- XCH_1
-- XCH_1
-- XCH_2
------

XCH_1
MOVX_4
INC_5
XCH_1
XCH_2

-- XCH_1
-- XCH_1
-- XCH_2
-- XCH_1
-- DJNZ_1
-- DJNZ_1
-- SJMP
-- MOV_9
-- MOV_9
-------

CLR_1
MOVC_1
INC_5
MOVX_3
INC_2
DJNZ_1

-- SJMP
-- MOV_9
-- MOV_1
-- ADD_4
-- CJNE_2
-- JNC
-- MOV_8
-- MOV_1
-- ADD_4
-- CJNE_2
-- JNC
-- RL
-- RL
-- ORL_2
-- MOV_8
-- MOV_1
-- ORL_1
-- JZ
-- MOV_1
-- JZ
-- INC_2
-- MOV_2
-- RL
-- MOV_18

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thiet ke 8051 Intel su dung VHDL

"10010000", -- MOV_18
"00000001",
"00100110",
"01110011", -- JMP
"10111011", -- CJNE_3
"00000001",
"00001100",
"11100101", -- MOV_2
"10000010",
"00101001", -- ADD_1
"11110101", -- MOV_8
"10000010",
"11100101", -- MOV_2
"10000011",
"00111010", -- ADDC_1
"11110101", -- MOV_8
"10000011",
"11100000", -- MOVX_2
"00100010", -- RET
"01010000", -- JNC
"00000110",
"11101001", -- MOV_1
"00100101", -- ADD_2
"10000010",
"11111000", -- MOV_5
"11100110", -- MOV_3
"00100010", -- RET
"10111011", -- CJNE_3
"11111110",
"00000110",
"11101001", -- MOV_1
"00100101", -- ADD_2
"10000010",
"11111000", -- MOV_5
"11100010", -- MOVX_1
"00100010", -- RET
"11100101", -- MOV_2
"10000010",
"00101001", -- ADD_1
"11110101", -- MOV_8
"10000010",
"11100101", -- MOV_2
"10000011",
"00111010", -- ADDC_1
"11110101", -- MOV_8
"10000011",
"11100100", -- CLR_1
"10010011", -- MOVC_1
"00100010", -- RET
"11111000", -- MOV_5
"10111011", -- CJNE_3
"00000001",
"00001101",
"11100101", -- MOV_2
"10000010",
"00101001", -- ADD_1
"11110101", -- MOV_8
"10000010",
"11100101", -- MOV_2
"10000011",
"00111010", -- ADDC_1
"11110101", -- MOV_8
"10000011",
"11101000", -- MOV_1
"11110000", -- MOVX_4
"00100010", -- RET
"01010000", -- JNC
"00000110",
"11101001", -- MOV_1
"00100101", -- ADD_2
"10000010",
"11001000", -- XCH_1
"11110110", -- MOV_13
"00100010", -- RET
"10111011", -- CJNE_3
"11111110",
"00000101",
"11101001", -- MOV_1
"00100101", -- ADD_2
"10000010",
"11001000", -- XCH_1
"11110010", -- MOVX_3
"00100010"); -- RET
begin
process(rst, clk)
begin

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thiet ke 8051 Intel su dung VHDL

if( rst = '1' ) then
data <= CD_8;
elsif( clk'event and clk = '1' ) then
if( rd = '1' ) then
data <= PROGRAM(conv_integer(addr));
else
data <= CD_8;
end if;
end if;
end process;
end BHV;

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#3

21-05-09 20:01
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Ni C Ng: Reverse
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i8051_all.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
--------------------------------------------------------------------------------- rst (active hi) : resets the 8051
-- clk (rising edge) : clocks the 8051
-- xrm_addr : this is the address of xram being requested
-- xrm_out_data : this is the data sent to the xram
-- xrm_in_data : this is the data received from the xram
-- xrm_rd (active lo) : asserted to signal a xram read
-- xrm_wr (active lo) : asserted to signal a xram write
-- p0_in : port 0's input direction
-- p0_out : port 0's output direction
-- p0_in : port 1's input direction
-- p0_out : port 1's output direction
-- p0_in : port 2's input direction
-- p0_out : port 2's output direction
-- p0_in : port 3's input direction
-- p0_out : port 3's output direction
-entity I8051_ALL is
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
xrm_addr : out UNSIGNED (15 downto 0);
xrm_out_data : out UNSIGNED (7 downto 0);
xrm_in_data : in UNSIGNED (7 downto 0);
xrm_rd : out STD_LOGIC;
xrm_wr : out STD_LOGIC;
p0_in : in UNSIGNED (7 downto 0);
p0_out : out UNSIGNED (7 downto 0);
p1_in : in UNSIGNED (7 downto 0);
p1_out : out UNSIGNED (7 downto 0);
p2_in : in UNSIGNED (7 downto 0);
p2_out : out UNSIGNED (7 downto 0);
p3_in : in UNSIGNED (7 downto 0);
p3_out : out UNSIGNED (7 downto 0));
end I8051_ALL;
------------------------------------------------------------------------------architecture STR of I8051_ALL is
component I8051_ALU
port(rst : in STD_LOGIC;
op_code : in UNSIGNED (3 downto 0);
src_1 : in UNSIGNED (7 downto 0);
src_2 : in UNSIGNED (7 downto 0);
src_3 : in UNSIGNED (7 downto 0);
src_cy : in STD_LOGIC;
src_ac : in STD_LOGIC;
des_1 : out UNSIGNED (7 downto 0);
des_2 : out UNSIGNED (7 downto 0);
des_cy : out STD_LOGIC;
des_ac : out STD_LOGIC;
des_ov : out STD_LOGIC);
end component;

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end component;

thiet ke 8051 Intel su dung VHDL

component I8051_DEC
port(rst : in STD_LOGIC;
op_in : in UNSIGNED (7 downto 0);
op_out : out UNSIGNED (8 downto 0));
end component;
component I8051_RAM
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (7 downto 0);
in_data : in UNSIGNED (7 downto 0);
out_data : out UNSIGNED (7 downto 0);
in_bit_data : in STD_LOGIC;
out_bit_data : out STD_LOGIC;
rd : in STD_LOGIC;
wr : in STD_LOGIC;
is_bit_addr : in STD_LOGIC;
p0_in : in UNSIGNED (7 downto 0);
p0_out : out UNSIGNED (7 downto 0);
p1_in : in UNSIGNED (7 downto 0);
p1_out : out UNSIGNED (7 downto 0);
p2_in : in UNSIGNED (7 downto 0);
p2_out : out UNSIGNED (7 downto 0);
p3_in : in UNSIGNED (7 downto 0);
p3_out : out UNSIGNED (7 downto 0));
end component;
component I8051_ROM
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (11 downto 0);
data : out UNSIGNED (7 downto 0);
rd : in STD_LOGIC);
end component;
component I8051_CTR
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
rom_addr : out UNSIGNED (11 downto 0);
rom_data : in UNSIGNED (7 downto 0);
rom_rd : out STD_LOGIC;
ram_addr : out UNSIGNED (7 downto 0);
ram_out_data : out UNSIGNED (7 downto 0);
ram_in_data : in UNSIGNED (7 downto 0);
ram_out_bit_data : out STD_LOGIC;
ram_in_bit_data : in STD_LOGIC;
ram_rd : out STD_LOGIC;
ram_wr : out STD_LOGIC;
ram_is_bit_addr : out STD_LOGIC;
xrm_addr : out UNSIGNED (15 downto 0);
xrm_out_data : out UNSIGNED (7 downto 0);
xrm_in_data : in UNSIGNED (7 downto 0);
xrm_rd : out STD_LOGIC;
xrm_wr : out STD_LOGIC;
dec_op_out : out UNSIGNED (7 downto 0);
dec_op_in : in UNSIGNED (8 downto 0);
alu_op_code : out UNSIGNED (3 downto 0);
alu_src_1 : out UNSIGNED (7 downto 0);
alu_src_2 : out UNSIGNED (7 downto 0);
alu_src_3 : out UNSIGNED (7 downto 0);
alu_src_cy : out STD_LOGIC;
alu_src_ac : out STD_LOGIC;
alu_des_1 : in UNSIGNED (7 downto 0);
alu_des_2 : in UNSIGNED (7 downto 0);
alu_des_cy : in STD_LOGIC;
alu_des_ac : in STD_LOGIC;
alu_des_ov : in STD_LOGIC);
end component;
-- synopsys_synthesis off
component I8051_DBG
port(op_in : in UNSIGNED (8 downto 0));
end component;
-- synopsys_synthesis on
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

rom_addr : UNSIGNED (11 downto 0);

rom_data : UNSIGNED (7 downto 0);
rom_rd : STD_LOGIC;
ram_addr : UNSIGNED (7 downto 0);
ram_out_data : UNSIGNED (7 downto 0);
ram_in_data : UNSIGNED (7 downto 0);
ram_out_bit_data : STD_LOGIC;
ram_in_bit_data : STD_LOGIC;
ram_rd : STD_LOGIC;
ram_wr : STD_LOGIC;
ram_is_bit_addr : STD_LOGIC;

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signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
begin

thiet ke 8051 Intel su dung VHDL

ram_is_bit_addr : STD_LOGIC;
dec_op_out : UNSIGNED (7 downto 0);
dec_op_in : UNSIGNED (8 downto 0);
alu_op_code : UNSIGNED (3 downto 0);
alu_src_1 : UNSIGNED (7 downto 0);
alu_src_2 : UNSIGNED (7 downto 0);
alu_src_3 : UNSIGNED (7 downto 0);
alu_src_cy : STD_LOGIC;
alu_src_ac : STD_LOGIC;
alu_des_1 : UNSIGNED (7 downto 0);
alu_des_2 : UNSIGNED (7 downto 0);
alu_des_cy : STD_LOGIC;
alu_des_ac : STD_LOGIC;
alu_des_ov : STD_LOGIC;

U_ALU : I8051_ALU port map(rst,

alu_op_code,
alu_src_1,
alu_src_2,
alu_src_3,
alu_src_cy,
alu_src_ac,
alu_des_1,
alu_des_2,
alu_des_cy,
alu_des_ac,
alu_des_ov);
U_DEC : I8051_DEC port map(rst,
dec_op_out,
dec_op_in);
U_RAM : I8051_RAM port map(rst,
clk,
ram_addr,
ram_in_data,
ram_out_data,
ram_in_bit_data,
ram_out_bit_data,
ram_rd,
ram_wr,
ram_is_bit_addr,
p0_in,
p0_out,
p1_in,
p1_out,
p2_in,
p2_out,
p3_in,
p3_out);
U_ROM : I8051_ROM port map(rst,
clk,
rom_addr,
rom_data,
rom_rd);
U_CTR : I8051_CTR port map(rst,
clk,
rom_addr,
rom_data,
rom_rd,
ram_addr,
ram_in_data,
ram_out_data,
ram_in_bit_data,
ram_out_bit_data,
ram_rd,
ram_wr,
ram_is_bit_addr,
xrm_addr,
xrm_out_data,
xrm_in_data,
xrm_rd,
xrm_wr,
dec_op_out,
dec_op_in,
alu_op_code,
alu_src_1,
alu_src_2,
alu_src_3,
alu_src_cy,
alu_src_ac,
alu_des_1,
alu_des_2,
alu_des_cy,
alu_des_ac,

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alu_des_ac,
alu_des_ov);

thiet ke 8051 Intel su dung VHDL

-- synopsys_synthesis off
U_DBG : I8051_DBG port map(dec_op_in);
-- synopsys_synthesis on
end STR;
-------------------------------------------------------------------------------- end of file -i8051_xrm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
--------------------------------------------------------------------------------- rst (active hi) : when asserted, the registers are set to default values
-- clk (rising edge) : clock signal - all ram i/o is synchronous
-- addr : this is the address of ram/reg being requested
-- in_data : this is the data being writen into the ram/reg
-- out_data : this is the data being read from the ram/reg
-- rd (active lo) : asserted to signal a ram/reg read
-- wr (active lo) : asserted to signal a ram/reg write
-entity I8051_XRM is
generic(storage_size : INTEGER := 2048);
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (15 downto 0);
in_data : in UNSIGNED (7 downto 0);
out_data : out UNSIGNED (7 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC);
end I8051_XRM;
------------------------------------------------------------------------------architecture BHV of I8051_XRM is
type XRM_TYPE is array (0 to storage_size-1) of UNSIGNED (7 downto 0);
signal xrm : XRM_TYPE;
begin
process(rst, clk)
begin
if( rst = '1' ) then
for i in 0 to storage_size-1 loop
xrm(i) <= CD_8;
end loop;
out_data <= CD_8;
elsif( clk'event and clk = '1' ) then
if( rd = '1' and conv_integer(addr) < storage_size ) then
out_data <= xrm(conv_integer(addr));
elsif( wr = '1' and conv_integer(addr) < storage_size ) then
xrm(conv_integer(addr)) <= in_data;
end if;
end if;
end process;
end BHV;
-------------------------------------------------------------------------------- end of file -i8051_tsb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
------------------------------------------------------------------------------entity I8051_TSB is
end I8051_TSB;

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end I8051_TSB;

thiet ke 8051 Intel su dung VHDL

------------------------------------------------------------------------------architecture BHV of I8051_TSB is

component I8051_ALL
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
xrm_addr : out UNSIGNED (15 downto 0);
xrm_out_data : out UNSIGNED (7 downto 0);
xrm_in_data : in UNSIGNED (7 downto 0);
xrm_rd : out STD_LOGIC;
xrm_wr : out STD_LOGIC;
p0_in : in UNSIGNED (7 downto 0);
p0_out : out UNSIGNED (7 downto 0);
p1_in : in UNSIGNED (7 downto 0);
p1_out : out UNSIGNED (7 downto 0);
p2_in : in UNSIGNED (7 downto 0);
p2_out : out UNSIGNED (7 downto 0);
p3_in : in UNSIGNED (7 downto 0);
p3_out : out UNSIGNED (7 downto 0));
end component;
component I8051_XRM
generic(storage_size : INTEGER := 2048);
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (15 downto 0);
in_data : in UNSIGNED (7 downto 0);
out_data : out UNSIGNED (7 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC);
end component;
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
begin

rst : STD_LOGIC := '1';

clk : STD_LOGIC := '0';
addr : UNSIGNED (15 downto 0);
in_data : UNSIGNED (7 downto 0);
out_data : UNSIGNED (7 downto 0);
rd : STD_LOGIC;
wr : STD_LOGIC;
p0_in : UNSIGNED (7 downto 0);
p0_out : UNSIGNED (7 downto 0);
p1_in : UNSIGNED (7 downto 0);
p1_out : UNSIGNED (7 downto 0);
p2_in : UNSIGNED (7 downto 0);
p2_out : UNSIGNED (7 downto 0);
p3_in : UNSIGNED (7 downto 0);
p3_out : UNSIGNED (7 downto 0);

rst <= '0' after 50 ns;

clk <= not clk after 25 ns;
U_ALL : I8051_ALL port map (rst, clk,
addr, out_data, in_data, rd, wr,
p0_in, p0_out, p1_in, p1_out,
p2_in, p2_out, p3_in, p3_out);
U_XRM : I8051_XRM port map (rst, clk, addr, out_data, in_data, rd, wr);
end BHV;
------------------------------------------------------------------------------configuration CFG_I8051_TSB of I8051_TSB is
for BHV
end for;
end CFG_I8051_TSB;
-------------------------------------------------------------------------------- end of file --

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