DESIGN AND HARDWARE IMPLEMENTATION MODIFIED

MULTILEVEL CASCADED H-BRIDGE INVERTER

ABSTRACT
Inverters are an essential part in many applications including photovoltaic generation. With the
increasing penetration of renewable energy sources, the drive for efficient inverters is gaining more
and more momentum. In this paper, output power quality, power loss, implementation complexity,
cost, and relative advantages of the popular cascaded multilevel H-bridge inverter and a modified
version of it are explored. An optimal number of levels and the optimal switching frequency for such
inverters are investigated, and a five-level architecture is chosen considering the trade-offs. This
inverter is driven by level shifted in-phase disposition pulse width modulation technique to reduce
harmonics, which is chosen through deliberate testing of other advanced disposition pulse width
modulation techniques. To reduce the harmonics further, the application of filters is investigated, and
an LC filter is applied which provided appreciable results. This system is tested in
MATLAB/Simulink and then implemented in hardware after design and testing in Proteus ISIS. The
general cascaded multilevel H-bridge inverter design is also implemented in hardware to demonstrate
a novel low-cost MOSFET driver build for this study. The hardware setups use MOSFETs as
switching devices and low-cost ATmega microcontrollers for generating the switching pulses via
level shifted in-phase disposition pulse width modulation. This implementation substantiated the
effectiveness of the proposed design.

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CHAPTER 1
INTRODUCTION
Inverter is an electronic circuit which converts direct current to alternating current.
The inverters are used for emergency backup power in a home, in aircraft systems to convert
the aircraft DC power to AC. The AC power is used mainly for electrical devices like lights,
radar, radio, motor, and other devices. Voltage source inverter produces an output voltage
with levels 0, +VDC or -VDC. They are known as two-level inverter. To obtain a quality output
voltage or a current waveform with a minimum amount of ripple content, they require high
switching frequency along with various pulse width modulation (PWM) techniques. In high-
power and high-voltage applications, these two-level inverters have some limitations in
operating at high frequency mainly due to switching, conduction losses and constraints of
device ratings. Therefore, multilevel inverters have been introduced.

A multilevel inverter is a power electronic circuit which is capable of providing

desired alternating voltage level at the output using multiple lower level DC voltages as an
input. The multilevel inverters have drawn tremendous interest in the power industries.

A multilevel inverter has several advantages over a conventional two-level inverter

that uses high switching frequency pulse width modulation. With increase in number of DC
voltage sources in the input side, a sinusoidal like waveform can be generated at the output.
As a result, the total harmonic distortion (THD) decreases and quality of output waveform
increases. In addition, lower switching losses, lower voltage stress of dv / dt on switches, and
better electromagnetic interference are the other most important advantages of multilevel
inverter.

Multilevel inverters have an arrangement of power switching devices and capacitor

voltage sources. They are suitable for high-voltage applications because of their ability to
synthesize output voltage waveforms with a better harmonic spectrum and attain higher
voltages with a limited maximum device rating. The different types of multilevel inverter
requires more number of switches, diodes, capacitors and voltage sources where in total
harmonic distortion and electrical stress on device increases. Capacitors and diodes are not

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used in the designed hardware for cascaded H-bridge five level inverter. The developed
hardware on cascaded H-bridge five level inverters consists of modularity, simplicity of
control, reliability and they require the less number of power semiconductor devices to
generate a particular level. As a result, the losses and total cost of the inverter decreases
resulting into increased efficiency.

The inverters are comprised of a series connection of basic units which consist of
different arrays of power switches and DC voltage sources. The inverters are divided into two
main groups, i.e. symmetric cascaded multilevel inverters and asymmetric cascaded
multilevel inverters. The asymmetric cascaded multilevel inverters generate a higher number
of output levels in comparison with the symmetric cascaded multilevel inverters with the
same number of power electronic devices because of the different amplitude of its DC
voltage sources. As a result, the installation space and total cost of an asymmetric cascaded
multilevel inverter is lower than that of a symmetric cascaded multilevel inverter.

New basic unit of cascaded H-bridge five level inverter is developed to increase the
number of output levels by using a less number of power electronic devices. The developed
hardware in my project for five level inverter consists of IRF 840 N channel power
MOSFET’s as switching devices and DC voltage sources.

The developed hardware is mainly focused to increase number of output voltage

levels by using less number of switches. The Hardware is developed for cascaded H-bridge
inverter to obtain 5 different levels of output voltage with the separate input DC supply of
12V. Sinusoidal pulse width modulation technique is employed for eliminating lower order
harmonics and to produce high quality output voltage waveform. Arduino mega 2560
microcontroller is used to generate the switching pulses to have the control on the operation
of the inverter circuit. Switching pulses are generated by writing a C program in the
microcontroller. TLP 250 driver circuit provides isolation between the power circuit and
control circuit. Voltage regulator is used to provide a constant DC supply for the
microcontroller and driver circuits.

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CHAPTER 2
LITERATURE SURVEY

2.1 REVIEW OF LITERATURE SURVEY

To carry out the development of hardware, some of the IEEE journal and conference
papers on cascaded H-bridge multilevel inverters are referred among them brief explanations
of few papers are listed in the following:

1. Sreenivasulu Mamila , Suresh Kumar Anisetty and M. Rama Pallavi “ A New Cascaded
H-Bridge Multilevel Inverter With Reduced Switch Count” 2017 International
Conference on Smart Technology for Smart Nation (ICSTSN) 978-1-5386-0569-1$31.00
©2017 IEEE.
The above mentioned publishers explained about the cascaded H-bridge multilevel
inverter using less number of switches. As the number of switches is reduced, the output level
also increases due to which conduction and switching losses are reduced. The proposed
multilevel inverter includes series connected modules which can generate only unidirectional
positive voltage. In order to get the bidirectional voltage an H-bridge is connected to the
series connected modules. The proposed block diagram uses sinusoidal pulse width
modulation technique (SPWM). Generally SPWM requires (L-1) carriers in the proposed
block diagram where in only (L+1/2) carriers are much sufficient for the operation of block.
Due to the use of less number of carriers controlling of the circuit becomes less complex, size
and installation cost also reduces.

The paper employs sinusoidal pulse width modulation technique as it has several advantages
mentioned as follows:
1. The steps of the output voltage are modulated by adjusting the amplitude of reference sine
wave.
2. With the increase in the carrier frequency percentage of total harmonic distortion can be
reduced.
3. SPWM includes level shifting PWM and phase shifting PWM.
4. The paper had employed level shifting PWM technique for multilevel inverter.

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The publishers verified the results of single phase configuration using the software
MATLAB/SIMULINK. The paper explains that LS-PWM where, in phase disposition (IPD)
modulation technique gives the best harmonic profile than compared to phase opposition
disposition (POD) and alternate phase opposition disposition (APOD). The simulation results
are verified for various modulation index ratios (MI) with the following output voltage level.
The simulated values are as follows:
1. Carrier frequency KHz.
2. Reference sine frequency 50 Hz.
3. Modulation index (1 to 0.5).

It is observed that the percentage of total harmonic distortion reaches as per IEEE standards
without filtering requirements. The proposed unit is able to operate for both symmetrical as
well as asymmetrical configuration as mentioned by the publishers.

2. T V V S Lakshmi , Noby George, Umashankar S and Kothari D P “Cascaded seven level

inverter with reduced number of switches using level shifting PWM technique” 2013
International Conference on Power, Energy and Control (ICPEC) 978-1-4673-6030-
2/13/$31.00 ©2013 IEEE.
The paper explains about multilevel inverter and its advantages. The paper proposes
two new topologies of 7- level cascaded multilevel inverter with reduced number of switches
than that of conventional type which has 12 switches. The topologies consist of circuits with
9 switches and 7 switches for the same 7-level output. Therefore with less number of
switches, requirement of gate drive circuitry is minimized and also very few switches will be
conducting for specific intervals of time. The SPWM technique is implemented using
multicarrier wave signals. Level shifted triangular waves are used in comparison with
sinusoidal reference to generate sine PWM switching sequence. The number of level shifted
triangular waves depends on the number of levels in the output. i.e. for n levels, n-1 number
of carrier waves.

The implemented model uses 1 KHz SPWM pulses with a modulation index of 0.8.
The circuits are simulated using SPWM technique and effect of the harmonic spectrum is also
analyzed. A comparison is made for the topologies with 9 switches and 7 switches and an

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effective reduction in THD has been observed for the circuits with less number of switches.
The THD for 9 switches is 14% and the THD for 7 switches is 12.5%.

PROPOSED 7-SWITCH TOPOLOGY
Apart from the H-bridge, only one switch will be conducting at every instant and thus
making the operation less complex. There are two schemes of carried based modulation and
they are phase shifting and level shifting methods. Phase shifting scheme produces higher
amount of total harmonic distortion when compared to level shifting scheme. Therefore level
shifting is taken into consideration in the proposed work. Level shifting scheme is further
divided into three schemes namely in-phase disposition, phase opposition disposition and
alternate phase opposition disposition, where in with level shifting scheme an ‘N’ level
inverter requires ‘N-1’carrier waves. In-phase disposition involves all the carriers that are in
phase. All the carrier waves above zero reference are in phase while the ones below zero are
180 degrees out of phase in case of phase opposition disposition. Each carrier is 180 degrees
in phase difference with its neighboring carrier in alternate phase opposition disposition.

The publishers employed phase opposition disposition LS-PWM scheme for the pulse
generation for both 9 switch and 7 switch topologies. Positive pulses are generated when
reference wave is greater than all the carrier waves. Zero level is produced when reference is
greater than lower carriers and lesser than the upper carriers. Negative pulses are produced
when reference is lesser than all the carrier waves.

Circuits are simulated using MATLAB/SIMULINK software tool and total harmonic
distortions for both the circuits are obtained. It can be seen that there is a reduction in THD
content for the 7-switch topology when compared to that of 9-switches. Phase opposition
disposition level shifting method is followed for the pulse generation for both the topologies.

3. Rahul Nair, Mahalakshmi R, Dr. Sindhu Thampatty K.c. “Performance of Three Phase
11-level Inverter with reduced number of switches using different PWM Techniques”
2015 IEEE International Conference on Technological Advancements in Power & Energy
978-1-4799-8280-6/15/$31.00 ©2015 IEEE.
The paper explains about the new three phase configuration to generate 11-level
output with low total harmonic distortion (THD). In phase disposition (IPD), alternate phase
disposition (APD), carrier overlap (CO) and variable frequency (VF) pulse width modulation

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(PWM) techniques are used to generate switching pulses. The waveforms obtained after
implementing the series LC filter at the inverter output is analyzed in the paper.

The proposed inverter configuration has 8 switches and 3 DC sources per phase. The
series combinations among the three DC sources are V DC, 2 VDC and -2 VDC can be used to
generate eleven DC levels at the inverter output in a single cycle.

To control the frequency and harmonics of the output voltage of the inverter, one has
to select the most appropriate PWM technique. The sinusoidal PWM method has been
employed to the power switches in which a reference sinusoidal wave of fundamental
frequency is compared to high frequency carrier wave. The PWM techniques discussed in
this paper are in phase disposition level shift pulse width modulation (LS-PWM), anti-phase
disposition (APD) PWM and carrier overlap (CO) PWM and variable frequency (VF) PWM.
The amplitude modulation index is maintained at 0.9 and the frequency modulation index is
maintained at 200. The RMS value of the fundamental component of the output voltage
waveform and total harmonic distortion are observed using MATLAB/SIMULINK in the
scope. In all the PWM techniques, 'N' number of carrier signals are used to generate 2N+1
voltage levels.

From the simulation results, it was found that VF-PWM provides minimum THD of
12.51% in the inverter output voltage when compared to the other PWM methods. The
publishers analyzed and concluded that VF-PWM is best technique for inverter switching
because small inductance can be used in the LC filter placed in series to the inverter output to
generate a rectified AC sine wave of low THD of 1.77%.

4. Venu sonti, Sachin Jain, Vivek Agarwal ” A New Low Cost and High Efficiency
Cascaded Half-Bridge Multilevel Inverter with Reduced Number of Switches” 2014
IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)
978-1-4799-6373-7/14/$31.00 ©2014 IEEE.
The publishers implemented a new low cost and efficient cascaded multilevel inverter
(MLI) configuration. The proposed multilevel inverter requires less number of switching
devices and isolated power supplies compared to the basic multilevel inverter. It eliminates
the problem of neutral point fluctuations, DC offset current, diode reverse recovery problem
etc. as observed in conventional NPC and Flying capacitor configurations. Further, the given

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multilevel inverter also has the advantage of low conduction and switching losses. Thus the
proposed multilevel inverter has the advantages of low cost and better efficiency. The paper
also gives the generalized version of proposed configuration for (2m+1) levels.
The proposed multilevel inverter consists of 10 switches and four isolated power
supplies among them only five switches are conducting in a given state and the proposed
configuration also have the advantage of lower conduction and switching losses. Further, the
proposed configuration can be used for symmetrical and asymmetrical operation.

The proposed configuration can be extended to 2m+1 levels by cascading the

individual two level inverters where m is the number of DC sources used in topology. The
value of m is an even number and its starts from m=2. The operation of proposed cascaded
multilevel inverter in asymmetrical configuration for phase voltage levels are + 5/6 V DC, 0,
-5/6 VDC.

The proposed configuration can be operated in both symmetrical and asymmetrical

modes depending on the values of DC voltage source. In the proposed configuration, two
switches are operated at low switching frequency so the switching and conduction losses are
reduced. From the output results, depending on the value of modulation index the number of
levels in the output voltage changes. The simulation was carried out in
MATLAB/SIMULINK to verify the operation of proposed cascaded multilevel inverter
configuration in symmetrical and asymmetrical mode.

5. C. Dhanamjayulu and S. Meikandasivam, “Implementation and Comparison of

Symmetric and Asymmetric Multilevel Inverters for Dynamic Loads” 2017 International
Conference on Smart Technology for Smart Nation (ICSTSN) 2169-3536 ©2017 IEEE.
The publishers had implemented and comparison is made for both symmetric
hybridized cascaded multilevel inverter and an asymmetric multilevel inverter using a
switched capacitor unit for 17 level inverters. The symmetric hybridized multilevel inverter
topology consists of a modified H-bridge inverter which resulted into increased quality output
voltage waveform from the three levels by using a bi-directional switch at the midpoint of a
dual-input dc source. In the proposed asymmetric multilevel inverter DC sources are replaced
with the switched capacitor unit which in turn boosts the output voltage and generates twice
the voltage levels at the loads.

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2.2 PROBLEM STATEMENT AND ITS SOLUTION TOPOLOGY
A Cascaded H-Bridge multilevel inverter is a series connection of multiple H-bridge
inverters. Each H-bridge inverter has the same configuration as a typical single-phase full-
bridge inverter.

The cascaded H-bridge multilevel inverter introduces the idea of using separate DC
sources to produce an AC voltage waveform. Each H-bridge inverter is connected to its own
DC source VDC. By cascading the AC outputs of each H-bridge inverter, an AC voltage
waveform is generated at the output. By choosing the appropriate switches each H-bridge
inverter can generate three different voltages namely +V DC, 0 and –VDC.
MATLAB/SIMULINK 2018b is used as software tool for the simulation of the following
models.
 Single phase full bridge inverter and cascaded H-bridge five level inverter using
single phase pulse width modulation scheme.
 Cascaded H-bridge five and seven level inverter using single phase pulse width
modulation scheme.
 Cascaded H-bridge five and seven level inverter using sinusoidal pulse width
modulation scheme.
 Cascaded H-bridge five level inverter using level shifting pulse width modulation
scheme.

Later comparison is made with respect to total harmonic distortion for the following simulink
models
 Single phase full bridge inverter with cascaded H-bridge five level inverter employing
single phase pulse width modulation scheme.
 Cascaded H-bridge five and seven level inverter employing single phase pulse width
modulation scheme.
 Cascaded H-bridge five and seven level inverter employing sinusoidal pulse width
modulation scheme.
 Cascaded H-bridge five level inverter using level shifting pulse width modulation
scheme with single phase PWM and sinusoidal PWM schemes.
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 To overcome the problems associated with single phase full bridge inverter like high total
harmonic distortion, high electromagnetic interference, low quality output voltage waveform,
high conduction and switching losses, hardware is going to be developed for “cascaded H-
bridge five level inverter with reduced switch count employing sinusoidal pulse width
modulation technique” to obtain 5 different levels of output voltage (i.e. 24V, 12V, 0, -12V
and – 24V approximately) with two separate DC sources form 12V adapter each and
MOSFET’s as switching device.

Gate pulses can be generated by using microcontroller ARDUINO MEGA 2560 to

generate pulse width modulation signals to have control over the switches of inverter. To
generate the gate pulses in the microcontroller a program can be written in c language.
Multimeter is used to measure the total output voltage and current. Digital storage
oscilloscope is used to observe the PWM switching pulses and output voltage waveforms
across the cascaded H-bridge five level inverter. Further comparison will be made for both
simulation and hardware results for cascaded H-bridge five level inverter, where in the results
may vary or remain same due to the switching and conduction losses.

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CHAPTER-3
MULTILEVEL INVERTER
Multilevel inverters have received more and more attention because of their high
voltage operation capability, low switching losses, high efficiency and low output of Electro
Magnetic Interference (EMI). The term multilevel starts with the two-level inverter
introduced by Nabae et al (1981). Nowadays, multilevel inverters are becoming increasingly
popular in power applications. Multilevel inverters have the ability to meet the increasing
demand of power and power quality associated with reduced harmonic distortion and lower
electromagnetic interference.

Multilevel inverter has several advantages over a conventional two-level inverter that
uses high switching frequency pulse width modulation (PWM). The most attractive features
of a multilevel inverter are as follows:

1. They can generate output voltages with extremely low distortion and lower dv/dt.
2. They draw input current with very low distortion.
3. They generate smaller common-mode (CM) voltage.
4. They can operate with a lower switching frequency.

3.1 TOPOLOGY OF MULTILEVEL INVERTERS

Multilevel inverters have an arrangement of power switching devices and capacitor
voltage sources. Multilevel inverters are suitable for high-voltage applications because of
their ability to synthesize output voltage waveforms with a better harmonic spectrum and
attain higher voltages with a limited maximum device rating.

Mainly there are three types of multilevel inverters:

 Diode-clamped (neutral-clamped),
 Capacitor-clamped (flying capacitors) and
 Cascaded H-bridge inverter.

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 Multilevel
Inverters

Common DC Separate DC
Sources Sources

Diode- Capacitor-
Clamped Cascaded H-Bridge
Clamped

Fig. 3.1 Multilevel inverter topology

3.1.1 DIODE-CLAMPED INVERTER

The diode-clamped inverter is also known as the neutral-point clamped inverter
(NPC) which was introduced by Nabae et al (1981). The main concept of this inverter is to
use diodes to limit the power devices voltage stress. The voltage over each capacitor and each
switch is VDC. An n level inverter needs
 No. of voltage sources: (n-1),
 No. of DC bus capacitors: (n-1),
 No. of switching devices: 2(n-1) and
 No. of clamping diodes: (n-1) (n-2).
APPLICATIONS
1. Static VAR compensation.
2. Variable speed motor drives.
3. High voltage system interconnection.
4. High voltage DC and AC transmission lines.
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ADVANTAGES
1. A large number of levels ‘n’ yields a small harmonic distortion.
2. All of the phases share a common DC bus.
3. Reactive power flow can be controlled.
4. High efficiency for fundamental switching frequency.
5. Relatively simple control methods.

3.1.2 CAPACITOR-CLAMPED INVERTER

The capacitor-clamped multilevel inverter known as flying capacitor is similar to the
diode-clamped inverter was presented in Hochgraf et al (1994) and Lai et al (1996). The
capacitor-clamped multilevel inverter topology provides more flexibility in waveform
synthesis and balancing voltage. In capacitor-clamped inverter, the clamping diodes in the
diode-clamped topology are replaced by balancing capacitors or floating capacitors to
balance the voltages. The inverter uses capacitors to limit the voltage of the power devices.
The voltage over each capacitor and each switch is VDC. Each phase-leg has an identical
structure. The size of the voltage increment between two capacitors determines the size of the
voltage levels in the output waveform.
 No. of voltage sources: (n-1),
 No. of DC bus capacitors: (n-1),
 No. of switching devices: 2(n-1) and
 No. of balancing capacitors: {(n-1) (n-2)}/2.

APPLICATIONS
1. Induction motor control using DTC (Direct Torque Control) circuit.
2. Static VAR generation.
3. Both AC-DC and DC-AC conversion applications.
4. Converters with Harmonic distortion capability.
5. Sinusoidal current rectifiers.

ADVANTAGES
1. Large ‘n’ allows the capacitors extra energy during long discharge transient.
2. Phase redundancies are available for balancing the voltage levels of the capacitors.
3. Lower Total Harmonic Distortion when the number of levels ‘n’ is high.
4. Active and Reactive power flow can be controlled.

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3.1.3 CASCADED H-BRIDGE MULTILEVEL INVERTER
The cascaded H-bridge multilevel inverter has drawn tremendous interest due to the
greater demand of medium-voltage high-power inverters. The cascaded inverter uses series
strings of single phase full bridge inverters to construct multilevel phase legs with separate
DC sources. A single H-bridge is shown in Figure 3.2. A single H-bridge is a two-level
inverter. Each single-phase full-bridge inverter generates three voltages at the output are
VDC, 0, and - VDC. The four switches S1, S2, S3 and S4 are controlled to generate three discrete
outputs Vout with levels VDC, 0, and -VDC.

Fig 3.2 Single H-Bridge Topology

Fig 3.3 Cascaded H-Bridge Five Level Inverter

Fig 3.3 shows a single phase five-level cascaded H-bridge inverter by connecting two
two-level conventional full bridge inverters in series .Switch pairs S1 and S3 and S2 and S4 are
complementary to each other. The different voltage level that can be obtained at the output
terminals are 2VDC, VDC, 0, -VDC and -2VDC. The number of levels in the output voltage can be
increased by two by adding an identical inverter in series.

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APPLICATIONS

1. Motor drives.
2. Active filters.
3. Electric vehicle drives.
4. DC power source utilization.
5. Power factor compensators.
6. Back to back frequency link systems.
7. Interfacing with renewable energy resources.
ADVANTAGES
1. The series structure allows a scalable, modularized circuit layout and packaging due
to the identical structure of each H-bridge.
2. No extra clamping diodes or voltage balancing capacitors are necessary.
3. Switching redundancy for inner voltage levels is possible because the phase voltage is
the sum of the output of each bridge.
Several switching strategies have been proposed for cascaded H-bridge converters. PWM
technique is extensively used for eliminating harmful low-order harmonics in inverters. In
PWM control, the inverter switches are turned ON and OFF several times during a half cycle
and output voltage is controlled by varying the pulse width.

Sinusoidal pulse width modulation (SPWM):

A sinusoidal pulse width modulation method is also known as triangulations, sub
oscillation, sub harmonic method is very popular in industrial applications. In this technique a
high frequency triangular wave is compared with the sinusoidal reference wave determining
the switching instant. The modulating signal is a sinusoidal of amplitude Am, and the
amplitude of triangular carrier wave is Ac, then the ratio m= Am ÷ Ac is well known as
modulation index. It is noted that by controlling the modulation index one can control the
magnitude of applied output voltage and frequency of inverter. The block of sinusoidal pulse
width modulation is given below Fig. 3.4

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 Fig. 3.4 Schematic circuit for comparison of modulating and carrier signals.

Switching logic will be :

Vo = +VDC if Vr > Vc
Vo = -VDC if Vr < Vc
Where,

Vr is the modulating sinusoidal signal

Vc is the carrier triangular signal
Vo is the rms output voltage of the inverter
VDC is the DC link voltage
Modulating frequency = 50Hz
Carrier frequency = 10 KHz

Level shifting pulse width modulation:

In the LS PWM method, the amplitude of the each carrier signal is defined as ratio of
amplitude of the reference signal to the number of sub modules. The position of the carrier
signals are adjusted by adding and the amplitudes of the carrier signal so that a sub module
carrier signals separated which adds 120 degree phase difference to reference angle. In level
shifting method the ‘N’ level inverter requires ‘N-1’ carrier waves.

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 CHAPTER-4
BLOCK DIAGRAM OF CASCADED H-BRIDGE FIVE LEVEL
INVERTER AND ITS DESCRIPTION

SINGLE PHASE
230V AC, 50 Hz

STEP DOWN STEP DOWN

TRANSFORMER TRANSFORMER

RECTIFIER RECTIFIER

12V DC
SMPS
FILTER ADAPTER
FILTER

12V DC
VOLTAGE SMPS
REGULATOR ADAPTER
(IC 7805)

DRIVER CASCADED H-
MICROCONTROLLER CIRCUIT BRIDGE FIVE
(ARDUINO MEGA 2560) (TLP 250) LEVEL INVERTER

DIGITAL
RESISTIVE
STORAGE
LOAD
OSCILLOSCOPE

Fig. 4.1 Block diagram of cascaded H-bridge five level inverter with reduced number of
switches

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 Figure 4.1 shows the complete block diagram of the developed hardware for cascaded
H-bridge five level inverter which consists of transformer, rectifier,  filter,  voltage regulator
LM 7805 IC, cascaded H-bridge five level inverter, microcontroller (arduino mega 2560),
resistive load of 100Ω and digital storage oscilloscope. The brief explanation of each block is
given as follows:

Transformer: It is static device which transfers power from one circuit to the other circuit
with constant frequency. It works on the principle of electromagnetic induction. Transformer
does not have any rotating parts so the efficiency of the transformer is high compare to the all
electrical equipment’s.

Rectifier: It  is a device which converts the ac signal into dc signal. The output voltage of a
rectifier circuit contains unwanted ac components (components of supply frequency f and its
harmonics) along with dc component. In order to reduce ac components from the rectifier
output voltage a filter circuit is required.

Filter: It is a device which passes dc component to the load and blocks ac components of the
rectifier output. Filter is typically constructed from reactive circuit elements such as
capacitors and/or inductors and resistors.

Driver circuit: The main function of driver circuit is to amplify the signals which are
generated from microcontroller unit. TLP driver circuit also provides isolation between the
power circuit as well as the control circuit. TLP250 is more suitable for MOSFET and IGBT.
The main difference between TLP250 and other MOSFET drivers is that TLP250 driver is
optically isolated. It means that input and output of TLP250 driver is isolated from each
other.

Microcontroller (ARDUINO MEGA 2560): It is a small computer on a single integrated

circuit which consists of core, memory and processor on it. A program is written for the
control of the circuit. There are many different types of the microcontroller used for different
applications and Arduino mega 2560 is used to have the control over the inverter circuit.
Arduino can sense the environment by receiving input from a variety of sensors and
can affect its surroundings by controlling lights, motors, and other actuators. The
microcontroller on the board is programmed using the Arduino programming language
(based on Wiring) and the Arduino development environment (based on Processing). Arduino

18
projects can be stand-alone or they can communicate with software running on a computer
(e.g. Flash, Processing and Max MSP). The boards can be built by hand or purchased pre
assembled; the software can be downloaded for free. The hardware reference designs (CAD
files) are available under an open-source license; you are free to adapt them to your needs.

Voltage regulator: Voltage source in a circuit may have fluctuations which may not provide
fixed output voltage. A voltage regulator maintains constant value of output voltage. 7805 IC
is a member of 78xx series of fixed linear voltage regulators used to maintain such
fluctuations which are a popular voltage regulator integrated circuit (IC). The xx in 78xx
indicates the output voltage it provides.

SMPS ADAPTER: A switched-mode power supply is an electronic power supply that

incorporates a switching regulator to convert electrical power efficiently. Like other power
supplies, an SMPS transfers power from a DC or AC source (often mains power) to DC loads
such as a personal computer, while converting voltage and current characteristics.

19
CHAPTER 5
Existing System

Modes Of Operation For Cascaded H-Bridge Five Level Inverter

Modes of operation:
According to the switching states of the MOSFET’s used in the designed hardware for
cascaded H-bridge five level inverter is as shown in fig.5.1.

General structure of multilevel inverter. Each 4-switch block represents an H-bridge, each
equipped with its own DC source

Mode 1: In this mode of operation switches S1, S4, S5 and S8 are conducting where as the
remaining switches are turned off and produce the positive cycle of output voltage is shown
in the below fig 5.2

Vo=V 1+V 2

Mode 2: In this mode of operation switch S 2 and S6 are turned off where as the remaining
switches are turned on. Switch S 1 and S4 are conducting to produce the positive cycle of
output voltage which is shown in the below fig 5.3
V 1+V 2
Vo=
2

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Mode 3: In this mode of operation all the switches are turned off and produces zero output
voltage which is equal to 0V which is shown in the below fig 5.4
Mode 4: In this mode of operation switches S1 and S5 are turned off where as the remaining
switches are turned on. Switch S 2 and S3 are conducting to produce the negative cycle of
output voltage which is shown in the below fig 5.5
−V 1−V 2
Vo=
2
Mode 5: In this mode of operation switches S1, S4, S5 and S8 are turned off where as the
remaining switches are conducting to produce the negative cycle of output voltage which is
shown in the below fig 5.6
Vo=−V 1−V 2
.

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CHAPTER 6
PROPOSED SYSTEM

In this project, both general switching sequences and PWM switching are implemented in
cascaded modified H-bridge MLI. If the general switching sequences are used, the MOSFETs
used as the switching devices toggle between on and off at a frequency of 50 Hz (frequency
of the residential supply). But for PWM switching, this frequency becomes more than 1 kHz.
Therefore, switching loss for the switching sequences is insignificant as compared to the
switching loss for PWM switching. However, PWM follows ideal sinusoidal wave closely,
which results in less THD in the inverter output. In the case of using switching sequences,
discrete staircase sinewaves or quantized sinewaves are generated, thus the output does not
follow ideal sinusoidal shape, producing a higher THD. 5-level output can be generated using
the modified cascaded H-bridge configuration (shown in Fig. 2b). In this configuration, two
H-bridges are connected in such a way that it can generate 5-level output with reduced
number of switches. There are 6 switches in this modified circuit rather than the 8 switches
required in the general CHB configuration. The general switching sequence for this
architecture to produce 5 voltage levels at the output are shown in Table 1. From Fig. 4,
where the operation of the modified CHB inverter by switching sequences is shown, it can be

22
seen that for any case, two-thirds of the total MOSFETs conduct. For the cases of +V and −V
outputs, two MOSFETs, and one body diode conducts. For +2V and −2V outputs, 3
MOSFETs conduct. Therefore, it is evident that the modified H-bridge configuration reduces
switching and conduction losses as it uses less switching elements to produce the same
outputs

Generation of four distinct voltage levels in the modified 5-level cascaded H-bridge multilevel
inverter, when operated by switching sequences shown in Table 1. (a) +V. (b) −V. (c) +2V. (d) −2V.

TABLE 1. Switching sequences for modified 5-level cascaded H-bridge inverter.

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CHAPTER 7
DEVELOPMENT OF HARDWARE FOR CASCADED H-
BRIDGE FIVE LEVEL INVERTER

The components used for the developed hardware for cascaded H-bridge five level
inverter employing sinusoidal pulse width modulation method includes the following:
 Input AC supply of 230V, 50Hz
 Step down transformer (12V -6V-12V)
 Diode bridge rectifier (DB 107)
 Filter (Capacitor)
 Voltage regulator (LM 7805 IC)
 Microcontroller (Arduino mega 2560)
 Driver circuit (TLP 250)
 SMPS adapter of 12V DC
 N-channel MOSFET (IRF 840)
 Resistive load (100Ω)
 Digital storage oscilloscope
AC supply of 230V, 50Hz input is easily available everywhere which is used for
turning on the developed hardware.

7.1 STEP DOWN TRANSFORMER (12V-6V-12V)

It is static device which transfers power from one circuit to the other circuit with
constant frequency. It works on the principle of electromagnetic induction. Transformer does
not have any rotating parts so the efficiency of the transformer is high compare to the all
electrical equipment’s. In the developed hardware two center tap transformers of rating 12V-
6V-12V are used. Input AC supply of 230V is given to primary windings of step down
transformer and secondary windings are connected to diode bridge rectifier IC DB107 which
is readymade.

Ratings of step down transformer:

 Voltage rating: 25V
 Current rating: 1A

24
 Fig. 7.1 Step down transformer

7.2 RECTIFIER (DB107)

It is a type of converter which is used for converting ac to dc. The process of
converting ac into dc is called as rectification. The output voltage from a rectifier circuit has a
pulsating character i.e. it contains unwanted ac components (components of supply
frequency f and its harmonics) along with dc component. In order to reduce ac components
from the rectifier output voltage a filter circuit is required.
Rating of rectifier:
 Maximum recurrent peak reverse voltage: 1000V
 Maximum RMS bridge input voltage: 700V
 Maximum DC blocking voltage: 1000V
 Maximum average forward output current at TA = 40ºC: 1A

Fig. 7.2 Bridge rectifier

7.3 FILTER (1000µF CAPACITOR)

Filter is a component which is used for the reduction of harmonics to remove the
unwanted components from the system. It plays a very improvement role for improving the
efficiency of the overall system. Filter is typically constructed from reactive circuit elements
such as capacitors and/or inductors and resistors. Capacitor is used as filter circuit.
Capacitor value = 1000µF
Voltage rating = 25V

25
 Fig. 7.3 Filter as capacitor

7.4 VOLTAGE REGULATOR

Voltage regulators are commonly used in electronic circuits to provide constant DC
output voltage for the variable input voltage.

7.4.1 7805 IC
This voltage regulator find applications in most of the projects where 78 indicates
that it is a positive voltage regulator where as the last digit 05 indicates that it maintains 5V
constant output voltage.

7805 IC rating and pin description of LM7805 IC

 Input voltage range 7V - 20V
 Output Current rating is 0.5 mA to 1A
 Output voltage range VMax = 5.2 V ,VMin =4.8 V
 Output Power rating ≤ 15W
 Operating temperature - 40ºC to 125ºC
Pin 1: Input voltage of 7V – 35V.
Pin 2: Connected to ground which is neutral pin equally for both input and output.
Pin 3: Regulated output of 5V (4.8 V to 5.2 V)

230V-12V 1(Vcc) 3(VO)

DB107 7805 IC

+ C=1000µF

1Φ 230V
2
AC (GND) MICROCONTROLLER

Fig.7.4 Pin diagram connection of 7805 IC

7.5 MICROCONTROLLER (ARDUINO MEGA 2560)

Arduino can sense the environment by receiving input from a variety of sensors and
can affect its surroundings by controlling lights, motors, and other actuators. The

26
microcontroller on the board is programmed using the Arduino programming language and
the arduino development environment. Arduino projects can be stand-alone or they can
communicate with software running on a computer (e.g. Flash, Processing, Max MSP). The
hardware reference designs (CAD files) are available under an open-source license which is
free to adapt them to your needs.

The Arduino Mega 2560 is a microcontroller board based on the ATmega2560. It has
54 digital input/output pins (of which 15 can be used as PWM outputs), 16 analog inputs, 4
UARTs (hardware serial ports), a 16 MHz crystal Oscillator, a USB connection, a power
jack, an ICSP header, and a reset button. It contains everything needed to support the
microcontroller; simply connect it to a computer with a USB cable or power it with a AC-to-
DC adapter. The Mega 2560 is an update to the arduino mega, which it replaces. The
Mega2560 differs from all preceding boards in that it does not use the FTDI USB-to-serial
driver chip.

7.6 TLP 250 DRIVER CIRCUIT

The main function of driver circuit is to amplify the signals generated from micro
controller. TLP driver circuit also provides isolation between the power circuit as well as the
control circuit. TLP250 is more suitable for MOSFET and IGBT.
 Input supply = 10-35 V
 Input current = 11 mA (max)
 Output current = ± 1.5 mA (max)
 Output voltage ≤ 70ºC = 35V
7.7 MOSFET (IRF 840)
IRF 840MOSFET is the third generation power MOSFET with the best combination of
fast switching, ruggedized device design, low on-resistance and cost-effectiveness.it is
preferred for industrial applications where power dissipation levels is approximately 50 W.
The low thermal resistance and low package cost contribute to its wide acceptance
throughout the industry.

N-channel MOSFET’s are used as switching devices for designing cascaded H -bridge
five level inverter. According to the switching table the MOSFET’s are turned on and off for
obtaining particular desired level. The designed hardware generates 5 different voltage levels

27
which have possibilities of five switching states (repeated sequences). The ratings of IRF 840
MOSFET’s are as follows:
 Drain to source voltage (VDS) = 500V
 Gate to source voltage (VGS) = 500V
 Drain current ID = 8A
IRF 840 is used in the developed hardware as the result output current is 0.24A with total
output voltage V=24V and resistive load R=100Ω, hence the rated current should be more
than 10-15 times the output current.

Internal Schematic
Diagram
Fig 7.8 IRF 840 n-channel MOSFET

7.8 RESISTIVE LOAD:

Resistive load of 100Ω is used across the developed hardware on cascaded H-bridge
five level inverter.

7.9 SMPS ADAPTER:

A switched-mode power supply is an electronic power supply that incorporates
a switching regulator to convert electrical power efficiently. Like other power supplies, an
SMPS transfers power from a DC or AC source (often mains power) to DC loads such as
a personal computer, while converting voltage and current characteristics.

7.10 DIGITAL STORAGE OSCILLOSCOPE:

28
 Digital storage oscilloscope is a device in which the signals (waveforms) can be
stored and analyzed firmly as compared to analog techniques (cathode ray oscilloscope) and
can be retrieved from the stored location for the any further requirements.

CHAPTER 8
EXPERIMENTAL SETUP AND ITS RESULTS

The hardware for cascaded H-bridge inverter employing sinusoidal pulse width
modulation method is designed to obtain five different voltage levels with two separate DC
sources from 12V SMPS adapter each employing sinusoidal pulse width modulation scheme
resulted in to staircase waveform which is nearly sinusoidal in nature. Sinusoidal PWM
technique is a modulation scheme where triangular waves are compared with reference sine
wave to generate PWM switching pulses. The prototype model for cascaded H-bridge five
level inverter employing sinusoidal pulse width modulation technique is tested in the power
electronics laboratory and the observations are made in the digital storage oscilloscope.
Calculation of output current across the resistive load:
Output voltage: Input DC supply of 12V each from SMPS adapter
Vo=V 1+V 2
Vo=12+ 12Vo=24 V

Resistive load = 100Ω

Vo
Output current IO = R
24
= 100

IO = 0.24 A

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CHAPTER 8
POSSIBLE OUTCOME

Fig 8.8 Five level output voltage waveform for cascaded H-bridge five level inverter

30
CHAPTER 9
ADVANTAGES AND APPLICATIONS

9.1 ADVANTAGES
Cascaded H-bridge multilevel inverter has advantages over conventional two stage
inverter which are given in the following:

1. Reduction in total harmonic distortion.

2. Conduction and switching losses are minimized.
3. Filtering and driver circuit requirements are minimized.
4. High quality output voltage waveform with low distortion.
5. Low voltage stress on switches.
6. Low common mode voltage.
7. Better electromagnetic interference (EMI).

9.2 APPLICATIONS
24V AC applications for the developed hardware of cascaded H-bridge five level
inverter:

1. They are used in motor applications like small gear motors, micro AC
synchronous motors, small AC synchronous gear motors, Automatic Debug
Monitor CCTV Product Remote Controller AC Synchronous Motor and so on.
2. Used in E-bikes.

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 PAPER PUBLISHED

The outcome of the dissertation work is published in the form of article/paper in the “Journal
of Emerging Technologies and Innovative Research” – Volume 6, Issue 6, June-2019 with
ISSN: 2349-5162, pp.736-745.

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