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log 2 40=5.321928095
27−1=127
120
=7 , rem 8
16
120 en hexadecimal es 0x78, y 0x78 a binario es:
0 x 7 → 0 b 0111
0 x 8→ 0 b 1000
120 en binario es 0b 0111 1000
89
=5 , rem 9
16
89 en hexadecimal es 0x59
0 xF → 1111
0 x → 0100
0xF4 en binario es 0b 1111 0100
0 xB2
+0 x9 F
0 x 151
El resultado de la suma de 0xB2 + 0x9F = 0x151
9. Compute 0xB2 – 0x9F and give the result in hex. Check your work by verifying that 0xB2+
~(0x9F) + 0x1 produces the same result. To compute ~(0x9F), complement each bit.
10. Draw the logic network and derive the truth table for the logic function F = (A&B) | C.
A B C F
0 0 0 0
0 0 1 1
0 1 0 0 11. Derive the CMOS transistor network that implements the NOR
0 1 1 1 function.
1 0 0 0
1 0 1 1
1 1 0 1 12. Compute 0xC3 >> 2; give the value in hex (this is a right shift by two).
1 1 1 1
0 x C 3→ 0 b 1100 0011
0 x C 3≫ 2 →0 b 0011 0000
0 b 0011 0000 → 0 x 30
El valor de 0xC3 con desplazamiento a la derecha por dos es 0x30
13. Compute 0x2A << 1; give the value in hex (this is a left shift by one).
0 x 2 A → 0 b 00101010
0 x 2 A ≪1 → 0 b 01010100
0 b 0101 0100 →0 x 54
1
Periodo= =2.5 μs
400 kHz
15. Given a 30 percent duty cycle clock with a high pulse width of 20 µs, what is the clock
frequency in kHz?
PW H
Periodo= ×100 %
Duty cycle
20 μs
Periodo= ×100 %=66.66667 μs
30 %
1
Frecuencia= =15 kHz
66.66667 μs
16. Design an n-bit subtractor using an adder with a carry-in input and the fact that A – B = A +
~B + 1
17. Design an n-bit adder/subtractor that has an external input called SUB that when 1,
performs a subtraction, when 0, performs an addition. (Hint: Use an adder with a carry-in input
and a mux.)
Cuando SUB = 0, S = A + B
19. Design a counter that can count either up or down. Assume that you have incrementer and
decrementer building blocks available.
0x4A 0x6F 0x73 0x75 0x61 0x74, la traducción carácter por carácter produce el nombre de Josuat.