2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
Development of FPGA based TCP/IP communication
module for Embedded Systems of Nuclear Reactors
2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE) 978-1-7281-4142-8/20/$31.00 ©2020 IEEE 10.1109/ic-ETITE47903.2020.9
Aditya Gour12, Tom Mathews12, R P Behera1, M Sakthivel1, T Jayanthi12, B K Panigrahi12
1
Indira Gandhi Centre for Atomic Research, Kalpakkam, India
2
Homi Bhabha National Institute, Mumbai, India
Email: adityagour@igcar.gov.in
Abstract—Distributed digital control architecture is being
followed for plant data communication and control of final
control elements in current and upcoming generation of nuclear
power plants. Ethernet communication using TCP/IP protocol
plays a key role in interconnecting over 40,000 signals that are
geographically distributed across the plant with centralized
server and display stations located in main control room. TCP/IP
Communication modules are used in each embedded system for
sending and receiving digitized data over plant backbone.
Offloading TCP/IP communication tasks from the main
processor guarantees real time performance for safety critical
and safety related applications in nuclear power plant. This
approach simplifies software architecture and makes CPU
function independent of communication tasks, thereby making
overall system dependable & predictable. Design of such TCP/IP
communication module for better maintainability, smoother
certification and replacement for commercially available module
is described in this paper.
Keywords— TCP/IP communication Module, FPGA, VHDL,
Data Acquisition & Control System, PFBR
I. INTRODUCTION
Prototype Fast Breeder Reactor is being commissioned at
Kalpakkam, India. All Safety Critical and Safety Related
instrumentation and control (I&C) systems are developed and
qualified in-house by certification agencies [1]. Distributed
control architecture is used for current and upcoming fast
breeder reactors in India as shown in figure -1.
Figure 1: Distributed Control System Architecture
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As per this architecture various sensors and actuators are
grouped and connected to nearest data acquisition & control
systems (DAQs) placed in local control centers (LCC). With
the help of switched network concept these DAQs are located
in multiple LCCs to communicate their data and receive
control signals from the control room [2]. Approximately
40,000 signals are connected to central server in Prototype Fast
Breeder Reactor (PFBR). TCP/IP communication plays a key
role for successful operation of this architecture. Design of
entire I&C for Nuclear Island is done indigenously for safety,
security and certification reason. Existing data acquisition &
control systems are designed with commercially available
TCP/IP modules which offload routine communication tasks
from the main processor. This approach spares the CPU
resources for time critical applications, makes the software
architecture simpler & reliable eliminating the need for porting
real time operating system to the processor and hence the real
time safety critical tasks are executed independently of
communication tasks [3]. This TCP/IP communication module
is designed and developed in-house for upcoming fast breeder
reactors to improve upon number of socket support,
certification process, eliminating dependency on third party
vendors and component obsolescence issues. This paper
describes the hardware design of the above mentioned TCP/IP
communication module proposed for data acquisition &
control systems for upcoming nuclear reactors.
This paper is organized as follows: Section-II describes the
design requirements for the communication module, Section-
III describes the concept behind this design, Section –IV
describes in performance of the RTL design on the
development board. Section – V describes the design details of
the final product. Section – VI describes the testing of this
module with one of the data acquisition system. Conclusion &
future work in described in section – VII.
II. REQUIREMENTS OF TCP/IP COMMUNICATION MODULE
The design requirements for the TCP/IP communication
module are as follows:
1. The entire TCP/IP communication task shall be
implemented on a programmable logic device like
FPGA.
2. The RTL design should be generic and portable to
any FPGA device and should be modifiable for ASIC
implementation.
1
 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
3. Microprocessors / microcontroller based design with the overall software complex and difficult to validate
software TCP/IP stack shall not be used for better completely.
maintainability and avoiding software unreliability & 3. External SRAM or DDR memory is required for
complex operating system. executing the stack along with OS.
4. VHDL being a strongly typed language [6] shall be 4. More power consumption because of more number of
preferred over other hardware descriptive languages. components like processor, memory etc.
5. Design shall be done in accordance with IEC 62566 5. More space requirement
standard [7]. In view of the above mentioned issues, the approach
6. Register interface of the module shall be suitably illustrated in figure-2 is implemented. The logic for entire
designed to interface the TCP/IP engine with any TCP/IP stack (excluding Physical Layer functionality) is
parallel bus interface of processor or microcontroller implemented in VHDL and ported in to FPGA. Typical
based CPU card. TCP/IP protocol layers (best described in reference [5]) are
7. Sufficient memory shall be provided to store the send shown in figure-3.
& receive TCP/IP data and upon send or receive
command from the processor, the data shall be send
or received via TCP/IP communication.
8. Dimensions and electrical connections shall be
compatible with commercially available module
(60mm x 25mm).
9. Minimum of 10 parallel connections (Sockets) shall
be supported with data throughput better than 500
Kbps.
10. RTL as well as Hardware design shall be thoroughly
verified & validated by independent teams.
The block diagram of the desired system is shown in figure-2.

Figure 3: TCP/IP Protocol (Courtesy TCP/IP Guide.com)

Many of the underlying sublayer protocols (like TELNET,

FTP, SNMP etc.) of the TCP/IP are generally not required for
data acquisition and control systems deployed for industrial
applications. Hence the VHDL code for the required layers
consisting of EMAC, ARP, IP, IGMP, UDP and TCP protocol
was developed. Appropriate Test benches were developed and
with the input stimulus from Wireshark capture files the
design was simulated. After simulation the RTL design was
tested on a FPGA reference board (shown in Figure - 4) with
FPGA, RGMII PHY and other peripherals.
Figure 2: TCP/IP communication Module Requirements

III. CONCEPT FOR HARDWARE DESIGN OF TCP/IP

COMMUNICATION MODULE
Functionality of TCP/IP communication module are achieved
by porting a software TCP/IP stack onto processor or
processor based SoC with PHY and DDR memory support [4].
But this approach would have the following limitations:
1. Long term device availability from SoC
manufacturer.
2. Software TCP/IP stack along with real time operating
system needs to be ported onto processor. This makes
Figure 4: Development board for testing

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 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
IV. PERFORMANCE TESTING ON THE REFERENCE BOARD
The multiple socket support was tested by running RTL
design with 20 sockets support on FPGA development board
configured as a TCP server and connecting it via LAN cable
to desktop computer running 20 instances of Tera Term client
software as shown in figure - 5. For measuring throughput 1
Mega Byte of data was written continuously into the send data
buffer and the number of clock periods required to send this
data was measured independently via a counter with clock
period of 8.33 ns. The values of this 32 bit counter was
observed via a Xilinx chipscope tool. The best performance
was achieved when we were able to transmit 8 Mbyte of data
through a switched network in 3.78 sec over IGCAR LAN
which meant the data throughput of 2.11 Mbps.
VI. TESTING OF TCP/IP COMMUNICATION MODULE WITH CPU
Figure 5: Demo for 20 TCP/IP sockets connected with
FPGA Reference Board
V. DESIGN OF TCP/IP COMMUNICATION MODULE
Based on the concept the TCP/IP communication module was
developed. The block diagram for the schematic design is
shown in figure – 6.
Figure 6: Block Diagram for the Schematic Design
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Industrial grade FPGA device is selected to accommodate up
to 3 times larger logic required for 20 sockets support. PHY is
selected to support RGMII interface. Level translators are
provided for compatibility with 5V TTL devices. Dual
redundant 120 MHz clock oscillators are provided for core
logic operation. Flash is provided for power on FPGA
configuration using BPI mode. RJ45 connector is chosen with
integrated magnetics. Component placement and PCB layout
is done to dimensionally and electrically match with the
commercially available TCP/IP module (Wiz-NM7010). The
layout is done in 12 layers. Fabricated module is shown in
figure – 7.
Figure 7: Fabricated TCP/IP communication module
BOARDS
The fabricated TCP/IP communication modules are assembled
on CPU boards (figure-8) of one of the data acquisition &
control system (DAQs) designed at EIG, IGCAR. This DAQs
consists of dual CPUs and set of field input/output boards
(Thermocouple input, relay output, leak detector input etc.) as
shown in figure - 9.
Figure 8: CPU Board of reference data acquisition system
Figure 9: Reference DAQ for Testing TCP/IP
Communication Module
 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
This DAQs acquire data from field input/output boards and
communicates data to control room server via TCP/IP
communication and the command issued from servers (display
stations) is received by this DAQs and appropriate output is
generated. For testing this system a Qt based client software
(GUI) (shown in figure-10) was developed which receives
TCP/IP data from DAQs (communication module) and also
provides command interface. 545 bytes of data is
communicated every second to 4 different sockets. After
continuous testing the satisfactory performance of the TCP/IP
module was concluded.
Figure 10: GUI for testing DAQs along with TCP/IP
communication Module
VII. CONCLUSION & FUTURE WORK
Distributed Control Systems Architecture is being followed
for Fast Breeder Reactors. TCP/IP communication is a
backbone for this architecture because it plays the key role in
interfacing thousands of field equipments to the central control
room. TCP/IP communication offload modules are extensively
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used in various DAQs which offloads the communication
tasks from CPUs without affecting real time performance.
FPGA based TCP/IP communication modules are
indigenously designed for secured plant data communication,
white-box testing, independent verification & validation,
smoother certification, performance enhancements and
overcoming component obsolescence issues up to certain
extent. All the layers of TCP/IP protocol except Physical layer
are implemented using VHDL and ported on to FPGA. This
communication module is also tested with a reference data
acquisition and control system. In future the verification of the
RTL design using Universal Verification Methodology and
performance evaluation of the module on the existing CPU
board of PFBR will be done.
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