Chapter 5 Control Design

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 Topic 01: Basic Concepts and
Hardwired Control
 Basic Concepts
 Introduction
 Multicycle Operations
 Two approaches for control unit design
 Hardwired Control
 Design of GCD processor
 Design of A DMA Controller

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 Basic Concepts

 General structure and behavior of control units

 Design of hardwired controllers

 Characterized by the use of fixed logic circuits

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 Introduction

Simple processor composed of a datapath unit (DP) and control unit (CU)

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 Three types of control
signals that implements
an addition instruction of
the form ADD A, B

 Function select:
Add

 Storage select:
Read A, Read B, Write A

 Data Routing:
Select p-t, Select u-w,
select v,x.

The processor composed of a datapath unit (DP) and control unit (CU)
configured to implement the add operation A:=A+B.

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 Multicycle Operations

ADD AL, BL
ADDC AH, BH

Cycl Function Storage Control Data

e Select Routing
1 Add Read AL, Read Select p-t,
BL, Write AL Select u-w,
Select v-x
2 Add with carry Read AH, Read Select p-t,
BH, Select u-w,
Write AH Select v-x

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 LOOP: if COND1= true then ADD A,B
else SUB A, B;
if COND2= true then go to OUTPUT
else LOOP;
OUTPUT: ………….

Next address Function select

Current Condition Storage Data
address Select C Control routing
C =true C ǂ true C =true C ǂ true

ADR1 COND1 ADR2 ADR2 ADD SUB … ….

ADR2 COND2 ADR3 ADR1 ….. …… …. …….

ADR3 ……… ……….. ……… …… ……. ……. ………..

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 Two approaches for control unit design
A hard-wired control unit
: a sequential logic circuit to generate specific fixed sequences
of control signals → change in behavior only by redesign.
A microprogrammed control unit
: by organizing control signals into microinstructions. The
signals are implemented by a kind of software(or firmware) rather
than hardware.
In design : change the contents of control memory.
A microprogrammed CPU can execute programs written in the
machine language of other computers.
Disadvantage:
 Slower due to fetch.
 more costly due to the presence of the control
memory and its access circuits.
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 Two approaches for control unit design

(a) (b)
Fig. General Structure of (a) a hardwired and (b) a microprogrammed control unit.

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 Hardwired Control
Design method 1 : The classical method of sequential circuit design.
For a P-state circuit,  log2P flip-flops are required.
Design method 2 : One-hot method, one flip-flop per state. Expensive in
terms of flip-flop, but simplify CU design and debugging.

State tables for a finite-state machine: (a) Mealy type and

(b) Moore type
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 Procedure GCD

gcd (in:X,Y; out:Z);

register XR, YR, TEMPR;
XR:=X; (Input the data)
YR:=Y;
while XR>0 do begin
if XR≤YR then begin (Swap XR and YR)
TEMPR:=YR;
YR:=XR;
XR:=TEMPR; end
XR:=XR-YR; (Substract YR from XR)
end
Z:=YR; (Output the result)
end gcd;
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 GCD processor
gcd(X,Y)= gcd(20,12)

Conditions Actions
XR := 20;YR :=12;
XR>0: XR > YR: XR := XR – YR =8;
XR>0: XR ≤ YR: YR :=8; XR :=12; XR := XR – YR =4;
XR>0: XR ≤ YR: YR :=4; XR :=8; XR := XR – YR =4;
XR>0: XR ≤ YR: YR :=4; XR :=4; XR := XR – YR =0;
XR≤ 0: Z :=4;

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 Fig. Hardware needed to implement the gcd procedure.

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 GCD processor

A Moore-type state table defining the control unit of the gcd processor

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 GCD processor
Classical method : S0 = 00, S1 = 01, S2 = 10 and S3 = 11

Fig. A excitation table for the control unit of the gcd processor
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 GCD processor
Classical method : S0 = 00, S1 = 01, S2 = 10 and S3 = 11

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 GCD processor

Fig. All-NAND classical design for the control unit of the gcd processor

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 GCD processor- One-hot method
S0 = 0001, S1 = 0010, S2 = 0100, and S3 = 1000
• The one-hot method is limited to a small number of states
• The next-state and output equations have a simple and
systematic form

A Moore-type state table defining the control unit of the gcd processor

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 GCD processor- One-hot method

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 GCD processor- One-hot method

Fig. All-NAND one-hot design for the control unit of the gcd processor
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 Eg. Design of A DMA Controller
Inputs: IOREQ Any of four data-transfer request signals
CONT Continue (indicates pending, unprocessed
requests)
MACK Memory transfer acknowledgment
PBGNT Processor bus grant (indicates availability of
data transfer bus)
Outputs: CE Count Enable (bookkeeping function)
CMREQ Channel memory request
CNTLD Counter load (bookkeeping function)
RLD Register load (bookkeeping function)
PBREQ Processor bus request for control of data-
transfer bus

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 Eg. Design of A DMA Controller

Fig. state behavior of the DMA controller – State transition graph

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 Eg. Design of A DMA Controller
Inputs Outputs
Present Next
IOREQ CONT MACK PBGNT state state PBREQ CNTLD CMREQ RLD CE

0 d d d S0 S0 0 0 0 0 0
1 d d d S0 S1 0 0 0 0 0
d d d 0 S1 S1 1 0 0 0 0
d d d 1 S1 S2 1 0 0 0 0
d d 0 d S2 S2 0 1 1 0 0
d d 1 d S2 S3 0 1 1 0 0
d d d d S3 S4 0 0 0 0 1
d 0 d d S4 S0 0 0 0 1 0
d 1 d d S4 S5 0 0 0 1 0
d d 0 d S5 S5 0 0 1 0 0
d d 1 d S5 S3 0 0 1 0 0
Figure. Condensed state table of DMA controller
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 Eg. Design of A DMA Controller
Six state-transition equations
The output equations

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 Eg. Design of A DMA Controller

Fig. One-hot design for the

DMA controller

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 References
 Hayes, John P. Computer Architecture and
Organization, 3rd ed. McGraw-Hill, 1998.
 The third edition of Computer Architecture and
Organization is intended as a text for Computer
Technology courses at the undergraduate level.
 Copyright (c) 1998 by The McGraw-Hill Companies,
Inc.

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 Have a Nice Day!

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