Chapter 5 Control Design

1 Computer Architecture II (CT-404)

 Previous Topic
 Topic 01: Basic Concepts and Hardwired Control

2 Computer Architecture II (CT-404)

 Topic 02: Designing Hardwired
Control Units

 Multiplier Control
 CPU Control Unit
 Control Unit Design

3 Computer Architecture II (CT-404)

 Multiplier Control

Fig. Twos-
complement
multiplier
with a set of
control
points.

Computer Architecture II (CT-404)

4
 Implementing A Multiplier Control Unit

Begin
Yes
COUNT(7)=1?
S0 Q(0)=0?
No
No Yes
C2,C3,C4
S3 Yes
S1 C9, C10
Q(0)=0?
A:=A+M
A:=0
F:=M(7) and Q(0) or F No C2,C3, C7
COUNT:=0 C4,C5 S7
F:=0 S5 OUTBUS:=A
M:=INBUS
A:=A−M
C0,C1,C11
S4 Q(0):=0
S0
S C8 A(7):=F
2 S6 C6
A(6:0).Q:=A.Q(7:1) End
Q:=INBUS COUNT:=COUNT+1 OUTBUS:=Q

Cycle 0 Cycle 8 Cycle 9

Cycle 1 to 7

5 Computer Architecture II (CT-404) Fig. Flowchart for twos-complement multiplier

 Implementing A Multiplier Control Unit

Fig. State table for the multiplier control

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 Implementing A Multiplier Control Unit
The next state equations The output equations

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 Implementing A Multiplier Control Unit

Fig. All-NAND
classical design
for the
multiplier
control unit

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 Implementing A Multiplier Control Unit

Fig. All-NAND
one-hot design
for the
multiplier
control unit

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 CPU Control Unit

Fig. Organization of an
accumulator-based
CPU

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 CPU Control Unit
The accumulator-based CPU consists of a data path unit DPU
designed to execute the set of 10 basic single-address
instructions listed as follow:
Data transfer LD X
ST X
MOV DR, AC
MOV AC, DR
Data Processing ADD
SUB
AND
NOT
Program control BRA adr
BZ adr.

11 Computer Architecture II (CT-404)

 Instruction Set of an accumulator-based
CPU
Data Transfer

HDL format Assembly Comment

format
AC := M(X) LD X Load X from M into AC
M(X) := AC ST X Store contents of AC in M as X

DR:= AC MOV DR, AC Copy contents of AC to DR

AC:= DR MOV AC, DR Copy contents of DR to AC

12 Computer Architecture II (CT-404)

 Instruction Set of an accumulator-based
CPU
Data Processing
Assembly
HDL format Comment
format
AC := AC + DR ADD Add DR to AC
AC := AC - DR SUB Subtract DR from AC
AC := AC and DR AND And DR to AC
AC := not AC NOT Complement contents of
AC

13 Computer Architecture II (CT-404)

 Instruction Set of an accumulator-based
CPU
Program Control

HDL format Assembly Comment

format
PC := M (adr) BRA adr Jump to instruction with
address adr
If AC := 0 then BZ adr Jump to instruction adr
PC := M (adr) if AC = 0

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 Control points for accumulator-based
CPU

Fig. Control Signal Definition

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 Fig. Organization of a hardwired control unit for the accumulator-based CPU.

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 Implementing a Program Control Unit

Fig. State transition

graph for the
accumulator-based
CPU.

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 The next state equations

The output equations

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 Fig. One-hot implementation of the CPU state transition graph
19 Computer Architecture II (CT-404)
 References
 Hayes, John P. Computer Architecture and
Organization, 3rd ed. McGraw-Hill, 1998.
 The third edition of Computer Architecture and
Organization is intended as a text for Computer
Technology courses at the undergraduate level.
 Copyright (c) 1998 by The McGraw-Hill Companies,
Inc.

20 Computer Architecture II (CT-404)

 Have a Nice Day!

21 Computer Architecture II (CT-404)