EB CB TYPE USE

F R ACTIVE AMPLIFIER
F F SATURATION SWITCH ON
R R CUTTOFF SWITCH OFF
R F THIS WOULD STILL WORK BUT WONT BE THAT EFFICIENT
SO WE DON’T USE THIS TYPE.

HERE, IT IS SIMILAR TO A
CONDITION IN A CIRCUIT WHERE
SWITCH IS ON/OFF. EX-: WHEN A
SWITCH IS ON, HIGH CURRENT
FLOWS BUT VOLTAGE ACROSS IT IS
ZERO, HERE IT IS THE SATURATION
REGION WHICH ACTS AS SWITCH
ON.

AND WHEN THE SWITCH IS OFF NO

CURRENT FLOWS THROUGH IT BIUT
A VOLTAGE DO APPEARS ACROSS
THE SWITCH WHICH IS SAME HERE
IN THE CUTT-OFF REGION.

Here for the Q-Point we draw the

graph (straight line) of the eqn given
in the bottom left side of pic. And
wherever the plot intersects the
characteristics curve we have our
possible Q-Point, but in general it is
said to choose the Q-Point
somewhere in the middle, so here
we select the TICKED one as our Q-
Point

REASON WHY Q-POINT IS CHOOSED IN THE MIDDLE REGION.

After the biasing, the AC signal
comes into play due to which we
have signal excursion( depicted near
the ticked area), and if we choose
our Q-point somewhere near the
Second reason is that with our BJT we are given with a manufacturer’s sheet in which the max/min voltages,
current and power_max are mentioned beyond/below which the circuit won’t work so our Q-Point has to be
inside this range.

The yellow region is the region above the P-Max curve (where even for a small voltage we have high currents so
this region is not preferable AS IT COULD SPOIL THE DEVICE.)

The green region is the region which is allowed for choosing of Q-point as it passes all the constraints.

Rest regions are the prohibited area where we cannot select our Q-Point.

THERMAL STABILITY

IT HAPPENS ONLY IN BJT.

The temperature in the circuit rises which gives rises to the reverse collector base current (I CBO), which further gives rise to
the IC (as Ic has two components - one of ib and one of icbo), and when IC is increased the junction temperature is further increased AND AGAIN
ICBO INCREASE….. and this goes on till the device gets burnt.

So in order to avoid this we have to input a resistor in the emitter lead.

Now when the temp is increased IC increases which further gives rise to I E by the alpha eqn of these two, which increase the
term IERE is increased which decreases VBE according to the equation in left bottom side. This further decreases I B, which
decreases IC because of the beta relation between these 2 and now the problem is solved.

BIASING

1. Make device in active region

by setting the dc sources in
such way that EB- F.Biased,
CB-R.Biased
2. Choose the Q-Point correctly
in active region
3. Thermal stability.
Presence of DC components on a transmission line can
significantly affect the performance of a digital circuit. In
communication systems, coupling capacitors are used to
block unwanted DC components. Blocking the DC
component helps to minimize energy loss and prevent
accumulation of charge in digital circuits.
In DC, f=0, so XC=infinite, i.e. open circuit, hence DC won’t
pass,
Now as we knew our RE was imp for thermal stability but its presence reduces our gain, so in order to overcome this we
connect a capacitor here. When the DC is working the capacitor is open circuit hence R E function for thermal stability, as soon
as DC is stopped due to coupling capacitor effect and AC comes into effect, due to high capacitance, the path of capacitor
becomes short circuit and all the current passes through there making R E vanish which would prevent the loss incurred in
amplifying.

For a basic numerical refer to Lecture-10, 18:20

BJT AS AMP
REFER TO LEC 8 PDF SMALL SIGNAL ANALYSSIS FOR Vbe, Vc

Here basically we have to find the amplification factor beta

and alpha…. here the input resistance is Ri which is also Rpi in
this case…and the output resistance is the resistor bw
collector and emitter…. I.e. Ro

Vo is volotage across Ro

Vi is voltage across Rpi

Vs is source voltage

And ratio of these two with Vo are not same

Now we know that ic is function of ib but increasing

Vc give rise to Ic also as can be seen from VI
characteristics.. This effect is due to base width
modulation (compare to CLM)

On increasing CB rev bias voltage the wisdth of CB

jn. Narrows and Is is inv. Prop. To width so Is inc.
Which give rise to Ic

Now the new eqn is in the pic below where it shows

that Ic is also a funct of Vc…Va is the value we get
on X axis after extension of plot.

Now new eqn for Ro is givcen and since in sat, Vce

is small it can be neglected…

Refer to lec 8 for Re

If we neglect early effect we can ignore Ro

COMMON EMMITTER

Here a Re is introduced , the same we did for thermal

stability….here we will see that when Re ios increased
Ri is increased and it makes the device stable but
reduces our gain…

Here we have found the expression for Ri

When we consider circuit with output at collector and input at
base we calculate Avo, and when RL is connected it is treated
as Av.

Here we have derived expression for Av with relation acc to

resistors

The diagram in second pic ,(top left) shows Avo vs Av(across

Rl), now one may argue that why Rc Rl in series whereas in
model they are shown in parallel, Beacause in the model we
took a current source…. and we know that a resistance in
series with voltage source can be represented as a resistance
in parallel with current source..so

Now when we talk about Rsignal Vsignal a new gain term TOTAL
GAIN Gv is introduced. Which is Vo/Vsig , expression is given
below.

We know that Rin is Re + re but it is in emitter and when the same

Is reflected in base it is increased by factor of beta + 1
Voltage across re is called Vpi

NUMERICAL IN LEC 15

COMMON BASE

Same phase voltage gain..

For numerical watch LEC-16, Second half

COMMON COLLECTOR
 In this amplifier our main is to see that our input voltage
comes across the Rl without any attenuation for which
our Rin must be very large and at the same time our Ro
must be small….

Here in right side, the Rout is written when t he Rsig is

reflected in output terminal,

So from which we can see its a func of Rsig and Rin as we

know a func of Rl

Ro we say when we only see transistor config.

Rout when we attach a Vsig

To observe Ro/Rout, take Vsig =0 , reflect Resistor to

output side then check……

In Pi model, Vpi is voltage across re

For numerical LEC18 second half