1.1 The Boolean function A  BC is a 1.5 The logic function f  ( x. y )  ( x . y ) is

reduced form of the same as
(A) AB  BC   (A) f  ( x  y )( x  y )  
  (B) ( A  B)  ( A  C )  
(B) f  ( x  y )( x  y )  
  (C) AB  ABC  
  (D) ( A  C )  B   (C) f  ( x. y )( x . y )  

1.2 Boolean expression for the output of (D) None of the above
XNOR (equivalence) logic gate with 1.6 The Boolean expression
inputs A and B is (a  b  c  d )  (b  c ) simplifies to
(A) A B  A B
(A) 1 (B) a.b  
(B) A B  A B
  (C) a.b (D) 0
(C) ( A  B ) ( A  B ) 1.7 The Boolean expression AB  AC  BC
(D) ( A  B ) ( A  B)   simplifies to
1.3 The output of a logic gate is “1” when (A) BC  AC (B) AB  AC  B  
all its inputs are at logic “0”. The gate is (C) AB  AC (D) AB  BC  
either
1.8 The Boolean expression
(A) A NAND or an EX-OR gate
(X Y) (X  Y )  (X Y )  X
(B) A NOR or an EX-OR gate
(C) An OR or an EX-NOR gate simplifies to
(D) An AND or an EX-NOR gate (A) X (B) Y
1.4 For the circuit shown below the output F (C) XY (D) X + Y
is given by 1.9 If X = 1 in the logic equation
X
F
 
 X  Z Y  (Z  X Y )   
 
   X  Z ( X  Y )  1  then
(A) F = 1 (B) F = 0 (A) Y = Z (B) Y  Z  
(C) F = X (D) F  X   (C) Z = 1 (D) Z = 0

 
2 | Digital Electronics  
1.10 The Boolean function Y  AB  CD to 1.15 The Boolean expression of the output of
be realized using only 2-input NAND the logic circuit shown in figure is
gates. The minimum number of gates A

required is B

(A) 2 (B) 3 V
Y
(C) 4 (D) 5 C

1.11 The logical expression y  A  A B is (A) Y  A B  A B  C  

equivalent to (B) Y  A B  A B  C  
(A) y  AB (B) y  A B   (C) Y  A B  A B  C  
(C) y  A  B (D) y  A  B   (D) Y  A B  A B  C  
1.12 The number of distinct Boolean 1.16 For a 3-input logic circuit shown below,
expression of 4 variables is the output ‘Z ’ can be expressed as
P
(A) 16 (B) 256
(C) 1024 (D) 65536
Q Z
1.13 The complete set of only those Logic
Gates designated as Universal Gates is
R
(A) NOT, OR and AND Gates.
(A) Q  R (B) PQ  R
(B) XNOR, NOR and NAND Gates.
(C) Q  R (D) P  Q  R
(C) NOR and NAND Gates.
1.17 For the ring oscillator shown in the
(D) XOR, NOR and NAND Gates.
figure, the propagation delay of each
1.14 For the circuit shown in figure the inverter is 100 pico-sec. What is the
Boolean expression for the output Y in fundamental frequency of the oscillator
terms of inputs P, Q, R and S is output?
P
V0

Q
(A) 10 MHz (B) 100 MHz
Y
(C) 1 GHz (D) 2 GHz
R
1.18 A universal logic gate can implement
any Boolean function by connecting
sufficient number of them appropriately.
S
Three gates are shown.
F1 = X + Y F2 = X Y
(A) P  Q  R  S   X X
Y Y
(B) P  Q  R  S   Gate 1 Gate 2

(C) ( P  Q)  ( R  S ) X F3 = X + Y
Y
(D) ( P  Q )  ( R  S )   Gate 3

 
 Boolean Algebra & Logic Gate | 3 
1.19 In the figure shown, the output Y is P X
Q
required to be Y  AB  C D . The gates Z
M1
G1  and G2 must be,
A Y
G1 R
B (A) M 1  (P OR Q) XOR R  
G2 Y

C (B) M1  ( P AND Q) XOR R  

D
(C) M1  ( P NOR Q) XOR R  
(A) NOR, OR (B) OR, NAND
(C) NAND, OR (D) AND, NAND (D) M1  ( P XOR Q) XOR R  
1.20 In the circuit shown in the figure, if 1.23 If the input to the digital circuit
C  0, the expression for Y is consisting of a cascade of 20 X-OR
C gates is X, then the output Y is equal to
A 1
B
Y
Y
X
A
(A) 0 (B) 1
B
(C) X (D) X
(A) Y  A B  A B (B) Y  A B  A B  
1.24 For the logic circuit shown in figure, the
(C) Y  A  B (D) Y  A B  
required input condition (A, B, C) to
1.21 The output F in the digital logic circuit make the output (X) = 1 is
shown in the figure is A
XOR B
X
Y
AND X
C
F
(A) 1, 0, 1 (B) 0, 0, 1
Z (C) 1, 1, 1 (D) 0, 1, 1
XNOR 1.25 The minimum number of NAND gates
(A) F  X Y Z  X Y Z required to implement the Boolean
(B) F  X Y Z  X Y Z function A  A B  A B C is equal to

(C) F  X Y Z  X Y Z (A) Zero (B) 1

(C) 4 (D) 7
(D) F  X Y Z  X Y Z  
1.26 A ring oscillator consisting of 5
1.22 Which of the following Boolean
inverters is running at a frequency of 1.0
Expression correctly represents the
MHz. The propagation delay per gate is
relation between P, Q, R and M 1 ? _______ nsec.

 
4 | Digital Electronics  
1.27 A Boolean function f of two variables x
and y is defined as follows
f (0, 0)  f (0, 1)  f (1, 1)  1; f (1, 0)  0  
Assuming complements of x and y are
not available, the minimum cost solution
for realizing f using only 2-input NOR
gates and 2-input OR gates (each having
unit cost) would have a total cost of
(A) 1 unit (B) 4 unit
(C) 3 unit (D) 2 unit
1.28 Minimum number of 2-input NAND
gates required to implement the function,
F = ( X + Y ) (Z + W) is
(A) 3 (B) 4
(C) 5 (D) 6

 
 Boolean Algebra & Logic Gate | 5 
Answer Key : Boolean Algebra & Logic Gate
1.1 B 1.2 B, C 1.3 B 1.4 B 1.5 B
1.6 D 1.7 A 1.8 A 1.9 D 1.10 B
1.11 D 1.12 D 1.13 C 1.14 B 1.15 A
1.16 C 1.17 C 1.18 C 1.19 A 1.20 A
1.21 A 1.22 D 1.23 B 1.24 D 1.25 A
1.26 100 1.27 D 1.28 B



 
 
 
 

2.1 The number of product terms in the (C) X Y  Y Z  X Z

minimized sum-of-product expression
obtained through the following K-map (D) X Y  Y Z  X Z
(where, ‘d’ denotes don’t care states) 2.4 The SOP (sum of products) form of a
Boolean functions is  (0,1, 3, 7,11),
1 0 0 1
where inputs are A, B, C, D, (A is MSB,
0 d 0 0 and D is LSB). The equivalent
0 0 d 1 minimized expression of the function is

1 0 0 1 (A) ( B  C ) ( A  C ) ( A  B ) (C  D)

(A) 2 (B) 3 (B) ( B  C ) ( A  C ) ( A  C ) (C  D)

(C) 4 (D) 5 (C) ( B  C ) ( A  C ) ( A  C ) (C  D)
2.2 The minimal product-of-sums function
(D) ( B  C ) ( A  B ) ( A  B ) (C  D)
described by the K-map given in figure,
is 2.5 f ( A, B , C , D )   M (0, 1, 3, 4, 5,
AB 7,9,11, 12,13,14,15) is a maxterm
C 00 01 11 10 representation of Boolean function f (A,
0 1 1 0 0 A B, C, D) where A is the MSB and D is
the LSB. The equivalent minimized
1 0 0 0 0 representation of this function is
(A) ( A  C  D)( A  B  D)
C
(B) ACD  ABD
(A) AC (B) A  C
(C) A  C (D) AC (C) ACD  ABCD  ABCD
2.3 The Boolean expression (D) ( B  C  D)( A  B  C  D)
XYZXY ZXYZXY ZXYZ ( A  B  C  D)
can be simplified to 2.6 Consider the following Sum of Products
(A) X Z  X Z  Y Z expression, F.
(B) X Y  Y Z  Y Z F  ABC  ABC  ABC  ABC  ABC

 
2 | Digital Electronics  
The equivalent Product of Sums 2.10 Following is the K-map of a Boolean
expression is function of five variables P, Q, R, S and
(A) F  ( A  B  C )( A  B  C )( A  B  C ) X. The minimum sum-of-product (SOP)
(B) F  ( A  B  C )( A  B  C )( A  B  C ) expression for the function is
(C) F  ( A  B  C )( A  B  C )( A  B  C ) PQ PQ
RS 00 01 11 10 RS 00 01 11 10
(D) F  ( A  B  C )( A  B  C )( A  B  C )
00 0 0 0 0 00 0 1 1 0
2.7 The output expression for the Karnaugh
01 1 0 0 1 01 0 0 0 0
map shown below is 11 1 0 0 1 11 0 0 0 0
BC
A 00 01 11 10 10 0 0 0 0 10 0 1 1 0

0 1 0 0 1 X=0 X=1
1 1 1 1 1 (A) P Q S X  P Q S X  Q R S X  Q R S X
(A) A  B (B) A  C (B) Q S X  Q S X
(C) A  C (D) A  C
(C) Q S X  Q S X
2.8 The Boolean expression for the truth
table shown below is (D) Q S  Q S
A B C f 2.11 The Boolean expression Y  A B C D
0 0 0 0
 A B C D  A B C D  A B C D can be
0 0 1 0
0 1 0 0 minimized to
0 1 1 1 (A) Y  A B C D  A B C  AC D
1 0 0 0 (B) Y  A B C D  B C D  A B C D
1 0 1 0
1 1 0 1 (C) Y  A B C D  B C D  A B C D
1 1 1 0 (D) Y  A B C D  B C D  A B C D
(A) B( A  C ) ( A  C ) 2.12 Which one of the following gives the
(B) B( A  C ) ( A  C ) simplified sum of products expression
for the Boolean function
(C) B ( A  C ) ( A  C )
F  m0  m2  m3  m5
(D) B ( A  C ) ( A  C )
2.9 The minimized form of the logical where, m0 , m2 , m3  and m5 are minterms
expression corresponding to the inputs A, B and C
( A B C  A B C  A B C  A B C ) is with A as the MSB and C as the LSB?
(A) AC  B C  A B (A) AB  ABC  ABC
(B) AC  B C  A B (B) AC  AB  ABC
(C) AC  B C  A B (C) AC  AB  ABC
(D) AC  B C  A B (D) ABC  AC  ABC

 
 KMAP | 3 

2.13 The Boolean expression AC  B C is 2.16 A minimized form of the function F is

equivalent to (A) F  X Y  Y Z
(A) AC  B C  AC (B) F  X Y  Y Z
(B) B C  AC  B C  A C B (C) F  X Y  Y Z
(C) AC  B C  B C  A B C (D) F  X Y  Y Z
(D) A B C  A B C  A B C  A B C 2.17 Which of the following circuits is a
2.14 If the function W, X, Y and Z are as realization of the above functions F?
follows (A) X

W  R  PQ  R S F
Y
X  PQ R S  PQ R S  PQ R S Z

Y  R S  P R  PQ  PQ (B) X
Z  R  S  PQ  PQ R  PQ S F
Y
Then
Z
(A) W  Z , X  Z
(C) X
(B) W  Z , X  Y
F
(C) W  Y
Y
(D) W  Y  Z Z
2.15 The simplified form of the Boolean (D) X
expression Y  ( A B C  D) ( A D  B C ) F
can be written as Y
Z
(A) A D  B C D
2.18 The output expression for the Karnaugh
(B) A D  B C D
map shown below is
(C) ( A  D) ( B C  D) CD
AB 00 01 11 10
(D) A D  B C D 00 0 0 0 0
01 1 0 0 1
Common Data for Questions 2.16 and 2.17 11 1 0 1 1
The following Karnaugh map represents a 10 0 0 0 0
functions F (A) BD  BCD (B) BD  AB
F
YZ
X 00 01 11 10
(C) BD  ABC (D) BD  ABC

0 1 1 1 0

1 0 0 1 0

 
4 | Digital Electronics  
Answer Key : KMAP
2.1 A 2.2 A 2.3 B 2.4 A 2.5 A
2.6 A 2.7 B 2.8 A 2.9 A 2.10 B
2.11 D 2.12 B 2.13 D 2.14 A 2.15 A
2.16 B 2.17 D 2.18 D



 
 
 
 

Q.1 Consider the circuit shown in the figure. Q.3 Consider the multiplexer based logic
circuit shown in the figure.
Y 0 W 0
MUX 0
F MUX 0
0 1 MUX
F
1 MUX
1
1
X S1
Z S2
The Boolean expression F implemented Which one of the following Boolean
by the circuit is functions is realized by the circuit?
(A) F  W S1S 2
(A) X Y Z  X Y  Y Z
(B) F  W S1  W S2  S1S2
(B) X Y Z  X Z  Y Z
(C) F  W  S1  S 2
(C) X Y Z  X Y  Y Z
(D) F  W  S1  S2
(D) X Y Z  X Z  Y Z Q.4 In a half-subtractor circuit with X and Y
as inputs, the Borrow (M) and difference
4.28 A 16 bit ripple carry adder is realized
( N  X  Y ) are given by
using 16 identical full adders (FA) as
(A) M  X  Y , N  XY
shown in the figure. The carry-
(B) M  X Y , N  X  Y
propagation delay of each FA is 12 ns
(C) M  X Y , N  X  Y
and the sum-propagation delay of each
(D) M  X Y , N  X  Y
FA is 15 ns. The worst case delay (in ns)
Q.5 The output Y of a 2-bit comparator is
of this 16-bit adder will be_______.
logic 1 whenever the 2 - bit input A is
A0 B0 A1 B1 A14 B14 A15 B15
greater than the 2 - bit input B. The
C0 C1 C14 C15
number of combinations for which the
FA0 FA1 FA14 FA15
output is logic 1, is
(A) 4 (B) 6
S0 S1 S14 S15
(C) 8 (D) 10

 
2 | Digital Electronics  
Q.6 The logic function implemented by the Q.9 In the following circuit, X is given by
circuit below is (ground implies a logic 0 I0 0 I0
1 I1 1 I1
“0”) 4-to-1 4-to-1
X
1 I2 MUX 1 I2 MUX
4 ´1 MUX
I0 0 I3 S1 S0 0 I3 S1 S0

I1 A B C
Y F (A) X  A B C  A B C  A B C  A B C
I2
(B) X  A B C  A B C  A B C  A B C
I3 S1 S0 (C) X  A B  B C  AC
(D) X  A B  B C  AC
P Q
Q.10 The minimum number of 2-to-1
(A) F = AND (P, Q) multiplexers required to realize a 4-to-1
(B) F = OR (P, Q) multiplexer is
(A) 1 (B) 2
(C) F = XNOR (P, Q)
(C) 3 (D) 4
(D) F = XOR(P, Q) Q.11 Without any additional circuitry, an 8:1
Q.7 What are the minimum number of 2 to 1 MUX can be used to obtain
multiplexers required to generate a 2- (A) Some but not all Boolean functions
of 3 variables.
input AND gate and a 2-input EX - OR
(B) All functions of 3 variables but
gate? none of 4 variables.
(A) 1 and 2 (B) 1 and 3 (C) All functions of 3 variables and
some but not all of 4 variables.
(C) 1 and 1 (D) 2 and 2
(D) All functions of 4 variables.
Q.8 The Boolean function realized by the Q.12 A 4 1 MUX is used to implement a 3-
logic circuit shown is input Boolean function as shown in
figure. The Boolean functions
C I0
F ( A, B, C ) implemented is
D I1 4 ´1
F ( A, B, C , D) A I0
MUX
I2 I1 4 to 1
'1' I2 MUX
F (A, B, C)
I3 S1 S0
'0' I3
S1 S0
A B

(A) F  m (0,1,3,5,9,10,14) B C
(A) F ( A, B, C )  (1, 2, 4, 6)
(B) F  m (2,3,5, 7,8,12,13)
(B) F ( A, B, C )  (1, 2, 6)
(C) F  m (1, 2, 4,5,11,14,15) (C) F ( A, B, C )  (2, 4,5, 6)
(D) F  m (2,3,5, 7,8,9,12) (D) F ( A, B, C )  (1,5, 6)

 
 Combinational Circuits | 3 
Q.13 Consider the following circuit which (A) Y I0
2:1
uses a 2-to-1 multiplexer as shown in MUX D
the figure below. The Boolean expression I1
S
for output F in terms of A and B is X
S
Y I0
0 2:1
MUX B
Y F I1

1 S
(B) X I0
2:1
MUX D
A B I1
S
(A) A  B (B) A  B Y
S
X I0
(C) A  B (D) A  B 2:1
MUX B
3.10 A Boolean function f (A, B, C, D) = I1
M (1, 5, 12, 15) is to be implemented
using an 8 × 1 multiplexer (A is MSB). (C) Y I0
2:1
The inputs ABC are connected to the MUX B
I1
select input S2 S1 S0 of the multiplexer S
X
respectively. Which one of the following S
Y I0
options gives the correct inputs to pins 2:1
0, 1, 2, 3, 4, 5, 6, 7 in order? MUX D
I1

0
1 (D) X I0
2:1
2
MUX B
3 I1
4 f ( A, B, C , D) S
Y
5 S
6 X I0
7 S 2:1
S1 S0
2 MUX D
I1
A B C
Q.16 In the TTL circuit shown, S2 to S0 are
(A) D, 0, D, 0, 0, 0, D, D
selection lines and X 7 to X 0 input lines.
(B) D, 1, D, 1, 1, 1, D, D S0 and X 0 are LSBs. The output Y is
(C) D, 1, D, 1, 1, 1, D, D 1

0
(D) D, 0, D, 0, 0, 0, D, D X 0 X1 X 2 X 3 X 4 X 5 X 6 X 7

4.26 If X and Y are inputs and the difference E

8 : 1 MUX
(D = X – Y) and the Borrow (B) are the C S2
B S1
outputs, which one of the following A S0
diagrams implements a half-subtractor? Y

 
4 | Digital Electronics  
(A) Indeterminate Q.20 The output F of the 4 to 1 MUX shown
(B) A  B in figure is
(C) A B 3
+ 5V
(D) C ( A  B)  C ( A  B) 2
MUX
Q.17 The output of the circuit shown in figure 1 F
is equal to 0 S1 S0
A
B
X Y

(A) x y  x (B) x  y
A
B (C) x  y (D) x y  x
(A) 0 Q.21 The output Y in the circuit below is
(B) 1 always “1” when
(C) A B  A B P

(D) ( A  B)  ( A  B)
Q.18 The logic realized by the circuit shown Q
Y
in figure is
C R
I0
I1 4 ´1
I2 MUX F (A) two or more of the input P, Q, R are
C I3 “0”
S1 S0 (B) two or more of the inputs P, Q, R
are “1”
A B
(A) F  A C (B) F  A  C (C) any odd number of the inputs P, Q,
R is “0”
(C) F  B C (D) F  B  C
(D) any odd number of the inputs P, Q,
Q.19 The circuit shown in figure has 4 boxes
R is “1”
each described by inputs P, Q, R and
output Y, Z with Q.22 A bulb in a staircase has two switches,
Y  PQ R one switch being at the ground floor and
the other one at the first floor. The bulb
Z  RQ  R P  Q P can be turned ON and also can be turned
The circuit acts as a OFF by any one of the switches
Q
irrespective of the state of the other
switch. The logic of switching of the
P bulb resembles
P Q P Q P Q P Q
(A) an AND gate (B) an OR gate
Z R Z R Z R Z R
Y Y Y Y (C) an XOR gate (D) a NAND gate
Q.23 The minimum number of 2-input NAND
gates required to implement a 2-input
Output
(A) 4 bit adder giving P + Q XOR gate is
(B) 4 bit subtractor giving P – Q (A) 4 (B) 5
(C) 4 bit subtractor giving Q – P (C) 6 (D) 7
(D) 4 bit adder giving P + Q + R

 
 Combinational Circuits | 5 
Answer Key : Combinational Circuits
3.1 B 3.2 195 3.3 D 3.4 C 3.5 B
3.6 D 3.7 A 3.8 D 3.9 A 3.10 C
3.11 C 3.12 A 3.13 D 3.14 B 3.15 A
3.16 B 3.17 B 3.18 B 3.19 B 3.20 B
3.21 B 3.22 C 3.23 A



 
 
 
 

4.1 In a J-K flip-flop we have, J  Q and
K  1 (see figure). Assuming the flip-
flop was initially cleared and then
clocked for 6 pulses, the sequence at the
Q output will be
4.4 A sequential circuit using D Flip-Flop
and logic gates is shown in figure,
where X and Y are the inputs and Z is the
output. The circuit is

J Q Q X

D Q Z
CLK
1 K CLK Q
Y
R Q Z

(A) 010000 (B) 011001

(C) 010010 (D) 010101
(A) S-R Flip-Flop with inputs X = R and
4.2 An R-S latch is
Y = S.
(A) combinational circuit
(B) synchronous sequential circuit (B) S-R Flip-Flop with inputs X = S and
(C) one bit memory element Y = R.
(D) one clock delay element (C) J-K Flip-Flop with inputs X = J and
4.3 A master-slave flip-flop has the Y = K.
characteristic that
(D) J-K Flip-Flop with inputs X = K and
(A) change in the input immediately
reflected in the output. Y = J.

(B) change in the output occurs when
the state of the master is affected.
(C) change in the output occurs when
the state of the slave is affected.
(D) both the master and the slave states
are affected at the same time.
4.5 Two D flip-flops, as shown below, are
to be connected as a synchronous counter
that goes through the following Q1 Q0
sequence
00  01  11  10  00  …

 
2 | Digital Electronics  
The inputs D0 and D1 respectively 4.8 The digital circuit shown in the figure
should be connected as works as

D0 Q0 D1 Q1
LSB MSB D Q
X
CLK Q0 CLK Q1 CLK Q
Clock
(A) J-K flip-flop
(A) Q1 and Q0
(B) Clocked RS flip-flop
(B) Q0 and Q1 (C) T flip-flop
(C) Q1Q0 and Q1Q0 (D) Ring counter
4.9 The frequency of the clock signal
(D) Q1Q0 and Q1Q0
applied to the rising edge triggered D
4.6 Two D flip-flops are connected as a flip-flop shown in figure is 10 kHz. The
synchronous counter that goes through frequency of the signal available at Q is
the following QB QA sequence
D Q
00  11  01  10  00  ...
The connections to the inputs DA and
10 kHz CLK Q
DB are
(A) 10 kHz (B) 2.5 kHz
(A) DA  QB , DB  QA
(C) 20 kHz (D) 5 kHz
(B) DA  Q A , DB  Q B 4.10 For a flip-flop formed using two NAND
(C) DA  (QA Q B  Q AQB ), DB  QA gates as shown in figure. The unstable
state corresponds to
(D) DA  (QAQB  Q A Q B ), DB  Q B X
Q
4.7 Consider the given circuit.
A
Q
Y

CLK (A) X  0, Y  0 (B) X  0, Y  1

(C) X  1, Y  0 (D) X  1, Y  
B
4.11 For a J-K flip-flop, its J input is tied to
In this circuit, the race around
its own Q output and its K input is
(A) does not occur
connected to its own Q output. If the
(B) occurs when CLK = 0 flip-flop is fed with a clock of frequency
(C) occurs when CLK = 1 and A = B = 1 1 MHz. Its Q output frequency will be in
(D) occurs when CLK = 1 and A = B = 0 _______ MHz.

 
 Sequential Circuits | 3 
4.12 The clock frequency applied to the 4.16 The circuit shown in the figure is a
digital circuit shown in figure below is 1 D Q Q
kHz. If the initial state of the output Q D Latch D Latch
of the flip-flop is ‘0’, then the frequency En Q En Q

of the output waveform Q in kHz is

CLK

(A) Toggle Flip Flop.

X Q
T Q (B) J-K Flip Flop.
CLK (C) S-R Latch.
Q
Q (D) Master-Salve D Flip Flop.
4.17 A three bit pseudo random number
(A) 0.25 (B) 0.5 generator is shown. Initially the value of
(C) 1 (D) 2 output Y  Y2Y1Y0 is set to 111. The
4.13 A cascade of three identical modulo-5
value of output Y after three clock cycles
counters has an overall modulus of
is
(A) 5 (B) 25 Y2 Y1 Y0
(C) 125 (D) 625
4.14 The current state QA QB of a two J-K D2 Q2 D1 Q1 D0 Q0
flip-flop system is 00. Assume that the
clock rise-time is much smaller than the
CLK
delay of the J-K flip-flop. The next state
of the system is (A) 000 (B) 001
5V (C) 010 (D) 100
QA QB 4.18 In the latch circuit shown, the NAND
J J gates have non-zero, but unequal
QA propagation delays. The present input
K K condition is : P = Q = ‘0’. If the input
condition is changed simultaneously to
CLK
P = Q = ‘1’, the outputs X and Y are
(A) 00 (B) 01
X
Q
(C) 11 (D) 10
4.15 A MOD-n counter using a synchronous
binary up-counter with synchronous
clear input is shown in the figure. The Q
Y
value of n is _______.
(A) X = ‘1’, Y = ‘1’
4-Bit Binary QA QA
Counter (B) Either X = ‘1’, Y = ‘0’ or X = ‘0’,
QB QB

CLOCK CLK QC QC Y = ‘1’

CLEAR QD QD (C) Either X = ‘1’, Y = ‘1’ or X = ‘0’,
Y = ‘0’
(D) X = ‘0’, Y = ‘0’

 
4 | Digital Electronics  
4.19 For the circuit shown, the counter state
(Q1Q0 ) follows the sequence
1 J4 Q4 1 J3 Q3 1 J2 Q2 1 J1 Q1 1 J0 Q0
CLK CLK CLK CLK CLK

1 K4 1 K3 1 K2 1 K1 1 K0

Clock
D0 Q0 D1 Q1
4.23 The initial contents of the 4-bit serial-in-
parallel-out, right-shift, Shift Register
CLK
shown in the figure is 0110. After three
(A) 00, 01, 10, 11, 00 … clock pulses are applied, the contents of
(B) 00, 01, 10, 00, 01 … the Shift Register will be
Clock
(C) 00, 01, 11, 00, 01 …
0 1 1 0
(D) 00, 10, 11, 00, 10 … Serial in

4.20 A 4 bit ripple counter and a 4 bit

synchronous counter are made using flip Å
flops having a propagation delay of 10
ns each. If the worst case delay in the (A) 0000 (B) 0101
ripple counter and the synchronous (C) 1010 (D) 1111
counter be R and S respectively, then 4.24 A pulse train with a frequency of 1 MHz
(A) R = 10 ns, S = 40 ns is counted using a modulo-1024 ripple-
(B) R = 40 ns, S = 10 ns counter built with J-K flip flops. For
(C) R = 10 ns, S = 30 ns proper operation of the counter, the
(D) R = 30 ns, S = 10 ns maximum permissible propagation delay
4.21 The given figure shows a ripple counter per flip flop stage is _______ nsec.
using positive edge triggered Flip-Flops.
4.25 A 4-bit modulo-16 ripple counter uses J-
If the present state of the counter is
K flip-flops. If the propagation delay of
Q2Q1Q0  011 then its next state Q2Q1Q0
each FF is 50 ns, the maximum clock
will be
1 1
frequency that can be used is equal to
1
T0 Q0 T1 Q1 T2 Q2 (A) 20 MHz (B) 10 MHz
(C) 5 MHz (D) 4 MHz
CLK
Q0 Q1 Q2 4.26 The present output Qn of an edge
(A) 010 (B) 100 triggered J-K flip-flop is logic 0. If J =
(C) 111 (D) 101 1, then Qn 1
4.22 Five J-K flip-flops are cascaded to form
(A) cannot be determined
the circuit shown in Figure. Clock
pulses at a frequency of 1 MHz are (B) will be logic 0
applied as shown. The frequency (in (C) will be logic 1
kHz) of the waveform at Q3 is _______. (D) will race around

 
 Sequential Circuits | 5 
4.27 Figure shows a MOD-k counter, here k (C) A=0 A =1

is equal to A=0

Q=0 Q =1

J0 Q0 J1 Q1
A =1

1 K0 Q0 1 K1 Q1 (D) A =1 A =1
A=0

Q=0 Q =1
(A) 1 (B) 2
(C) 3 (D) 4 A=0

4.28 A 0 to 6 counter consists of 3 flip-flops 4.30 The circuit shown consists of J-K flip-
and a combinational circuit of 2 input flops, each with an active low
gate(s). The combination circuit consists asynchronous reset ( Rd input). The
of counter corresponding to this circuit is
(A) one AND gate Q0 Q1 Q2
1 J Q 1 J Q 1 J Q
(B) one OR gate Clock

1 K Rd 1 K Rd 1 K Rd
(C) one AND gate and OR gate
(D) two AND gates
(A) a modulo-5 binary up counter.
4.29 The state transition diagram for the logic
(B) a modulo-6 binary down counter.
circuit shown is
(C) a modulo-5 binary down counter.
2 : 1 MUX
D Q X1 (D) a modulo-6 binary up counter.
Y
CLK Q X 0 Select

(A) A =1 A=0
A =1

Q=0 Q =1

A=0

(B) A=0 A=0

A =1

Q=0 Q =1

A =1

 
6 | Digital Electronics  
Answer Key : Sequential Circuits
4.1 D 4.2 C 4.3 C 4.4 D 4.5 A
4.6 D 4.7 A 4.8 C 4.9 D 4.10 A
4.11 0.5 4.12 B 4.13 C 4.14 C 4.15 7
4.16 D 4.17 D 4.18 B 4.19 B 4.20 B
4.21 B 4.22 62.5 4.23 C 4.24 100 4.25 C
4.26 C 4.27 C 4.28 D 4.29 D 4.30 A



 
 
 
 

5.1 Consider a four bit D to A converter. (C)

The analog value corresponding to a
digital signals of values 0000 and 0001
are 0 V and 0.0625 V respectively. The
analog value (in Volts) corresponding to (D)
the digital signal 1111 is ____.
5.2 A 4-bit D-to-A converter is connected to
a free-running 3-bit UP counter, as
shown in the following figure. Which of 5.3 For the 4 bit DAC shown in figure, the
the following waveforms will be output voltage V0 is
observed at V0 ? 1 kW 7 kW
1 kW +15 V
Q2 D3
V0
D2 V0
R R R
Q1 D1

Clock Q0 D0 1 kW
-15 V
2R 2R 2R 2R 2R
3-bit 4-bit
Counter DAC
1V 1V
In the figure shown above, the ground
has been shown by the symbol . (A) 10 V (B) 5 V
(A) (C) 4 V (D) 8 V
5.4 The number of comparators required in
a 3-bit comparator type ADC is
(A) 2 (B) 3
(B) 11 11
(C) 7 (D) 8
10 10
9 9
5.5 The resolution of a 4-bit counting ADC
8 8 is 0.5 Volts. For an analog input of 6.6
V, the digital output of the ADC will be
3 3
2 2 (A) 1011 (B) 1101
1 1
0 0 (C) 1100 (D) 1110

 
2 | Digital Electronics  
5.6 An 8-bit successive approximation analog 5.9 A student has made a 3-bit binary down
to digital converter has full scale reading counter and connected to the R-2R
of 2.55 V and its conversion time for an ladder type DAC [Gain  ( 1k /2 R ) ]
analog input of 1 V is 20 s. The as shown in figure to generate a
conversion time for a 2 V input will be staircase waveform. The output achieved
(A) 10 s (B) 20 s is different as shown in figure. What
(C) 40 s (D) 50 s could be the possible cause of this error?
R R R 1 kW
5.7 A temperature in the range of – 40°C to
55°C is to be measured with a resolution 2R 2R 2R 2R +12V
of 0.1°C. The minimum number of ADC D2 _
bits required to get a matching dynamic 1 kHz
D1
V0
clock +
range of the temperature sensor is Counter
D0 – 12V
(A) 8 (B) 10 10 kW
(C) 12 (D) 14
5.8 A 2-bit flash Analog to Digital
Converter (ADC) is given below. The 7
6
input is 0  VIN  3 Volts. The expression
5
for the LSB of the output B0 as a 4
Boolean function of X 2 , X 1 and X 0 is 3
2
3V
1

100 W 0

X2 0 1 2 3 4 5 6 7
t (ms)

(A) The resistance values are incorrect.

200 W
B1 (B) The counter is not working properly.
X1 Digital (C) The connection from the counter to
Circuit
B0 DAC is not proper.
200 W (D) The R and 2R resistance are inter-
X0 changed.
5.10 Among the following four, the slowest
100 W
ADC (analog-to-digital converter) is
(A) Parallel-comparator (i.e. flash) type
VIN
(B) Successive approximation type
(A) X 0 [ X 2  X 1 ] (C) Integrating type
(B) X 0 [ X 2  X 1 ] (D) Counting type
(C) X 0 [ X 2  X 1 ]
(D) X 0 [ X 2  X 1 ]

 
 ADC & DAC | 3 
Answer Key : ADC & DAC
5.1 0.9375 5.2 B 5.3 B 5.4 C 5.5 D
5.6 B 5.7 B 5.8 A 5.9 C 5.10 C



 
 
 
 

6.1 The range of signed decimal numbers 6.6 11001, 1001 and 111001 correspond to
that can be represented by 6-bit 1's the 2’s complement representation of
complement number is which one of the following sets of
(A) – 31 to + 31 (B) – 63 to + 63 number?
(C) – 64 to + 63 (D) – 32 to + 31
(A) 25, 9 and 57 respectively
6.2 4-bit 2's complement representation of a
decimal number is 1000. The number is (B) – 6, – 6 and – 6 respectively
(A) +8 (B) 0 (C) – 7, – 7 and – 7 respectively
(C) – 7 (D) – 8 (D) – 25, – 9 and – 57 respectively
6.3 X = 01110 and Y = 11001 are two 5 - bit 6.7 A signed integer has been stored in a
binary numbers represented in two’s
byte using the 2’s complement format.
complement format. The sum of X and
We wish to store the same integer in a
Y represented in 2’s complement format
using 6 bits is 16 bit word. We should
(A) 100111 (B) 001000 (A) Copy the original byte to the less
(C) 000111 (D) 101001 significant byte of the word and fill
6.4 An equivalent 2’s complement the more significant byte with zeros
representation of the 2’s complement (B) Copy the original byte to the more
number 1101 is
significant byte of the word and fill
(A) 110100 (B) 001101 the less significant byte with zeros
(C) 110111 (D) 111101
(C) Copy the original byte to the less
6.5 The two numbers represented in signed
significant byte of the word and
2’s complement form are
make each bit of the more significant
P = 11101101 and Q = 11100110
byte equal to the most significant bit
If Q is subtracted from P, the value
obtained in signed 2’s complement form of the original byte
is (D) Copy the original byte to the less
(A) 100000111 (B) 00000111 significant bytes well as the more
(C) 11111001 (D) 111111001 significant byte of the word

 
2 | Digital Electronics  
6.8 In the sum of products function (C) PROM contains a fixed AND array
f ( X , Y , Z )  (2,3, 4,5), the prime and a programmable OR array.
implicates are (D) PLA contains a programmable AND
(A) X Y , X Y array and a programmable OR array.
6.15 A PLA can be
(B) X Y , X Y Z , X Y Z
(A) as a microprocessor
(C) X Y Z , X Y Z , X Y (B) as a dynamic memory
(D) X Y Z , X Y Z , X Y Z , X Y Z (C) to realize a sequential logic
6.9 Consider the Boolean function, (D to realize a combinational logic
F ( w, x, y, z )  w y  x y  w x y z 6.16 The logic function implemented by the
w x y  x z  x y z following circuit at the terminal OUT is
Vdd
Which one of the following is the
complete set of essential prime
implicants? OUT

(A)  w, y, x z , x z (B) w, y , x z P Q
(C)  y, x y z (D) y , x z , x z
6.10 For an n-variable Boolean function, the
maximum number of prime implicants is
(A) 2(n  1) (B) n / 2
(A) P NOR Q (B) P NAND Q
(C) 2n (D) 2( n1) (C) P OR Q (D) P AND Q
6.11 Which of the following is an invalid 6.17 For the NMOS logic gate shown in
state in 8 4 2 1 Binary Coded Decimal figure the logic function implemented is
counter VDD
(A) 1000 (B) 1001
(C) 0011 (D) 1100
6.12 A dynamic RAM consists of F
(A) 6 transistors
(B) 2 transistors and 2 capacitors A D

(C) 1 transistor and 1 capacitor

(D) 2 capacitors only B C E
6.13 Each cell of a static Random Access
Memory contains
(A) 6 MOS transistors.
(A) A B C D E
(B) 4 MOS transistors and 2 capacitors
(C) 2 MOS transistors and 4 capacitors (B) ( A B  C ) ( D  E )
(D) 1 MOS transistor and 1 capacitors (C) A ( B  C )  D E
6.14 Choose the correct statements (s) from
the following : (D) ( A  B) C  D E
(A) PROM contains a programmable
AND array and a fixed OR array.
(B) PLA contains a fixed AND array
and a programmable OR array.

 
 Miscellaneous - Number System | 3 
Answer Key : Miscellaneous - Number System
6.1 A 6.2 D 6.3 C 6.4 D 6.5 B
6.6 C 6.7 C 6.8 A 6.9 D 6.10 D
6.11 D 6.12 C 6.13 A 6.14 C&D 6.15 D
6.16 D 6.17 C

