ESDC

Electronics System Design for Communication

SPRING 2019

Introduction
Outline
 Global Objectives
 Course organization
 Bibliography
 Previous knowledge
 Evaluation
 Global Objective
 To provide skills to understand the general organization,
principles and design methods of integrated computing and
communication systems.
PART 1
PART 2 PART 3
Design
methodology

SPECIFIC COMMUNICATION SYSTEMS

Communication Technology
architectures
Configurable System on
Chip ICs 0: Introduction3
Course organization
THEORY
PART 1: DESIGN METHODOLOGY and TOOLS (J. Altet)
PART 2: NETWORK PROCESSOR ARCHITECTURES (A. Rubio)
PART 3: TECHNOLOGY, SYSTEM MERIT FACTORS (F. Moll)

LABORATORY
Design strategies for System on Chip Designs
Design of a communications electronic system based on an
embedded processor.

Josep Altet, josep.altet@upc.edu, C4 - 204

Antonio Rubio, antonio.rubio@upc.edu, C4 –207
Francesc Moll, francesc.moll@upc.edu, C4 - 206

0: Introduction
Bibliography

First part Second part Third part

• Digital Integrated Circuits, J.M. Rabaey and A.P. Chadrakasan,

Prentice Hall
• Data Communication and Networking, B.A. Forouzan, McGraw-
Hill
• Network processor design, Morgan Kaufmann Series in Computer
Architecture and Design
• The ZYNQ Book, XILINX corporation
• Mastering the FreeRTPS Real Time Kernel

0: Introduction
5
Previous knowledge
 We do not start from scratch…
 Should review undergraduate concepts.
 Prerequisites:
◦ Basic digital design and analysis:
 Registers, State Machines, Counters, Combinational
systems. Schematics & waveform analysis.
◦ Hardware Description Language:VHDL.
◦ Review of basic CMOS logic gates
 Working principle
 Design of basic CMOS gate schematic
 NMOS and PMOS basic equations
Organization
L (Thu A) L (Thu B)
Week Date (Mon) T (Mon) G41 G43
Introducti
1 18F PART 1 on
2 25F PART 1 Lab 1
3 4M PART 1 Lab 1
4 11M PART 1 Lab 1
5 18M PART 2 Lab 1
6 25M PART 2 Lab 2
7 1A PART 2 Lab 2
8 8A Control1 Lab 2
9 15A
10 22A Lab 2
PART 2
11 29A (Tecno) Lab 3
PART 3:
12 6M delay Lab 3
PART 3:
13 13M power Lab 3
PART 3: LP
14 20M tech Lab 3

PART 3:
15 27M new tech
Evaluation
 FINALMARK :
1/3*Laboratory + 2/3*Theory

 IMPORTANT: Requirement to
pass the subject: to work and
present all the mandatory
laboratory assignments.

0: Introduction 8
 Evaluation: “Theory”
There is a mid-term control on April 8th: C (control).
Includes Part 1 and Part 2.
Final Exam FE: June 5th. This final exam will have two
sections:
FE1 (final exam first section): Part 1 and 2 of the
course.
FE2 (final exam second section): Part 3 of the
course.
FE = 0.5FE1+0.5FE2
Mathematics:
Theory = max (FE, (0.5*C+0.5*FE1)+0,5*FE2)
If C >=8 you can skip FE1, in this case FE1=C.

0: Introduction 9
Evaluation Laboratory
 Lab = (Lab1+Lab2+Lab3)/3
 Labi (i= 1, 2 or 3) = 0,5* Tutorial + 0,1*
Prelab + 0,4 * Optional
 In laboratory: Always give credit to your
sources
◦ OK to use code from external sources if
properly acknowledged
◦ Plagiarism and copy will be severely penalized
◦ Point to references to your sources (internal
or external)