HALF ADDER USING DATA FLOW MODELING

module h_df(s, cy, a, b);

output s;

output cy;

input a;

input b;

assign s=a^b;

assign cy=a&b;

endmodule

TEST BENCH PROGRAM

module h_tb_v;

reg a;

reg b;

wire s;

wire cy;

h_df uut (

.s(s),

.cy(cy),

.a(a),

.b(b)

);

initial begin

a = 0; b = 0;

#100; a = 0; b = 1;

#100; a = 1; b = 0;

#100; a = 1; b = 1;

End

Endmodule