FIGURE 3.1 System For Illustrating Boolean Applications To Control

FIGURE 3.1 System for illustrating Boolean applications to control.
Copyright ©2006 by Pearson Education, Inc.

Curtis Johnson
Upper Saddle River, New Jersey 07458
Process Control Instrumentation Technology, 8e] All rights reserved.
FIGURE 3.2 Solution for Example 3.5.

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FIGURE 3.3 Solution for Example 3.6.

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FIGURE 3.4 Generic model of a computer bus system.

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FIGURE 3.5 Tri-state buffers allow multiple signals to share a single digital line in the bus.

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FIGURE 3.6 A basic comparator compares voltages and produces a digital output.

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FIGURE 3.7 Diagram of a solution to Example 3.7.

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FIGURE 3.8 Many comparators use an open-collector output.

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FIGURE 3.9 A comparator output will “jiggle” when a noisy signal passes through the reference voltage level.

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FIGURE 3.10 A generic DAC diagram, showing typical input and output signals.

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FIGURE 3.10 (continued) A generic DAC diagram, showing typical input and output signals.

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FIGURE 3.11 A generic DAC diagram, showing typical input and output signals.

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FIGURE 3.12 A typical DAC is often implemented using a ladder network of resistors.

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FIGURE 3.13 A generic ADC diagram, showing typical input and output signals and noting the conversion time.

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FIGURE 3.14 A typical data-acquisition timing diagram using an ADC. The read operation may occur at any time after the end-of-
convert has been issued by the ADC.

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FIGURE 3.15 One common method of implementing an ADC is the successive approximation of parallel-feedback system using an
internal DAC.

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FIGURE 3.16 The dual-slope ADC uses an op amp integrator, comparator, and counter. This is commonly used in digital voltmeters.

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FIGURE 3.17 A typical timing diagram of a dual-slope ADC. Since both slopes depend upon R and C, the ADC output is independent
of the values of these components.

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FIGURE 3.18 Analog circuit for Example 3.19.

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FIGURE 3.19 Input signal for Example 3.20.

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FIGURE 3.20 The basic concept of a sample-and-hold circuit for use with the ADC.

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FIGURE 3.21 The sampled signal is literally “held” during the ADC conversion process.

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FIGURE 3.22 A S/H often uses a FET as an electronic switch.

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FIGURE 3.23 During (a) sampling and (b) holding, equivalent circuit resistance creates nonideal effects.

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FIGURE 3.24 An ADC can be interfaced directly to the computer bus if it has tri-state outputs. Address decoding is required so the
ADC can be operated by computer software.

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FIGURE 3.25 General diagram of a frequency-based analog-to-digital converter.

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FIGURE 3.26 The LM331 is a common voltage-to-frequency converter useful in frequency-based ADCs.

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FIGURE 3.27 The 555 timer is useful for generation of a frequency that depends upon resistance or capacity.

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FIGURE 3.28 Response from Example 3.24.

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FIGURE 3.29 Typical layout of a data-acquisition board for use in a personal computer expansion slot.

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FIGURE 3.30 An analog multiplexer acts as a multiposition switch for selecting particular inputs to the ADC.

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FIGURE 3.31 Software for data acquisition involves operations to start the ADC, test the EOC, and input the data.

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FIGURE 3.32 Solution to Example 3.25.

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FIGURE 3.33 The sampling rate can disguise actual signal details.

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FIGURE 3.34 Pressure data for Example 3.27.

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FIGURE 3.35 Linearization by table look-up can be accomplished by the operations in this flowchart.

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FIGURE 3.36 System for Problems 3.10 and 3.14.

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FIGURE 3.37 System for Problem S3.3.

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FIGURE 3.1 System For Illustrating Boolean Applications To Control

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FIGURE 3.1 System for illustrating Boolean applications to control.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

Copyright ©2006 by Pearson Education, Inc.

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