Experiment 10

Timers and Time Base Generation

Timers/Counters

Almost every microcontroller comes with one or more (sometimes many more) built-in timer/-
counters, and these are extremely useful to the embedded programmer. The term timer/counter
itself reflects the fact that the underlying counter hardware can usually be configured to count
either regular clock pulses (making it a timer) or irregular event pulses (making it a counter).
Sometimes timers are also called “hardware timers” to distinguish them from software timers
which are bits of software that perform some timing function.

What is a Timer?

We use timers every day - the simplest one can be found on your wrist. A simple clock will time
the seconds, minutes and hours elapsed in a given day - or in the case of a twelve hour clock,
since the last half-day. ARM timers do a similar job, measuring a given time interval.

Micro-controllers, such as the LM4F120 utilize hardware timers to generate signals of various
frequencies, generate pulse-width-modulated (PWM) outputs, measure input pulses, and trigger
events at known frequencies or delays. The LM4F120 parts have several different types of timer
peripherals which vary in their configurability. The simplest timers are primarily limited to
generating signals of a known frequency or pulses of fixed width. While more sophisticated
timers add additional hardware to utilize such a generated frequency to independently generate
signals with specific pulse widths or measure such signals.

How a Timer Works?

An ARM timer in simplest term is a register. Timers generally have a resolution of 16/32
or 32/64 bits. So a 16 bit timer is 16 bits wide, and is capable of holding value within 0-
65535. But this register has a magical property - its value increases/decreases automatically at
a predefined rate (supplied by user). This is the timer clock and this operation does not need
CPUs intervention.

An example of a basic timer is illustrated in Figure 10.2. This timer has four components
a controller, a prescaler (PSC), an “auto-reload” register (ARR) and a counter (CNT). The
function of the prescaler is to divide a reference clock to lower frequency. The LM4F120 timers

85
86 CHAPTER 10. TIMERS AND TIME BASE GENERATION

Timer Register

have 8-bit prescaler registers for 16-bit timers which can divide the reference clock by any value
1..255 and 16-bit prescalar for 32-bit timer which can divide the reference clock by any value
1..65535. The counter register can be configured to count up, down, or up/down and to be
reloaded from the auto reload register whenever it wraps around (an “update event”) or to
stop when it wraps around. The basic timer generates an output event (TGRO) which can be
configured to occur on an update event or when the counter is enabled (for example on a GPIO
input). CHAPTER 10. TIMERS

TIMxCLK
CK_INT TRGO
(RCC)
Trigger
Controller
CK_PSK

ARR
Auto Reload

PSC CNT
CK_CNT
Prescaler Counter

FigureBasic
10.1: Timer
Basic Timer

To understandfrom
the0three
to 3 (ARR) andmodes
counter then is reset to 0. Figure
consider When the10.3.
reset occurs, an “update
In these examples, we assume
event” is generated. This update event may be tied to TRGO, or in more
a prescaler of complex
1 (counter clock
timers withiscapture/compare
half the internal clock),
channels andhave
it may a auto reload
additional value of 3. Notice
effects
(described
that in “Up” mode, the below).
counterSimilarly, in “Down”
increments from mode,
0 to 3the counter
(ARR) anddecrements from 3to 0. When the
then is reset
to 0 and then is reset to 3 (ARR). In Down mode, an update “event” (UEV)
reset occurs, an “update event” is generated. This update event may be tied to TRGO, or in
is generated when the counter is reset to ARR. Finally, in Up/Down mode,
more complex thetimers with
counter capture/compare
increments to ARR, thenchannels it may
decrements to 0, have additional
and repeats. effects. Similarly,
A UEV
is generated
in “Down” mode, before decrements
the counter each reversal with
fromthe effect
3 to that then
0 and the period in Up/Down
is reset to 3 (ARR). In Down
mode is one shorter than in either Up or Down mode.
mode, an update “event” (UEV) is generated when the counter is reset to ARR. Finally, in
Many timers extend this basic module with the addition of counter
Up/Down mode, the counter
channels such as increments to ARR,
the one illustrated then decrements
in Figure to refers
10.3. The “x” 0, andtorepeats.
the A UEV is
channel
generated before eachnumber – frequently,
reversal timersthat
with the effect support
the multiple
period inchannels.
Up/Down Withmode
this is one shorter
modest additional hardware, an output can be generated whenever the count
than in either register
Up or Down
reaches mode.
a specific value or the counter register can be captured when
a specific input event occurs (possibly a prescaled input clock).
An important use of counter channels is the generation of precisely
timed pulses. There are two variations of this use – “one-pulse” pulses, in
which a single pulse is generated, and pulse width modulation, in which a
 87

CNT 0 1 2 3 0 1 2 3 0
Up
UEV

CNT 3 2 1 0 3 2 1 0 3
Down
UEV

Up/Down CNT 2 3 2 1 0 1 2 3 2

UEV

CK CNT ®
Stellaris LM4F120H5QR M
CK INT

Counter Modes (ARR=3, PSC=1)

Figure 10.2: Counter Modes (ARR=3, PSC=1)
Figure 5-5. Main Clock Tree
Clock Configuration
series of pulses is generated with the counter UEV period. The pulse width is
controlled by the Capture/Compare Register (CCR). For example, the channel
The clock system
output on the Stellaris
(OCxREF) may tied Launchpad
to whetheris the
extremely flexible.is greater
CNT register The clock
(or tree
less)of system
than the Compare
clock configuration is shownregister. In Figure
in Figure 10.4 10.4 we illustrate the use of two channels
for one-pulse and PWM outputs. Here we assume that the ARR is 7 and the
CCR is 3. In PWM mode, ARR XTALacontrols the period, and CCR controls the
pulse width (and hence the duty PWRDN cycle).
b
In one-pulse mode, the pulse begins
CCR cycles after an initial trigger event, and has a width of ARR-CRR. It
isMOSCDIS
possible
a to use multiple channels to create a set of synchronized, pulses

beginning at precise delays from PLL

each other. b,d
BYPASS
Main OSC channel may (400
A timer alsoMHz)
be used to DIV400
measurec pulse widths a,d
– in effect
USESYSDIV

decoding pwm signals. There are many other÷2

configuration options for the
STM32 timers including mechanisms to synchronize multiple timers both to
IOSCDIS a
each other and to external signals.
System Clock
In the remainder of this chapter we consider two timer applications in-
Precision
Internal OSC ÷ SYSDIVe
cluding
(16 MHz)PWM output (Section 10.1), input pulse measurement (Section 10.2).
In Chapter 13 ÷we 4 show how to use a timer to control b,d
BYPASS
DMA transfers for an
audio player and in Chapter 14 we use a timer to sample and analog input at
Internal OSC
regular
(30 kHz)intervals.

Hibernation
OSC OSCSRC b,d
(32.768 kHz)
Revision: 1396a85 (2013-01-07) 141

System Clock Tree

The internal system clock (SysClk), is derived from any of the four reference sources plus two
others: the output of the main internal PLL and the precision internal oscillator divided by
four (4 MHz 1%). The frequency of the PLL clock reference must be in the range of 5 MHz
Note: a. Control provided by RCC register bit/field.
to 25 MHz (inclusive). Following table
b. Control shows
provided by how
RCC the various
register clock
bit/field sources
or RCC2 can be
register usedifin
bit/field, a
overridden with RCC
system. USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden
bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
f. Control provided by UARTCC, SSICC, and ADCCC register field.
 The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 5 MHz to 25 MHz (inclusive).
Table 5-3 on page 217 shows how the various clock sources can be used in a system.
88 CHAPTER 10. TIMERS AND TIME BASE GENERATION
Table 5-3. Clock Source Options
Clock Source Drive PLL? Used as SysClk?
Precision Internal Oscillator Yes BYPASS = 0, Yes BYPASS = 1, OSCSRC = 0x1
OSCSRC = 0x1
Precision Internal Oscillator divide by No - Yes BYPASS = 1, OSCSRC = 0x2
4 (4 MHz ± 1%)
Main Oscillator Yes BYPASS = 0, Yes BYPASS = 1, OSCSRC = 0x0
OSCSRC = 0x0
Low-Frequency Internal Oscillator No - Yes BYPASS = 1, OSCSRC = 0x3
(LFIOSC)
Hibernation Module 32.768-kHz No - Yes BYPASS = 1, OSCSRC2 = 0x7
Oscillator

5.2.5.2 Clock Configuration Clock Source Options

The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer
The additional encodings
Run-Mode over the RCC(RCC)
Clock Configuration register.and
When used, the Clock
Run-Mode RCC2 register field values
Configuration are
2 (RCC2)
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
registers provide control for the system clock. The RCC2 register is provided to extend fields
a larger assortment of clock configuration options. These registers control the following clock
that offer additional encodings over the RCC register. When used, the RCC2 register field
functionality:
values are used by the logic over the corresponding field in the RCC register. In particular,
■ Source of clocks in sleep and deep-sleep modes
RCC2 provides for a larger assortment of clock configuration options. These registers control
■ following
the System clock
clockderived from PLL or other clock source
functionality:
■ • Enabling/disabling of oscillators
Source of clocks in sleep and and PLL
deep-sleep modes
• System clock derived from PLL or other clock source
• Enabling/disabling of oscillators and PLL
• Clock
January 19, 2013 divisors 217
• Crystal input selection
Texas Instruments-Advance Information

To configure RCC and RCC2 clock configuration registers consult the data sheet of LM4F120.

Timers in LM4F120

The Stellaris General-Purpose Timer Module (GPTM) in LM4F120 contains six 16/32-bit
GPTM blocks and six 32/64-bit Wide GPTM blocks. Each 16/32-bit GPTM block provides two
16-bit timers/counters(referred to as Timer A and Timer B) that can be configured to operate
independently as timers or event counters. Complete register map of the GPTM is given in the
data sheet [pg. 684]. Some key registers are described below:

SYSCTL RCGCTIMER R - enable clock for GPTM (enable clock for Timer0)

TIMER0 CTL R - control Timer0 module

TIMER0 CFG R - control global operation of Timer0 module (use 16/32-bit mode)

TIMER0 TAMR R - control the mode for Timer0

TIMER0 TAPR R - set the prescalar for Timer0

TIMER0 TAILR R - load the starting count value into the timer when counting down and set
the upper bound for the timeout event when counting up
 89

How to Configure a Timer for Periodic Interrupts

The GPTM is configured for Periodic mode by the following sequence:

1. Enable the General Purpose Timer Module (GPTM) by asserting the appropriate TIMERn
bit in the RCGCTIMER register. [pg. 312]
2. Ensure the timer is disabled (TnEN bit in the GPTMCTL register is cleared for the
corresponding timer) before making any changes. [pg. 696]
3. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x04 to configure
in 16-bit mode. [pg. 686]
4. Write a value of 0x2 in the TnMR field of the GPTM Timer n Mode Register (GPTMT-
nMR) to configure it in periodic mode. [pg. 688]
5. Load the period value into the GPTM Timer n Interval Load Register (GPTMTnILR).
[pg. 715]
6. Load the prescale value into the GPTM Timer n Prescale Register (GPTMTnPR). [pg.
719]
7. Assert Timer A Time-Out Clear Interrupt (TATOCINT) bit of GPTM Interrupt Clear
Register (GPTMICR) to clear the time-out flag. [pg. 713]
8. Set Timer A Time-Out Interrupt Mask (TATOIM) bit of GPTM Interrupt Mask Register
(GPTMIMR) to enable the time-out interrupt. [pg. 704]
9. Set the priority in the corresponding NVIC Priority Register. [Table 2.9, pg. 101], [pg.
149]
10. Enable the correct interrupt in the corresponding NVIC Enable Register. [pg. 139]
11. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting. [pg.
696]

Source Code

Complete source code for generating the periodic interrupts for Timer 0A (configured in 16-bits).
This program toggles the state of PF1 with 1 Hz frequency.

Example 10.1: timer.h

/ / GPIO registers
# define SYSCTL_RCGCGPIO_R (∗(( volatile unsigned long ∗) 0 x400FE608 ) )
# define GPIO_PORTF_DATA_R (∗(( volatile unsigned long ∗) 0 x400253FC ) )
# define GPIO_PORTF_DIR_R (∗(( volatile unsigned long ∗) 0 x40025400 ) )
# define GPIO_PORTF_DEN_R (∗(( volatile unsigned long ∗) 0 x4002551C ) )

/ / Timer r e g i s t e r s
# d e f i n e SYSCTL_RCGCTIMER_R (∗(( volatile u n s i g n e d l o n g ∗) 0 x400FE604 ) )
90 CHAPTER 10. TIMERS AND TIME BASE GENERATION

# define TIMER0_CTL_R (∗(( volatile unsigned long ∗) 0 x4003000C ) )

# define TIMER0_CFG_R (∗(( volatile unsigned long ∗) 0 x40030000 ) )
# define TIMER0_TAMR_R (∗(( volatile unsigned long ∗) 0 x40030004 ) )
# define TIMER0_TAILR_R (∗(( volatile unsigned long ∗) 0 x40030028 ) )
# define TIMER0_TAPR_R (∗(( volatile unsigned long ∗) 0 x40030038 ) )
# define TIMER0_ICR_R (∗(( volatile unsigned long ∗) 0 x40030024 ) )
# define TIMER0_IMR_R (∗(( volatile unsigned long ∗) 0 x40030018 ) )

/ / NVIC r e g i s t e r s
# d e f i n e NVIC_EN0_R (∗(( volatile u n s i g n e d l o n g ∗) 0 xE000E100 ) )
# d e f i n e NVIC_PRI4_R (∗(( volatile u n s i g n e d l o n g ∗) 0 xE000E410 ) )

/ / constant values
# d e f i n e TIM0_CLK_EN 0 x_____ // enable clock f o r Timer0
# d e f i n e TIM0_EN 0 x_____ // d i s a b l e Timer0 before setup
# d e f i n e TIM_16_BIT_EN 0 x_____ // c o n f i g u r e 16− b i t t i m e r mode
# d e f i n e TIM_TAMR_PERIODIC_EN 0 x_____ // c o n f i g u r e p e r i o d i c mode
# d e f i n e TIM_FREQ_10usec 0 x_____ // select prescalaer for
// d e s i r e d f r e q u e n c y 1 0 0 kHz
# define TIM0_INT_CLR 0 x_____ // clear time out i n t e r r u p t
# define EN0_INT19 0 x_____ // e n a b l e i n t e r r u p t 19
# define PORTF_CLK_EN 0 x_____ // enable clock f o r port F
# define TOGGLE_PF1 0 x_____ // t o g g l e r e d l e d ( PF1 )
# define LED_RED 0 x_____ // c o n f i g u r e r e d l e d ( PF1 )

/ / f u n c t i o n headers
void GPIO_Init ( void ) ;
void T i m e r _ I n i t ( unsigned long period ) ;
void DisableInterrupts ( void ) ;
void EnableInterrupts ( void ) ;
void WaitForInterrupt ( void ) ;

Example 10.2: Timer0A Periodic Interrupt.c

# include " timers . h"

void T i m e r _ I n i t ( unsigned long period ) {

SYSCTL_RCGCTIMER_R | = TIM0_CLK_EN ; // enable clock f o r Timer0

TIMER0_CTL_R &= ~ ( TIM0_EN ) ; // d i s a b l e Timer0 before setup
TIMER0_CFG_R | = T I M _ 1 6 _ B I T _ E N ; // c o n f i g u r e 16− b i t t i m e r mode
TIMER0_TAMR_R | = TIM_TAMR_PERIODIC_EN ; // c o n f i g u r e p e r i o d i c mode
TIMER0_TAILR_R = p e r i o d ; // set i n i t i a l load value
TIMER0_TAPR_R = T I M _ F R E Q _ 1 0 u s e c ; // set prescalaer for desired
f r e q u e n c y 1 0 0 kHz
TIMER0_ICR_R = T I M 0 _ I N T _ C L R ; // clear time out i n t e r r u p t
TIMER0_IMR_R | = TIM0_EN ; / / e n a b l e i n t e r r u p t mask f o r
 91

Timer_0A

DisableInterrupts () ;
/ / Set p r i o r i t y f o r i n t e r r u p t
NVIC_PRI4_R = ( NVIC_PRI4_R & 0 x00FFFFFF ) | 0 x40000000 ;
NVIC_EN0_R | = E N 0 _ I N T 1 9 ; / / e n a b l e i n t e r r u p t 19

TIMER0_CTL_R | = TIM0_EN ; // enable Timer_0A

EnableInterrupts () ;
}

void GPIO_Init () {

SYSCTL_RCGCGPIO_R | = PORTF_CLK_EN ;
GPIO_PORTF_DIR_R | = LED_RED ;
GPIO_PORTF_DEN_R | = LED_RED ;
}

void Timer0A_Handler ( void ) {

TIMER0_ICR_R = T I M 0 _ I N T _ C L R ;
GPIO_PORTF_DATA_R ^ = TOGGLE_PF1 ;

i n t main ( v o i d ) {
Timer_Init (50000) ; // g e n e r a t e a s q u a r e wave f o r 2 Hz
GPIO_Init () ; // i n i t i a l i z e PF1 a s d i g i t a l o u t p u t
while (1) ;
}