Vls I Lab Manual 2021

CVR COLLEGE OF ENGINEERING
Verilog HDL (Verilog Hardware Description Language)
The Verilog HDL is used to design combinational and sequential digital blocks. Any
design functional desciption can be synthesized/implemented using Design file. The design
functioanl simulation is done by using Testbench. Both the design file and test benches starts
with module keyword and ends with endmodule keyword. Use // for single line comments.
Design File
The digital logic design file can be written by using the block diagram with the truth
table and gate level structural connection/boolean equation/algorithm of the design.
The basic syntax of the design file is shown below.
Syntax:
module name of the module(input ports list,output ports list);
input input ports;
output output ports;
Functionality & Timing
endmodule
Note: The text in bold are the keywords in verilog and compulsory for all design files.
Functionality in design file:
The functionality is modelled in four different ways based on the design functional
level abstraction. i.e
S.No Name of Modeling Modeling Selection Verilog Keywords for design

identity
1 Gate level/ When the architecture is All basic primitives like and, or,
Structural modeling known in terms of gate nand, nor etc. And also some
level or structural user designed module names like
connections of user ha,fulladder etc.
designed blocks.
2 Data flow Modeling When the boolean Use assign keyword before the
equation is known in boolean equation.
terms of Sum of
Products or Product of
Sums.
3 Behavioral/Algorith If functionality is not Use always keyword with
m level modeling described either in sensitivity list using begin and
structural or in boolean end for behavior description.
equations then use Here use if-else,if-elseif-else,case
this.i.e. For the behavior etc statements.
or algorithm of the Note: Declare all output ports and
design is known using left hand side variables of inside
truth table. always block as reg.
4 Switch level/ If the MOS transistor Uses keywords like nmos, pmos,
transistor level logic circuit is known suppy1, supply0 etc.
modeling use this.
VLSI DESIGN LAB Page 1

Test Bench
The digital logic design functionality is verified by simulating the test bench. The test
bench syntax is same for structural/dataflow/behavioral/transistor modelings of all
combinational and sequential designs.
The basic structure of a testbench is shown in below steps.
1. Declare the module name of testbench as “tb_module name of design file” without
any port list and paranthesis.
2. Declare all input ports as type reg with same number of bits of design file.
3. Declare all output ports as type wire with same number of bits of design file.
4. Instantiate the design file that is under test using name wise port mapping or
positional wise port mapping with unit under test name.
5. Use separate initial blocks with begin and end for all inputs with time delays to
generate test stimuli or test patterns according to the truth table input conditions. The
time delays are cumulative values.
6. Use separate always blocks with begin and end for all repetative input logic swithing
ports. (Ex: For clock the logic switching is always between logic-0 and logic-1.)
7. Use the system tasks like $monitor, $display etc with initial keyword to monitor the
simulation output results in simulation console window.
8. Use the system tasks like $stop, $finish with initial keyword to stop the simulation
process after the specified time delay.
9. End the testbench by using endmodule keyword
Note:
The test bench simualtion resutls can be analyzed in textual or graphical form by
uisng binary or decimal or octal or hexa decimal formates by using the following notations as
shown in table.
S.No Number format Notation
1 Binary %b
2 Decimal %d
3 Octal %o
4 Hexa Decimal %h
Example:

The testbench for half adder design file (ha.v) with a,b inputs and sum,carry outputs is
shown below.
module tb_ha;
reg a,b;
wire sum,carry;
//LOGIC FOR PORT MAPPING
ha a0(a,b,sum,carry); //a0 is the instance name for positional mapping

OR
ha a1(.a(a),.b(b),.sum(sum),.carry(carry)); //a1 is the instance name for name wise
mapping
//END OF PORT MAPPING
initial
begin
a=1’b0;
#40 a=1’b1;
end
initial
begin
a=1’b0;
#20 a=1’b1;
#20 a=1’b0;
#20 a=1’b1;
end
initial
$monitor($time, “the values of a=%b b=%d sum=%h and carry=%o”,a,b,sum,carry);
initial
#400 $stop;
endmodule
NOTE: Use the following name wise mapping for the above half adder (ha.v) testbench file
instead of ha a0(a,b,sum,carry); //a0 is the instance name for this positional mapping.
The clock signal for time period 20 time units i.e.clk is logic -1 for 10 time units and
logic-0 for other 10 time units and this process will repeat till the end of simulation process.
The clock generation syntax is shown below. For multiple line input declations use begin and
end statements for initial or always blocks.
initial
clk=1’b1;
always #10 clk=~clk;
NOTE: In verilog HDL blocking statements(=) are used for combination design and non
blocking statements(<=) are used for sequential designs.
FPGA Design using XILINX Tools: Use Verilog HDL.

The FPGA is a pre tested, pre fabricated and pre characterized IC. The Xilinx is a
company which provides different FPGA kits and corresponding tools for the specified
FPGA Design flow. All FPGA tools from Xilinx Company are integrated as design suite
called as Xilinx Integrated Software Environment (ISE) Design suite. The following table
gives the design action and corresponding Xilinx Company based tool.
S.No Design Action Tool Name
Design Entry HDL Text Editor

1
2 Synthesis Xilinx Synthesis Tools (XST)
3 Simulation ISE Simulator
4 Timing/Floor planning Plan Ahead
5 Place and Route FPGA Editor
6 Power Analysis XPower Analyzer
7 Device Configuration Impact
S.No Purpose Cable Name
1 Downloading .bit file on to FPGA from CPU JTAG Cable
FPGA board specifications for downloading the Verilog program:
SPARTAN-3 XC3S400-PQ208-5
TYPE NAME
FAMILY SPARTAN-3
DEVICE XC3S400
(XCXilinx Comapany )
(3SSparatan-3)
(400 Gate count interm of Kilo gates)
PACKAGE PQ208(208 I/O pins)
SPEED -4/-5 (in propagation delay)
SEMI-CUSTOM/FULL-CUSTOM CADENCE TOOLS LIST

About Cadence Design Systems

The Cadence Company is a leading provider of EDA and semiconductor IP. The
Cadence company custom/analog tools help engineers design the transistors, standard cells,
and IP blocks that make up SoCs. The Cadence digital tools automate the design and
verification of Giga-Scale, Giga-Hertz SoCs at the latest semiconductor processing nodes.
The Cadence IC packaging and PCB tools permit the design of complete boards and
subsystems.
Semi-Custom VLSI Design Cadence Tools

The Semi-Custom VLSI Design starts with Verilog HDL design entry using
simulation/synthesis/Place & Route etc for a specific manufacturing foundry library. The
following table gives the design action and corresponding Cadence tool.
Design Entry VHDL/Verilog HDL
LibraryTSMC/GPDK 45nm/90nm/180nm
S.No Design Action Tool Name-License type-Version Tool Commands/ Design Steps
1. Compilencvlog/ncvhdl
1 Simulation Incisive Enterprise Simulator-XL-14.1 2. Elaboratencelab
3. Simulatencsim
2
Synthesis Encounter RTL Compiler-XL/GXL- Tool Commandrc -gui
14.1 1. Generic synthesize -to_generic
2. Mappedsynthesize -to_mapped
3.Incrementalsynthesize
-to_increment
Tool Commandencounter
1. Design Import
2. Specify Floorplan
3.Power PlanningAdd Rings/Add
strips
3 Placement and Encounter Digital Implementation 4.Special Route
Routing System-XL-14.1 5. Placement
6. Timing Analysis with Pre CTS
7. Optimization with Pre CTS
8. Synthesize clock tree
9.Timing Analysis with Post CTS
10.Optimization with Post CTS
11. Routing using NanoRoute
12.OA/GDSII

I. VERILOG PROGRAMS:
 Design Entry, Test Bench Creation, Functional Verification, Synthesis, Place &
Route, Post Place & Route Simulation, Floor Plan, Critical Path Analysis, I/O
Configuration and Pin Assignment, Generation of configuration files using
Xilinx/Altera software tools and FPGA Prototyping to be taught in these experiments.
 All types of modelling styles are to be emphasized for each experiment. HDL based
design flow should be taught.
1. Logic Gates
2. 2-to-4 Decoder
3. 8-to-3 Encoder with out and with parity
4. 4-bit Comparator
5. Multiplexer/Demultiplexer
6. Full Adder /Full Subtractor
7. SR,D, JK, T Flip-flops
8. Shift Registers
9. 4-bit binary, BCD counters synchronous/asynchronous reset or any sequence
counter.
10. Finite State Machine Design

Experiment No: 01
Logic Gates
Aim: To design logic gates using dataflow modeling style and verify the functionality, and
implement using Xilinx.
Tools Required: Xilinx ISE 12.4 Version, JTAG Cable, Adaptor 5v/4A
XILINX FAMILY SPARTAN 3
Device XC3S400
Package PQ208
Speed -4/-5
Synthesis XST(Verilog/VHDL)
Simulator ISE Simulator
Block Diagram Logic Diagram
Truth Table:
Verilog Code:
module allgates(a, b, andout, orout,xorout,nandout,norout,xnorout,invout,);
input a,b;
output andout,orout,xorout,nandout,norout,xnorout,invout;
assign andout=a&b;
assign orout=a | b;
assign norout=~(a | b);
assign nandout=~(a&b);
assign xorout=a ^ b;
assign xnorout=~(a ^ b);
assign invout=~a;
endmodule

Test Bench: Write the testbench according to the testbench structure by using truth table
inputs of the design.
RESULT ANALYSIS
Synthesis Result: Observe the synthesis result by comparing with the block diagram and
note down the timing delay values.
Device Utilization Summary/Gate Count: Observe the device utilization summary for the
selected FPGA board using FPGA tools.
(OR)
Observe the gate count for the selected IC foundry based technology library using Cadence
tools.
Simulation Results: Observe simulation results according to the testbench stimuli by using
timing waveforms. Analyze the simulation results by using textual results available in
simulation tool console window.
Implementation Results/Place & Route Results:
Observe FPGA implementataion results by downloading .bit file using JTAG cable with the
help of view/edit Place and Route results.
(OR)
Observe semic custom ASIC or cell based ASIC implementation/place and route results by
using Encounter Digital Implementation Cadence tools.
VIVA-VOCE QUESTIONS:
1. Draw the symbol, truth table of a primitive gate.
2. What are the advantages of Verilog HDL compared to programming languages.
3. Design NAND gate using OR gates and Inverters.
4. Define simulation and synthesis.
5. What is the difference between FPGA and ASIC.
ASSIGNMENT:
1. Design all logic gates using structural modeling with assign keyword.
2. Design all logic gates using behavioral modeling with always blocks.
3. Design all logic gates using any modeling style and use 8x1 multiplexer at the outputs
of and select only one gate output based on selection lines.
Experiment No: 02
2-to-4 Decoder
Aim: To design 2-to-4 decoder using behavioral modeling style and verify the functionality,
and implement using Xilinx.
Device XC3S400
Package PQ208
Speed -4/-5
Truth Table:
Verilog Code:
module dec24(EN,A1,A0,D3,D2,D1,D0);
input EN,A1,A0;
output reg D3,D2,D1,D0;
always@( EN,A1,A0)
begin
if(EN==1’b1)
{D3,D2,D1,D0}=4’d0;
else
begin
case({A1,A0})
2’b00: {D3,D2,D1,D0}=4’b0001;
2’b01: {D3,D2,D1,D0}=4’b0010;
2’b10: {D3,D2,D1,D0}=4’b0100;
2’b11: {D3,D2,D1,D0}=4’b1000;
default: {D3,D2,D1,D0}=4’b0000;
endcase
end
end
endmodule

RESULT ANALYSIS
(OR)
tools.
(OR)
1. What is the concatenation operator in Verilog HDL.
2. Represent the value of 145 in binary,decimal,octal and hexadecimal formats of
Verilog HDL.
3. What is the effect of presence and obsence of default statement in case statement in
RTL schematic of the design.
4. What is the difference between decoder and encoder.
5. Represent the 2-to-4 decoder output in vector form in verilog HDL.
ASSIGNMENT:
1. Design 2-to-4 decoder using dataflow modeling.
2. Design 3-8 decoder using structural connection of 2-to-4 decoders and other logic
gates.
3. Design 2-to-4 decoder using vector I/O representation with any modeling.
4. Design 2-to-4 decoder using only NAND gates.
Experiment No: 03
8-to-3 Encoder (without and with priority)
Aim: To design 8-to-3 Encoder (without and with priority) using behavioral modeling style
and verify the functionality, and implement using Xilinx.

Device XC3S400
Package PQ208
Speed -4/-5
Truth Table:
Verilog Code:
A) 8-to-3 Encoder (without priority)
module enc83(en,i,y);
input en;
input [0:7]i;
output [2:0]y;
reg [2:0]y;
always@(en,i)
begin
if(en)
y=3’d0;
else
case(i)
8'b10000000: y = 3’d0;
8'b01000000: y = 3'd1;
8'b00100000: y = 3'd2;
8'b00010000: y = 3'd3;
8'b00001000: y = 3’d4;
8'b00000100: y = 3'd5;
8'b00000010: y = 3'd6;
8'b00000001: y = 3'd7;

default: y = 3'd0;
endcase
end
endmodule
B)8-to-3 Encoder (with priority)
Verilog Code:
8-to-3 Encoder (with priority)
module prienc83(D,Q);
input [7:0]D;
output [2:0]Q;
reg [2:0]Q;
always@(D)
begin
if(D[7]==1’b1)
Q=3’d7;
else if(D[6]==1’b1)
Q=3’d6;
Q=3’d5;
Q=3’d4;
Q=3’d3;
Q=3’d2;
Q=3’d1;
Q=3’d0;
else
Q=3’d0;
end
end
endmodule

RESULT ANALYSIS
(OR)
tools.
(OR)
1. What is the difference between priority encoder and normal encoder.
2. What are the applications of priority encoder.
3. Write the basic syntax of case statement.
4. Based on which specifications the case statement (or) if-else statement will be used in
the design file.
5. What are the logic levels supported by verilogHDL.
ASSIGNMENT:
1. Design 8-to-3 encoder using if-else statements.
2. Design 8-to-3 encoder using structural connections of 4-to-2 encoder and other logic
gates.
3. Design 4-to-2 encoder using dataflow modeling with boolean equations.

Experiment No: 04
4-Bit Comparator
Aim: To design 4-bit comparator using behavioral modeling style and verify the
functionality, and implement using Xilinx.


Device XC3S400
Package PQ208
Speed -4/-5
Truth Table
Verilog Code:
module comp4bit(a,b,agtb,aeqb,altb);
input [3:0] a,b;
output agtb,aeqb,altb;
reg agtb,aeqb,altb;
always@(a,b)
begin
if(a>b)
begin
agtb=1’b1;
aeqb=1’b0;
altb=1’b0;

end
else if(a==b)
begin
agtb=1’b0;
aeqb=1’b1;
altb=1’b0;
end
else
begin
agtb=1’b0;
aeqb=1’b0;
altb=1’b1;
end
end
endmodule
RESULT ANALYSIS
(OR)
tools.
(OR)
1. Define comparator.
2. What are the applications of comparator.
3. What is the full form of JTAG.

4. What is the use of ternary or conditional operator.

ASSIGNMENT:
1. Design 2-bit comparator using dataflow or structural modeling.
Experiment No: 05
8-to-1 Multiplexer and 1-to-8 Demultiplexer
Aim: To design 8x1 multiplexer and 1X8 demultiplexer using behavioral modeling style and
verify the functionality, and implement using Xilinx.
Device XC3S400
Package PQ208
Speed -4/-5

Block Diagram Logic diagram
Truth Table
Verilog Code:
module mux81(s,d,y);
input [2:0]s;
input [7:0]d;
output y;
reg y;
always@( s,d)
begin
case(s)
3’b000: y= d[0];
3’b001: y= d[1];
3’b010: y= d[2];
3’b011: y= d[3];
3’b100: y= d[4];
3’b101: y= d[5];
3’b110: y= d[6];
3’b111: y= d[7];
default: y= 1’b0;
endcase
end
endmodule
B)1X8 Demultiplexer
Truth Table
Verilog Code
module demux(d, sel, y);
input d;
input [2:0] sel;
output [7:0] y;
reg [7:0] y;
always @( d or sel)
begin
y=8’d0;
if( sel==3'b000)
y[0]=d;
else if( sel==3'b001)
y[1]=d;
y[2]=d;


y[3]=d;
y[4]=d;
y[5]=d;
y[6]=d;
y[7]=d;
else
y=8’dX;
end
endmodule
RESULT ANALYSIS
(OR)
tools.
(OR)
1. Draw 2x1 multiplexer and explain its operation using truth table.
2. Difference between multiplexer and decoder.
3. Design any one logic gate using 4x1 multiplexer.

4. How to access two or more bits of a vector in verilog HDL.

5. Why the output is declared as reg in behavioral modeling.
ASSIGNMENT:
1. Design 8x1 multiplexer using 4x1 and 2x1 multiplexers.
2. Design 2-bit 2x1 multiplexer using behavioral modeling.
3. Design 8x1 multiplexer using if-else statements.
4. Design 4x1 multiplexer using assign statements.
5. Design 1X8 Demultipliexer using case statement.
Experiment No: 06
Full Adder and Full Subtractor
Aim: To design full adder and full subtractor using structural, dataflow and behavioral
modeling style and verify the functionality, and implement using Xilinx.
Device XC3S400
Package PQ208
Speed -4/-5

Truth Table
Verilog Code: FULL ADDER USING BEHAVIORAL MODELING

module fa(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
reg sum,carry;
always@(a,b,cin)
begin
{carry,sum}=a+b+cin;
end
endmodule
Verilog Code: FULL ADDER USING DATA MODELING

module fulladder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;

assign sum = a ^b^ cin;

assign carry = ((a ^b) & cin) | (a & b));
endmodule
Verilog Code: FULL ADDER USING STRUCTURAL MODELING

module fulladder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
wire w1,w2,w3;
xor x1(w1,a,b);
xor x2(sum,w1,cin);
and x3(w2,a,b);
and x4(w3,w1,cin);
or x5(carry,w2,w3);
endmodule
B) Full Subtractor
Truth Table
Verilog Code:
module full_subtractor ( a ,b ,c ,diff ,borrow );

input a ;
input b ;
input c ;
output diff ;
output borrow ;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
RESULT ANALYSIS
(OR)
tools.
(OR)
1. What is the difference between half adder and full adder.
2. Draw the truth table for half adder.
3. What is the full form of FPGA.
4. Define simulation.
ASSIGNMENT:
1. Design half adder using data flow.
2. Design full adder using half adder and logic gates.
3. Design full subtractor using structural and behavioral HDL modeling.

Experiment No: 07
SR, D, JK,T Flip Flops

Aim: To design SR-Flip Flop,D-Flip Flop, JK-Flip Flop and T-Flip Flop using behavioral
Device XC3S400
Package PQ208
Speed -4/-5
A) SR-Fliop Flop
Truth Table
Verilog Code:
module srff(clk,rst,s,r,q);
input clk,rst,s,r ;
output q;
reg tq;
always @ (posedge clk or posedge rst)
begin
if(rst==1'b1)
tq<=1'b0;
else if (s==1'b0 & r==1'b0)
tq<=tq;
else if (s==1'b0 & r==1'b1)
tq<=1'b0;
else if (s==1'b1 & r==1'b0)
tq<=1'b1;
else if (s==1'b1 & r==1'b1)
tq<=1’bx;
end
assign q=tq;
endmodule
B) D-Flip Flop

Truth Table
Verilog Code
module dff(d, clk, rst, q);

input d,clk,rst;
output q;
reg tq;
always@(posedge clk or negedge rst)
begin
if(~rst)
tq <=1’b0;
else
tq <= d;
end
assign q=tq;
endmodule
C) JK-Flip Flop
Truth Table

Verilog Code:
module jkff(clk,rst,j,k,q);
input clk,rst,j,k ;
output q;
reg tq;
always @ (posedge clk or posedge rst)
begin
if(rst==1'b1)
tq<=1'b0;
else if (j==1'b0 & k==1'b0)
tq<=tq;
else if (j==1'b0 & k==1'b1)
tq<=1'b0;
else if (j==1'b1 & k==1'b0)
tq<=1'b1;
else if (j==1'b1 & k==1'b1)
tq<=~tq;
end
assign q=tq;
endmodule
D) T-Flip Flop
Truth Table
Verilog Code
module tff(clk,rst,t,q);
input clk,rst,t;
output q;
reg tq;

always @(posedge clk or posedge reset)

begin
if (reset)
tq <= 1'b0;
else if(t==1)
tq <= ~tq;
end
assign q=tq;
endmodule
RESULT ANALYSIS
(OR)
tools.
(OR)
1. What is the difference between latch and flip-flop.
2. Define setup time and hold time.
3. Define critical path.
4. What is the difference between blocking and non blocking statements.
5. What is the full form of ASIC.
ASSIGNMENT:

1. Design D flip-flop using negative edge triggering of clock.

2. Design S-R flip-flop using asynchronous preset and synchronous reset.
3. Design J-K filp-flop using set and clear.
Experience-08
Shift Registers
Aim: To design 8-bit shift Register using behavioral modeling style and verify the
Device XC3S400
Package PQ208
Speed -4/-5

Truth table
Verolog Code:
module shift (clk, load, si, d, so);
input clk, si, load;
input [3:0] d;
output so;
reg [3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= {si, tmp[3:1]};
end
assign so = tmp[3];
endmodule
RESULT ANALYSIS
(OR)
tools.

(OR)
1. What is meant by shift register
2. Types of shift registers
3. What is the difference between synchronous reset and asynchronous reset.
4. What is the difference between blocking and non blocking statements.
5. What is the full form of FPGA.
ASSIGNMENT:
1. Design 8-bit shift left register.
2. Design universal shift register.
3. Design 8-bit register.
Experiment No: 09
4-BIT BINARY,BCD COUNTERS(SYNCHRONOUS/ASYNCHRONOUS)
Aim: To design 4-Bit Binary,BCD Counters(synchronous/asynchronous) using behavioral

Device XC3S400
Package PQ208
Speed -4/-5

A) 4-Bit Binary Counter with synchronous reset

Truth table
Verilog code:
module counter(clk,rst,q);
input clk,rst;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (rst)
q <= 4'd0;
else
q <= q + 4'd1;
end
endmodule
B) BCD Counter with asynchronous reset

Truth table

Verilog Code:
module bcdcount(clk,rst,q);
input clk,rst;
output [3:0] q;
reg [3:0] tq;
always @(posedge clk,posedge rst)
begin
if (rst)
tq <= 4'd0;
else
begin
if(tq>=4’d9)
tq<=4’d0;
else
tq <=tq + 4'd1;
end
end
assign q=tq;
endmodule
RESULT ANALYSIS
(OR)
tools.

(OR)
1. What is the difference between clear and reset.
2. What is the difference between set and preset.
3. What is the difference between synchronous input and asynchronous input.
4. What is the difference between level triggering and edge triggering.
5. What is the range of BCD numbers.
6. What is the differnce between BCD counter and binary counter.
7. What is the difference between synchronous and asynchronous counters.
8. What are the different types of counters.
ASSIGNMENT:
1. Design 3-bit binary counter using asynchronous preset and reset.
2. Design 4-bit ring counter using structural modeling.
3. Design 3-bit up/down counter using behavioral modeling.
4. Design a sequence counter with counting sequence as 0001,1011,1100,0100, 1011,
0101 using behavioral modeling.
Experiment No: 10
Finite State Machine
Aim: To design 2-bit binary counter using mealy finite state machine and verify the
Device XC3S400
Package PQ208
Speed -4/-5
Block Diagram State Diagram

Truth Table Logic Diagram
Verilog code:
module count2(clk,rst);
input clk,rst;
reg [1:0]state,next;
parameter s0=2’b00;
parameter s1=2’b01;
parameter s2=2’b10,s3=2’b11;
always@(posedge clk or posedge rst)
begin
if(rst)
state<=s0;
else
state<=next;
end
always@(state)
begin
case(state)

s0: begin
next=s1;
end
s1: begin
next=s2;
end
s2: begin
next=s3;
end
s3: begin
next=s0;
end
default: begin
next=s0;
end
endcase
end
endmodule
RESULT ANALYSIS
(OR)
tools.
(OR)

1. Difference between mealy and moore machines.

2. What is the difference between parameter and `define.
ASSIGNMENT:
1. Design 2-bit moore counter using three always blocks.
2. Design a sequence detector to detect 0110.
3. Design a sequence counter with counting sequence as 0001,1011,1100,0100, 1011,
0101 using one always block.
II. CMOS VLSI Circuit Design

• Perform Schematic capture, Simulation, Layout, Physical Verification, Design Rule
Check, LVS Check, Parasitic Extraction, Place and Route, Static Timing Analysis, IR
drop analysis and Crosstalk analysis using EDA Tools.
• Perform all types of analysis like Transient, DC, AC etc. wherever possible.
1) CMOS Inverter schematic and layout

2) CMOS NAND schematic and layout
3) CMOS NOR schematic and layout
4) CMOS Full Adder
5) Static / Dynamic Latch (or) Flip Flop design
6) Pass transistor circuits (or) Transmission gate based circuits design
7) Analog circuit simulation of Common Source (or) Common Drain amplifier

8) Introduction to SPICE and simulation of basic analog circuits: Inverter /

Differential amplifier / Current mirrors etc.
Full-Custom VLSI Design using Cadence Tools
The Full-Custom VLSI Design starts with MOS transistor level design entry using
Schematic/Simulation/Layout/Design Rule Check/ Layout Vs Schematic/ GDSII/OA etc
for a specific manufacturing foundry library. The simulation is done for
ac/dc/transient/noise and other analysis using SPICE model files. The following table
gives the design action and corresponding Cadence tool.
Design Entry MOS transistor level design entry
LibraryTSMC/GPDK 45nm/90nm/180nm
Cadence Full Custom Analog/Mixed Signal Tool invoking command: virtuoso &
S.N Design Action Tool Name-License type-Version
o
1 Schematic Entry Virtuoso(R) Schematic Editor –XL-6.1.7
Symbol
2 Virtuoso(R) Symbol Editor –XL-6.1.7
generation
Test Bench
3 Virtuoso(R) Schematic Editor –XL-6.1.7
Schematic Entry
Pre-Simulation/
4 Virtuoso(R) Analog Design Environment XL-6.1.7
Post-Simulation
5 Layout Virtuoso(R) Layout Suite- XL-6.1.7
Design Rule
6 Cadence® Physical Verification System Design Rule Checker
Check
Cadence® Physical Verification System Layout vs. Schematic
Layout Vs.
7 Checker XL
Schematic
Full Custom Design flow using Cadence Tools
Fig. Design Flow

Schematic Capture
The transistor level schematic is designed by using pseudo nmos logic/cmos

logic/DCVS/Clocked cmos logic/Domino logic etc for mos digital logic.
The basic cmos topology as shown in the Fig consists of pull-up network with
pmos transistors and pull-down network with nmos transistors connected in between
VDD and GND. The pull-up and pull-down network are complementary to each
other. The schematic design is entered by using Virtuoso(R) schematic Editor –XL-
6.1.7
Create Symbol Fig. CMOS TOPOLOGY
The symbol view of a circuit module is an icon that represents the collection
of all components within the module. A symbol view of the circuit is also required for
some of the subsequent simulation steps, therefore the schematic capture of the circuit
topology is usually followed by the creation of a symbol to represent the entire circuit.
It is generated using Virtuoso(R) Symbol Editor –XL-6.1.7
Simulation using Test Bench

The testbench for any cmos design can be designed by using schematic
symbol with defined input voltage/current and sinusoidal/nonsinusoidal sources
based on the types of output analysis. Testbench schematic entry is done using
Virtuoso(R) Schematic Editor –XL-6.1.7.The simulation results can be analyzed
using transient/ac/dc/noise and other responses based on the selected design input.
The design functionality is verified by sepctre SPICE Simulation tool using
Virtuoso(R) Analog Design Environment XL-6.1.7.
Layout
The graphical representation of the transistor level schematic for IC
manufacturing is called layout. The layout is drawn by converting stick diagrams into
layers based design by following IC foundry λ based or scalable design rules. For
CMOS designs the layouts can be drawn using either N-well or P-well fabrication
process. The layout is entered using Virtuoso(R) Layout Suite- XL-6.1.7
LAYOUT ELEMENTS FOR N-WELL CMOS FABRICATION
S.No Type Schematic Layout Explanation

Cross section of poly
and n-diffusion is
called NMOS layout.
1 NMOS N-diffusion is
Transistor selected using Oxide
Enclosure with N-
implant.
Cross section of poly

and p-diffusion is
PMOS called PMOS layout.
2 Transistor P-diffusion is
selected using Oxide
Enclosure with P-
implant

Use N-well with N-

implant, metal1,
3 VDD contact, oxide to create
P-tie for VDD
connection.
Use N-implant,
4 GND metal1, contact, oxide
to create P-tie for
GND connection.(P-
well is not required as
P-substrate is readily
available for NMOS
transistors)
Deign Rule Check(DRC)

The created mask layout must conform to a complex set of design rules. A tool
built into the Layout Editor, called Cadence® Physical Verification System Design
Rule Checker, is used to detect any design rule violations during and after the mask
layout design. The designer must perform DRC, and make sure that all errors are
eventually removed from the mask layout, before the final design is saved.
Layout vs schematic check (LVS)
After the mask layout design of the circuit is completed, the design should be
checked against the schematic circuit description created earlier. By comparing the
original network with the one extracted from the mask layout the designer can check
that the two networks are indeed equivalent in terms of I/O names and VDD, GND
connections.LVS check is done by using ASSURA Physical Verification System
Layout Vs. Schematic Checker-XL-6.1.7
Note that the LVS check only guarantees a topological match. In other words,
a successful LVS will not guarantee that the extracted circuit will actually satisfy the
performance requirements. Any errors that may show up during LVS such as
unintended connections between transistors, or missing connections/devices, etc.
should be corrected in the mask layout- before proceeding to post-layout simulation.
Extraction
The circuit extraction is performed after layout vs schematic check of a design
in order to create a detailed net-list for the simulation tool. The circuit extraction is
done by using ASSURA Parasitic Extraction. The circuit extractor is capable of
identifying the individual transistors and their interconnections as well as the parasitic
resistances and capacitances that are inevitably present between these layers.
Post Layout Simulation

The electrical performance of a full-custom design can be best analyzed by
performing a post-layout simulation on the extracted circuit net-list. The detailed
(transistor-level) simulation performed using the extracted netlist must be verified by
sepctre SPICE Simulation tool using Virtuoso(R) Analog Design Environment XL-
6.1.7.

Experiment No: 01
Layout of CMOS Inverter
Aim: To design CMOS Inverter and implement its layout using GPDK 90nm technology.
Tools Required: Cadence 6.1.7

ENTRY TYPE NAME OF THE TOOL
Schematic Entry Composer Schematic
Symbol Creation Composer Symbol
Tb Creation Composer Schematic
Simulation Analog Design Environment
Layout Virtuoso
DRC Assura
LVS Assura
Schematic Symbol

Testbench Layout
ResultAnaysis
The simulation results can be analyzed using transient and DC responses.
1. Define Noise Margin.
2. Draw I-V characteristics of CMOS inverter.
ASSIGNMENT:
1. Design NMOS depletion load inverter.
2. Design Pseudo NMOS inverter.
3. Perform I-V Characteristics of NMOS and PMOS transistor.
Experiment No: 02
Layout of CMOS NAND
Aim: To design CMOS NAND gate and implement its layout using GPDK 90nm
technology.
Tools Required: Cadence6.1.7
Layout Virtuoso
DRC Assura
LVS Assura
Schematic Symbol

Test Bench
Result Anaysis
The simulation results can be analyzed using transient response.
1. Draw the stick diagram of CMOS AND gate.
2. What is meant by Design Rule Checker?

ASSIGNMENT:
1. Design CMOS AND gate and perform its LVS.
Experiment No: 03
Layout of CMOS NOR
Aim: To design CMOS NOR gate and implement its layout using GPDK 90nm technology.
Tools Required:
Layout Virtuoso
DRC Assura
LVS Assura
Schematic Symbol
Test Bench Layout
ResultAnaysis
The simulation results can be analyzed using transient and LVS responses.
1. Draw the stick diagram of CMOS OR gate.
2. What is meant by GPDK?
ASSIGNMENT:

1. Design CMOS OR gate and perform its LVS.

2. Design and simulate CMOS XOR gate.
Experiment No: 04
CMOS Full Adder
Aim: To design and simulate the CMOS Full Adder using GPDK 90nm technology.
Tools Required:
Layout Virtuoso
DRC Assura
LVS Assura
Schematic

Symbol Test Bench
Result Anaysis
1. Draw the logic diagram of full adder.
2. What is meant by 90nm technology?
ASSIGNMENT:
1. Design and simulate CMOS Half Adder.
2. Design and simulate CMOS Full Subtractor.

Experiment No: 05
D Flip-Flop
Aim: - To design and simulate a D flip flop (register) using GPDK 90nm technology.
Layout Virtuoso
DRC Assura
LVS Assura
Schematic Symbol
Test Bench

Result Analysis:
1. Draw the D-flipflop using nand gates.
2. Difference between flip-flop and latch.
ASSIGNMENT:
1. Design and simulate 2-bit counter using D-Flip-flop.
Experiment No: 06
Pass Transistor
Aim : - To design and simulate a Pass Transistor using gpdk 90nm technology.

Layout Virtuoso
DRC Assura
LVS Assura
Schematic :

Result Analysis:
The simulation results can be analyzed using transient response
1. Draw the xor gate using pass transistor logic.
2. Draw 2x1 mux using pass transistor logic .
3. What are the disadvantages of pass transistor logic
ASSIGNMENT:
1. Implement XOR gate using pass transistor logic
Experiment No: 07
Common Source Amplifier
Aim: To design common source amplifier and common drain and verify functionality
using 90nm technology of GPDK by using Cadence tools
Layout Virtuoso
Drc Assura
Lvs Assura
Schematic
DC Response
 Initially set DC Voltage to 1V.

 In DC current source in “idc” set to “Iref" parameter for now.

 In input voltage source “vsin” set AC magnitude to 1V and leave other parameters
without filling.
 After opening ADE-L now select option variables  copy from varaibles, then it will
be added in design varaibles filed.
 Now choose “dc” then select Design varaible option in sweep varaible field and select
Varaible name as Iref by selecting “Select Design Varaible” button, then set sweep
range from 0(start) to 1mv(stop) as shwon in the Fig 2.
Figure 2- DC Analaysis Window

 Now select ok and run the simulation
 After plotting DC response place a marker and note current at 0.5mv output voltage
which is midpoint of VDD as shown in the Fig 3. These are called as bias points.
Figure 3- DC Response
AC Response
 Now analyze AC Response by substituting the current and voltages. Substitute
current in Idc and dc voltage in “vsin” signal source.
 Now select “ac” option and select “frequency” option as sweep variable and
mention seep range(say start 1 and stop 10M) and Logarithmic value(say 100/150
points per decade).

 Next do simulation and plot AC Response.
Figure 4 AC Response
Gain calculation using calculator

 First select “wave” button then select “vf” button and then select on output pin,
then it shows VF(“/vout”) in the panel
 Next again select on input pin then it shows VF(“/vin”)
 Now select on “/” button in the calculator then it shows VF(“/vout”)/VF(“vin”).
 Then select “mag” button from the function panel then it shows
mag(VF(”/vout”)/VF(“/vin”))
 Now select “db20” button from the function panel then it shows
db20(mag(VF(”/vout”)/VF(“/vin”))).
 Now click evaluate it will show the gain value.
Transient Response
 Now analyze transient response by setting input frequency and amplitude(say
5mv,10KHZ) in “vsin”

SIMULATION RESULTS:
Use the transistor level schematic design for Common source and common drain amplifiers
for gain calculations. Apply the pulse/sinusoidal/rectangular voltage inputs for SPICE code
and observe the outputs using Virtuoso Analog Design Environment setup using
normal/parametric/monto-corlo setups for transient/ac/dc/noise analysis.
PERFORMANCE ANALYSIS:
Analyze the simulated design for gain, static timing analysis, delay calculations, power
calculations, cross talk analysis using waveform/Virtuoso(R) visualization and analysis XL
calculator options.
1. Define Amplifier.
2. Expand ADEL?
3. Explain the working of CS Amplifier
ASSIGNMENT:
1. Implement CD Amplifier.

Experiment No: 08
Introduction to SPICE and simulation of basic analog circuits

Inverter / Differential amplifier
Aim: To design inverter using spice code and verify its simulation using
45nm/90nm/180nm technologies of GPDK/TSMC libraries by using Cadence tools
Layout Virtuoso
Drc Assura
Lvs Assura
Spice code for CMOS Inverter:-

Simulator lang=spectre
global 0 vdd!
include "/home/cadence/full-custom/gpdk090_v4.4/models/spectre/gpdk090.scs"
section=NN
PM0 (Y A vdd! vdd!) gpdk090_pmos1v w=(120n) l=100n
PM1 (Y A 0 0) gpdk090_nmos1v w=(120n) l=100n
V0 (A 0) vsource type=pulse val0=0 val1=1 period=20n width=10n
V1 (vdd! 0) vsource dc=1 type=dc
tran tran stop=120n
First enter SPICE code of inverter by using command gedit “inv.scs” in the
user director say (/home/btech/icfb) now source the tool by using the command
“source /home/cadence/cshrc/cshrc_IC”.

Next give the command for doing simulation “spectre inv.scs” then it will
compile the file and shows errors or warning if any and displays here. If any errors or
warnings are there clear those and compile once again. Now give the command “viva
&” for doing simulation. After giving the command the Next license window will
appear as shown in the Fig.
By selecting Yes button in the Next license window generates CDS.log

window and virtuoso® Visualization and Analysis XL Editor as shown in the Fig.
In virtuoso® Visualization and Analysis XL Editor Window goto File open Results
then a select waveform database window will appear as shown the Fig.
Here select inv.raw file and click open, with this option the signals will appear in the
Browser field of virtuoso® Visualization and Analysis XL Editor window as shown
in the Fig.

Now select the “tran” field it will show the input and output signals. Here select input
wave form and select plot signal icon which is shown in the Fig. with this option it
will display input signal similarly plot the output wave form.
The simulated wave form is shown the Fig.
Simulated Waveform:-
RESULT ANALYSIS

SIMULATION RESULTS: Use the transistor level schematic design for CMOS inverter
and create SPICE code for the design. Apply the pulse/sinusoidal/rectangular voltage inputs
for SPICE code and observe the outputs using Virtuoso Analog Design Environment setup
using normal/parametric/monto-corlo setups.
PERFORMANCE ANALYSIS:
Analyze the simulated design for static timing analysis, delay calculations, power
calculations, cross talk analysis using waveform/Virtuoso(R) visualization and analysis XL
calculator options.
1. SPICE stands for__________________
2. What is the difference between normal simulation and SPICE simulation.
3. What is netlist.
4. What is the netlist language in HDL designs and in transistor level designs.
5. What is the simulator used in Cadence for normal/SPICE simulation.
6. What are the different options in Calculator.
7. What is the Model library used in this SPICE simulation.
8. What is the difference between GDSII and OA.
ASSIGNMENT:
1. Write SPICE code for PMOS transistor
2. Write SPICE code for any CMOS circuitry.
3. Design differential amplifier using SPICE code.
4. Write SPICE code for two input NAND gate
5. Write SPICE code for two input NOR gate

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CVR COLLEGE OF ENGINEERING

Verilog HDL (Verilog Hardware Description Language)

Functionality & Timing

S.No Name of Modeling Modeling Selection Verilog Keywords for design

VLSI DESIGN LAB Page 1

The basic structure of a testbench is shown in below steps.

VLSI DESIGN LAB Page 2

//LOGIC FOR PORT MAPPING

ha a0(a,b,sum,carry); //a0 is the instance name for positional mapping

FPGA Design using XILINX Tools: Use Verilog HDL.

VLSI DESIGN LAB Page 3

S.No Design Action Tool Name

Design Entry HDL Text Editor

2 Synthesis Xilinx Synthesis Tools (XST)

3 Simulation ISE Simulator

4 Timing/Floor planning Plan Ahead

5 Place and Route FPGA Editor

6 Power Analysis XPower Analyzer

7 Device Configuration Impact

S.No Purpose Cable Name

1 Downloading .bit file on to FPGA from CPU JTAG Cable

FPGA board specifications for downloading the Verilog program:

VLSI DESIGN LAB Page 4

About Cadence Design Systems

Semi-Custom VLSI Design Cadence Tools

VLSI DESIGN LAB Page 5

VLSI DESIGN LAB Page 6

Block Diagram Logic Diagram

VLSI DESIGN LAB Page 7

Block Diagram Logic Diagram

VLSI DESIGN LAB Page 9

8-to-3 Encoder (without and with priority)

VLSI DESIGN LAB Page 11

Block Diagram Logic Diagram

VLSI DESIGN LAB Page 12

B)8-to-3 Encoder (with priority)

VLSI DESIGN LAB Page 13

VLSI DESIGN LAB Page 14

VLSI DESIGN LAB Page 15

XILINX FAMILY SPARTAN 3

Block Diagram Logic Diagram

VLSI DESIGN LAB Page 16

VLSI DESIGN LAB Page 17

4. What is the use of ternary or conditional operator.

VLSI DESIGN LAB Page 18

Simulator ISE Simulator

Block Diagram Logic diagram

Block Diagram Logic Diagram

VLSI DESIGN LAB Page 20

else if( sel==3'b011)

VLSI DESIGN LAB Page 21

4. How to access two or more bits of a vector in verilog HDL.

Full Adder and Full Subtractor

VLSI DESIGN LAB Page 22

Simulator ISE Simulator

Block Diagram Logic Diagram

Verilog Code: FULL ADDER USING BEHAVIORAL MODELING

Verilog Code: FULL ADDER USING DATA MODELING

VLSI DESIGN LAB Page 23

assign sum = a ^b^ cin;

Verilog Code: FULL ADDER USING STRUCTURAL MODELING

VLSI DESIGN LAB Page 24

Implementation Results/Place & Route Results: