Part 3 Modeling Counters in VHDL

VHDL allows user to model counters using a single PROCESS and arithmetic operators mainly
+ and -.

A counter can be specified as

X+ = X +1 UP mode
Or X+ = X – 1 DOWN mode

Example 1
Write the behavioral VHDL code to synthesize a Mod-16 UP counter

If (Clk’event and Clk =’1’) means at every positive edge of Clk, then increment state. When the
signal state reaches “1111”, it will automatically roll over to “0000”.

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Example 2
Write the behavioral VHDL code to synthesize a Mod-16 UP counter. Provide a mean to reset
(clear) the counter at any instant of time.

In time interval 0.. 120 ns, the counter is reset

In time interval 120 ns .. 360 ns, counter counts every 50 ns
It is once again cleared during the interval 360 ns .. 480 ns
In the remaining time, CLR is disabled, the counter scans through the 16 states.

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Example 3 Truncated counter
Write the behavioral VHDL code to synthesize a Mod-10 UP counter. Provide a mean to reset
(clear) the counter at any instant of time.

In a Mod_10 counter, w the counter reaches 9, it should roll-over to zero.

Therefore, we should test when the counter reaches 9 to clear it.

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Example 4 Truncated counter
Write the behavioral VHDL code to synthesize a Mod-10 DOWN counter. Provide a mean to
reset (clear) the counter at any instant of time.

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Example 5 Truncated counter

Write the behavioral VHDL code to synthesize a Mod-6 UP/DOWN counter. Provide a mean to
reset (clear) the counter at any instant of time.

1. 0 .. 80 ns Clear
2. 80 ns .. 620 ns UP mode
3. 620 ns .. 980 ns DOWN mode
4. 980 ns .. 1.12 µs UP
5. 1.12 µs .. 1.38 µs DOWN

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Exercises

1. Write a behavioral VHDL code to synthesize a Mod-10 UP/DN counter. The counter should
increment/decrement at the negative edge of the clock.
Provide a mean (active HIGH) to clear the counter at any instant of time.
Perform a functional simulation

2. Write a behavioral VHDL code to synthesize a counter that will cycle through the following
sequence 0, 2, 5, 9, 13, 15, 0, 2, … Changes should occur during the negative edge of the clock.
Provide a mean to preset your counter to 5 at any instant of time.
Perform a functional simulation

3. Write a behavioral VHDL code to synthesize a Mod-12 UP counter. The counter should
increment at the negative edge of the clock. Provide a mean to enable or disable your counter at
any instant of time
Perform a functional simulation