Microprocessor MCQ UNIT 6: MP - U6 MCQ Saj

1
MP _U6 MCQ SAJ

Microprocessor MCQ UNIT 6
((MARKS)) 1
(1/2/3...)
((QUESTION)) This type of interrupts cannot be avoided by processor.
((OPTION_A)) Non Maskable
((OPTION_B)) Maskable
((OPTION_C)) Exceptions
((OPTION_D)) All the above
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupts are the _______events
((OPTION_A)) External
((OPTION_B)) Internal
((OPTION_C)) Both A and B
((OPTION_D)) None of the above
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
2
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) In 80386, we can give interrupt to the machine by giving signals on
((OPTION_A)) INTR
((OPTION_B)) NMI
((OPTION_C)) INTA
((OPTION_D)) Both A and B
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
3
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which interrupts used in critical condition?
((OPTION_A)) INTR
((OPTION_B)) Single step
((OPTION_C)) NMI
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
4
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The interrupt can be disabled by using instruction______
((OPTION_A)) CLD
((OPTION_B)) STI
((OPTION_C)) CLI
((OPTION_D)) STI
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupts can be of____
((OPTION_A)) Hardware
((OPTION_B)) Software
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which is the following interrupt having lowest priority?

5
MP _U6 MCQ SAJ
((OPTION_A)) NMI
((OPTION_B)) INTR
((OPTION_C)) Faults
((OPTION_D)) Single step
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which is the interrupt having highest priority?
((OPTION_A)) INTO
((OPTION_B)) NMI
((OPTION_C)) Single Step
((OPTION_D)) INTA
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) This ______masks NMI interrupt
((OPTION_A)) IF
((OPTION_B)) INTR
6
MP _U6 MCQ SAJ
((OPTION_C)) NMI
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) If IF=0, then it will masks
((OPTION_A)) INTR interrupt
((OPTION_B)) NMI interrupt
((OPTION_C)) RF interrupt
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) STI and CLI instructions will be executed only when
((OPTION_A)) CPL = IOPL
((OPTION_B)) CPL >= IOPL
((OPTION_C)) CPL <IOPL
((OPTION_D)) Both A and C

7
MP _U6 MCQ SAJ
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) This____will masks debug faults in 80386
((OPTION_A)) INTA
((OPTION_B)) TF
((OPTION_C)) RF
((OPTION_D)) NMI
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
8
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) 80386 support ______number of interrupts.
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) 256
((OPTION_D)) 255
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Exceptions are generated by
((OPTION_A)) Internal events
((OPTION_B)) External events
((OPTION_D)) Hardware failures
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) These exceptions are detected and serviced before the executions of
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MP _U6 MCQ SAJ
Instructions
((OPTION_A)) Traps
((OPTION_B)) Faults
((OPTION_C)) Aborts
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) INT 2 interrupts belong to the_____
((OPTION_A)) Faults
((OPTION_B)) Traps
((OPTION_C)) Non maskable interrupts
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) INT 8 belongs to the___
((OPTION_A)) Traps
10
MP _U6 MCQ SAJ
((OPTION_B)) Aborts
((OPTION_C)) Faults
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
11
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The event such as illegal values comes under the category of _____
((OPTION_A)) Interrupt
((OPTION_B)) Trap
((OPTION_C)) Debug faults
((OPTION_D)) aborts
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) This event related to exception of type fault.
((OPTION_A)) Hardware error
((OPTION_B)) Segment overruns
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
12
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which exception generates page fault exception?
((OPTION_A)) Exception 9
((OPTION_B)) Exception 11
((OPTION_C)) Exception 14
((OPTION_D)) Exception 15
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Non maskable interrupts assigned at vector number
((OPTION_A)) 1
((OPTION_B)) 2
((OPTION_C)) 3
((OPTION_D)) 5
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) This instruction needs to be executed to find old state of machine

13
MP _U6 MCQ SAJ
((OPTION_A)) RET
((OPTION_B)) IRET
((OPTION_C)) INT
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDT contain ____number of gate descriptors.
((OPTION_A)) 1024
((OPTION_B)) 512
((OPTION_C)) 256
((OPTION_D)) 255
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) For storing the information about segments how many bytes are needed in
Descriptor table?
((OPTION_A)) 6
14
MP _U6 MCQ SAJ
((OPTION_B)) 7
((OPTION_C)) 8
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The size of GDT table is____
((OPTION_A)) 1 GB
((OPTION_B)) 1024 KB
((OPTION_C)) 64 KB
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) One GDT can contain many
((OPTION_A)) GDT
((OPTION_B)) IDT
((OPTION_C)) GATE
15
MP _U6 MCQ SAJ
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The descriptor which is not used in IDT is
((OPTION_A)) Trap gate descriptor
((OPTION_B)) Interrupt gate descriptor
((OPTION_C)) Task gate descriptor
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
16
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Trap gate descriptor defined in_____
((OPTION_A)) LDT
((OPTION_B)) IDT
((OPTION_C)) TASK
((OPTION_D)) GDT
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The first 16 bits from LSB in trap gate defines
((OPTION_A)) Base address
((OPTION_B)) Limit
((OPTION_C)) Segment selector
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Exception 11 or 14 generated, when

17
MP _U6 MCQ SAJ
((OPTION_A)) P bit marked present
((OPTION_B)) P bit not marked present
((OPTION_C)) P bit marked reserved
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The size of segment selector in interrupt gates is
((OPTION_A)) 20 bits
((OPTION_B)) 16 bits
((OPTION_C)) 32 bits
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Upon execution of IRET instruction,
((OPTION_A)) EFLAGs will be reset
((OPTION_B)) EFLAGs will be set

18
MP _U6 MCQ SAJ
((OPTION_C)) EFLAGs will be popped from stack
((OPTION_D)) A or B
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) When IF flag cleared in interrupt gate descriptor, then
((OPTION_A)) 80386 POP status of EFLAG
((OPTION_B)) 80386 returns to the main program
((OPTION_C)) 80386 masks further hardware initiated interrupts
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which is not the type of IDT descriptors?
((OPTION_A)) Trap gates
((OPTION_B)) System gates
((OPTION_C)) Task gates
((OPTION_D)) Interrupt gate

19
MP _U6 MCQ SAJ
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which gate gives information regarding privilege level violation exception
((OPTION_A)) Trap
((OPTION_B)) Task
((OPTION_C)) IDT
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
20
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is true about microcontroller?

((OPTION_A)) A microcontroller is a small and low-cost microcomputer
((OPTION_B)) It is designed to perform the specific tasks of embedded

systems
((OPTION_C)) Microcontroller consists of the processor, the memory, Serial

ports, peripherals.
((OPTION_D)) All of the above

((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
21
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) For serial Communication Microcontroller needs separate IC to be attached externally
((OPTION_A)) Some times
((OPTION_B)) NO, it has inbuilt facility
((OPTION_C)) Yes
((OPTION_D)) Nothing is correct
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
22
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which instruction used to access interrupt descriptor table?
((OPTION_A)) LGDT
((OPTION_B)) IIDT
((OPTION_C)) SIDT
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Microcontroller is not suitable for ------------------------.
((OPTION_A)) Light sensing and controlling device
((OPTION_B)) Temperature sensing and controlling device
((OPTION_C)) Industrial Instrumentation Device
((OPTION_D)) Extensive Data Processing
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
23
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) The processor sets the ____ bit if an event external to the program caused
((OPTION_A)) RST
((OPTION_B)) EXT
((OPTION_C)) ERR
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The processor sets the ____if the index portion of the error code refers to a
gate descriptor in the lOT.
((OPTION_A)) P bit
((OPTION_B)) I-bit
((OPTION_C)) X bit
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
24
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Microcontrollers can be used for -----------
((OPTION_A)) Light sensing and controlling device
((OPTION_B)) Temperature sensing and controlling device
((OPTION_C)) Industrial Instrumentation Device
((OPTION_D)) All of the mentioned
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Interrupt 4- occurs after execution of ______instruction
((OPTION_A)) INTO
((OPTION_B)) OF
((OPTION_C)) IF
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Bounds Check fault when occurs generates_____

25
MP _U6 MCQ SAJ
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupt 7 generated means error is
((OPTION_A)) Invalid Opcode
((OPTION_B)) Double Fault
((OPTION_C)) Coprocessor Not Available
((OPTION_D)) None of these
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Coprocessor Not Available exception generates when
((OPTION_A)) The processor encounters an ESC (escape) instruction, and the EM

(emulate) bit of
CRO (control register zero) is set.
26
MP _U6 MCQ SAJ
((OPTION_B)) The processor encounters either the WAIT instruction or an ESC

instruction and both
the MP (monitor coprocessor) and TS (task switched) bits of CRO are set.
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which register usually store the output generated by ALU in several
arithmetic and logical operations?
((OPTION_A)) accumulator
((OPTION_B)) Special function Register
((OPTION_C)) Timer Register
((OPTION_D)) Stack Pointer
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
27
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which is not the class of double fault exception?
((OPTION_A)) benign exceptions
((OPTION_B)) contributory exceptions
((OPTION_C)) page faults
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The error code is always___, when processor pushes error code onto stack
Of double fault handler.
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) Undefined
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
28
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) If any other exception occurs while attempting to invoke the double-fault
handler___
((OPTION_A)) The processor restarted
((OPTION_B)) The processor shuts down.
((OPTION_C)) Processor restarts execution of instruction
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is the most appropriate criterion for choosing the right
((OPTION_A)) speed
((OPTION_B)) availability
((OPTION_C)) ease with the product

((OPTION_D)) all of the mentioned
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
29
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Why microcontrollers are not called general purpose computers?

((OPTION_A)) because they have built in RAM and ROM
((OPTION_B)) because they design to perform dedicated task
((OPTION_C)) because they are cheap
((OPTION_D)) because they consume low power

((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) When Contributory double fault exception 12 generates means the error is,
((OPTION_A)) Invalid TSS
((OPTION_B)) Stack exception
((OPTION_C)) Page fault
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
30
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) When Contributory double fault exception 14 generates means the error is,
((OPTION_A)) Invalid TSS
((OPTION_B)) Stack exception
((OPTION_C)) Page fault
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupt ___occurs if during a task switch the new TSS is invalid
((OPTION_A)) 7
((OPTION_B)) 8
((OPTION_C)) 10
((OPTION_D)) 14
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
31
MP _U6 MCQ SAJ
((QUESTION)) A microcontroller at-least should consist of:

((OPTION_A)) RAM, ROM, I/O ports and timers
((OPTION_B)) CPU, RAM, I/O ports and timers
((OPTION_C)) CPU, RAM, ROM, I/O ports and timers
((OPTION_D)) CPU, ROM, I/O ports and timers

((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) This error code CS id + EXT not indicates condition______
((OPTION_A)) Stack segment selector RPL < > CPL
((OPTION_B)) Stack segment selector is outside table limit
((OPTION_C)) Code segment selector is not outside table limit
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
32
MP _U6 MCQ SAJ
((QUESTION)) Exception ____occurs when the processor detects that the present bit of a
zero.
((OPTION_A)) 10
((OPTION_B)) 11
((OPTION_C)) 12
((OPTION_D)) 13
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) If we say microcontroller is 8-bit then here 8-bit denotes size
((OPTION_A)) ALU
((OPTION_B)) Size of data bus
((OPTION_C)) Size of control bus
((OPTION_D)) Size of address bus
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
33
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupt 11, generated when
((OPTION_A)) Segment not present
((OPTION_B)) Invalid segment
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The processor generates exception 11, because processor
((OPTION_A)) Attempting to load the CS
((OPTION_B)) Attempting to load the DS
((OPTION_C)) Attempting to load the ES
((OPTION_D)) All of these
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
34
MP _U6 MCQ SAJ
((QUESTION)) Unlike microprocessors, microcontrollers make use of batteries
((OPTION_A)) high power dissipation
((OPTION_B)) low power consumption
((OPTION_C)) low voltage consumption
((OPTION_D)) low current consumption

((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The EXT bit of the error code is set if
((OPTION_A)) an event internal to the program caused an interrupt
((OPTION_B)) an event external to the program caused an interrupt
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
35
MP _U6 MCQ SAJ
36
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION))
((OPTION_A))
((OPTION_B))
((OPTION_C))
((OPTION_D))
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) I-bit is set if
((OPTION_A)) if the error code refers to an IDT entry
((OPTION_B)) if the error code refers to an IDTR
((OPTION_C)) if the error code refers to an GDT entry
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
37
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which exception generated by the processor to implement virtual

memory at the segment level
((OPTION_A)) Segment invalid
((OPTION_B)) Segment not defined
((OPTION_C)) Segment not present
((OPTION_D)) Both B or C
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
38
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) A stack fault occurs; by using the instructions
((OPTION_A)) ADD
((OPTION_B)) LEAVE
((OPTION_C)) INC
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
39
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) A stack fault occurs due to the instruction
((OPTION_A)) PUSH
((OPTION_B)) POP
((OPTION_C)) Enter
((OPTION_D)) All of the above
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
40
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) MOV AX, [BP+6]). ENTER causes this stack fault due to
((OPTION_A)) Stack is empty
((OPTION_B)) Stack in small
((OPTION_C)) Memory is not initialized
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
41
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) This instruction is not going to cause stack fault
((OPTION_A)) LSS
((OPTION_B)) MOV
((OPTION_C)) POP
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
42
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which is not the cause of exception 13?
((OPTION_A)) Exceeding segment limit when using CS, DS, ES, FS, or GS
((OPTION_B)) Exceeding segment limit when referencing a descriptor table
((OPTION_C)) Transferring control to a segment that is not executable
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
43
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Loading eRO with PG= 1 and PE=O, generates exception__
((OPTION_A)) 10
((OPTION_B)) 11
((OPTION_C)) 12
((OPTION_D)) 13
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
44
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Writing into a read-only data segment or into a code segment; generates
((OPTION_A)) General Protection Exception
((OPTION_B)) Stack Exception
((OPTION_C)) Segment Not Present
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
45
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Page fault refers to exception
((OPTION_A)) 12
((OPTION_B)) 13
((OPTION_C)) 14
((OPTION_D)) 15
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
46
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Page fault exception occurs when
((OPTION_A)) PG=1
((OPTION_B)) PG=0
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
47
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) processor detects following condition while translating a linear address to
address
((OPTION_A)) The page-directory or page-table entry needed for the address translation
has zero in its
present bit
((OPTION_B)) The current procedure does not have sufficient privilege to access the
indicated page.
((OPTION_D)) B only
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
48
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) In page fault error code tells the exception handler
((OPTION_A)) Whether the exception was due to a not present page or to an access rights
violation.
((OPTION_B)) Whether the processor was executing at user or supervisor level at the time
of the
exception
((OPTION_C)) Whether the memory access that caused the exception was a read or write.
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
49
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The processor stores in____ the linear address used in the access that
caused page fault exception
((OPTION_A)) CR0
((OPTION_B)) CR1
((OPTION_C)) CR2
((OPTION_D)) CR3
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
50
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Interrupt 16 is
((OPTION_A)) Device not available
((OPTION_B)) Device is missing
((OPTION_C)) Coprocessor Error
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
51
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The processor generates coprocessor error by receiving signal on____
((OPTION_A)) ERROR
((OPTION_B)) ERROR#
((OPTION_C)) NMI
((OPTION_D)) INTR
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The ERROR# pin on 80387 causes which fault___
((OPTION_A)) Data point error
((OPTION_B)) Floating point error
((OPTION_C)) Device not available
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
52
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The interrupt for which the processor has highest priority among all the
((OPTION_A)) Mouse interrupt
((OPTION_B)) keyboard interrupt
((OPTION_C)) NMI
((OPTION_D)) INT
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
53
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) In case of string instructions, the NMI interrupt will be served only after
((OPTION_A)) initialisation of string
((OPTION_B)) the occurrence of the interrupt
((OPTION_C)) complete string is manipulated
((OPTION_D)) execution of some part of the string
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
54
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The NMI pin should remain high for atleast
((OPTION_A)) 4 clock cycles
((OPTION_B)) 2 clock cycles
((OPTION_C)) 1 clock cycles
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
55
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The INTR signal can be masked by resetting the
((OPTION_A)) TRAP flag
((OPTION_B)) INTERRUPT flag
((OPTION_C)) MASK flag
((OPTION_D)) DIRECTION flag
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
56
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) For the INTR signal, to be responded to in the next instruction cycle, it
…….. in the last clock cycle of the current instruction
((OPTION_A)) high
((OPTION_B)) Low
((OPTION_C)) High or low
((OPTION_D)) Unchanged
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
57
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Once the processor responds to an INTR signal, the IF is automatically
((OPTION_A)) set
((OPTION_B)) reset
((OPTION_C)) High
((OPTION_D)) None of above
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
58
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Once the CPL is selected, it can be changed by
((OPTION_A)) HOLD
((OPTION_B)) transferring control using system descriptors
((OPTION_C)) transferring control using gate descriptors
((OPTION_D)) transferring control using interrupt descriptors
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
59
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The data segments defined in GDT (global descriptor table) and the LDT
criptor table) can be accessed by a task with
((OPTION_A)) privilege level 0
((OPTION_B)) privilege level 1
((OPTION_C)) privilege level 2
((OPTION_D)) privilege level 3
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
60
MP _U6 MCQ SAJ
((MARKS)) 2
(1/2/3...)
((QUESTION)) A task with privilege level 0, does not refer to all the lower level privilege
((OPTION_A)) GDT (global descriptor table)
((OPTION_B)) LDT (local descriptor table)
((OPTION_C)) IDT (interrupt descriptor table)
((OPTION_D)) None of the given
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
61
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The task requesting an access to a descriptor is allowed to access after
((OPTION_A)) type of descriptor
((OPTION_B)) privilege level
((OPTION_C)) type of descriptor and privilege level
((OPTION_D)) corresponding segment
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) A CALL instruction can reference only a code segment descriptor with
((OPTION_A)) DPL less privilege than CPL
((OPTION_B)) DPL equal privilege to CPL
((OPTION_C)) DPL greater privilege than CPL
((OPTION_D)) all of the mentioned
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
62
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The RPL of a selector that referred to the code descriptor must have
((OPTION_A)) less privilege than CPL
((OPTION_B)) greater privilege than CPL
((OPTION_C)) equal privilege than CPL
((OPTION_D)) any privilege regarding CPL
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
63
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) The instruction that refers to only code segment descriptors with DPL
equal to or less than the task CPL is
((OPTION_A)) CALL
((OPTION_B)) RET
((OPTION_C)) ESC
((OPTION_D)) RET & IRET
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
64
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) An exception is generated when
((OPTION_A)) privilege test is negative
((OPTION_B)) an improper segment is referenced
((OPTION_C)) referenced segment is not present in physical memory
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which of the following is a system segment register?
((OPTION_A)) GDTR
((OPTION_B)) LDTR
((OPTION_C)) IDTR
((OPTION_D)) None of above
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The registers that are together, known as system address registers are
65
MP _U6 MCQ SAJ
((OPTION_A)) GDTR and IDTR
((OPTION_B)) IDTR and LDTR
((OPTION_C)) TR and GDTR
((OPTION_D)) LDTR and TSR
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The descriptor table that the 80386 supports is
((OPTION_A)) GDT (Global descriptor table)
((OPTION_B)) IDT (Interrupt descriptor table)
((OPTION_C)) LDT (Local descriptor table)
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The RF is not automatically reset after the execution of
((OPTION_A)) IRET
((OPTION_B)) POPA
66
MP _U6 MCQ SAJ
((OPTION_C)) IRET and POPF
((OPTION_D)) IRET and PUSHF
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) During the instruction cycle of 80386, any debug fault can be ignored is
((OPTION_A)) VM flag is set
((OPTION_B)) VM flag is cleared
((OPTION_C)) RF is cleared
((OPTION_D)) RF is set
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) In protected mode of 80386, the VM flag is set by using
((OPTION_A)) IRET instruction
((OPTION_B)) task switch operation
((OPTION_C)) IRET instruction or task switch operation
((OPTION_D)) none of the mentioned

67
MP _U6 MCQ SAJ
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The gate descriptor contains the information of
((OPTION_A)) destination of control transfer
((OPTION_B)) stack manipulations
((OPTION_C)) privilege level
((OPTION_D)) All the mentioned
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The gate that is used to specify corresponding service routine is
((OPTION_A)) call gate and trap gate
((OPTION_B)) task gate and interrupt gate
((OPTION_C)) interrupt gate and trap gate
((OPTION_D)) task gate and trap gate
((CORRECT_C C
HOICE))
(A/B/C/D)
68
MP _U6 MCQ SAJ
((EXPLANATI
ON))
(OPTIONAL)
The gate that uses word count field is
((MARKS)) 1
(1/2/3...)
((QUESTION))
((OPTION_A))
((OPTION_B))
((OPTION_C))
((OPTION_D))
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION))
((OPTION_A))
((OPTION_B))
((OPTION_C))
((OPTION_D))
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
69
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION) Which pin is used to differentiate between memory and I/O

)
operations
((OPTION_A) M/IO#
)
((OPTION_B) IN
)
((OPTION_C) OUT
)
((OPTION_D) None of the above

)
((CORRECT_ A
CHOICE))
(A/B/C/D)
((EXPLANAT
ION))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) I/O instructions do not go through the segmentation and
paging unit
((OPTION_A)) Yes
((OPTION_B)) No
((OPTION_C)) Both A & B

70
MP _U6 MCQ SAJ
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IN and OUT instruction drives the 80386 M/IO# pin --------
((OPTION_A)) high
((OPTION_B)) low
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) From I/O port address which pins are used to select a
byte, word, double word of I/O data
((OPTION_A)) BL3# - BL0#

71
MP _U6 MCQ SAJ
((OPTION_B)) A2 and A1
((OPTION_C)) A1 and A0
((CORRECT_CH A
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) If memory mapped I/O is udes then number of I/O
locations can be upto -------------
((OPTION_A)) 4GB
((OPTION_B)) 2GB
((OPTION_C)) 1GB
((OPTION_D)) 8GB
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The I/O system is divided into how many banks?
((OPTION_A)) 1
72
MP _U6 MCQ SAJ
((OPTION_B)) 2
((OPTION_C)) 3
((OPTION_D)) 4
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The address range for memory bank is from ------- to -----------
((OPTION_A)) 0000 to FFFF
((OPTION_B)) 000 to FFF
((OPTION_C)) 00 to FF
((OPTION_D)) 0 to F
((CORRECT_CH A
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The address range for 80386 to 80387 is from ------- to -------
73
MP _U6 MCQ SAJ
((OPTION_B)) 800000F8 to 800000FF
((OPTION_C)) 8000 to 8FFF
((OPTION_D)) 8000 to 800F
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to copy data from port
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) OUTS
((OPTION_D)) OUT
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
74
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to input string from port
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) OUTS
((OPTION_D)) OUT
((CORRECT_CH B
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to output string to port
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) OUTS
((OPTION_D)) OUT
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
75
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to output to port
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) OUTS
((OPTION_D)) OUT
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to take input string from port as
Byte?
((OPTION_A)) INSB
((OPTION_B)) INSW
((OPTION_C)) INSD
((CORRECT_CH A
OICE)) (A/B/C/D)
76
MP _U6 MCQ SAJ
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
Word?
((OPTION_A)) INSB
((OPTION_B)) INSW
((OPTION_C)) INSD
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
Double Word?
((OPTION_A)) INSB
((OPTION_B)) INSW
((OPTION_C)) INSD

77
MP _U6 MCQ SAJ
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to output string to port as
Byte?
((OPTION_A)) OUTSB
((OPTION_B)) OUTSW
((OPTION_C)) OUTSD
((CORRECT_CH A
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
Word?
((OPTION_A)) OUTSB
78
MP _U6 MCQ SAJ
((OPTION_B)) OUTSW
((OPTION_C)) OUTSD
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
Double word?
((OPTION_A)) OUTSB
((OPTION_B)) OUTSW
((OPTION_C)) OUTSD
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
79
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) I/O protection can be achieved using ----------
((OPTION_A)) I/O privilege level
((OPTION_B)) I/O permission bitmap
((OPTION_C)) Both of these
((CORRECT_CH C
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which is not I/O sensitive instruction?
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) IOPL
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
80
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((OPTION_A)) OUT
((OPTION_B)) OUTS
((OPTION_C)) IOPL
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) CLI
((OPTION_B)) STI
((OPTION_C)) All of the above
((CORRECT_CH D
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
81
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which is/are I/O sensitive instruction?
((OPTION_A)) CLI
((OPTION_B)) STI
((OPTION_C)) All of the above
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is the condition for I/O instruction?
((OPTION_A)) CPL <= IOPL
((OPTION_B)) CPL < IOPL
((OPTION_C)) CPL > IOPL
((OPTION_D)) CPL = IOPL
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
82
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) If CPL > IOPL, then what will happen?
((OPTION_A)) instruction will be executed
((OPTION_B)) General protection violation exception
((OPTION_C)) None of these
((CORRECT_CH B
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which exception is generated if Code is not at PL0
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
83
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Where I/O persmission bitmap is Present?
((OPTION_A)) TSS top portion
((OPTION_B)) TSS bottom portion
((OPTION_C)) IOPL
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The size of I/O permission bitmap is
((OPTION_A)) Fixed
((OPTION_B)) Variable
((OPTION_C)) Both
((CORRECT_CH B
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
84
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is the address for bank 0 in I/O organization?
((OPTION_A)) 0000 to FFFC
((OPTION_B)) 0000 to F000
((OPTION_C)) 0000 to 9999
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which of the instruction is not used for input?
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) INS
((OPTION_D)) OUT
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
85
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) INS
((OPTION_D)) OUTS
((CORRECT_CH D
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) INS
((OPTION_D)) OUTSB
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
86
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) INS
((OPTION_D)) OUTSW
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) IN
((OPTION_B)) INS
((OPTION_C)) INS
((OPTION_D)) OUTSD
((CORRECT_CH D
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
87
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which of the instruction is not used for output?
((OPTION_A)) OUT
((OPTION_B)) OUTSB
((OPTION_C)) OUTS
((OPTION_D)) IN
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) OUT
((OPTION_B)) OUTSB
((OPTION_C)) OUTS
((OPTION_D)) INS
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
88
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((OPTION_A)) OUT
((OPTION_B)) OUTSB
((OPTION_C)) OUTS
((OPTION_D)) INSB
((CORRECT_CH D
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) OUT
((OPTION_B)) OUTSB
((OPTION_C)) OUTS
((OPTION_D)) INSW
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
89
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((OPTION_A)) OUT
((OPTION_B)) OUTSB
((OPTION_C)) OUTS
((OPTION_D)) INSD
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which fields are considered during I/O instructions?
((OPTION_A)) CPL
((OPTION_B)) IOPL
((CORRECT_CH C
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
90
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for IN instruction?
((OPTION_B)) CPL <= IOPL
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for INS instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
91
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for INSB instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for INSW instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
92
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for INSD instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((QUESTION)) 1
((OPTION_A)) Which condition is required for OUT instruction?
((OPTION_B)) CPL = IOPL
((OPTION_C)) CPL <= IOPL
((OPTION_D)) CPL > IOPL
((CORRECT_C None of these

HOICE))
(A/B/C/D)
((EXPLANATI B
ON))
(OPTIONAL)
93
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for OUTS instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for OUTSB instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
94
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for OUTSW instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is required for OUTSD instruction?
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
95
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for IN instruction?
((OPTION_B)) CPL < = IOPL
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for INS instruction?
((CORRECT_C C
HOICE))
(A/B/C/D)
96
MP _U6 MCQ SAJ
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for INSB instruction?
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for INSW instruction?

97
MP _U6 MCQ SAJ
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for INSD instruction?
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((QUESTION)) 1
((OPTION_A)) Which condition is generating exception for OUT
instruction?
((OPTION_B)) CPL = IOPL
((OPTION_C)) CPL <= IOPL
((OPTION_D)) CPL > IOPL

98
MP _U6 MCQ SAJ

HOICE))
(A/B/C/D)
((EXPLANATI C
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for OUTS
instruction?
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for OUTSB
instruction?

99
MP _U6 MCQ SAJ
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for OUTSW instruction?
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which condition is generating exception for OUTSD instruction?

100
MP _U6 MCQ SAJ
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IN and OUT instruction drives the 80386 M/IO# pin low
((OPTION_A)) True
((OPTION_B)) false
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IN and OUT instruction drives the 80386 M/IO# pin high
101
MP _U6 MCQ SAJ
((OPTION_A)) True
((OPTION_B)) false
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The address range for memory bank is from ------- to -----------
((OPTION_B)) 000A to FFFF
((OPTION_C)) 0001 to FFFE
((OPTION_D)) 0001 to 000F
((CORRECT_CH A
OICE)) (A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION) M/IO# pin is used to differentiate between memory and I/O

)
operations
102
MP _U6 MCQ SAJ
((OPTION_A) True
)
((OPTION_B) False
)
((OPTION_C) Both A & B

)
((OPTION_D) None of the above

)
((CORRECT_ A
CHOICE))
(A/B/C/D)
((EXPLANAT
ION))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) I/O instructions do not go through the segmentation and
paging unit
((OPTION_A)) True
((OPTION_B)) False
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
103
MP _U6 MCQ SAJ
((QUESTION)) CPL <= IOPL condition is required for IN instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for INS instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
104
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for INSB instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for INSW instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
105
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for INSD instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((QUESTION)) 1
((OPTION_A)) CPL <= IOPL condition is required for OUT instruction?
((OPTION_B)) No
((OPTION_C)) Yes
((OPTION_D)) Both A & B

HOICE))
(A/B/C/D)
((EXPLANATI B
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
106
MP _U6 MCQ SAJ
((QUESTION)) CPL <= IOPL condition is required for OUTS instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for OUTSB
instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
107
MP _U6 MCQ SAJ
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for OUTSW
instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) CPL <= IOPL condition is required for OUTSD
instruction?
((OPTION_A)) No
((OPTION_B)) Yes
((CORRECT_C B
HOICE))
(A/B/C/D)
108
MP _U6 MCQ SAJ
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is the size of IVT?
((OPTION_A)) 1K
((OPTION_B)) 2K
((OPTION_C)) 3K
((OPTION_D)) 4K
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is the byte size of single IVT entry?
((OPTION_A)) 1 byte
((OPTION_B)) 2 byte
((OPTION_C)) 3 byte
((OPTION_D)) 4 byte
((CORRECT_C D
HOICE))
(A/B/C/D)
109
MP _U6 MCQ SAJ
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What is pair is used to point IVT entry?
((OPTION_A)) CS:IP
((OPTION_B)) DS:IP
((OPTION_C)) ES:IP
((OPTION_D)) FS:IP
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) 8 bit vector is shifted by how many bits?
((OPTION_A)) 1 bit
((OPTION_B)) 2 bit
((OPTION_C)) 3 bit
((OPTION_D)) 4 bit
((CORRECT_C B
HOICE))
(A/B/C/D)
110
MP _U6 MCQ SAJ
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which table is used in protected mode for interrupts and exception?
((OPTION_A)) IDT
((OPTION_B)) LDT
((OPTION_C)) GDT
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The IDT comprises of 8 byte gate descriptor for task, trap or interrupt
gates
((OPTION_A)) True
((OPTION_B)) False

111
MP _U6 MCQ SAJ
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The IDT comprises of ------------ gate descriptor for task, trap or interrupt
gates
((OPTION_A)) 8 byte
((OPTION_B)) 4 byte
((OPTION_C)) 2 byte
((OPTION_D)) 1 byte
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The IDT comprises of 8 byte gate descriptor for -----------
((OPTION_A)) Task
((OPTION_B)) trap
((OPTION_C)) interrupt gates

112
MP _U6 MCQ SAJ
((OPTION_D)) all of the above
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The IDT has maximum size of ------ descriptors
((OPTION_A)) 255
((OPTION_B)) 256
((OPTION_C)) 257
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDTR stands for ---------------
((OPTION_A)) Interrupt Descriptor Table register
((OPTION_B)) Interrupt definition table register
((OPTION_C)) Interrupt default table register

113
MP _U6 MCQ SAJ
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDT stands for ---------------
((OPTION_A)) Interrupt Descriptor Table
((OPTION_B)) Interrupt definition table
((OPTION_C)) Interrupt default table
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDT contains -------
((OPTION_A)) Vectors
((OPTION_B)) Gate descriptors
((OPTION_C)) Gates
114
MP _U6 MCQ SAJ
((OPTION_D)) Tasks
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDTR register is how many bits?
((OPTION_A)) 32 bits
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Where IDT will reside?
((OPTION_A)) Anywhere in physical memory
((OPTION_B)) Anywhere in virtual memory

115
MP _U6 MCQ SAJ
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) If all 256 descriptor are not required the limit can be set to -----
((OPTION_A)) 7FF H
((OPTION_B)) FFF H
((OPTION_C)) 6FF H
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDTR consist of base address of ----
((OPTION_A)) 8 bits
116
MP _U6 MCQ SAJ
((OPTION_D)) 32 bits
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) IDTR consists of Limit size of ----
((OPTION_A)) 8 bits
((OPTION_D)) 32 bits
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to load interrupts?
((OPTION_A)) LLDT
((OPTION_B)) LGDT
((OPTION_C)) LIDT
117
MP _U6 MCQ SAJ
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which instruction is used to store interrupts?
((OPTION_A)) SLDT
((OPTION_B)) SGDT
((OPTION_C)) SIDT
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)

Microprocessor MCQ UNIT 6: MP - U6 MCQ Saj

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Microprocessor MCQ UNIT 6: MP - U6 MCQ Saj

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1

MP _U6 MCQ SAJ

((QUESTION)) This type of interrupts cannot be avoided by processor.

((OPTION_A)) Non Maskable

((OPTION_D)) All the above

((QUESTION)) Interrupts are the _______events

((OPTION_C)) Both A and B

((OPTION_D)) None of the above

((QUESTION)) In 80386, we can give interrupt to the machine by giving signals on

((OPTION_D)) Both A and B

((QUESTION)) Which interrupts used in critical condition?

((OPTION_B)) Single step

((OPTION_D)) All the above

((QUESTION)) The interrupt can be disabled by using instruction______

((QUESTION)) Interrupts can be of____

((OPTION_C)) Both A and B

((OPTION_D)) None of the above

((QUESTION)) Which is the following interrupt having lowest priority?

((OPTION_D)) Single step

((QUESTION)) Which is the interrupt having highest priority?

((OPTION_C)) Single Step

((QUESTION)) This ______masks NMI interrupt

((OPTION_D)) None of the above

((QUESTION)) If IF=0, then it will masks

((OPTION_A)) INTR interrupt

((OPTION_B)) NMI interrupt

((OPTION_D)) None of the above

((QUESTION)) STI and CLI instructions will be executed only when

((OPTION_A)) CPL = IOPL

((OPTION_B)) CPL >= IOPL

((OPTION_C)) CPL <IOPL

((OPTION_D)) Both A and C

((QUESTION)) This____will masks debug faults in 80386

((QUESTION)) 80386 support ______number of interrupts.

((QUESTION)) Exceptions are generated by

((OPTION_A)) Internal events

((OPTION_B)) External events

((OPTION_C)) Both A and B

((OPTION_D)) Hardware failures

((OPTION_D)) All the above

((QUESTION)) INT 2 interrupts belong to the_____

((OPTION_C)) Non maskable interrupts

((OPTION_D)) None of the above

((QUESTION)) INT 8 belongs to the___

((OPTION_D)) None of the above

((OPTION_C)) Debug faults

((QUESTION)) This event related to exception of type fault.

((OPTION_A)) Hardware error

((OPTION_B)) Segment overruns

((OPTION_C)) Both A and B

((OPTION_D)) None of the above

((QUESTION)) Which exception generates page fault exception?

((QUESTION)) Non maskable interrupts assigned at vector number

((QUESTION)) This instruction needs to be executed to find old state of machine

((OPTION_D)) All the above

((QUESTION)) IDT contain ____number of gate descriptors.

((OPTION_D)) None of the above

((QUESTION)) The size of GDT table is____

((OPTION_D)) None of the above

((QUESTION)) One GDT can contain many

((OPTION_D)) None of the above

((QUESTION)) The descriptor which is not used in IDT is