STOP WATCH, ALARM AND CLOCK TIMER

WITH SEVEN SEGMENT DISPLAY

INTERFACE

by

Atif Sadiq
BEE173111
Farakh Ali
BEE173096
Syed Hassham Ali
BEE173071

A Term Project Report submitted to the

DEPARTMENT OF ELECTRICAL ENGINEERING

Faculty of Engineering
Capital University of Science & Technology,
Islamabad
January, 2021
 ABSTRACT
This report is about the stop watch, clock and alarm with seven segment
display. Time is the most precious and valued thing in this universe. The only way to
succeed is to follow the time and the fundamental thing to follow time is to know what
exactly the time is. This is the main motivation for this project where a watch is
implemented on the FPGA using seven segment and VGA interface to provide user the
knowledge of the time while using the FPGA so that user can not only know the time
but also use that time in the algorithms as well.

In the literature, there are different techniques used to implement the watch on
FPGA but the limitation is that all the features of clock are not implemented in a single
product and the watch is not interfaced with the VGA so this develops the problem
statement of this project in which the watch is implemented using seven segment and
VGA interface and the features of stop watch, setting and resetting minutes, hours and
seconds are also included in this project
.
First of all, watch is implemented by incrementing seconds at the clock
frequency of 1Hz and then incrementing minutes after sixty seconds and then
incrementing hours after sixty minutes. Then the stop watch is implemented by
modifying the watch implemented before and at the end alarmtimer is implemented.
After the watch implementation, it is interfaced with the seven segments of FPGA. The
time on all the seven segments is shown simultaneously by operating seven segments
at the clock frequency of 500Hz. After the seven-segment interface, the time is
displayed on the monitor screen using VGA interface. For this purpose, a rom of digits
from 0 to 9 is defined which contains the binary image of those digits and on the basis
of the time, the image from the ROM is selected and displayed on the monitor screen.
As a result, the watch, stop watch and the alarm is displayed on the seven segments as
well as on the monitor screen using VGA interface. This project can be recommended
to the users who want to access the time while programming on the FPGA kit.

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 TABLE OF CONTENTS
ABSTRACT ................................................................................................................... 1
TABLE OF CONTENTS ............................................................................................... 2
LIST OF FIGURES ........................................................................................................ 3
Chapter 1 ......................................................................................................................... 4
INTRODUCTION .......................................................................................................... 4
1.1 Project Idea ............................................................................................................... 5
1.2 Purpose of the Project ......................................................................................... 5
1.3 Project Specifications ............................................................................................... 5
1.4 Applications of the Project ................................................................................. 5
1.5 Report Organization ............................................... Error! Bookmark not defined.
Chapter 2 ......................................................................................................................... 6
LITERATURE REVIEW ............................................................................................... 6
2.1 Background Theory .................................................................................................. 6
2.2 Related Technologies ............................................................................................... 7
2.2.1 Verilog ....................................................................................................... 7
2.2.3 Xilinx ISE .................................................................................................. 7
2.3 Related Projects ........................................................................................................ 7
2.3.1 Traffic Light Control.................................................................................. 7
2.4 Limitations and Bottlenecks of the Existing Work .................................................. 8
2.5 Problem Statement.................................................................................................... 8
2.6 Summary................................................................................................................... 8
Chapter 3 ......................................................................................................................... 9
PROJECT DESIGN AND IMPLEMENTATION ......................................................... 9
3.1 Proposed Design Methodology ................................................................................ 9
3.2 Details about Algorithms ........................................................................................ 12
3.2.1 Watch ....................................................................................................... 12
3.2.2 Stop Watch ............................................................................................... 12
3.2.4 Clock divider............................................................................................ 12
3.2.5 Seven Segment Interface.......................................................................... 13
3.2.6 VGA interface .......................................... Error! Bookmark not defined.
3.3 Implementation Procedure ...................................................................................... 14
3.4 Summary................................................................. Error! Bookmark not defined.
Chapter 4 ....................................................................................................................... 15

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PROJECT RESULTS AND EVALUATION .............................................................. 15
4.1 Presentation of the findings .................................................................................... 15
4.1.1 Software Results ...................................................................................... 15
4.1.2 Hardware Results ..................................................................................... 16
4.2 Discussion on the findings ...................................................................................... 17
4.3 Limitations of the working prototype ..................................................................... 17
4.4 Summary................................................................................................................. 17
Chapter 5 ....................................................................... Error! Bookmark not defined.
CONCLUSION AND FUTURE WORK ..................... Error! Bookmark not defined.

LIST OF FIGURES

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Figure 1 state diagram of traffic light controller .......................................................... 9
Figure 2 simulation results of traffic light controller .................................................... 9
Figure 3 Moor type FSM of the project ....................................................................... 12
Figure 4 clock division................................................................................................. 14
Figure 5 Block diagram for implementation ............................................................... 16
Figure 6 waveform of watch ........................................................................................ 17
Figure 7 waveform of stop watch................................................................................. 18

Chapter 1

INTRODUCTION

The idea of the time is provided by the natural phenomena such as day and night etc.
The more advanced form of knowing time is the watch but living in the programming
world dealing with the microcontrollers and FPGA how we get the idea of the time.

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This is a question which is answered by this project. A watch is implemented in the
FPGA which can be used to keep idea of the time in the programming environment.

1.1 Project Idea

The main idea of this project is to implement stop watch on the FPGA using the seven
segments and the VGA interface. In FPGA, sometimes the information of time
becomes necessary for controlling and scheduling different events which is provided
by this project. The watch is also extendable to the stop watch. The uniqueness of this
idea is that it is not only implemented on the FPGA but also on the monitor using
VGA interface which is relatively complex and tricky task.

1.2 Purpose of the Project

The main purpose of this project is to implement the knowledge of the verilog
programming to design a specific product which in this case is the stop watch which
has different features and functions and then to display the data on the seven segments
and monitor screen. The data in this project is the hours, minutes and the seconds of
the watch.

1.3 Project Specifications

Following are the specifications of this project:

• Watch which can be set to a specific time and reset as well.

• Stop watch which can be stopped at any specific instant, resumed as well as
reset.

• Displaying watch, stop watch and alarm with seven segments.

• Displaying watch, stop watch and alarm on monitor screen using 7 segment
interface.

1.4 Applications of the Project

This project can be used at any place where there is need to track the time of the day
or to record the time of a specific event or to alarmthe time left for an event to occur.

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In a specific situation this project can be recommended to the users who want to
access the time in programming while working on the FPGA kit.

Chapter 2

LITERATURE REVIEW
2.1 Background Theory
In this project, stopwatch and alarm clock are implemented. Normal clock can track
time of day whereas stopwatch can be used to time a specific event and alarm clock
with seven segment display. The project is implemented on FPGA. Seven segment

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and LCD with VGA interface are used to display the output while the software tool
used is Xilinx ISE. The seven-segment used in this project is an electronic display
device used to display decimal numbers whereas LCD is an electronic display and
VGA is standard type of connection for videos devices. Similarly, Xilinx ISE is
software tool which can be used to synthesize FPGA.

2.2 Related Technologies

Technologies used in this project are Verilog programming language, Spartan 3E
FPGA and Xilinx ISE.

2.2.1 Verilog
Verilog is Hardware Description Language (HDL) used to design, simulate and verify
complex VLSI circuits. Following are main features of Verilog:

 Multi-level of abstraction
 Support for describing concurrency
 Support for describing bit level variables and behavior

.
2.2.3 Xilinx ISE
Xilinx ISE design software is the industry´s only free, fully featured front-to-back end
FPGA design solution for Linux and Windows. Xilinx ISE can be used for FPGA
design, HDL synthesis, simulation and implementation.

2.3 Related Projects

Project which is closely related to this project is briefly discussed below:

2.3.1 Traffic Light Control

In this project, Traffic lights are controlled using a controller implemented on Spartan
3E FPGA and it is designed to control four signals on intersection of two roads. In this
project timers are used for transition among different signals. State diagram of
controller is shown below:

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 Figure 1 state diagram of traffic light controller

2.4 Limitations and Bottlenecks of the Existing Work

Firstly, the bottleneck of majority of existing projects is that watch, stop watch and
alarm clock, all of them are not yet implemented in one single project as a whole and
secondly, only seven segment or VGA interface is used to display time both of them
are not used at a same time for displaying the results.

2.5 Problem Statement

Problem statement of project is to “Design an FPGA based system in which watch,
stop watch and alarm clock all are implemented and results are shown on seven
segments”.

2.6 Summary
In start of chapter background theory of project is discussed. After that technologies
like Verilog, FPGA and Xilinx ISE are explained. Then related project which is
Traffic Light Controller is discussed and finally limitations of existing work and
Problem Statement of this project is described.
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Chapter 3

PROJECT DESIGN AND IMPLEMENTATION

This chapter discusses the design used to implement this project and achieve the
desired result. Also, this chapter include the detail of the state diagram which is
implemented to carry out this project.

3.1 Proposed Design Methodology

This section will discuss the method which is used to implement this project. The
project is divided in to different blocks with each block dedicated to achieve one of
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the desired goals set in the chapter one of the report. Switches are used as input to
choose the operation to be performed and on the different input combinations of the
switches, states of the state machine change. The finite state machine of the project is
shown below:

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 Figure 3 Moor type FSM of the project

There are four states in this project which are as below:

• Idle state

• Normal Watch

• Stop watch

• Alarm

On the reset and 00 input, output state is the idle state. When the input is 01, idle state
is changed in to normal watch and when input is 10 normal watch is changed to stop
watch and on 11 to alarm clock. Just like this other 2 states are working depending on
the input.

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3.2 Details about Algorithms
In this project, algorithms of different functional blocks are designed and
implemented which include the watch, stop watch and alarm clock with seven
segment display. The design details of each functional block are shown below:

3.2.1 Watch
This section will be discussing the watch which is basically functioning on the
principles of normal clock in which seconds positive edged triggered. The clock is
working on 10Hz clock. On the clock we can display maximum of 10 hours on one
seven segment that is 0 to 9 and 0 to 59 for minutes and 0 to 9 for the case of seconds.
Push buttons are used to set and reset the watch and toggle between the various
modes.

3.2.2 Stop Watch

This section will be discussing the stop watch which is also functioning on the
principle of normal clock in which seconds are incremented on every positive edge of
input clock of one hertz because in normal watch the frequency of seconds is one
hertz and minutes are incremented when seconds reaches 10 and in a similar fashion
hours are incremented when minutes reaches 60.
In this, user can start, stop and reset the clock by using push buttons. For this one push
button is used to start the stop watch and by pushing again that button, watch will be
stopped and then again pushing it will resume it from where it has been stopped.
Moreover, on reset watch will start from zero.

3.2.3 Clock divider

This section will be discussing the clock divider which is basically to slow down the
input clock coming from the FPGA. In Verilog it is implemented in behavioral level.
A divide factor depending upon the required clock is calculated then a counter is used
to count till that divide factor and as soon as the counter reaches the divide factor,
state of clock is inverted. Well, in this way a slower clock is generated for further use.
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 Figure 4 clock division

The above diagram shows two different clocks driven from the source clock on the
basis of different divide factors.
Similarly, the divide factor for the new clock is obtained by the relation given below:

X=

Divide factor = - 1

The above equation is used to calculate the divide factor. This module is used to
reduce the frequency from 50 MHz to 25MHz, 500 Hz and 1 Hz so that it can be used
in VGA, seven segment display and in normal clock respectively.

3.2.5 Seven Segment Interface

After the implementation of watch, stop watch and the step-down counter, the next
step is to show the results on the seven-segment display. The FPGA used in this
project has interface of four common anode seven segment displays whose anodes are
common with each other. The data lines of the four seven segments are also common
with each other. The refresh rate of one seven segment display is 60 Hz and since the
four seven segments are used simultaneously so the operating frequency of seven
segment displays should be greater than or equal to 240hz which is obtained by the
clock divider. At the frequency of 240 Hz or greater, the toggling of seven segment
displays are not detectable and it seems that all the four seven segments are on
simultaneously and displaying the data. So, a clock of 240 Hz or more is generated an
on the positive edge of that clock the seven segments are on and off in an alternative

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manner and data is sent to the seven segment displays. In this way, the data of the
watch and other modules is displayed on the seven segments.

3.3 Implementation Procedure

Now that the algorithms of the project are designed the next step is to implement the
designed algorithms and display the output on the seven segments and the monitor
screen. The block diagram for the implementation of the designed algorithm is shown
below:

Figure 5 Block diagram for implementation

The modules for the watch, stop watch and the alarm are implemented and the output
of these modules is provided to the binary to BCD converter which converts the
binary outputs of the modules to the binary coded decimals. Then the output of binary
to BCD is provided to the two different ROMs of the seven segments. The seven-
segment rom provides the seven-segment sequence according to the input provided to
it which is then fed to the seven segment and the results are displayed on the seven
segments.

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Chapter 4

PROJECT RESULTS AND EVALUATION

This chapter is all about the results of the project and then discussions on the findings
of the project. In this chapter the results of the algorithm design along with different
simulations and the hardware results are discussed in detail.

4.1 Presentation of the findings

This project has two different parts as far as the results are concerned. The first part
deals with the simulations of the project on the modelsim software then the second
part deals with the results on the hardware which is the FPGA board.

4.1.1 Software Results

There are two main functional blocks whose results are verified first in the simulations
and then in the hardware.

4.1.1.1 Watch
The module of the watch is first implemented on the model sim then after its
verification on the modelsim it is implemented on the FPGA board. The simulation
result of the model sim for the watch module is shown below:

Figure 6 waveform of watch

Here it can be seen that on every positive edge of the clock of 10 hertz the seconds are
implemented by one which is the behavior of a watch.

4.1.1.2 Stop watch

The module of the stop watch is first implemented on the model sim then after its
verification on the Modelsim it is implemented on the FPGA board. The simulation
result of the model sim for the stop watch module is shown below:

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 Figure 7 waveform of stop watch

Here it can be seen that on every positive edge of the clock of one hertz the seconds
are implemented by one and one the stop flag becomes high then the seconds retained
their value of 3 on the next positive edge of the clock which is the behavior of a stop
watch.

4.1.2 Hardware Results

After implementing the designed algorithms on modelsim, the next step was to
implement them on the FPGA board to get the results in the real time environment.
The watch, stop watch and the countdown timer are implemented on the FPGA and
the selection between them is made by the combination of two slide switches. Then
the results are shown on the seven segments as well as the monitor screen. Different
outputs of watch, stop watch and alarm on seven segment and the monitor are shown
here:

4.1.2.1 Results of watch

Below are the results of watch on the seven segments as well as on the monitor.

Then the results on the monitor screen are as follows:

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It can be seen that the results match with the designed algorithm and the watch is
behaving as expected.

4.2 Discussion on the findings

Overall, the results of the project are very similar to the proposed ones in the chapter
one. The selection of watch, stop watch and the alarm is controlled by the slide
switches and their results are simultaneously displayed on the seven segments display.

4.3 Limitations of the working prototype

Due to the restrictions in the working environment the display was only possible to be
done using the available 7 segments that were only 4. So in accordance with the
objectives set single digits were set for hours and seconds and double digits for
minutes .

4.4 Summary
In this chapter, the results of the different functional blocks of the project are
discussed along with the Modelsim simulations but no hardware due to the pandemic
closure. Overall, the results of the project are very similar to the proposed ones in the
one and the only limitation of this project is that the time is not as the standard one but
due to the restriction in 7 segments we are using hours and seconds from 0 to 9 while
the minutes are from 0 to 59.

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