2017 IEEE Electrical Power and Energy Conference (EPEC)
FPGA Implementation of a Phaselet Method for
High Speed Distance Relaying - Preliminary Results
Xingxing (Shane) Jin, Student Member, Ramakrishna (Rama) Gokaraju, Senior Member, Eli F. Pajuelo, Member, IEEE
Department of Electrical and Computer Engineering
University of Saskatchewan
Saskatoon, SK, Canada S7N 5A9
Abstract—Fault clearing time is critical to the safety of power
system equipment. Most state-of-art distance relays operate at
the speed of one cycle or even longer. There are a few sub-cycle
algorithms such as half-cycle type Fourier, least error square,
traveling wave, and wavelet type methods. This paper utilizes a
sub-cycle (phaselet) method for estimation. The algorithm and
testing with IEC 61850 Sampled Value and GOOSE communi-
cation protocols was discussed in detail in the recently accepted
paper by the authors in the IEEE Transactions on Smart Grids
[1]. The main focus of this paper is on the hardware imple-
mentation of the phaselet method on field programmable gate
arrays (FPGAs) to achieve high speed and the hardware-in-the-
loop testing. The FPGA implementation of the method helps in
parallelizing the algorithm and provides fast computation speed
compared to sequential execution on digital signal processor
(DSP). The algorithm is implemented on Xilinx Virtex 6 board.
The FPGA relay is tested using hardware-in-the-loop simulations
with a real time digital simulator (RTDS).
I. I NTRODUCTION
Fault clearing time is critical to the reliable operation of
power systems. During a short circuit in an EHV system, fault
current levels can reach 10 to 20 times normal current levels.
The protective relays for EHV systems must be able to detect
the fault very quickly, within a few milliseconds and send
a signal to the circuit breaker to prevent fault current levels
reaching dangerous proportions in the system. The presence
of such high speed relaying schemes also helps the utilities to
transmit more power on the system during normal steady-state
conditions. Most current digital relay implementations operate
at the speed of one cycle or even longer. These speeds are
slower than solid state relays whose operating times can vary
from a quarter cycle to a half cycle.
Digital filter technologies play an important role in digital
protection relaying schemes, especially the full cycle discrete
Fourier transform (FCDFT) algorithm. FCDFT requires one
full cycle of samples to obtain an accurate phasor estimation.
This is not fast enough for EHV systems in which the
decisions must be made in less than one cycle [2]. In the
literature, a few sub-cycle relaying methods are proposed in
[1], [2], [3], [4]. References [3], [4] suggested to use a half-
cycle DFT (HCDFT) to estimate the phasors to speed up the
relay operation compared to the FCDFT. However, the main
problem with HCDFT is that it rejects the even harmonic terms
and cannot filter out the decaying dc component. Reference [1]
discussed a variable filtering window method using phaselet
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equations to determine the magnitude and phase angle of a
phasor quantity. It combined the benefits of FCDFT (i.e. its
high accuracy) as well as HCDFT (ie to obtain high speed).
It also showed that a proper phase angle estimation is equally
important as the magnitude for accurate trip decision (near
boundary). Research on sub-cycle phaselets to determine the
magnitude of a phasor and offline testing results first appeared
in a conference paper in mid-1990’s [5], [6].
On the hardware side, there is a need for a new generation
of protective devices that equipped with advanced technologies
that make two-way digital communication possible where each
device has much higher computational capacity [7]. FPGA
technology provides the required level of performance and
capability as follows: 1) it exceeds the computing power of
digital signal processors (DSPs) by breaking the paradigm
of sequential execution. 2) it is field programmable silicon
chips. It is very cost-effective to incorporate future upgrade
to keep pace with power grid requirements without modifying
the board layout or replace the entire device. 3) large capacity
of computational resources and input/output (I/O) interfaces
enables convergence of multiple function devices into a single
IED, lowering the cost of smart grid systems as a whole.
Another trend is the increasing popularity of the Ethernet
based communication protocol: IEC 61850 [8]. It offers self-
descriptive object data models, standardized configurability
with Substation Configuration Language (SCL), full interop-
erations among IEDs from different manufacturers, and lower
integration costs. It is now becoming one of the essential
protocols for digital relays.
This paper presents the FPGA implementation of the phase-
let method. Fifteen states are extracted from the algorithm
and each state is composed of many arithmetic and logi-
cal operations. Each operation is carried out by dedicated
hardware units, running in parallel. This strategy accelerates
the calculations compared to DSP’s sequential processing
approach.
Also, this paper discusses hardware-in-the-loop testing us-
ing RTDSTM with IEC 61850 communication protocols [8]
as the input and output of the FPGA based phaselet relay.
This provides realistic performance of the proposed relay in a
digital substation environment using the IEC 61850 protocols
along with hardware-in-the-loop simulations.
 2017 IEEE Electrical Power and Energy Conference (EPEC)

Start

receive 1 new raw

Fault current waveform

during-fault data
variable windows
DC-offset removal
(mimic filter)

calculate phaselet

pre-fault full N Y
disturbance==1
cycle window

calculate full calculate varied

Sample index
cycle phasor window phasor

Fig. 1. Adaptive filtering window concept. N Y

Window==full
W ulll
cycle
TABLE I
S TANDARD D EVIATION & R EACH VALUES FOR VARIOUS W INDOW
L ENGTHS three phase Æ
disturbance=0
symmetrical sequence
w(cy) 0.45 0.5 0.6 0.7 0.8 0.9 1
σr (n) 22.9% 21.8% 20.3% 19% 17.7% 16.5% 15.6%
σθ (n) 13.4o 13.1o 12.6o 11.5o 10.2o 9.4o 9.2o Y disturbance N
reach 70.1% 72.4% 74.2% 74.7% 76.3% 78.4% 80.2% detector
(ANSI 50DD)

disturbance=1, disturbance=0,
II. P HASELET-BASED D ISTANCE P ROTECTIVE R ELAY window=size of phaselet window=full cycle

Phaselets are sectional integrals of products of the input calculate

sample values and the Fourier coefficients. They are added to
generate phasors over a set of linearly expanding windows,
as shown by the dashed line rectangles in Figure 1. Each
rectangle in the figure stands for a filtering window.
During steady state, the phaselets are combined across one
cycle and the window size is fixed to one cycle, resulting in an
equivalent to a FCDFT, as shown by the solid line rectangle in
Figure 1. After a disturbance is introduced, the filtering win-
dow is changed immediately to a phaselet size. Since all the
pre-fault samples are blocked by the filter, the estimated phasor
responds more directly to the change observed in voltage and
current measurements. As new samples become available, the
window size is expanded until it reaches one complete cycle,
as shown by the dashed line rectangles in Figure 1. Before
another new disturbance is identified, phaselets continue to be
summed to form a FCDFT in a recursive fashion.
The complete flow chart of the algorithm is shown in Figure
2. A mimic filter is used at the beginning to remove the
decaying dc offset component. A disturbance detector based
on symmetrical sequence calculations is used. The output of
the disturbance detector triggers the process of the adaptive
phasor estimation.
The estimation error is analyzed mathematically for various
filtering window sizes in [1]. Assuming that the relay inputs
have uncorrelated errors and error variances are constants, the
standard deviation values of the magnitude error, σr (n) and
phase angle error σθ (n), are shown in Table I. The adaptive
Mho characteristics is obtained by combining the magnitude
and phase angle errors in phasor domain [1]. The reach settings
are listed in the last row of Table I.
impedance
Mho
characteristic
decision
Return
Fig. 2. Adaptive filtering window concept.
III. H ARDWARE I MPLEMENTATION ON FPGA
The algorithm is implemented on FPGA and consists of
three components, as shown in Figure 3. The IEC 61850
interface implements the SV and GOOSE communication
protocols as the input and output of the FPGA relay, as shown
in Figure 5. SV packages from the RTDS are taken by this
module and the extracted current and voltage measurements
are then fed into the distance element. The distance element
is the core of the design. It calculates the fault impedance
and determines the trip logic. Trip signals from the distance
element are packed in GOOSE format and sent out through
this module as well. The structure of a SV packet is also shown
in Figure 5.
The state machine is the global control component of the
entire design. It determines the specific operation at any given
moment based on the status of the distance element and the
condition of I/O. These three modules will be discussed in
detail in the following sections.

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 2017 IEEE Electrical Power and Energy Conference (EPEC)

Start of Frame Destination Source Length/

Preamble Ethertype VLAN Tag Data (SV) Pad FCS
Delimiter(0xD5) Address Address Type
RTDS
FPGA
V6EMAC

Rx FIFO

Interface
Decoder

Receive
GOOSE

SV

GMII PHY
SV

Interface
FPGA

Embedded Ethernet MAC

Transmit
Interface
Tx FIFO
GOOSE
Encoder
IEC 61850 Communication Interface Distance
IOBs PHY
Element

Ia,b,c,n , Va,b,c,n

Configurations
Trip

Control &

Counters
Statistics
Interrupt
Mimic Filter IEC 61850
Communication
Interface
State Machine

Adaptive Phasor Estimation

Disturbance
Detector
I(N), I(N+1)...
V(N), V(N+1)...
Fig. 5. FPGA layout of the IEC 61850 interface.
3 Phases to Symmetrical Components

Impedance Calculation
this work, a Xilinx LogiCORE Virtex-6 Embedded Tri-Mode
Adaptive Mho Characteristics Ethernet Media Access Controller (V6EMAC) [9] is included
Distance Element as part of the IEC 61850 communication interface as shown in
Figure 5. The incoming SV packets arrive in physical sublay-
ers (PHY) through either copper medium or fiber optics. The
Fig. 3. Overall architecture of the proposed distance relaying scheme.
packets are then forwarded to the input/output banks (IOBs)
of the FPGA chip. The PHY interface provides the logic to
interface the data streams between the IOBs and the Embedded
Ethernet MAC, which contains the key blocks such as flow
SV GOOSE TimeSync
Application

control, transmit engine, receive engine, configurations access,

Layer

etc. The SV frames are buffered at Rx FIFO. Current and

Specific Communication Service Mapping (SCSM) voltage measurements are then extracted by the SV decoder
to feed the distance element. On the other side, trip signals
UDP/IP are inserted into the data field of a GOOSE frame and sent
Communication

out through V6EMAC.

Layers

ISO/IEC 8802-3 Ethertype
ISO/IEC 8802-3
Fig. 4. IEC 61850 SV and GOOSE protocol stack.
A. IEC 61850 Communication Interfaces
IEC 61850 defines the communications between devices
in the substations and the system requirements. Figure 4
shows the overall protocol profiles. Specific Communication
Service Mapping (SCSM) provides detailed instructions and
specifications as to the mechanisms and rules required to
implement the applications. SV is the application that encodes
four phase currents and four phase voltages into a multicast or
unicast Ethernet packet. GOOSE is a controlled application in
which various formats of data are grouped into a data set and
embedded into Ethernet data packets. In this paper, the dataset
only includes trip signals. Different from other applications,
SV and GOOSE are directly connected to the data link layer
through ISO/IEC 8802-3 Ethertype, which provides context
for interpretation of the data field of an Ethernet data frame.
This direct configuration minimizes the communication delay.
Ethernet has been widely used in computer networks since
1980s and Ethernet Intelligent Property (IP) solutions are
available for FPGA. Considering Xilinx FPGA is used through
Preamble contains an alternating pattern of ones and zeros
to synchronize the incoming packet with the physical layer.
Start of Frame is an 8-bit value (0xD5) indicating the start
of a frame. Ethertype equals 0x88BA for SV and 0x88B8 for
GOOSE. Virtual local area network (VLAN) tags specify the
IDs of virtual LANs and their priority. Pad contains extra data
(if necessary) to make up the frame length to its minimum
size. Frame check sequence (FCS) is used to check for any
damaged frames. GOOSE packet has a similar format but has
different and flexible specifications for data fields to accept
user-defined data.
B. Distance Element & State Machine Diagram
The phaselet-based algorithm is mapped to the distance
element module of the FPGA. Fifteen internal states are
extracted from the algorithm, as shown in Figure 6. These
states are precisely controlled by a state machine, which is
used to model a system that transits among a finite number
of internal states [10]. The transitions depend on the current
state and the external triggering events. In this work, the state
machine serves as the global control of the entire design. It
determines the specific operation at any given moment based
on the status of the distance element and the condition of
V6EMAC. Figure 6 demonstrates these fifteen states of the
design, as well as the allowable transitions between them
and the corresponding triggering conditions. Once a new SV

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 2017 IEEE Electrical Power and Energy Conference (EPEC)

GOOSE
14: Encode
sent
TABLE II
Trip to
GOOSE FPGA H ARDWARE U SAGE
Packet SV packet ready
Trip == 1
New packet
starts
0: Idle Hardware Slice Registers Slice LUTs DSP Blocks
Voltage &
11:
Disturbance
ready 1:Decode
current ready Available 301440 150720 768
13: Mho
Disturbance SV Packet
Detector Usage 149,279(49.5%) 111,258(73.8%) 526(68.5%)
Impedance
Symmetrical ready 2: Byte to Voltage & current in
12: New packet
components starts
Floating floating point format ready
ready Impedance Point
TABLE III
W == N 5: Save M AIN T EST PARAMETERS
7: First 3: Mimic
10: abc2pn0 Phaselet
Phasor Filter
Element
Phasor Filtering output
ready W == P ready Parameter Value
Sample index %
Phasor
8: Various
P != 0 4: Phaselet Sampling rate 80 samples per cycle
Window 6: Phaselet
ready Element
Phasor Phaselet size 4 (samples)
P<W<N
Phasor
ready Sample index % P == 0
Disturbance detector cutoff setting 2%
9: Full
Window Fault resistance 0.01 Ω
Phasor W == N

Fig. 6. State machine representation: FPGA-based distance relay.

AC

packet is ready at the RX FIFO, it leaves Idle state and

starts to extract the current and voltage measurements. Because
SV
the data are transmitted in integer format according to IEC
GTNET-SV
61850 standards, it is desirable to convert to floating point
format to achieve a higher accuracy through the calculation.
GOOSE
After the data conversion, the mimic filter is applied and the
filtering outputs form phaselet elements. If the sample index
RTDS GTNET-GSE
is not a multiple of the phaselet size P , the phaselet elements
are saved for the next phaselet calculation. Otherwise, P
phaselet elements compose one phaselet and then enter into the
phasor calculation stage. Three options are available based on SV
GOOSE Ethernet Switch
the size of the current window W , as shown in the figure. FPGA

Importantly, the variable window phasors and full window

Fig. 7. IEC 61850-based IED development platform.
phasors are all calculated in a recursive way to minimize
computation. Once phasors are obtained, a three phase to
Bus 1 200 km Bus 2
symmetrical components transformation is needed to calculate
apparent impedance. Moreover, if W =N (one full cycle), Zs
the disturbance detector is enabled to provide system status Es
P+jQ
information to the next iteration’s adaptive phasor estimation.
Adaptive Mho characteristics then decide if a system fault FPGA
Relay
happened. If yes, a trip signal is initiated and encoded to
a GOOSE packet. The Tx FIFO transmits the packet to
V6EMAC, which then further sends it out to the RTDS. If Fig. 8. 400 kV power system used for testing.
not, then it waits until a new SV packet arrives.
Table II lists the main FPGA hardware resources utilization
4,800 Hz. Two Gigabit Transceiver Network Interface (GT-
of the complete design. The amount of available resources for
NET) cards [12] are configured to realize the IEC 61850 SV
the Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA chip are
and GOOSE protocols.
also listed [11]. Around 50-70% of the hardware is occupied
Inside the FPGA, V6EMAC runs at a data rate of 100
and additional protective elements can be further added to
Mb/s, which is much higher than the bandwidth of two
enable more functionality. The FPGA can finish processing
IEDs. The main clock is 125 MHz. The secondary clock
one SV packet in 4.04 μs, which is much shorter than the
(12.5 MHz) is generated to interface with the PHY device
sampling step of 208 μs.
(12.5 MHz×8 bits/s = 100 Mb/s). The synthesize tool is Xilinx
IV. R ESULTS ISE Design Suite Version 14.7.
Figure 8 shows the 400 kV power system under consid-
A. Hardware-in-the-Loop Testing Platform eration. The generator source impedance is Zs = 5.781 +
Figure 7 shows the IED test platform developed to eval- j52.025 Ω. The load is P = 400 M W , Q = 50 M V ar. Other
uate the proposed FPGA relay. The RTDS sampling rate is settings used in the test are summarized in Table III.

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 2017 IEEE Electrical Power and Energy Conference (EPEC)
(a) Operating times (cycles) for l-g faults
(b) Operating times (cycles) for l-l faults
(c) Operating times (cycles) for 3-phase faults
Fig. 9. Operation times for different distance relays.
B. Operating Time
Figure 9 shows the operating times for various fault sce-
narios. The speed for relay A [13] and relay B [14] are also
presented according to their data sheet. Relay A uses short-
window orthogonal filters [13], whereas relay B uses HCDFT.
The speed of the phaselet method is faster than other
methods. For close-in faults, the operating times are similar.
For remote end fault, the FPGA relay can operate between 0.7-
0.8 cycles. This is also faster than a recent work of FCDFT-
based FPGA relay [7]: the operation speed is 1.4 cycles, 1.3
cycles and 1.3 cycles for l-g, l-l and 3-phase faults respectively
when faults applied at 50% of the reach setting.
C. Relay Reliability
A reliable relay has two attributes: dependability and secu-
rity. The proposed relay is dependable since it always trips
for the faults within the reach setting. In terms of security,
we applied faults at the remote terminal bus with source
impedance ratio equals to 10. The probability of incorrect
trips are listed in Table IV. FCDFT has the lowest incorrect
tripping rate due to the longer one cycle filter. Phaselet has
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TABLE IV
I NCORRECT T RIPPING P ROBABILITY WITH SIR=10
Phaselet - not include
Fault type FCDFT Phaselet
phase angle error
l-g 5% 33% 6%
l-l 0% 9% 0%
3-phase 0% 0% 0%
full security for l-l and 3-phase faults, but has a 6% possibility
to incorrectly trip for a l-g fault. If the phase angle errors are
not considered, the incorrect trip rate increases to 33% and
9% for l-g and l-l faults respectively. This indicates that phase
angle errors are important to assure the trip reliability for the
phaselet method.
V. C ONCLUSION
The FPGA implementation of the high speed distance relay
using phaselets are presented. The relay is tested using an
RTDS simulator. The latest digital substation communication
protocols (IEC 61850 SV and GOOSE) are used to verify the
realistic performance of the relay. The need for power ampli-
fiers and analog interfaces is not necessary with these Ethernet
based communication. The operating speed is between 0.6 to
0.8 cycles, which is faster than other state-of-the-art relaying
methods. The relay is fully dependable and is secure as well.
ACKNOWLEDGMENTS
The authors would like to thank Mr. Rudi Wierckx and
Dr. Om Nayak for the valuable feedback they have provided
on the research carried out in this paper.
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