Embedded Hardware Design - (EL-203)

Project Report on Dadda Multiplier

Submitted to: Professor Biswajit Mishra

Submitted by: Ayush Gupta (201701046)

INDEX

● Abstract
● Introduction
● Design and Implementation
● VHDL Code
● Result
● References

Abstract

Multipliers are an important part of many high-performance systems, including filters,

microprocessors, and so on. Since the multiplier is usually the slowest factor in the
system, the output of a system is largely determined by the performance of its
multipliers. It's also the one that takes up the most room. As a result, maximising the
multiplier's speed and region is a significant design consideration.Dadda multipliers take
up less space and work better than Wallace multipliers. As a result, the emphasis of this
report is on the design of these multipliers.

Introduction

In 1965, computer scientist Luigi Dadda invented the Dadda multiplier, a hardware
multiplier design. It's similar to the Wallace multiplier, but it's faster (for all operand
sizes) and uses fewer gates (for all but the smallest operand sizes).
They try to keep the number of gates and the input/output delay to a minimum. Dadda
multipliers have a less costly reduction step as a result of this, but the final numbers
may be a few bits longer, necessitating slightly bigger adders.

Architecture

There are three stages to the Dadda multiplier architecture. The first stage involves
using Baugh-complement Wooely's two’s complement array multiplication algorithm to
generate partial products. Unlike traditional two's complement multiplication, which
produces both positive and negative bits, the signs of all partial product bits are all
positive. After the reduction, the final product is also in two's complement shape. The
partial product arrangement for an 8x8 multiplier is shown in the diagram below, with
dots representing partial products.

In the second step, Dadda's column compression technique is used to minimise the
partial product matrix to a height of two. The following is an iterative method for doing
so:
● Let h1=2 and repeat hj+1= floor (1.5*hj) for increasing values of j. COntinue this
 until the largest j is reached, for which there exists at least one column in the
present stage of the matrix with more dots than hj. Using this equation we get
h1=2, h2=3, h3=4, h4=6, h5=9 and so on. For example in the first stage of the 8x8
Dadda multiplier max height of the columns is 8 therefore the value of h jis 6
meaning heights of the column are reduced to a maximum of 6. Similarly when
height of column is 6 and value of hjis 4 height is reduced to a maximum of 4.

● All the columns with height greater than hj, are reduced to a height of hj using
either half adder or full adder. If height is to be reduced by 1 use half adder else
use full adder.

● Stop the reduction if the height of the matrix becomes two.

VHDL Code

library ieee;
use ieee.std_logic_1164.all;

package dadda_utils is
function and_8b(b: std_logic; word: std_logic_vector) return std_logic_vector;
function sum_2b(a: std_logic; b: std_logic) return std_logic;
function sum_3b(a: std_logic; b: std_logic; c: std_logic) return std_logic;
function carry_2b(a: std_logic; b: std_logic) return std_logic;
function carry_3b(a: std_logic; b: std_logic; c: std_logic) return std_logic;
end;

package body dadda_utils is

function and_8b(b: std_logic; word: std_logic_vector) return std_logic_vector is
variable res: srd_logic_vector(7 downto 0);
begin
for i in 0 to 7 loop
res(i) :=word(i) and b;
end loop;
return res;
end function;
function sum_2b(a: std_logic; b: std_logic) return std_logic is
begin
return a xor b;
end;
function sum_3b(a: std_logic; b: std_logic; c: std_logic) return std_logic is
begin
return a xor b xor c;
end;

function carry_2b(a: std_logic; b: std_logic) return std_logic is

Begin
return a and b;
end;

function carry_3b(a: std_logic; b: std_logic; c: std_logic) return std_logic is

begin
return (a and b) or (a and c) or (b and c);
end;

end package body;

Result

Result after multiplying two 8 bit numbers in VHDL is shown below:

References:
● www.wikipedia.com
● www.xilinx.com
● https://www.ijert.org/research/asic-implementation-of-dadda-multiplier-IJERTV8IS
070198.pdf
● Circuit Design using VHDL by Pedroni