CHAPTER 3: THYRISTORS

Prepared By: SANDEEP KUMAR K

ASSISTANT PROFESSOR
DEPARTMENT OF MECHATRONICS
ACHARYA INSTITUTE OF TECHNOLOGY
Introduction
 Thyristor is the most important type of power
semiconductor devices.
 They are extensively used in power electronic
circuits.
 They are operated as bi-stable switches from
non-conducting to conducting state.
 A Thyristor is a four layer, semiconductor of p-n-p-
n structure with three p-n junctions. It has three
terminals, the anode, cathode and the gate.
 The word Thyristor is coined from Thyratron and
transistor. It was invented in the year 1957 at Bell
Labs.
SILICON CONTROLLED RECTIFIER
(SCR)
Gate Cathode

+
n
19
10
-3
cm
+
n
19
10 cm
-3
 10m


J3 - 17 -3
p 10 cm 30-100m


J2
–
n
13
10 -5 x 10
14
cm
-3 50-1000m

J1
p
+
17
10 cm
-3
 30-50m
19 -3
p 10 cm

Anode
QUALITATIVE ANALYSIS
 When the anode is made positive with respect the
cathode junctions j1 and j3 are forward biased
and junction j2 is reverse biased.
 With anode to cathode voltage being small, only
leakage current flows through the device. The
SCR is then said to be in the forward blocking
state.
 If VAK is further increased to a large value, the
reverse biased junction will breakdown due to
avalanche effect resulting in a large current
through the device.
 The voltage at which this phenomenon occurs is
called the forward breakdown voltage (VBO)
 Once the SCR is switched on, the voltage drop
across it is very small, typically 1 to 1.5V.
V-I Characteristics of SCR
Effects on gate current on forward
blocking voltage
LATCHING CURRENT (IL)
After the SCR has switched on, there is a
minimum current required to sustain conduction
even if the gate supply is removed. This current is
called the latching current. associated with turn
on and is usually greater than holding current.
HOLDING CURRENT (IH)
After an SCR has been switched to the on state
a certain minimum value of anode current is
required to maintain the Thyristor in ON state. If
the anode current is reduced below the critical
holding current value, the Thyristor cannot
maintain the current through it and turns OFF.
QUANTITATIVE ANALYSIS
TWO TRANSISTOR MODEL
Derivation for anode current
General transistor equation is
IC= αIE + ICBO
For transistor 1

IC1= α1IE1+ ICBO1 ; IE1 = IA

There fore IC1= α1IA+ ICBO1 --------- Eq 1
For transistor 2

IC2= α2IE2+ ICBO2 ; IE2 = IK and IK = IA + IG

There fore IC2= α2(IA + IG )+ ICBO2 ------ Eq 2
IA= IC1 + IC2
IA=α1IA+ ICBO1 + α2(IA + IG )+ ICBO2

 I C2  I B1
 2 I g  I CBO1  I CBO 2
 IA 
1  1   2 
THYRISTOR TURN ON

Thyristor is turned ON by increasing the

Anode current,
this can be accomplished by one of the
following ways
 Thermal Turn on or High Temperature
Triggering
 Light Triggering
 High Voltage Triggering
 dv/dt Triggering
 Gate Triggering
Thermal Turn on or High
Temperature
 The width of depletion layer of SCR decreases
with increase in junction temperature.
 Therefore in SCR when VAR is very near its
breakdown voltage, the device is triggered by
increasing the junction temperature.
 By increasing the junction temperature the
reverse biased junction collapses thus the device
starts to conduct.
 This type of turn on many cause thermal run
away and is usually avoided.
 Light Triggering
 For light triggered SCRs a special
terminal is made inside the inner P layer
instead of gate terminal.
 When light is allowed to strike this
terminal, free charge carriers are
generated.
 When intensity of light becomes more
than a normal value, the Thyristor starts
conducting.
 This type of SCRs are called as LASCR
High Voltage Triggering

 In this mode, an additional forward voltage is applied

between anode and cathode.
 When the anode terminal is positive with respect to
cathode(VAK) , Junction J1 and J3 is forward biased
and junction J2 is reverse biased.
 No current flows due to depletion region in J2 is
reverse biased (except leakage current).
 As VAK is further increased, at a voltage VBO (Forward
Break Over Voltage) the junction J2 undergoes
avalanche breakdown and so a current flows and the
device tends to turn ON(even when gate is open)
 This type of turn on is destructive and should be
avoided.
 dv/dt Triggering
 When the device is forward biased, J1 and J3 are
forward biased, J2 is reverse biased.
 Junction J2 behaves as a capacitor, due to the
charges existing across the junction.
 If voltage across the device is V, the charge by Q
and capacitance by C then,
ic = dQ/dt
Q = CV
ic = d(CV) / dt
= C. dV/dt + V. dC/dt
as dC/dt = 0
ic = C.dV/dt
 Therefore when the rate of change of voltage
across the device becomes large, the device may
turn ON, even if the voltage across the device is
small.
 A high value of charging current may damage the
Thyristor and the device must be protected
against high .
 The manufacturers will specify the allowable .
Gate Triggering
 This is most widely used SCR triggering method.
 Applying a positive voltage between gate and
cathode can Turn ON a forward biased Thyristor.
 When a positive voltage is applied at the gate
terminal, charge carriers are injected in the inner
P-layer, thereby reducing the depletion layer
thickness.
 As the applied voltage increases, the carrier
injection increases, therefore the voltage at which
forward break-over occurs decreases
 Three types of signals are
used for gate triggering.
1. DC gate triggering
2. AC Gate Triggering
3. Pulse Gate Triggering
DC gate triggering

 A DC voltage of proper polarity is applied

between gate and cathode ( Gate terminal
is positive with respect to Cathode).
 When applied voltage is sufficient to
produce the required gate Current, the
device starts conducting.
 One drawback of this scheme is that both
power and control circuits are DC and
there is no isolation between the two.
 Another disadvantages is that a continuous
DC signal has to be applied. So gate
power loss is high.
AC Gate Triggering:-

 Here AC source is used for gate

signals.
 This scheme provides proper isolation
between power and control circuit.
 Drawback of this scheme is that a
separate transformer is required to
step down ac supply.
 There are two methods of AC voltage
triggering namely (i) R Triggering (ii)
3. Pulse Gate Triggering

 In this method the gate drive consists of

a single pulse appearing periodically (or)
a sequence of high frequency pulses.
 This is known as carrier frequency
gating.
 A pulse transformer is used for
isolation.
 The main advantage is that there is no
need of applying continuous signals, so
the gate losses are reduced.
SWITCHING CHARACTERISTICS (DYNAMIC
CHARACTERISTICS)
THYRISTOR TURN-ON CHARACTERISTICS
di/dt protection
 A Thyristor requires minimum time to
spread the current conduction uniformly
through out the junctions.
 If the rate of rise of Anode current is very
fast compared to the spreading velocity of
turn on process, HOTSPOT heating will
occur and device may fail due to excessive
temperature.
 The Thyristor can be protected from
excessive di/dt by connecting inductor in
di/dt protection

di VS

dt LS
dv/dt protection
 The dv/dt across the Thyristor is limited by using
snubber circuit as shown in figure (a) below. If
switch is closed at t=0 , the rate of rise of
voltage across the Thyristor is limited by the
capacitor . When Thyristor is turned on, the
discharge current of the capacitor is limited by the
resistor as shown in figure (b) below.

Fig. (a)
Fig. (b)
 The voltage across the Thyristor will rise
exponentially as shown in fig above.
1
VS  i  t  RS   i  t  dt  Vc  0  for t 0
C
Assuming Vc(0)=0
Now applying Laplace transform

OR

Now applying Inverse Laplace transform we get

Where  s  RS CS
GATE TRIGGERING METHODS

The different methods of gate triggering are the

following

 R-triggering.
 RC triggering.
 UJT triggering.
RESISTANCE TRIGGERING
vO
a b
LOAD

i R1

R2
vS=Vmsint
D VT

R Vg
 A simple resistance triggering circuit is as shown.

 The resistor R1 limits the current through the

gate of the SCR. R2 is the variable resistance
added to the circuit to achieve control over the
triggering angle of SCR.

 Resistor ‘R’ is a stabilizing resistor. The diode D is

required to ensure that no negative voltage
reaches the gate of the SCR.
VS VS VS
Vmsint

3 4 3 4 3 4
 2 t  2 t  2 t

Vg Vgt Vg Vg Vgp>Vgt
Vgp=Vgt

Vgp Vgp Vgt t t t

Vo Vo Vo

t t t
io io io

t 0 t t
270
VT VT VT

3 4
t  2 t t
 0 0
0 =90 <90
90

(a) (b) (c)

Design
V
 With , R2=0 we need to ensure that I
m
gm
I, gm
where
R 1
is the V
R1  m
I gm
maximum Ror peak gate current of the SCR.
2 0
Therefore
Vgm
 Also with , we
Vgm need
Vm R to ensure that the
R1  R ‘R’ does not exceed ,
voltage drop across resistor
the maximum  gate R1  Vgm R  Vm R
Vgmvoltage
 Vgm R1  R Vm  Vgm 
Vgm R1
R
Vm  Vgm
RESISTANCE CAPACITANCE
TRIGGERING
vO

LOAD
+
R
D2 VT

-
vS=Vmsint
D1
VC C
 Capacitor ‘C’ in the circuit is connected to shift the
phase of the gate voltage.
 Diode D1 is used to prevent negative voltage from
reaching the gate cathode of SCR.
 In the negative half cycle, the capacitor charges to
the peak negative voltage of the supply (-Vm)
through the diode D2 .
 The capacitor maintains this voltage across it, till
the supply voltage crosses zero. As the supply
becomes positive, the capacitor charges through
resistor ‘R’ from initial voltage of (-Vm) , to a
positive value.
 When the capacitor voltage is equal to the gate
trigger voltage of the SCR, the SCR is fired and the
capacitor voltage is clamped to a small positive
Waveform
Vmsint Vmsint
vs vs
V gt Vgt

-/2 0 -/2 0
0 t 0 t
vc vc
vc vc
a a a a
vo   vo
Vm Vm
0
   t  t
vT vT

Vm
  0  t
-Vm t  
 -Vm
(2+)

(a) (b)
Case 1: R  Large.
 When the resistor ‘R’ is large, the time taken for the
capacitance to charge from (-Vm) to Vgt is large,
resulting in larger firing angle and lower load voltage.
 Case 2: R  Small
When ‘R’ is set to a smaller value, the capacitor
charges at a faster rate towards Vgt resulting in early
triggering of SCR and hence VL is more.
When the SCR triggers, the voltage drop across it
falls to 1 – 1.5V. This in turn lowers, the voltage
across R & C. Low voltage across the SCR during
conduction period keeps the capacitor discharge
during the positive half cycle.
RC FULL WAVE
vO

LOAD
+
+
D1 D3 R
VT

vd -

C
vS=Vmsint
D4 D2
-
 Waveform
vs Vmsint vs Vmsint

t t

vd
vd vd

vc vc vgt vc t vgt t
vo vo
  

t t
vT vT

t
(a) (b)
 UNI-JUNCTION TRANSISTOR (UJT)
B2 B2

Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie VBB

- -
B1 B1 B1
(a) (b) (c)
 UJT is an n-type silicon bar in which p-type
emitter is embedded. It has three terminals
base1, base2 and emitter ‘E’.
 Between B1 and B2 UJT behaves like ordinary
resistor and the internal resistances are given as
RB1 and RB2 with emitter open RBB=RB1+RB2 .
 When VBB is applied across B1 and B2 , we find
that potential at A is
VBB RB1  RB1 
VAB1   VBB   
RB1  RB 2  RB1  RB2 
 is intrinsic stand off ratio of UJT and ranges
between 0.51 and 0.82. Resistor RB2 is between 5
Negative Resistance
to 10K. Region
V
Cutoff e Saturation
region region
VBB
R load line
Vp
Peak Point

Valley Point

Vv

0 Ip Iv Ie
UJT RELAXATION OSCILLATOR

 UJT is highly efficient switch. The switching times

is in the range of nanoseconds. Since UJT
exhibits negative resistance characteristics it can
be used as relaxation oscillator.
 The circuit diagram is as shown with R1 and R2
being small compared V to RB1
Capacitor
charging
V and
e
+V RB2 of UJT.
Capacitor
discharging
BB
VBB T2=R1C
Vp
R R2
B2 VP
E T1=RC Vv
VV

T t
C B1
Ve R1 v
o Vo
1


t
(a) (b)
SYNCHRONIZED UJT
OSCILLATOR

R1
+ +

i1 R R2
D1 D3
B2
Pulse Transf
+ E
Vdc Z VZ
B1 G1
C1 To SCR
vc C Gates
G2
D4 D2
C2
- - -
 DIGITAL FIRING CIRCUIT
A A
Preset
(’N’ no. of counting bits)
Logic circuit
Clk B +
Fixed frequency max G1
n-bit Flip - Flop Modulator
Oscillator
Counter min S (F / F) B +
(ff) G2
Driver stage
En R
Reset Reset
Load

fC y(’1’ or ‘0’)
Sync Carrier
Signal (~6V) Frequency
ZCD Oscillator
C (  10KHz)
D.C. 5V
supply

A A