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Digital System Design with PLDs and FPGAs

Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese

Your Idea or Expectation 2

• What is your idea of this course?

• Why are you learning this course?
• What do you think should be taught?

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Course Objective 3

• Digital Systems Design

– Specifications to Implementation
– Algorithm to Architecture (Front end design)
– Partitioning, Design of blocks, Timing Analysis
– Device Technology: PLD, FPGA
– Design entry: VHDL
– Case studies (Communications, Embedded Systems,
Computer Architecture)
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Pre-requisite 4

• Digital Systems
– Boolean Algebra, Minimization
– Gates, Combinational Logic
– Flip-flops, Registers, Counters
– Timing
– CMOS circuits
• Basics of Micro-processors
• Basics of Computer Architecture
• Basics of Communication Networks
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Course Contents 5

• Advanced Digital Design

– Top-down Design, Data path, Controllers, Timing, …
• Programmable Logic Devices (PLD’s)
– Architecture, Applications, Optimal Design, …
• Field Programmable Gate Arrays (FPGAs)
– Architecture, Applications, Optimal Design, …
• VHDL (VHSIC-Hardware Description Language)
– VHDL for Synthesis
• Case Studies
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At the end of the course … 6

System Level
• Given a set of specifications for a digital system,
you will be able to design the system meeting the
specifications.
• In particular, given an algorithm you will be able
to design the datapath and the controller(s) to
implement the functionality.

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At the end of the course … 7

Digital Systems
• You will be able to design the datapath using
higher level combinational and sequential blocks.
• You will be able to solve the functional and timing
problems in the datapath.
• You will be able to resolve various issues related
to the controller design.
• You will be able to resolve synchronization issues.
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At the end of the course … 8

VHDL
• You will be able to write a VHDL code to implement a
particular design/block.
• You will be able to analyze a VHDL code and infer what
circuit a synthesis tool might generate out of a code.
• You will know how the VHDL simulation tool simulates the
code.
• You will be able to write test benches to automate the
verification process.

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At the end of the course … 9

PLDs
• You will be able to choose a particular PLD for a
particular application.
• You will be able to design and code to exploit the
architectural features of PLD

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At the end of the course … 10

FPGAs
• You will be able to choose a particular FPGA for a
particular application.
• You will be able to use FPGAs in your design,
meeting the area and delay constraints and estimate
the power consumption.
• You will be able to design and code to exploit the
architectural features of FPGA.
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Exercises 11

• Suggest Exercises for you to work

• Exercises covers various aspects covered in course,
deal with concepts
• Mini Project
• Use PLD, FPGA Free Tools from Xilinx, Altera,
Atmel, Lattice etc.
• If possible, try to work on PLD/FPGA kits
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References 12

• John F Wakerly, Digital Design: Principles and

Practices, Prentice Hall
• Kevin Skahil, VHDL For Programmable Logic,
Addison Wesley.
• Zainalabedin Navabi, VHDL. Analysis and
Modelling of Digital Systems, McGraw-Hill
• Neil H E Weste, David Harris, Ayan Banerjee,
CMOS VLSI Design, Pearson Education.
• Papers, FPGA Data sheets
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Digital System Design with PLDs and FPGAs

Overview

Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese

Hierarchy 14

• Learning
– Bottom up
– Transistor => Gates => Combinational => Sequential =>
Computing Blocks/Controllers => System
• Design
– Top down
– Processor => ALU, Reg, … =>
– ALU => Adder, Sub
– Adder => Gates => Transistors
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Learning: Level 0 - MOS Transistors 15

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Learning: Level 1 - Gates 16

A B Q
0 0 0
0 1 0
1 0 0
1 1 1

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Learning: Level 2 - Full Adder 17

A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Learning: Level 3 - Adder 18

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Learning: Level 4 - Multiplier 19

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Design: Top Down 20

Level 0 Level 1

Level 2 Level 3 Level 4

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Digital Design: Major Constituents 21

• Function / Logic
• Combinational
– Boolean Algebra, Minimization, Functions, Gates,
Encoders, Decoders, Multiplexers, Demultiplexers,
Parity circuits, Comparators, Priority encoders, Open-
drain outputs, and Tri-state outputs, Schmitt-trigger
inputs, Adders, Subtractors, Incrementer, Decrementer,
…

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Major Constituents: Functionality / Logic 22

• Sequential
– Flip-Flops, Latches
– Counters, Registers, Shift Registers
– Finite State Machines (FSM)
– ROM, EPROM, EEPROM
– SRAM, SSRAM
– DRAM, SDRAM
– FIFO
– CAM
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Minimization 23

• Karnaugh Maps
– Graphical tool, for humas
• Quine-McCluskey (QM)
– Minimal solution, Complexity
• Espresso
– Heuristic based on QM, Faster
– Near minimal solution

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Minimization 24

• Multi-Level minimization
– Decomposition (in to multiple terms)
– Extraction of common sub-expressions of multiple
outputs
– Factoring
– Substitution
– Flattening

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Functions and Gates: AND 25

A B Y A, B and Y Active High

0 0 0
A Y
0 1 0 B
1 0 0
1 1 1 A, B and Y Active Low
A B Y
A Y
0 0 0 B
0 1 0
1 0 0 Y=AB
1 1 1 Y/ = A/ + B/ De Morgan’s Theorem

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Functions and Gates: AND 26

• AND Gate – AND, and OR Functions

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Functions and Gates: NAND 27

A B Y A, B Active High and

0 0 1 Y Active Low - AND
0 1 1 A
Y
1 0 1 B
1 1 0
A B Y A, B Active Low, Y Active High
- OR
0 0 1
0 1 1 A
Y
1 0 1 B

1 1 0
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Functions and Gates: NAND 28

A B Y
Invert
0 0 1
A Y
0 1 1
1 0 1 NAND – Universal Gate
1 1 0 AND, OR and Invert functions

NAND Gate – AND, OR, and Invert Functions

AND Gate – AND and OR Functions
NOR Gate – AND, OR, and Invert Functions
OR Gate – AND and OR Functions
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Functions and Gates 29

AND - OR

NAND - NAND

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Functions and Gates 30

Y = (A/ + B/) C/
A
B
Y
C

A
B
Y
C

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Encoder 31

• In a binary encoder, distinct inputs are coded in to binary

outputs (e.g. 8 inputs are encoded to 3 binary bits).
Implementation uses OR gates
• When we assign priority to inputs, then the encoder is
called priority encoder
I0
I1 O2
O1
O0
I7

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Encoder 32

• An encoder can encode some input code to another

code but, the number of output bits will be less
than input bits

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Decoder 33

• In a binary decoder, binary inputs are decoded to produce

distinct outputs (e.g. 3 bit binary number is decoded to
produce 8 distinct outputs). Implementation uses AND gates
• A general decoder can convert a code to another code and
number of bits in input will be less than the number of bits
in the output
O0
O1
I2
I1
I0
O7

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Tri-State Gates 34

EN • 0, 1, Z (High Impedance)
A Y • Multiplexing
• Buses

EN/
A Y
EN

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Multiplexer 35

0 1 2 3
B
Y
C
D

sel

• 4 to 1 Mux (1 bit), 4 AND gates of 1+2 inputs, an OR gate

of 4 inputs
• 2n to 1 Mux (1 bit), 2n AND gates of 1+n inputs, and an OR
gate of 2n inputs

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De-Multiplexer 36

W
3 2 1 0

A X
Y
Z

sel

• 1 to 4 De-Mux (1 bit), 4 AND gates of 1+2 inputs

• 1 to 2n De-Mux (1 bit), 2n AND gates of 1+n inputs

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Multiplexer / De-multiplexer 37

A A

3 2 1 0
0 1 2 3
B B
C C
D D

sel sel

• Text book Picture

• Real Systems
– May not be symmetrical or ordered
– You may not see a explicit de-multiplexers
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Latch / Flip Flop 38

Latch Flip-Flop
D Q D Q

CK CK

CLK

QL

QD

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Major Constituents: Timing 39

• Combinational Circuits
– tpd: Propagation delay
– tPLH: tpd when output switches from L to H
– tPHL: tpd when output switches from H to L

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Flip-Flop Timing 40

D Q ts: Setup time: Minimum time

input must be valid before the
active clock edge
CK

th: Hold time: Minimum time

input must be valid after the
CLK
active clock edge
D ts
th tco: Propagation delay for
input to appear at the output
Q
from active
tco clock edge

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Major Constituents: Timing 41

5 ns 5 ns 5 ns 5 ns
A B

Static-0 Hazard
A

B Static-1 Hazard
OR Gate
Y A: 1 0

50 55 60 65 70 t ns Model

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Timing: Static-0 Hazard Real Life 42

Interconnect / Logic delay

A
B Y
C

C: 1, B: 0 1, A: 1 0

• Unbalanced path delay, Switching / glitches at Y

• May not be problem in synchronous sequential circuits
• Power dissipation

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Dynamic Hazard 43

A 10 ns
Y 0 1 0 5 ns
Z 1 0 1 0

5 ns X 1 0

45 50 55 60 65 t ns

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Electrical Characteristics 44

• Voltages, Currents, Power dissipation

• VOH, VOL, IOH, IOL
• VIH, VIL, IIH, IIL VOH = VDD – IOH * RON
VDD
VOHmin @ IOHmax
IOH

VOL = IOL * RON

IOL

VOLmax @ IOLmax
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Electrical Characteristics 45

Fanout
VOHmin Min (IOHmax /IIHmax ,
NMH
VIHmin IOLmax/IILmax)
VILmax
VOLmax NML
Power Dissipation
PD = C * V2DD * f

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Low Power Design 46

• PD = C * V2DD * f

• Transistor Level (Feature size)

• Circuit Level (e.g. Balanced Path delay)
• System level (Power down, Clock freeze)
• Architecture
• Algorithms
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High Frequency Designs 47

• Transmission Lines
• Reflections
• Cross talk
• Ground loops
• Back end Tools

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Device Technology 48

• Full Custom (ASIC)

– High NRE Cost, High Volume
– Large Turn around time
– Custom design from scratch
– Use of library cells
• Semi Custom (Mask Programmable / Standard Cell)
– Design in terms of standard blocks
– Medium NRE Cost, Medium Volume
– Medium Turn around time

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Device Technology 49

• Field Programmable (FPGA)

– Low NRE Cost, Low-Medium Volume
– Low Turn around time

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VLSI Technology 50

• PMOS is getting faster (hole mobility)

• Strained silicon
• Current Feature Size 22 nm (Intel Core i3, i5, i7)
• Future Feature Size 14 nm
• Inverter Delay 5-7 ps

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Design Methodology 51

• Front-end design
– Specifications => Gate and Flip-flop Net list
– Algorithm => Architecture => Circuit
• Back-end design
– Gate and Flip-flop Net list => Chip Masks
– Circuit => Transistor Level Circuit => Chip masks
– Circuit => Configuration pattern (FPGA)

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Design Methodology 52

• Data Path (Registers, Combinational)

• Controller(s) (FSM’s)
• Metric, Constraints: Area, Delay, Power

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Sequential Circuits: Data Path 53

FF Comb FF

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Controller: Finite State Machine 54

Next Present
State State
Inputs
NSL FF OL Outputs

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System on Chip / Intellectual Property 55

• System on Board System on Chip

– Embedded System on Chip
– Reduced power dissipation
– Reduced chip interconnects
– Reduced device size
• Programmable System on Chip
– ASIC Domain FPGA Domain

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SoC (Typical) 56

• One ore more processor cores

– Control, Communication, DSP
• Number of peripherals
– Timer, I/O’s, Memory controllers, UART, USB, …
• On-Chip Bus Architecture
• Network Interfaces
• Custom Hardware
– Codec's, Packet processing, Signal processing etc.
• Firmware
– RTOS, Protocol stacks, Application software

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Intellectual Property (Digital Hardware) 57

• Soft IP
– HDL Design
• Firm IP
– Synthesized Circuit
• Hard IP
– Place and Routed IP

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Dynamic / Runtime Reconfiguration 58

• FPGA / ASIC
• A part of the Device is reprogrammed to implement a
different functionality
• Other part may or may not be used
• Saves area, power and achieve lower delay
• Reconfiguration time is important
• Granularity is important
• Flexibility is important

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System Modeling 59

• Architecture Exploration, Performance Modeling, High

level Synthesis
• Hardware-Software partitioning
– Cost-performance trade-offs
• Hardware: Concurrent, Higher performance, Higher cost
• Software: Sequential, Lower performance, More flexible
• SystemC
• SystemVerilog: Verification
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Application Areas 60

• Communication Networks
– Physical layer (Mixed-mode design)
– Data link layer (Digital, Mostly in hardware, control in OS
Drivers)
– Network layer (Processing in Hardware for Network elements
like Switches and Routers)
• Signal Processing
– Filters, Codecs, Compression, etc.
• Computer Architecture
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