LG 42PJ250-SA Chassis PB02A

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
PLASMA TV
SERVICE MANUAL
CHASSIS : PB02A
MODEL : 42PJ250 42PJ250-SA

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL63140201(1004-REV00) Printed in Korea

CONTENTS
CONTENTS ............................................................................................................................... 2
SAFETY PRECAUTIONS ...........................................................................................................3
SPECIFICATION.........................................................................................................................4
ADJUSTMENT INSTRUCTION ..................................................................................................8
BLOCK DIAGRAM ...................................................................................................................15
EXPLODED VIEW ...................................................................................................................16
SVC. SHEET ................................................................................................................................
Copyright ©2010 LG Electronics Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in
the Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to
prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the Do not use a line Isolation Transformer during this check.
servicing of a receiver whose chassis is not isolated from the AC Connect 1.5 K/10watt resistor in parallel with a 0.15 uF capacitor
power line. Use a transformer of adequate power rating as this between a known good earth ground (Water Pipe, Conduit, etc.)
protects the technician from accidents resulting in personal injury and the exposed metallic parts.
from electrical shocks. Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
It will also protect the receiver and it's components from being Reverse plug the AC cord into the AC outlet and repeat AC
damaged by accidental shorts of the circuitry that may be voltage measurements for each exposed metallic part. Any
inadvertently introduced during the service operation. voltage measured must not exceed 0.75 volt RMS which is
corresponds to 0.5 mA.
If any fuse (or Fusible Resistor) in this monitor is blown, replace it In case any measurement is out of the limits specified, there is
with the specified. possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
When replacing a high wattage resistor (Oxide Metal Film
Resistor, over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts. Leakage Current Hot Check circuit
Due to high vacuum and large surface area of picture tube, AC Volt-meter
extreme care should be used in handling the Picture Tube.
Do not lift the Picture tube by it's Neck.
Good Earth Ground

Leakage Current Cold Check(Antenna Cold Check) such as WATER PIPE,
With the instrument AC plug removed from AC source, connect To Instrument's CONDUIT etc.
0.15uF
an electrical jumper across the two AC plug prongs. Place the exposed
AC switch in the on position, connect one lead of ohm-meter to METALLIC PARTS
the AC plug prongs tied together and touch other ohm-meter
lead in turn to each exposed metallic parts such as antenna
terminals, phone jacks, etc. 1.5 Kohm/10W
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATIONS
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application Range
(1) This spec sheet is applied all of PDP TV with PB02A chassis.
Model Name Market Brand

42PJ250-SA Brazil LG
2. Specification
Each part is tested as below without special appointment.
(1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 °C ± 5 °C
(2) Relative Humidity : 65 % ± 10 %
(3) Power Voltage : Standard input voltage (100 V - 240 V ~ 50 / 60 Hz)
* Standard Voltage of each product is marked by models
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test Method
(1) Performance : LGE TV test method followed.
(2) Demanded other specification
Safety : UL, CSA, IEC specification, CE
EMC : FCC, ICES, IEC specification, CE
Model Name Market Appliance

42PJ250-SA Brazil Safety : IEC/EN60065
4. General Specification
No Item Specification Remark
1. Receiving System 1) SBTVD / NTSC / PAL-M / PAL-N
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 07-69 (VHF high/UHF)
4) CATV : 02~135
3. Input Voltage 1)AC 100 ~ 240V 50/60Hz
4. Market BRAZIL
5. Screen Size 127 cm (50 inch) Wide(1365 X 768) 50PJ350-SA, 50PJ250-SA
106 cm (42 inch) Wide(1024 X 768) 42PJ350-SA, 42PJ250-SA
42PJ230-SB
6. Aspect Ratio 16:9
7. Tuning System FS
8. Module PDP50T1#### (1365 X 768) 50PJ350-SA, 50PJ250-SA
PDP42T1#### (1024 X 768) 42PJ350-SA, 42PJ250-SA
42PJ230-SB
9. Operating Environment 1) Temp : 0 deg ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1)Temp : -20 deg ~ 60 deg
2) Humidity : 0 ~ 90 %
5. Component Input (Y, CB/PB, CR/PR)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.50 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 67.50 60 148.50 HDTV 1080P
10. 1920*1080 67.432 59.94 148.352 HDTV 1080P
11. 1920*1080 27.00 24.00 74.25 HDTV 1080P
12. 1920*1080 26.97 23.976 74.176 HDTV 1080P
13. 1920*1080 33.75 30.00 74.25 HDTV 1080P
14. 1920*1080 33.71 29.97 74.176 HDTV 1080P
6. RGB Input (PC)

PC DDC
1. 640*350 31.468 70.09 25.17 EGA X
2. 720*400 31.469 70.08 28.32 DOS 0
3. 640*480 31.469 59.94 25.17 VESA(VGA) 0
4. 800*600 37.879 60.31 40.00 VESA(SVGA) 0
5. 1024*768 48.363 60.00 65.00 VESA(XGA) 0
6. 1280*768 47.776 59.870 79.5 CVT(WXGA) 0
7. 1360*768 47.712 60.015 85.50 VESA (WXGA) 0
8. 1280*1024 63.981 60.020 108.00 VESA (SXGA) 0
9. 1600*1200 75.00 60.00 162 VESA (UXGA) 0
10 1920*1080 67.5 60 148.5 HDTV 1080P 0
7. HDMI Input(PC/DTV)
PC DDC
1 640*350 31.468 70.09 25.17 EGA X
2 720*400 31.469 70.08 28.32 DOS 0
3 640*480 31.469 59.94 25.17 VESA(VGA) 0
4 800*600 37.879 60.31 40.00 VESA(SVGA) 0
5 1024*768 48.363 60.00 65.00 VESA(XGA) 0
6 1280*768 47.776 59.870 79.5 CVT(WXGA) 0
7 1360*768 47.712 60.015 85.50 VESA (WXGA) 0
8 1280*1024 63.981 60.020 108.00 VESA (SXGA) 0
9 1600*1200 75.00 60.00 162 VESA (UXGA) 0
10 1920*1080 67.5 60 148.5 HDTV 1080P 0
DTV
1 720*480 31.50 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.50 60 148.50 HDTV 1080P
8 1920*1080 67.432 59.94 148.352 HDTV 1080P
9 1920*1080 27.00 24.00 74.25 HDTV 1080P
10 1920*1080 26.97 23.976 74.176 HDTV 1080P
11 1920*1080 33.75 30.00 74.25 HDTV 1080P
12 1920*1080 33.71 29.97 74.176 HDTV 1080P
ADJUSTMENT INSTRUCTION
1. Application Range 4. PCB Assembly Adjustment

This spec. sheet applies to PB02A Chassis applied PDP TV
all models manufactured in TV factory.
4-1. Using RS-232C

- Adjust 3 items at 3-1 PCB assembly adjustments
2. Specification “ (3) Adjustment sequence” one after the order.
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation (1) Adjustment protocol
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs.
(3) The adjustment must be performed in the circumstance of
25 cC ± 5 cC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep 100 V - 240 V,
50 / 60 Hz.
(5) Before adjustment, execute Heat-Run for 5 minutes.
V After Receive 100% Full white pattern (06CH) then

process Heat-run
(or “8. Test pattern” condition of Ez-Adjust status) < See ADC Adjustment RS232C Protocol_Ver1.0 >
V How to make set white pattern
1) Press Power ON button of Service Remocon
2) Press ADJ button of Service remocon. Select “10. (2) Necessary items before Adjustment items
O Pattern Generator : (MSPG-925FA)
Test pattern” and, after select “White” using
O Adjust 480i Comp1
navigation button, and then you can see 100% Full
White pattern. (MSPG-925FA:model :209, pattern :65) – Comp1 Mode
O Adjust 1080p Comp1
* In this status you can maintain Heat-Run useless any
pattern generator (MSPG-925FA:model :225 , pattern :65) – Comp1 Mode
O Addjust RGB (MSPG-925FA:model :225 , pattern :65)
* Notice: if you maintain one picture over 20 minutes
(Especially sharp distinction black with white pattern – – RGB-PC Mode
13Ch, or Cross hatch pattern – 09Ch) then it can
appear image stick near black level. * If you want more information then see the below Adjustment
method (Factory Adjustment)
(3) Adjustment sequence

O aa 00 00: Enter the ADC Adjustment mode.
3. Adjustment items O xb 00 40: Change the mode to Component1 (No actions)
O ad 00 10: Adjust 480i Comp
3-1. PCB Assembly adjustment O ad 00 10: Adjust 1080p comp

O xb 00 60: Change to RGB-PC mode(No action)
(1) Adjust 480i Comp1
O ad 00 10: Adjust 1080p RGB
(2) Adjust 1080p Comp1/RGB
O xb 00 90: Endo of Adjustmennt
- If it is necessary, it can adjustment at Manufacture Line
- You can see set adjustment status at “9. ADJUST
CHECK” of the “In-start menu”
3-2. Set Assembly Adjustment

(1) EDID (The Extended Display Identification Data )
(2) Color Temperature (White Balance) Adjustment
(3) Make sure RS-232C control
(4) Selection Factory output option
5. Factory Adjustment
-> PB02A : USE INTERNAL ADC(S7) : using internal pattern.
5-1. Auto Adjust Component

480i/1080p RGB 1080p
(1) Summary : Adjustment component 480i/1080i and RGB
1080p is Gain and Black level setting at Analog
to Digital converter, and compensate the RGB
deviation
(2) Using instrument
1) Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator
(It can output 480i/1080i horizontal 100 % color bar
pattern signal, and its output level must setting
0.7 V ± 0.1 V p-p correctly)
Caution : Set Volume 0 after adjustment
5-2. Use Internal ADC(S7)

< Adjustment pattern : 480i / 1080p 60Hz Pattern >
- ADJ(EZ ADJUST) -> 6.ADC Calibration -> ADC
Calibration(START)
* You must make it sure its resolution and pattern cause every
instrument can have different setting 5-3. EDID(The Extended Display
2) Adjustment method 480i Comp1, Adjust 1080p
Identification Data) / DDC(Display Data
Comp1/RGB (Factory adjustment) Channel) download
O ADC 480i Component1 adjustment - (1) Summary
- Check connection of Component1 1) It is established in VESA, for communication between
- MSPG-925FA Ë Model: 209, Pattern 65 PC and Monitor without order from user for building user
O Set Component 480i mode and 100% Horizontal condition. It helps to make easily use realize “Plug and
Color Bar Pattern(HozTV31Bar), then set TV set to Play” function.
Component1 mode and its screen to “NORMAL” 2) For EDID data write, we use DDC2B protocol.
O ADC 1080p Component1 / RGB adjustment
- Check connection both of Component1 and RGB 5-4. Auto Download
- MSPG-925FA Ë Model: 225, Pattern 65
(1) After enter Service Mode by pushing “ADJ” key,
O Set Component 1080p mode and 100% Horizontal
(2) Enter EDID D/L mode.
Color Bar Pattern(HozTV31Bar), then set TV set to
(3) Enter “START” by pushing “OK” key.
Component1 mode and its screen to “NORMAL”
O After get each the signal, wait more a second and
Caution
enter the “IN-START” with press IN-START key of
- Never connect HDMI & D-sub Cable when the user
Service remocon. After then select “7. External ADC”
downloading .
with navigator button and press “Enter”.
- Use the proper cables below for EDID Writing.
O After Then Press key of Service remocon “Right
Arrow(VOL+)”
O You can see “ADC Component1 Success”
O Component1 1080p, RGB 1080p Adjust is same
method.
O Component 1080p Adjustment in Component1 input
mode
O RGB 1080p adjustment in RGB input mode
O If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”
* Edid data and Model option download(RS232)
5-5. Manual Download

(1) Write HDMI EDID data
1) Using instruments
- Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
- S/W for DDC recording (EDID data write and read)
- D-sub jack
- Additional HDMI cable connection Jig.
2) Preparing and setting.
- Set instruments and Jig. Like pic.5), then turn on PC
and Jig.
- Operate DDC write S/W (EDID write & read)
- It will operate in the DOS mode.
< For write EDID data, setting Jig and another instruments >
- EDID data (Model name = LG TV)

- 2010 EDID DATA CHECK SUM.
BLOCK(0) BLOCK(1)
HD HDMI1 3B 2C
HDMI2 3B 1C
HDMI3 3B 0C
RGB A3 25
FHD HDMI1 3B 2C
HDMI2 3B 1C
HDMI3 3B 0C
HDMI4 3B FC
RGB A3 25
Copyright ©2010 LG Electronics Inc. All rights reserved. - 10 - LGE Internal Use Only
(3) White Balance Adjustment
- If you can’t adjust with inner pattern, then you can adjust
it using HDMI pattern. You can select option at “Ez-Adjust
Menu – 7. White Balance” there items “NONE, INNER,
HDMI”. It is normally setting at inner basically. If you can’t
adjust using inner pattern you can select HDMI item, and
you can adjust.
- In manual Adjust case, if you press ADJ button of service

remocon, and enter “Ez-Adjust Menu – 7. White Balance”,
then automatically inner pattern operates. (In case of
“Inner” originally “Test-Pattern. On” will be selected in The
“Test-Pattern. On/Off”.
O Connect all cables and equipments like Pic.5)

O Set Baud Rate of RS-232C to 115200. It may set
115200 orignally.
O Connect RS-232C cable to set
O Connect HDMI cable to set
* See Working Guide if you want more information about EDID
communication.
5-6. Adjustment Color Temperature

(White balance)
(1) Using Instruments
1) Color Analyzer: CA-210 (CH 9)
- Using LCD color temperature, Color Analyzer (CA-
210) must use CH 9, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
2100. See the Coordination bellowed one.
2) Auto-adjustment Equipment (It needs when Auto-
adjustment – It is availed communicate with RS-232C :
Baud rate: 115200) V RS-232C COMMAND(Commonly apply)
3) Video Signal Generator MSPG-925F 720p, 216Gray RS-232C COMMAND
(Model: 217, Pattern 78)
(2) Connection Diagram (Auto Adjustment) [CMD ID DATA] Meaning
1) Using Inner Pattern wb 00 00 White Balance adjustment start.
wb 00 10 Start of adjust gain
(Inner white pattern)
wb 00 1f End of gain adjust
wb 00 20 Start of offset adjust
(Inner white pattern)
wb 00 2f End of offset adjust
wb 00 ff End of White Balance adjust
2) Using HDMI input (Inner pattern disappeared)
O wb 00 00”: Start Auto-adjustment of white balance.

O “wb 00 10”: Start Gain Adjustment (Inner pattern)
O “jb 00 c0” :
O…
O “wb 00 1f”: End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00 2f-
end)
O “wb 00 ff”: End of white balance adjustment (inner
pattern disappear)
< Connection Diagram for Adjustment White balance >
V Adjustment Mapping information * Attachment: White Balance adjustment coordination and color
temperature.
RS-232C COMMAND CENTER
[CMD ID DATA] MIN (DEFAULT) MAX O Using CS-1000 Equipment.
Cool Mid Warm Cool Mid Warm - COOL : T=11000K, _uv=0.000, x=0.276 y=0.283
- MEDIUM : T=9300K, _uv=0.000, x=0.285 y=0.293
R Gain jg Ja jd 00 184 192 192 192 - WARM : T=6500K, _uv=0.000, x=0.313 y=0.329
G Gain jh Jb je 00 187 183 159 192
B Gain ji Jc jf 00 192 161 95 192
Using CA-210 Equipment. (10 CH)
O
R Cut 64 64 64 127 - Contras value : 216 Gray
G Cut 64 64 64 127 Color Test Color Coordination
B Cut 64 64 64 127 temperature Equipment x y
COOL CA-210 0.276±0.002 0.283±0.002
O When Color temperature (White balance) Adjustment
MEDIUM CA-210 0.285±0.002 0.293±0.002
(Automatically)
- Press “Power only key” of service remocon and WARM CA-210 0.313±0.002 0.329±0.002
operate automatically adjustment.
- Set BaudRate to 115200.
O You must start “wb 00 00” and finish it “wb 00 ff”. - Brighness spec.
O If it needs, then adjustment “Offset”.
Item Min Typ Max Unit Remark
White 49 60 - cd/m - 100%Window White
(4) White Balance Adjustment (Manual adjustment) average Pattern
1) Test Equipment: CA-210
- Using PDP color temperature, Color Analyzer (CA- brightness - 100IRE(255Gray)
210) must use CH 10, which Matrix compensated - Picture: Vivid(Medium )
(White, Red, Green, Blue compensation) with CS- Brightness -20 +20 % - 85IRE(216Gray) 100%
2100. See the Coordination bellowed one.
2) Manual adjustment sequence is like bellowed one. uniformity Window White Pattern
- Turn to “Ez-Adjust” mode with press ADJ button of - Picture: Vivid(Medium)
service remocon.
- Select “10.Test Pattern” with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more 6. Test of RS-232C control.
10cm from center of PDP module when adjustment.
- Press “ADJ” button of service remocon and select - Press In-Start button of Service Remocon then set the “4.Baud
Rate” to 115200. Then check RS-232C control and
“7.White-Balance” in “Ez-Adjust” then press “G” button
of navigation key. (When press “G” button then set will
go to full white mode)
- Adjust at three mode (Cool, Medium, Warm)
- If “cool” mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then 7. Selection of Country option.
control R, G gain adjustment High Light adjustment. - Selection of country option is allowed only North American
- If “Medium” and “Warm” mode Let R-Gain to 192 and model (Not allowed Korean model). It is selection of Country
R, G, B-Cut to 64 and then control G, B gain about Rating and Time Zone.
adjustment High Light adjustment.
- All of the three mode (1) Models: All models which PB82C Chassis (See the first
Let R-Gain to 192 and R, G, B-Cut to 64 and then page.)
control G, B gain adjustment High Light adjustment. (2) Press “In-Start” button of Service Remocon, then enter the
- With volume button (+/-) you can adjust. “Option” Menu with “PIP CH-“ Button
- After all adjustment finished, with Enter (_ key) turn to (3) Select one of these three (USA, CANADA, MEXICO)
Ez-Adjust mode. Then with ADJ button, exit from defends on its market using “Vol. +/-“button.
adjustment mode
Caution : Don’t push The INSTOP KEY after completing the
function inspection
Caution : Inspection only PAL M
8. GND and ESD Testing 9-1. Adjustment method
(1) Vs adjustment (refer fig.1)
1) Connect + terminal of D.M.M. to Vs pin of
8-1. Prepare GND and ESD Testing. P812(42”:P811), connect -terminal to GND pin of
- Check the connection between set and power cord P812(42”:P811)
2) After turning VR901, voltage of D.M.M adjustment as
same as Vs voltage which on label of panel left/top (
deviation ; ±0.5V)
8-2. Operate GND and ESD auto-test.
(1) Fully connected (Between set and power cord) set enter (2) Va adjustment (refer fig.1)
the Auto-test sequence. 1) After receiving 100% Full White Pattern, HEAT RUN.
(2) Connect D-Jack AV jack test equipment. 2) Connect + terminal of D.M.M. to Va pin of
(3) Turn on Auto-controller(GWS103-4) P812(42”:P811), connect -terminal to GND pin of
(4) Start Auto GND test. P811(42”:P812).
(5) If its result is NG, then notice with buzzer. 3) After turning VR502,voltage of D.M.M adjustment as
(6) If its result is OK, then automatically it turns to ESD Test. same as Va voltage which on label of panel left/top
(7) Operate ESD test (deviation; ±0.5V)
(8) If its result is NG, then notice with buzzer.
(9) If its result is OK, then process next steps. Notice it with
Good lamp and STOPER Down.
10. Default Service option.

8-3. Check Items. 10-1. ADC-Set.
(1) Test Voltage
GND: 1.5KV/min at 100mA V R-Gain adjustment Value (default 128)
Signal: 3KV/min at 100mA V G-Gain adjustment Value (default 128)
V B-Gain adjustment Value (default 128)
(2) Test time: just 1 second.
V R-Offset adjustment Value (default 128)
(3) Test point
V G-Offset adjustment Value (default 128)
GND test: Test between Power cord GND and Signal cable
V B-Offset adjustment Value (default 128)
metal GND.
ESD test: Test between Power cord GND and Live and
neutral.
(4) Leakage current: Set to 0.5mA(rms)
10-2. White balance. Value.
CENTER (DEFAULT)
Cool Mid Warm
9. POWER PCB Ass’y Voltage R Gain 192 192 192
Adjustment G Gain 192 192 192
(Va/Vs Voltage Adjustment) B Gain 192 192 192
R Cut 64 64 64
(1)Test equipment : D.M.M 1EA G Cut 64 64 64
(2) Connection Diagram for Measuring : refer to fig.1 B Cut 64 64 64
10-3. Temperature Threshold

V Threshold Down Low 20
V Threshold Up Low 23
V Threshold Down High 70
V Threshold Up High 75
< fig.1 : 42HD Power PCB Assy Voltage adjustment >
11. USB DOWNLOAD
(*.epk file download)
V Put the USB Stick to the USB socket
V Press Menu key, and move OPTION
V After download is finished, remove the USB stick.
V Press “IN-START” key of ADJ remote control, check the

S/W version.
CAUTION
V Press “FAV” Press 7 times. - DO NOT REMOVE USB MEMORY CARD FROM USB PORT
WHEN YOU FIND BELOW DESCRIPTION
- " Do not remove the memory card from the port! "
V Select download file (epk file)
BLOCK DIAGRAM
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
400
601
900
604
602
910
520
206
207
204
200
590
501
580
240
201
A12
203
120
205
302
A9
202
304
305
301
303
A10
300
LV1
A21
A2
VCC_1.5V_DDR VCC_1.5V_DDR VCC_1.5V_DDR
VCC_1.5V_DDR
VCC_1.5V_DDR
DDR3 1.5V By CAP - Place these Caps near Memory VCC_1.5V_DDR
R1201
DDR3 1.5V By CAP - Place these Caps near Memory

R1204
R1227
1K 1%
R1224
1K 1%
1K 1%
1K 1%
A-MVREFDQ A-MVREFCA B-MVREFDQ
B-MVREFCA
0.1uF
1000pF
0.1uF
0.1uF
1000pF
1000pF
1%
0.1uF
1000pF
1%
1%
1%
R1202
R1205
R1228
C1205
C1216
R1225
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C1206
C1207
C1208
C1210
C1211
C1212
C1213
C1214
C1215
C1217
C1218
C1219
C1220
C1221
C1222
C1223
C1224
C1235
C1246
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
C1227
C1228
C1229
C1230
C1231
C1232
C1233
C1234
C1236
C1237
C1238
C1239
C1241
C1242
C1243
C1244
C1245
10uF
C1202
C1201
C1204
C1249
C1203
C1247
C1250
1K
C1248
1K
1K
1K
Close to DDR Power Pin Close to DDR Power Pin
CLose to DDR3 CLose to Saturn7M IC CLose to Saturn7M IC CLose to DDR3
VCC_1.5V_DDR
+1.5V_DDR_IN
L1201
R1215
B-TMA0 B-MA0
10
C1225 C1226
10uF R1216
R1213 0.1uF
10V B-TMA2 B-MA2
A-MA0 A-TMA0 16V 10
10
AR1211
R1214
B-TMA11 B-MA11
IC1202
A-MA2 A-TMA2
10 B-TMA1 B-MA1
H5TQ1G63BFR-H9C
AR1208
IC1201 B-TMA8 B-MA8
A-MA11 A-TMA11
H5TQ1G63BFR-H9C B-TMA6 B-MA6
N3 M8
A-MA1 A-TMA1 10 B-MA0 A0 VREFCA B-MVREFCA
A-MA8 A-TMA8 AR1214 P7
B-MA1 A1
A-MA6 A-TMA6 B-TMBA0 B-MBA0 P3
M8 N3 B-MA2 A2
A-MVREFCA VREFCA A0 A-MA0 10 B-TMA3 B-MA3 N2 H1
P7 AR1203 B-MA3 A3 VREFDQ B-MVREFDQ
A1
P3
A-MA1 IC101 B-TMA5 B-MA5 B-MA4
P8
A4
A-MBA0 A-TMBA0
H1
A2
N2
A-MA2 LGE101D (S7 Non_Tcon/RM) B-TMA7 B-MA7 B-MA5
P2
A5 R1226
A-MVREFDQ VREFDQ A3 A-MA3 A-MA3 A-TMA3 10 R8 L8
P8 B-MA6 A6 ZQ
A4 A-MA4 A-MA5 A-TMA5 AR1215 R2
P2 B-MA7 A7 240
R1203 A5 A-MA5 A-MA7 A-TMA7 B-TMA4 B-MA4 T8 1%
L8 R8 B8 A25 B-MA8
10 A-TMA0 A_DDR3_A0/DDR2_A13 B_DDR3_A0/DDR2_A13 B-TMA0 A8
ZQ A6 A-MA6 B9 B24 B-TMA12 B-MA12 R3 B2
240 R2 AR1204 A-TMA1 B_DDR3_A1/DDR2_A8 B-TMA1 B-MA9 A9 VDD_1
A7 A-MA7 A_DDR3_A1/DDR2_A8 B-TMBA1 B-MBA1 L7 D9
1% T8 A8 A24 B-MA10
A-MA4 A-TMA4 A-TMA2 A_DDR3_A2/DDR2_A9 B_DDR3_A2/DDR2_A9 B-TMA2 A10/AP VDD_2
A8 A-MA8 C21 P25 B-TMA10 B-MA10 R7 G7
B2 R3 A-MA12 A-TMA12 A-TMA3 B_DDR3_A3/DDR2_A1 B-TMA3 B-MA11 A11 VDD_3
VDD_1 A9 A-MA9 A_DDR3_A3/DDR2_A1 10 N7 K2
D9 L7 B10 C24 B-MA12
A-MBA1 A-TMBA1 A-TMA4 A_DDR3_A4/DDR2_A2 B_DDR3_A4/DDR2_A2 B-TMA4 A12/BC VDD_4
VDD_2 A10/AP A-MA10 A22 P26 AR1219 T3 K8
G7 R7 A-MA10 A-TMA10 A-TMA5 B_DDR3_A5/DDR2_A10 B-TMA5 B-MA13 A13 VDD_5
VDD_3 A11 A-MA11 A_DDR3_A5/DDR2_A10 B-TMRESETB B-MRESETB N1
K2 N7 10 A10 B26
A-TMA6 A_DDR3_A6/DDR2_A4 B_DDR3_A6/DDR2_A4 B-TMA6 VDD_6
VDD_4 A12/BC A-MA12 B22 R24 B-TMBA2 B-MBA2 M7 N9
K8 T3 AR1201 A-TMA7 B_DDR3_A7/DDR2_A3 B-TMA7 A15 VDD_7
VDD_5 A13 A-MA13 A_DDR3_A7/DDR2_A3 B-TMA13 B-MA13 R1
N1 C9 B25
A-MRESETB A-TMRESETB A-TMA8 A_DDR3_A8/DDR2_A6 B_DDR3_A8/DDR2_A6 B-TMA8 VDD_8
VDD_6 C23 T26 B-TMA9 B-MA9 M2 R9 VCC_1.5V_DDR
N9 M7 A-MBA2 A-TMBA2 A-TMA9 B_DDR3_A9/DDR2_A12 B-TMA9 B-MBA0 BA0 VDD_9
VDD_7 A15 A_DDR3_A9/DDR2_A12 10 N8
R1 B11 D24 B-MCK B-MBA1
A-MA13 A-TMA13 A-TMA10 A_DDR3_A10/DDR2_RASZ B_DDR3_A10/DDR2_RASZ B-TMA10 BA1
M3
R1238 R1237
VDD_8 A9 A26 R1222
VCC_1.5V_DDR R9 M2 A-MA9 A-TMA9 A-TMA11 B-TMA11 B-MBA2 BA2
56
VDD_9 BA0 A-MBA0 A_DDR3_A11/DDR2_A11 B_DDR3_A11/DDR2_A11 B-TMCK B-MCK C1240 A1
N8 A-MCK C10 C25 10
10 A-TMA12 B-TMA12 VDDQ_1
R1236 R1235
BA1 A-MBA1 A_DDR3_A12/DDR2_A0 B_DDR3_A12/DDR2_A0 J7 A8

M3 B23 T25 R1223 CK VDDQ_2
56
A-MBA2 R1206 A-TMA13 A_DDR3_A13/DDR2_A7 B_DDR3_A13/DDR2_A7 B-TMA13 0.01uF K7 C1

BA2 B-TMCKB B-MCKB
56
A1 C1209 A-MCK A-TMCK CK VDDQ_3
VDDQ_1 10 K9 C9
10
A8 J7 AR1220 B-MCKE CKE VDDQ_4
VDDQ_2 CK 0.01uF R1207 B-MCKB D2
56
C1 K7 A-MCKB A-TMCKB B-TMRASB B-MRASB VDDQ_5

VDDQ_3 CK B21 P24 L2 E9
C9 K9 A-MCKB 10 CS VDDQ_6
A-MCKE A-TMBA0 A_DDR3_BA0/DDR2_BA2 B_DDR3_BA0/DDR2_BA2 B-TMBA0 B-TMCASB B-MCASB K1 F1
VDDQ_4 CKE AR1202 A11 C26
D2 A-TMBA1 B-TMBA1 B-TMODT B-MODT B-MODT ODT VDDQ_7
VDDQ_5 A_DDR3_BA1/DDR2_CASZ B_DDR3_BA1/DDR2_CASZ J3 H2
E9 L2 A-MRASB A-TMRASB A23 R26
VDDQ_6 A-TMBA2 A_DDR3_BA2/DDR2_A5 B_DDR3_BA2/DDR2_A5 B-TMBA2 B-TMWEB B-MWEB VCC_1.5V_DDR B-MRASB
K3
RAS VDDQ_8
H9
CS A-MCASB A-TMCASB
F1 K1 10 B-MCASB CAS VDDQ_9
VDDQ_7 ODT A-MODT A12 D26 R1232 L3
H2 J3 A-MODT A-TMODT B-MWEB WE
VDDQ_8 A-MRASB A-TMCK A_DDR3_MCLK/DDR2_MCLK B_DDR3_MCLK/DDR2_MCLK B-TMCK R1219 10K J1
RAS VCC_1.5V_DDR A-MWEB A-TMWEB C11 D25
H9 K3 A-TMCKB B-TMCKB B-TMDQSL B-MDQSL NC_1
VDDQ_9 CAS A-MCASB A_DDR3_MCLKZ/DDR2_MCLKZ
B_DDR3_MCLKZ/DDR2_MCLKZ 10 T2 J9
L3 10 B12 E24 B-MRESETB NC_2
R1231 A-TMCKE A_DDR3_CKE/DDR2_DQ5 B_DDR3_CKE/DDR2_DQ5 B-TMCKE R1220 RESET
WE A-MWEB L1
J1 10K R1208 B-TMDQSLB B-MDQSLB NC_3
NC_1 A-MDQSL A-TMDQSL 10 L9
J9 T2 10 NC_4
NC_2 RESET A-MRESETB C20 N25 R1217 F3 T7
L1 R1209 A-TMODT B-TMODT B-MDQSL DQSL NC_6
NC_3 A_DDR3_ODT/DDR2_ODT B_DDR3_ODT/DDR2_ODT B-TMDQSU B-MDQSU G3
L9 A-MDQSLB A-TMDQSLB A20 M26 B-MDQSLB
10 A-TMRASB A_DDR3_RASZ/DDR2_WEZ B_DDR3_RASZ/DDR2_WEZ B-TMRASB 10 DQSL
NC_4 B20 N24 R1218
T7 F3 A-TMCASB B-TMCASB
NC_6 DQSL A-MDQSL R1211 A_DDR3_CASZ/DDR2_BA1 B_DDR3_CASZ/DDR2_BA1 B-TMDQSUB B-MDQSUB C7 A9
G3 A21 N26 B-MDQSU VSS_1
A-MDQSU A-TMDQSU A-TMWEB A_DDR3_WEZ/DDR2_BA0 B_DDR3_WEZ/DDR2_BA0 B-TMWEB 10 DQSU
DQSL A-MDQSLB 10 B7 B3
B-MDQSUB DQSU VSS_2
R1212 AR1212 E1
A9 C7 C22 R25 VSS_3
A-MDQSU A-MDQSUB A-TMDQSUB A-TMRESETB A_DDR3_RESETB B_DDR3_RESETB B-TMRESETB B-TMDQL1 B-MDQL1 E7 G8
VSS_1 DQSU 10
B3 B7 B-MDML DML VSS_4
VSS_2 DQSU A-MDQSUB B-TMDQL3 B-MDQL3 D3 J2
E1 AR1209 B-MDMU DMU VSS_5
VSS_3 C16 J25 B-TMDML B-MDML J8
G8 E7 A-MDQL1 A-TMDQL1 A-TMDQSL B-TMDQSL VSS_6
VSS_4 DML A-MDML A_DDR3_DQSL/DDR2_DQS0 B_DDR3_DQSL/DDR2_DQS0 B-TMDQU2 B-MDQU2 E3 M1
J2 D3 B16 J24 B-MDQL0 VSS_7
A-MDQL3 A-TMDQL3 A-TMDQSLB A_DDR3_DQSLB/DDR2_DQSB0B_DDR3_DQSLB/DDR2_DQSB0 B-TMDQSLB DQL0
VSS_5 DMU A-MDMU 10 F7 M9
J8 A-MDML A-TMDML B-MDQL1 DQL1 VSS_8
VSS_6 A16 H26 AR1213 F2 P1
M1 E3 A-MDQU2 A-TMDQU2 A-TMDQSU B-TMDQSU B-MDQL2 DQL2 VSS_9
VSS_7 DQL0 A-MDQL0 A_DDR3_DQSU/DDR2_DQSB1 B_DDR3_DQSU/DDR2_DQSB1 B-TMCKE B-MCKE F8 P9
M9 F7 C15 H25 B-MDQL3 VSS_10
10 A-TMDQSUB A_DDR3_DQSUB/DDR2_DQS1 B_DDR3_DQSUB/DDR2_DQS1 B-TMDQSUB DQL3
VSS_8 DQL1 A-MDQL1 B-TMDQL7 B-MDQL7 H3 T1
P1 F2 AR1210 B-MDQL4 DQL4 VSS_11
VSS_9 DQL2 A-MDQL2 A14 F26 B-TMDQL5 B-MDQL5 H8 T9
P9 F8 A-MCKE A-TMCKE A-TMDML B-TMDML B-MDQL5 DQL5 VSS_12
VSS_10 DQL3 A-MDQL3 A_DDR3_DML//DDR2_DQ13 B_DDR3_DML/DDR2_DQ13 G2
T1 H3 B18 L24 B-MDQL6
A-MDQL7 A-TMDQL7 A-TMDMU A_DDR3_DMU/DDR2_DQ6 B_DDR3_DMU/DDR2_DQ6 B-TMDMU 10 DQL6
VSS_11 DQL4 A-MDQL4 H7
T9 H8 A-MDQL5 A-TMDQL5 B-MDQL7 DQL7
VSS_12 DQL5 A-MDQL5 AR1216 B1
G2 C18 L25 VSSQ_1
DQL6 A-MDQL6 A-TMDQL0 A_DDR3_DQL0/DDR2_DQ3 B_DDR3_DQL0/DDR2_DQ3 B-TMDQL0 B-TMDQL0 B-MDQL0 D7 B9
H7 10 B13 F24 B-MDQU0 VSSQ_2
A-TMDQL1 A_DDR3_DQL1/DDR2_DQ7 B_DDR3_DQL1/DDR2_DQ7 B-TMDQL1 DQU0
DQL7 A-MDQL7 A19 L26 B-TMDQL2 B-MDQL2 C3 D1
B1 AR1205 A-TMDQL2 B-TMDQL2 B-MDQU1 DQU1 VSSQ_3
VSSQ_1 A_DDR3_DQL2/DDR2_DQ1 B_DDR3_DQL2/DDR2_DQ1 B-TMDQL6 B-MDQL6 C8 D8
B9 D7 C13 F25 B-MDQU2 VSSQ_4
A-MDQL0 A-TMDQL0 A-TMDQL3 A_DDR3_DQL3/DDR2_DQ10 B_DDR3_DQL3/DDR2_DQ10 B-TMDQL3 DQU2
VSSQ_2 DQU0 A-MDQU0 C19 M25 B-TMDQL4 B-MDQL4 C2 E2
D1 C3 A-MDQL2 A-TMDQL2 A-TMDQL4 B-TMDQL4 B-MDQU3 DQU3 VSSQ_5
VSSQ_3 DQU1 A-MDQU1 A_DDR3_DQL4/DDR2_DQ4 B_DDR3_DQL4/DDR2_DQ4 10 A7 E8
D8 C8 A13 E26 B-MDQU4 VSSQ_6
A-MDQL6 A-TMDQL6 A-TMDQL5 A_DDR3_DQL5/DDR2_DQ0 B_DDR3_DQL5/DDR2_DQ0 B-TMDQL5 DQU4
VSSQ_4 DQU2 A-MDQU2 B19 M24 AR1217 A2 F9
E2 C2 A-MDQL4 A-TMDQL4 A-TMDQL6 B-TMDQL6 B-MDQU5 DQU5 VSSQ_7
VSSQ_5 DQU3 A-MDQU3 A_DDR3_DQL6/DDR2_CKE B_DDR3_DQL6/DDR2_CKE B-TMDQU7 B-MDQU7 B8 G1
E8 A7 C12 E25 B-MDQU6 VSSQ_8
10 A-TMDQL7 A_DDR3_DQL7/DDR2_DQ2 B_DDR3_DQL7/DDR2_DQ2 B-TMDQL7 DQU6
VSSQ_6 DQU4 A-MDQU4 B-TMDQU3 B-MDQU3 A3 G9
F9 A2 AR1206 B-MDQU7 DQU7 VSSQ_9
VSSQ_7 DQU5 A-MDQU5 A15 G26 B-TMDQU5 B-MDQU5
G1 B8 A-MDQU7 A-TMDQU7 A-TMDQU0 B-TMDQU0
VSSQ_8 DQU6 A-MDQU6 A_DDR3_DQU0/DDR2_DQ15 B_DDR3_DQU0/DDR2_DQ15 B-TMDMU B-MDMU
G9 A3 A17 J26
A-MDQU3 A-TMDQU3 A-TMDQU1 A_DDR3_DQU1/DDR2_DQ9 B_DDR3_DQU1/DDR2_DQ9 B-TMDQU1 10
VSSQ_9 DQU7 A-MDQU7 B14 G24
A-MDQU5 A-TMDQU5 A-TMDQU2 A_DDR3_DQU2/DDR2_DQ8 B_DDR3_DQU2/DDR2_DQ8 B-TMDQU2 AR1218
C17 K25
A-MDMU A-TMDMU A-TMDQU3 A_DDR3_DQU3/DDR2_DQ11 B_DDR3_DQU3/DDR2_DQ11 B-TMDQU3 B-TMDQU6 B-MDQU6
10 B15 H24
A-TMDQU4 A_DDR3_DQU4/DDR2_DQM1 B_DDR3_DQU4/DDR2_DQM1 B-TMDQU4 B-TMDQU0 B-MDQU0
AR1207 A18 K26
A-TMDQU5 A_DDR3_DQU5/DDR2_DQ12 B_DDR3_DQU5/DDR2_DQ12 B-TMDQU5 B-TMDQU4 B-MDQU4
A-MDQU6 A-TMDQU6 C14 G25
A-TMDQU6 A_DDR3_DQU6/DDR2_DQM0 B_DDR3_DQU6/DDR2_DQM0 B-TMDQU6
A-MDQU0 A-TMDQU0 B17 K24
A-TMDQU7 A_DDR3_DQU7/DDR2_DQ14 B_DDR3_DQU7/DDR2_DQ14 B-TMDQU7 10
A-MDQU4 A-TMDQU4
R1221
B-TMDQU1 B-MDQU1
10 10
R1210
A-MDQU1 A-TMDQU1
10 10K R1234
B-MCKE
R1233 10K
A-MCKE
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX61373301 09/04/02
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR 12 13
Copyright © 2010 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
USB1 SIDE
SWITCH ADDED
+3.3V +3.3V
250_350
Capacitors on VBUSA should be
placed as closd to connector as possible. R1129 IC1101
AP2191SG-13 R1141
10K 10K P_+5V
250_350
NC
8 1
GND
READY
OUT_2 IN_1
7 2
$0.11
USB1_OCD OUT_1
6 3
IN_2
C1120
R1124 22 R1145 22 0.1uF
16V
FLG EN
5 4
C1122 C1116 250_350 250_350

10uF 100uF USB1_CTL 250_350
250_350 16V 16V
250_350 250_350
KJA-UB-4-0004
P1102
1
USB DOWN STREAM
USB1_DM_to_MAIN
2
USB1_DP_to_MAIN
3
D1100 D1102
CDS3C05HDMI1 CDS3C05HDMI1
5.6V 5.6V
4
10mm READY READY

5
USB2 REAR(SVC)
L1100 +5V
0LCML00003B
MLB-201209-0120P-N2
PJ230
JK1100 C1121
KJA-UB-0-0037 0.1uF
16V
2 USB2_DM_to_MAIN
3 USB2_DP_to_MAIN
D1101 D1103
4 CDS3C05HDMI1 CDS3C05HDMI1
5.6V 5.6V
READY READY
5

EAX61373301
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR USB HUB 11 13
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

SIDE CVBS
250_350
5A [YL]E-LUG
SIDE_CVBS_IN
4A [YL]O-SPRING C1016
D1022 R1044 47pF
3A [YL]CONTACT +3.3V 30V
75 50V
R1036
4B [WH]O-SPRING
JK1001
10K
R1019
PPJ237-01 3C [RD]CONTACT 1K
SIDE_CVBS_DET
C1013
D1020
[RD1]E-LUG
30V
6C 4C [RD]O-SPRING 0 . 1 u F READY
16V
5C [RD]E-LUG
[RD1]O-SPRING
AV 1
R1025 R1040
5C 10K PPJ235-01 10K
AV_RIN SIDE_LIN
JK1002 C1015
D1021
D1003 R1010 C1020 R1031 820pF
R1038
[RD1]CONTACT
470K
R1043
470K 820pF 12K
4C
12K
5.6V 50V
R1039
5B [WH1]O-SPRING R1026
10K
+3.3V_AVDD 10K
SIDE_RIN
AV_LIN C1014
D1019
R1037
470K
C1021 R1023 820pF
R1011 R1032
12K
D1004
R1042
470K 820pF 10K
4A [YL1]CONTACT 5.6V
50V 12K
AV_CVBS_DET
D1002 R1024
C1019 1K
5A [YL1]O-SPRING 5.6V 100pF

50V
AV_CVBS_IN READY
D1005 C1018
R1014
6A [YL1]E-LUG 30V 75 47pF
50V
6H [RD2]E-LUG
5H [RD2]O-SPRING_2 R1027
10K
COMP2_RIN COMPONENT 2 SPDIF
D1006 R1015 C1017 R1033
4H [RD2]CONTACT 5.6V
470K 820pF 12K
50V
R1028
10K +3.3V +3.3V
5G [WH2]O-SPRING COMP2_LIN
R1016 C1032 R1034
D1007 470K
5.6V 820pF 12K
50V R1058
5F [RD2]O-SPRING_1 1K C1024
IC1000
COMP2_Pr+ NL17SZ00DFT2G 10uF JK1003
D1008 READY C1023 16V JST1223-001
30V R1013 C1033 A VCC
0.1uF
[RD2]E-LUG-S 75 SPDIF_OUT 1 5
7F 10pF
50V B
NAND 50V
GND
R1060 COMP2_Pr- GATE
2
R1055
1
0 100
Fiber Optic
GND Y
3 4
5E [BL2]O-SPRING 1/16W VCC

5% COMP2_Pb+
2
R1051 C1022
R1012 READY 100
D1009 75 C1025 22pF
7E [BL2]E-LUG-S 30V 10pF READY VINPUT
3
50V COMP2_Pb- +3.3V_AVDD
R1061
4
0 R1000
10K FIX_POLE
4D [GN2]CONTACT 1/16W
5% COMP2_DET
R1001
D1000 1K
5D [GN2]O-SPRING 5.6V
READY COMP2_Y+
C1026
D1010 R1005 10pF
30V 75
6D [GN2]E-LUG 50V
R1062 COMP2_Y-
0
1/16W
6N [RD3]E-LUG 5%
5N [RD3]O-SPRING_2 R1029 10K

COMP1_RIN COMPONENT 1
D1011 R1018 C1027
5.6V 470K R1035
4N [RD3]CONTACT 820pF 12K
50V
R1030 10K
COMP1_LIN
5M [WH3]O-SPRING R1004 C1028 R1006
D1012 470K
5.6V 820pF 12K
50V
5L [RD3]O-SPRING_1 READY
COMP1_Pr+
R1020 C1029
75 10pF
D1013
7L [RD3]E-LUG-S 30V 50V
R1063
0 COMP1_Pr-
1/16W
5K [BL3]O-SPRING 5%
READY COMP1_Pb+
R1021 C1030
75 10pF
7K [BL3]E-LUG-S D1014
30V 50V +3.3V_AVDD
COMP1_Pb-
R1064 R1002
0 10K
4J [GN3]CONTACT R1003
1K
1/16W COMP1_DET
5%
D1001
5.6V
5J [GN3]O-SPRING
COMP1_Y+
D1015 READY
R1022 C1031
6J [GN3]E-LUG 30V 75 10pF

50V
R1065 COMP1_Y-
0
1/16W
5%

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX61373301
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK 10 13

250_350
RGB
D907
D908
D904
D905
D906
P900
SPG09-DB-010 +3.3V +3.3V
C900
0.1uF
16V
DSUB_R
FHD LVDS
R906
R956 R957 R958 R951 R952 R953
RED_GND 75
6
GND_2
1 11 RED L902
DSUB_R- 4.7K 0 4.7K 4.7K 0 4.7K
FHD
GREEN_GND
DDC_SDA/UART_TX
G
7
G
DDC_DATA
2 12 GREEN R959 22 R954 22
DSUB_G SDA1 SCL1
BLUE_GND
+3.3V_AVDD
S
8
S
R908
H_SYNC 75 Q904 Q903
3 13 BLUE
2N7002(F) 2N7002(F)
52
DSUB_G-
R911
NC
9
10K
51
V_SYNC
4 14 GND_1 L904
50
R974 0 R917 1K PC_SER_CLK
SYNC_GND
10 DSUB_DET 49 PC_SER_DATA
DDC_CLOCK C914
5 15 DDC_GND R973 0 D909 0.1uF HD R968 FHD 22
48 SCL1_1
30V 16V
READY READY P903 47
R969 FHD 100
READY +3.3V SMW200-26C +3.3V DISP_EN
16 46
R970 FHD 22
SHILED SDA1_1
R963 R964
45
DSUB_B
R907 3.3K 3.3K
44
75
2 1
43
R915 DSUB_B- 4 3
MOD_ROM_TX MOD_ROM_RX
22 42
L905 DSUB_HSYNC 6 5
C916 41
10pF
R916
22 50V
8 7
40
DSUB_VSYNC R962 22 R961 22
RXA0+
C917 SDA1_1 10 9 SCL1_1
HD HD 39 RXA0-
10pF
50V RXB0+ 12 11 RXB0- 38 RXA1+
RXB1+ 14 13 RXB1- 37 RXA1-
DDC_SCL/UART_RX RXB2+ 16 15 RXB2- 36 RXA2+
RXBCK+ 18 17 RXBCK- 35 RXA2-
RXB3+ 20 19 RXB3- 34
GND 22 21
RXB4+ RXB4- 33 RXACK+
PC_SER_DATA 24 23 PC_SER_CLK
32 RXACK-
R949 100
26 25 DISP_EN
HD 31
R960
ROM DOWNLOAD FOR PDP 250_350

27K 30
29
RXA3+
+5V_ST RXA3-
+3.3V_AVDD
IC901 28 RXA4+
AT24C02BN-10SU-1.8 27
HD LVDS
RXA4-
26
R975
1K
R903
C922 25
10
1 8
R912
R923 R924 0.1uF
4.7K 24
PC_SER_DATA 18K 4.7K RXB0+
2 7 23
C905 C908 RXB0-
220pF 220pF EDID_WP R929
0 22 RXB1+
50V 50V 3 6 DDC_SCL/UART_RX
R902 READY READY
R930 21
10 0 RXB1-
PC_SER_CLK 4 5 DDC_SDA/UART_TX
20 RXB2+
C901 C906 R976 C918 C919 R932
270pF 220pF D900 D901 1K 18pF 18pF 0
RGB_DDC_SCL 19 RXB2-
50V 50V 50V 50V R934
READY READY 0 18
RGB_DDC_SDA
17 RXBCK+
16 RXBCK-
15
14 RXB3+
13 RXB3-
+3.3V_ST
12 RXB4+
RS232C C902 C907
PC AUDIO 11 RXB4-
0.1uF 0.1uF C909
50V 50V 0.1uF 10
50V
C910
0.1uF 250_350 9
50V JK900
8
PEJ027-01
DOUT2
RIN2
C2-
C1-
C2+
C1+
SUB Board I/F

7
V-
V+
3 E_SPRING
6
8
4
7
2
6
6A T_TERMINAL1
5
IC900
MAX3232CDR
$0.179 7A B_TERMINAL1 +5V_ST 4 MOD_ROM_TX
PC_RIN P902
D910 R931 12507WS-12L 3 MOD_ROM_RX
4 R_SPRING C920 10K
5.6V 820pF R910
R935 2
15
16
50V R926
10
11
12
13
14
12K +3.3V_ST 4.7K

9
T_SPRING 470K
5
1
GND
VCC
DOUT1
ROUT2
ROUT1
DIN2
DIN1
RIN1
+3.3V_ST IR 1
7B B_TERMINAL2
PC_LIN C925
1/10W
10pF
R918
C921 R933
READY
C911 D911
10K
6B T_TERMINAL2 10K 2
TF05-51S
0.1uF 820pF
5%
R900 R901 50V R927 R938 R941 L903

50V 5.6V R936 10K 10K P904
4.7K 4.7K 470K MLB-201209-0120P-N2
12K
KEY1 3
RS232C_TXD L906 C930
MLB-201209-0120P-N2 10pF
RS232C_RXD
R905
D902 KEY2 4
100
R904 ADUC30S03010L_AMODIODE R937

100 30V 4.7K R945
PJ230 C926
R998 0 22 10pF 5
PC_SER_DATA LED_RED
R999 0 +3.3V D913
PC_SER_CLK C931
D914 D915 PJ230 D903 READY 6
30V 30V R914 10pF
PJ230 ADUC30S03010L_AMODIODE
PJ230 READY 4.7K
C903 220pF 50V 30V R946
22
SUB_SCL 7
C904
READY
220pF 50V
F o r 2 3 0 D e b u g g i n g PJ230 R909
4.7KREADY R947
IR C924 22
SUB_SDA 8
P906 10pF
READY
12507WR-03L
C923 9
10pF
READY
PJ230
+3.3V_ST READY
100K R980
CREADY R919
0 L900
1 MLB-201209-0120P-N2
DDC_SCL/UART_RX 10
Q900 B
+3.3V C927
SPG09-DB-009
2SC3052
R981 0 L901 0.1uF
READY
100K 2 MLB-201209-0120P-N2
E DDC_SDA/UART_TX 16V 11
R920 PJ230
P901
R939
4.7K L907 C932
6
MLB-201209-0120P-N2
10
3 0.1uF
LED_WHITE 12
16V
C933
4 10pF
1
13

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS/RS232//RGB 9 13

SIDE HDMI 5V_DET_HDMI_2
5V_DET_HDMI_3 C
250_350 5V_HDMI_45V_DET_HDMI_4 5V_HDMI_2
R833 10K
5V_HDMI_3 SHIELD READY B
C HPD2
SHIELD R851 R823 READY
R842 B 10K JACK_GND 20 E
Q805
R857 C 1K READY
HPD3
20 1K 2SC3875S(ALY)
Q806 20 1K Q807 R869
B 10K $0.47 C803
E - > $ 0 . 2 719 R822 R824
C808 2SC3875S(ALY) $0.27 2SC3875S(ALY) HPD4 1.8K 3.3K 0.1uF
$ 0 . 4 7 19 R841 R843 C810 16V
1.8K 3.3K 0.1uF 19 R856 R860 18 READY
->$0.28 HPD 1.8K 3.3K 0.1uF E READY READY
16V D806
18 16V READY READY
D807 18 17
+5V_POWER D808 AVRL161A1R1NT R826 22
17 READY READY DDC_SDA_2
AVRL161A1R1NT R845 22 17 16
DDC_SDA_3
DDC/CEC_GND AVRL161A1R1NT R858 22 R827 22
16 R844 DDC_SDA_4 DDC_SCL_2
22 16 15
SDA R859 22 READY
15 DDC_SCL_3
15 DDC_SCL_4 14
SCL R828 0
14 CEC_REMOTE
R846 0 14 13 READY
NC R878 0
CEC_REMOTE
13 CEC_REMOTE CK-_HDMI2
13 12
CEC
12 CK-_HDMI3 CK-_HDMI4
EAG59023302
12 11
CLK- CK+
10
EAG59023301
11 CK+_HDMI2
CK+ 11
10 CLK_SHIELD D0-
CK+_HDMI3 CK+_HDMI4 9 D0-_HDMI2
D0- 10
9 CLK+ D0_GND
D0-_HDMI3 8
D0_GND 9 D0-_HDMI4
8 DATA0- D0+
7 D0+_HDMI2
D0+ 8
7 DATA0_SHIELD D1-
D0+_HDMI3 6 D1-_HDMI2
D1- 7 D0+_HDMI4
6 DATA0+ D1_GND
D1-_HDMI3 5
D1_GND 6 D1-_HDMI4
5 DATA1- D1+
4 D1+_HDMI2
D1+ 5
4 DATA1_SHIELD D2-
D1+_HDMI3 3 D2-_HDMI2
D2- 4 D1+_HDMI4
3 DATA1+ D2_GND
D2-_HDMI3 2
D2_GND 3 D2-_HDMI4
2 DATA2- D2+
1 D2+_HDMI2
D2+ 2
1 DATA2_SHIELD
D2+_HDMI3
1 D2+_HDMI4
DATA2+
JK801 GND
READY
JK803 KJA-ET-0-0032
JK804
GND
10mm GND
5V_HDMI_2 +5V
5V_HDMI_3 +5V
5V_HDMI_4 +5V
A2
A1
A2
A1
A2
A1
READY
ENKMC2838-T112 IC801 ENKMC2838-T112
250_350 D805 D803
D804 AT24C02BN-10SU-1.8 READY
C
ENKMC2838-T112 IC804 READY
C
IC802
C
AT24C02BN-10SU-1.8 C805
AT24C02BN-10SU-1.8 0.1uF
A0 VCC
C809 C811 1 8
0.1uF
A0 VCC A0 VCC0 . 1 u F R831
1 8 1 8 18K
A1 WP READY R832 R834
R850 R864 2 7
18K 18K
18K A1 WP 18K EDID_WP
A1 WP 2 7 R867 R868 READY READY
2 7 R852 R853 A2 SCL R830 22
18K 18K
18K 18K EDID_WP 3 6 DDC_SCL_2
EDID_WP
A2 SCL R862 22 READY
A2 SCL R848 22 3 6
3 6 DDC_SCL_4 GND SDA
DDC_SCL_3 R829 22
4 5 DDC_SDA_2
GND SDA R863 22 READY
GND SDA R849 22 4 5
4 5 DDC_SDA_4
DDC_SDA_3
GND
GND
+3.3V +3.3V_ST
R875 0
READY
R871
0 MICOM_CEC_ON/OFF
R873 0
R800 R870
G
G
68K R877
68K 68K
Q800 Q801
BSS83 BSS83
D
B
S
D802
D
B
S
D801
MMBD301LT1G MMBD301LT1G
CEC_REMOTE HDMI_CEC_S7 CEC_REMOTE HDMI_CEC

HDMI_JACK R874
HDMI_JACK S7 MICOM
R872
0
0 READY
READY

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 8 13
HDMI

AMP
+3.3V
L703
+3.3V_AU_AVDD
120-ohm
This parts are Located

R705
on AVSS area. L702
1 u F 25V
R713
0 +3.3V_DVDD
470
2200pF
C719
4700pF
120-ohm
22K
AVSS 0.033uF
0.047uF
C710 4700pF 50V
C713
P_17V
AVSS
C712
C716
C714
C708
R714
R712
5 GVDD_OUT_1
470
Separate DGND AND AVSS 0.047uF
11 PLL_FLTP
10 PLL_FLTM
3 PVDD_A_2
2 PVDD_A_1
C724 C728 C729
6 SSTIMER
C721
22uF 68uF 68uF
12 VR_ANA
7 OC_ADJ
0.01uF 25V 35V 35V
4 BST_A
1 OUT_A
9 AVSS
1:S26;2:Q21 R720
8 NC
22
AUDIO_MASTER_CLK
C745 22pF
READY
+3.3V_AU_AVDD
AVDD 13 48 PGND_AB_2 L701
C736
C740
0.01uF
+3.3V_DVDD AD-9060
0.1uF
C701 C704 R710 TESTOUT
22 14 47 PGND_AB_1 2S 2F
50V
R717
10uF 16V 0.01uF C733
READY 3.3
MCLK 15 46 OUT_B 0.68uF
R730
1S 1F
4.7K
AVSS 50V
R718
R732
4.7K
R709
200 1% OSC_RES 16 45 PVDD_B_2 C737
0.1uF
3.3
C741
50V 50V 0.01uF SPK_L+
Q701
R731B
C 1% 18K
R711 DVSS_1 17 44 PVDD_B_1 C726
0.01uF
0.033uF
C731 4
Q700 C4.7K
2SC3875S(ALY)
VR_DIG 18 43 BST_B SPK_L-
R729
33K B
E TAS5709PHPR 3
1:AI3;5:O24 AC_DET PDN 19 42 BST_C SPK_R+
2SC3875S(ALY) IC700 2
E
C703
C705
4.7uF
LRCLK 20 41 PVDD_C_2
C700 0 . 1 u F 10V C725
50V SPK_R-
R702 22 READY READY 1000pF
50V
SCLK 21 40 PVDD_C_1 0.01uF
0.033uF
C730 L700
C738 1
C734 0.01uF
AD-9060
SDIN 22 39 OUT_C 2S 2F 0.1uF
50V
R715 SMAW250-H04R
C732
22 R724
SDA 23 38 PGND_CD_2 1S 1F
0.68uF
3.3 P703
50V
2:Q20 MS_LRCK R716
1 : S 2 6 ; 2 : Q 2 MS_SCK
1
22 R725 SCL 24 37 PGND_CD_1 C735 3.3
R726 0.1uF C739
22
1 : S 2 5 ; 2 : QMS_LRCH
20 50V 0.01uF
OUT_D 36
25
26
DVDD 27
28
GND 29
AGND 30
VREG 31
GVDD_OUT_2 32
33
34
35
C743 C742 C744

22pF 22pF 22pF
+3.3V_DVDD READY READY READY
PVDD_D_1
PVDD_D_2
RESET
BST_D
DVSS_2
STEST
R728 R744
2K 2K
R707 33
2:Q24 AMP_SDA
R708 33 P_17V
2:Q20 AMP_SCL
0 R746
R745
+3.3V_DVDD C706 C707

33pF 33pF
READY READY C720 C722 C723 C727
0
READY 0.01uF 22uF 68uF 68uF

1 u F 25V
CH_5 SCL1 25V 35V 35V

R706
R704
CH_5 SDA1
C717
33 2K
1:T8
AMP_RESET_N 0.033uF
+3.3V_DVDD C718
C702 50V
1000pF C715
READY 0.1uF
C709 C711
10uF 16V 0.01uF

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AUDIO AMP 7 13

+3.3V +3.3V_DE
L609
MLB-201209-0120P-N2
C691 C692 C693 C694 C695

10uF 0.1uF 0.1uF 0.1uF 0.1uF
6.3V 16V 16V 16V 16V
IC600
+1.2V_DE
AZ1117H-ADJTRE1(EH11A) R602
10
INPUT ADJ/GND R2
3 1
2
R601
OUTPUT 1.2K
R1 +1.2V_DE
+3.3V_DE R633 22
FE_TS_VLD
C697 C652 R632 22

10uF 10uF FE_TS_SYN
C685
6.3V 6.3V R631 22
0 . 0 1 u F C686
FE_TS_SERIAL
C688
C687
0 . 1 u F C689
C690 R630 22
0.1uF FE_TS_CLK
16V
0.1uF
1uF
1uF
+3.3V_DE
HDVDDL1
HDVDDH
VDDH_5
VDDH_4
VDDL_7
VSS_11
VSS_10
HDVPP
AGC_S
TEST0
TEST2
TEST1
DENA
DENB
SDOA
SDOB
PCKA
SCKA
PCKB
SCKB
GPO2
NC_4
NC_3
GPI2
RON
100
91
90
89
88
87
86
85
84
99
98
97
96
83
95
94
93
92
82
81
80
79
78
77
76
R628
READY
READY
VSS_1 1 75 VSS_9 R629
AVDD_S 2 74 INTB 2.2K 2.2K
0.1uF AII_S 3 73 INTA
C663 AIQ_S SADR
4 72
AVSS_S 5 71 VDDH_3
VRT_S SCL C684 0.1uF 22 R642
6 70 SCL1
VRB_S 7 69 SDA
22 SDA1
IC602
TCPO_S 8 68 VSS_8 R643
C664 0.1uF
VDDL_1 9 67 HDVDDL0
R640 2.2K MSCL_S SADR_S C683 0.1uF
MN884433
10 66
R641 2.2K MSDA_S NC_2
11 65
VSS_2 12 64 SADR_T
VSSH 13 63 VDDL_6
0.1uF PSEL VSS_7 C682 0.1uF
C665 14 62
ZSEL 15 61 ERRB
VDDL_2 16 60 SYNCB
0.1uF ACKI ERRA
C666 17 59
R621 TCPO_T 18 58 SYNCA
10K 1% IR_T TDO
19 57
VRT_T 20 56 CSEL1
C670 C667 0.1uF VRB_T CSEL0
21 55
0.1uF C668 0.1uF AVDD_T 22 54 TMS
16V C669 0.1uF
R622 100 AIN_T TRST
TUNER_IF_N 23 53
AIP_T 24 52 VDDL_5
TUNER_IF_P R623 100 AVSS_T VSS_6 C681 0.1uF
C671 25 51
0.1uF
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
16V
Close to R622,R623 +3.3V_DE
GPI1
GPI0
XI
TDI
VSS_3
VSS_4
VSS_5
TEST4
TEST3
NC_1
XO
AGCI_T
GPO1
GPO0
TCK
NRST
SHVPP
VDDL_3
VDDL_4
MSCL_T
VDDH_1
AGCR_T
VDDH_2
MSDA_T
SHVDDH
READY
R639
2.7K
R624 2.2K
R625 2.2K
DEMOD_RESET
READY
C696
0.1uF
C672 C674 C677 C679 C680 16V
0.1uF 0.1uF 0.1uF
0.1uF
0.1uF
16V 16V 16V 16V 16V
C678
0.1uF
R627 16V
1MREADY
ISDB_IF_AGC
R626 10K X602
25MHz
C673
0.1uF C675 C676
30pF 30pF
50V 50V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER 6 13

POWER B/D POWER Wafer 18P
P_17V
C524
+5V_ST C522 68uF
0.1uF 35V
L501 50V
P500
MLB-201209-0120P-N2 SMAW200-H18S1 +3.3V
R502 P_+5V +5V
C502 C508 C505 C504
10K
Q501
10uF 0.1uF 10uF 100uF
1 2 P_+5V SI3865BDV
10V 16V 16V
16V
3 4
READY L507
CB4532UK121E
R535
5 6 22K R1/C1 R2
R526 6 1
7 8
22
C521 C525 C585 C527
C530
9 10 ERROR_DET 0.1uF 10uF 100uF 100uF
10uF ON/OFF D2_1
11 12 16V 16V 16V 16V
16V RL_ON 5 $0.081 2
R506 100 13 14 S2
4 3
D2_2
RL_ON 15 16 C566
C565
17 18 22uF
560
R537
C513 R513 100 16V
4.7uF
AC_DET 10V
0.1uF 19
1uF 3225
16V C519
0.1uF C594
16V
R507 100
5V_ON
C514
0.1uF
16V
0 RL_ON
R544
P_17V
IC507
Stand-by (5VST --> +3.3V) MP8706EN-C247-LF-Z

Multi Power(3.3V -->2.5V) S7 core 2.5V
IN GND
1 8
+2.5V_AVDD
+5V_ST +3.3V_ST C541 0 . 1 u F
+3.3V_NEC_ST C590 C544
SW_1
2 7
VCC
10uF 0.1uF +3.3V
IC500 25V 50V R543 IC505
EAN58801701 L502 SW_2 FB 5.1K 0IPRPML001A
AP2121N-3.3TRE1 EAM44020101 C546
3 6 MIC39100
VIN 3 CB3216PA501E R2 1.8A
2 VOUT IN 1 3 OUT
0.1uF
BST EN/SYNC
4 5 +5V_TU
R539
1 2
1%
R545 47
39K
C500
C501 GND C509 C512 C515 R1 GND C567 C573 C580 C586 C589
10uF
0.1uF 10uF 10uF 0.1uF C562 C564 10uF 10uF 0.1uF 47uF 47uF
16V
16V 6.3V 6.3V 16V 10uF 0.1uF 6.3V 6.3V 16V 16V 16V
1%
IC506
R540
1.2K
AZ1117H-ADJTRE1(EH11A) 6.3V 16V
L520
10uH +7V R538
INPUT ADJ/GND 330
3 1
Vout=0.8*(1+R1/R2) 1%
2
OUTPUT
R541
Multi Power(5V -->3.3V)
1%
110
C545 C542
22uF 0.1uF
10V 16V
S7 DDR 1.5V
R527 0
S7M DDR 1.5V RL_ON
close to tuner
+5V_ST
1074 mA +3.3V_AVDD
P_+5V
L514
IC501 MLB-201209-0120P-N2
L503 C536 MP8706EN-C247-LF-Z +1.26V_VDDC
100pF
CIC21J501NE 50V
Vout=0.8*(1+R1/R2) C570
IN GND 0.1uF
1 8 16V
Replaced Part +1.5V_DDR_IN C526
C523 0 . 1 u F
+5V
C520 SW_1 VCC
1uF 10uF 2 7
R509 R1 25V 16V

SW_2
3
3A 6
FB
R530
62K
R531
3.3K
R515
200
IC504
AZ1085S-3.3TR/E1
+3.3V
IC502
10K 1% C528 650 mA
0.1uF C534
MP2212DN Close to IC BST EN/SYNC 1% 1% 1% 10uF
C531
22uF
INPUT 3 MAX 3A 2 OUTPUT
4 5 10V $0.122
R516
10V
1
39K
1K
FB EN/SYNC R500 ADJ/GND R546
R505
1 8 POWER_ON/OFF1 C553 C558 1K C569 C575 C581 C587
47uF
C588
11K L504 10uF 0.1uF 10uF 0.1uF 10uF 47uF
R518
1.2K
R2 16V 16V
1/10W GND SW_2 3.6uH 16V 16V A2[RD] A1[GN] 6.3V 16V 6.3V
5% 2
3A 7
NR8040T3R6N
L519
3.6uH D501
SAM2333
C
IN SW_1 C539
Placed on SMD-TOP 3 6 C540
S7 core 1.26V
0.1uF
22uF
BS VCC
10V For Debug
4 5 C537
C535
22uF 0.1uF
10V 50V Placed on SMD-TOP R1 R2
R501 0 1.26V 40.2K 71.5K
R503 1.2V 40.2K 82.5K
10 C538
1/10W 1uF 1.29V 40.2K 65.5K
1% 10V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 5 13
S_POWER

L323
+1.26V_VDDC VDDC
BLM18PG121SN1D VDDC
IC101
LGE101D (S7 Non_Tcon/RM)
C383 C380
C304 VDDC
10uF 0.1uF C309 C313 C321 C328 C335 C344 C349 C353
16V 16V C338 C341
6.3V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF H11 G18
VDDC_1 GND_1
H12 H9
VDDC_2 GND_2
H13 H10
VDDC_3 GND_3
H14 H18
VDDC_4 GND_4
VDDC H15 H19
+1.26V_VDDC +1.26V_MIU1VDDC J12
VDDC_5 GND_5
J10
VDDC_6 GND_6
L321 J13 J17
BLM18SG121TN1D VDDC_7 GND_7
J14 J18
VDDC_8 GND_8
J15 J19
C327 C333 C337 C340 C343 C381 VDDC_9 GND_9
16V C346 C351 C357 C363 C384 J16 K9
16V 16V 16V 16V 16V 16V 10uF VDDC_10 GND_10
0.1uF 0.1uF 16V 16V 16V L18 K10
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 6.3V 0.1uF VDDC_11 GND_11
K11
+1.26V_MIU0VDDC GND_12
+1.26V_MIU1VDDC H16 K12
A_DVDD GND_13
K19 K13
B_DVDD GND_14
VDDC K14
GND_15
L19 K15
VDDC_12 GND_16
M18 K16
VDDC_13 GND_17
M19 K17
+1.26V_VDDC +1.26V_MIU0VDDC VDDC_14 GND_18
N18 K18
L324 VDDC_15 GND_19
AVDD2P5_2.5 N19 L9
BLM18SG121TN1D VDDC_16 GND_20
N20 L10
+2.5V_AVDD L303 VDDC_17 GND_21
P18 L11
Place to S7m closely C386 VDDC_18 GND_22
BLM18PG121SN1D C385 P19 L12
10uF 16V VDDC_19 GND_23
6.3V 0.1uF P20 L13
VDDC_20 GND_24
C334 L14
C314 C322 C329 GND_25
16V 16V 16V 10uF Y12 L15
0.1uF 0.1uF 0.1uF 6.3V NC_13 GND_26
L16
GND_27
L17
GND_28
J11 M9
AVDD1P2 GND_29
L7 M10
DVDD_NODIE GND_30
C379 ADC2P5_2.5 M11
AVDD25_PGA_2.5 16V GND_31
L304 M12
0.1uF GND_32
BLM18PG121SN1D Place to S7m closely H7 M13
AVDD2P5_ADC_1 GND_33
J7 M14
AVDD2P5_ADC_2 GND_34
J8 M15
VDD33_3.3 Place to S7m closely AVDD25_REF GND_35
C315 M16
16V GND_36
AU25_2.5 M17
0.1uF GND_37
L8 N10
AVDD_AU25 GND_38
N11
C336 C339 C342 C345 C350 C356 C361 GND_39
16V C354 C371 N12
16V 16V 16V 16V 16V 10uF 10uF 22uF AVDD2P5_2.5
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND_40
AU25_2.5 0.1uF 6.3V 6.3V 16V W15 N13
L305 PVDD_1 GND_41
Y15 N14
BLM18PG121SN1D PVDD_2 GND_42
AVDD25_PGA_2.5 N15
GND_43
Place to S7m closely U8 N16
AVDD25_PGA GND_44
AVDD_NODIE_3.3 N17
GND_45
C317 P10
16V GND_46
M8 P11
0.1uF AVDD_NODIE GND_47
P12
GND_48
VDD33_DVI P13
GND_49
N9 P14
ADC2P5_2.5 AVDD_DVI_1 GND_50
L306 P9 P15
AVDD_DVI_2 GND_51
BLM18PG121SN1D N8 P16
AVDD_DMPLL_3.3 AVDD3P3_CVBS GND_52
P8 P17
AVDD_DMPLL GND_53
R10
Place to S7m closely AU33_3.3 GND_54
R11
C316 C323 GND_55
16V T7 R12
16V AVDD_AU33 GND_56
0.1uF 0.1uF U7 R13
AVDD_EAR33 GND_57
R14
VDD33_3.3 GND_58
R15
GND_59
T9 R16
AVDD33_T GND_60
R17
+3.3V_AVDD VDD33_DVI GND_61
AVDD_DMPLL_3.3 R8 R18
VDDP_1 GND_62
L310 L318 R9 T10
+1.5V_DDR_IN VDDP_2 GND_63
BLM18PG121SN1D Place to S7m closely BLM18PG121SN1D T8 T11
AVDD_DDR0_1.5 VDDP_3 GND_64
L300 T12
GND_65
BLM18PG121SN1D T13
Place to S7m closely C377 GND_66
C347 C352 C358 C362 V20 T14
16V 16V
16V 16V 10uF 0.1uF NC_5 GND_67
0.1uF 0.1uF 0.1uF 6.3V W20 T15
NC_8 GND_68
T16
C301 C306 C310 C318 C324 C332 GND_69
16V 16V 16V 16V 10uF U19 T17
0.1uF 10uF NC_2 GND_70
0.1uF 0.1uF 0.1uF 6.3V U20 T18
6.3V
NC_3 GND_71
V19 T19
NC_4 GND_72
FRC_LPLL_3.3 U10
L308 AVDD_NODIE_3.3 GND_73
W19 U11
BLM18PG121SN1D NC_7 GND_74
U18 U12
AVDD_DDR1_1.5 AVDD_LPLL GND_75
T20 U13
L301 C348 Place to S7m closely NC_1 GND_76
U14
BLM18PG121SN1D Place to S7m closely 16V GND_77
0.1uF Y14 U15
NC_14 GND_78
U16
GND_79
VDD33_3.3 U17
C302 C307 C311 C319 C325 C330 GND_80
16V V7
16V 16V 16V 10uF 10uF GND_81
0.1uF 0.1uF VDD33_3.3 R19 V8
0.1uF 0.1uF 6.3V 6.3V L309
AVDD_MEMPLL GND_82
BLM18PG121SN1D W14 V9
NC_6 GND_83
AVDD_DDR0_1.5 V10
GND_84
V11
GND_85
D15 V12
AVDD_DDR0_D_1 GND_86
D16 V13
E15 V14
E16 V15
AU33_3.3 AVDD_DDR0_D_4 GND_89
L314 AVDD_DDR1_1.5 E17 V16
AVDD_DDR0_C GND_90
BLM18PG121SN1D Place to S7m closely V17
GND_91
F16 V18
F17 W7
C366 C374 C375 AVDD_DDR1_D_2 GND_93
16V 10uF G16 W8
16V AVDD_DDR1_D_3 GND_94
0.1uF 0.1uF 6.3V G17 W9
H17 W10
AVDD_DDR1_C GND_96
W11
GND_97
W12
FRC_LPLL_3.3 GND_98
AB11 W13
L316 NC_22 GND_99
AB12 W16
AVDD_DDR0_1.5 BLM18PG121SN1D NC_23 GND_100
MVREF AC11 W17
NC_27 GND_101
R300 AC12 W18
1K C368 NC_28 GND_102
AA12 Y13
16V NC_18 GND_103
1% 0.1uF Y18
GND_104
R301 AA13
1K MVREF GND_106
AB13
1% GND_107
AC13
GND_108
G15 D17
MVREF GND_109
H23
GND_110
AF13
GND_111
Y7 J9
NC_9 GND_FU
Y8 U9
NC_10 PGA_VCOM
L320
BLM18PG121SN1D

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Main IC Power 3 13
ER_BLOCK

IC101
MUST BE LINE IMPEADANCE 100 OHM !! MODEL OPTION +3.3V
F1 W2
A_RXCP VIFP
R253 3.3K
3.3K
3.3K
R268 3.3K
R271 3.3K
R274 3.3K
R277 3.3K
F2 W1
A_RXCN VIFM
G2
42INCH
READY
READY
READY
FHD
A_RX0P
LCD
G3 V2 R228 22
R266
A_RX0N IP
R264
H3 V1 R229 22
A_RX1P IM
G1
A_RX1N R260 100
H1 Y2 C252 0 . 1 u F R246 47 MODEL_OPT_0
A_RX2P SSIF/SIFP TUNER_SIF 100
H2 Y1 C253 0 . 1 u F R247 47 C256 FE_BOOSTER_CTL R261 MODEL_OPT_1
R248
A_RX2N SSIF/SIFM 1000pF 300 R262 100
F5 2K RF_SWITCH_CTL MODEL_OPT_2
DDCDA_DA/GPIO24 READY READY READY 100
F4 U3 C234 0 . 1 u F R203 R263 MODEL_OPT_3
E6
DDCDA_CK/GPIO23 QP
V3
Close to IC
C235 0.1uF READY
HOTPLUGA/GPIO19 QM as close as possible R278 22
READY R204 2K +3.3V MODEL_OPT_4
R279 22
D3 Y5 R258 10K MODEL_OPT_5
READY
READY
CK+_HDMI2 B_RXCP IFAGC
R249
R250
4.7K
4.7K
C1 Y4 READY
CK-_HDMI2 B_RXCN RF_TAGC R252 22
D1 MODEL_OPT_6
D0+_HDMI2 B_RX0P R147 22 READY
D2 U1
D0-_HDMI2 B_RX0N TGPIO0/UPGAIN SCL1
E2 U2 R148 22 CH_5
D1+_HDMI2 B_RX1P TGPIO1/DNGAIN SDA1
3.3K
3.3K
3.3K
3.3K
3.3K
3.3K
3.3K
E3 R3 TU_SCL
D1-_HDMI2 B_RX1N TGPIO2/I2C_CLK
READY
50INCH
F3 T3 CH_6
READY
READY
READY
D2+_HDMI2 TU_SDA
PDP
HD
B_RX2P TGPIO3/I2C_SDA
E1
GND_C
D2-_HDMI2
R267
R254
B_RX2N
R265
R269
R272
R275
R276
D4 T2
DDC_SDA_2 DDCDB_DA/GPIO26 XTALIN C257 24pF
R227
E4 T1 X200
1M
DDC_SCL_2 DDCDB_CK/GPIO25 XTALOUT 24MHz
D5 L200
HPD2 HOTPLUGB/GPIO20
READY
22 C258 24pF L201
HDMI
AA2 G14 R158

CK+_HDMI4 C_RXCP SPDIF_IN/GPIO177 AMP_SDA
AA1 G13 R207 100
CK-_HDMI4 C_RXCN SPDIF_OUT/GPIO178 SPDIF_OUT
AB1
D0+_HDMI4 C_RX0P
AA3
D0-_HDMI4
AB3
C_RX0N
B7
MODEL OPTION
D1+_HDMI4 C_RX1P DM_P0 USB2_DM_to_MAIN
AB2 A7
D1-_HDMI4 C_RX1N DP_P0 USB2_DP_to_MAIN
AC2 PIN NAME PIN NO. HIGH LOW
D2+_HDMI4 C_RX2P
AC1 AF17
D2-_HDMI4 C_RX2N DM_P1 USB1_DM_to_MAIN MODEL_OPT_0 D6 LCD PDP
AB4 AE17
DDC_SDA_4 DDCDC_DA/GPIO28 DP_P1 USB1_DP_to_MAIN
AA4
DDC_SCL_4 DDCDC_CK/GPIO27 MODEL_OPT_1 D7 42INCH 50INCH
AC3
HPD4 HOTPLUGC/GPIO21
F14 R159 22 MODEL_OPT_2 E11 LED_NORMAL LED_MOVING
I2S_IN_BCK/GPIO175 SUB_SDA_NEC_TEMP
A2 F13
CK+_HDMI3 D_RXCP I2S_IN_SD/GPIO176 COMP2_DET
A3 F15 R160 22 MODEL_OPT_3 B9 FHD HD
CK-_HDMI3 D_RXCN I2S_IN_WS/GPIO174 SUB_SCL_NEC_TEMP
B3
D0+_HDMI3 D_RX0P
A1 D20 R208 22
D0-_HDMI3 D_RX0N BIT CLOCK I2S_OUT_BCK/GPIO181 MS_SCK
R209 22
IIS
B1 E20
D1+_HDMI3 D_RX1P MASTER CLOCK I2S_OUT_MCK/GPIO179 AUDIO_MASTER_CLK IC101
B2 D19 R210 22
D1-_HDMI3 D_RX1N SERIAL DATA I2S_OUT_SD/GPIO182 R211 22 MS_LRCH LGE101D (S7 Non_Tcon/RM)
C2 F18
D2+_HDMI3 D_RX2P I2S_OUT_SD1/GPIO183 MS_LRCK
C3 E18
D2-_HDMI3 D_RX2N I2S_OUT_SD2/GPIO184 MODEL_OPT_4
B4 D18
DDC_SDA_3 DDCDD_DA/GPIO30 I2S_OUT_SD3/GPIO185 MODEL_OPT_5 AE1 W26
C4 E19 R149 22 NC_48 LVACLKP/LLV6P/BLUE[3] RXACK+
DDC_SCL_3 DDCDD_CK/GPIO29 I2S_OUT_WS/GPIO180 AMP_SCL AF16 W25
E5 WORD SELECT NC_78 LVACLKN/LLV6N/BLUE[2] RXACK-
HPD3 READY AF1 U26
HOTPLUGD/GPIO22 RXA0+
R153 0 D6 NC_64 LVA0P/LLV3P/BLUE[9]
HDMI_CEC_S7 CEC/GPIO5 AE3 U25
N1 C236 2.2uF NC_50 LVA0N/LLV3N/BLUE[8] RXA0-
COMP1_LIN AD14 U24
LVDS OUT
R143 R146 LINE_IN_0L RXA1+
P3 C237 2.2uF NC_45 LVA1P/LLV4P/BLUE[7]
10K 10K LINE_IN_0R COMP1_RIN AD3 V26
R163 22 G5 P1 C238 2.2uF NC_34 LVA1N/LLV4N/BLUE[6] RXA1-
DSUB_HSYNC HSYNC0 LINE_IN_1L AV_LIN AF15 V25
DSUB
G6 P2 C239 2.2uF NC_77 LVA2P/LLV5P/BLUE[5] RXA2+
AUDIO IN
R164 22 AF2 V24
DSUB_VSYNC VSYNC0 LINE_IN_1R AV_RIN
R166 33 C215 0.047uF K1 P4 C240 2.2uF NC_65 LVA2N/LLV5N/BLUE[4] RXA2-
DSUB_R RIN0P LINE_IN_2L SIDE_LIN AE15 W24
R167 68 C216 0.047uF L3 P5 C241 2.2uF NC_62 LVA3P/LLV7P/BLUE[1] RXA3+
DSUB_R- RIN0M LINE_IN_2R SIDE_RIN AD2 Y26
R168 33 C203 0.047uF K3 R6 C242 2.2uF NC_33 LVA3N/LLV7N/BLUE[0] RXA3-
DSUB_G GIN0P LINE_IN_3L COMP2_LIN AD16 Y25
R169 68 C217 0.047uF K2 T6 C243 2.2uF NC_47 LVA4P/LLV8P RXA4+
DSUB_G- GIN0M LINE_IN_3R COMP2_RIN AD15 Y24
R170 33 C218 0.047uF J3 U5 C244 2.2uF NC_46 LVA4N/LLV8N RXA4-
DSUB_B BIN0P LINE_IN_4L PC_LIN AE16
R171 68 C219 0.047uF J2 V5 C245 2.2uF NC_63
DSUB_B- BIN0M LINE_IN_4R PC_RIN
R172 0 C204 1000pF J1 U6 C246 2.2uF
SOGIN0 LINE_IN_5L AC26
V6 C247 2.2uF LVBCLKP/LLV0P/GREEN[5] RXBCK+
LINE_IN_5R AC25
LVBCLKN/LLV0N/GREEN[4] RXBCK-
AA26
R139 33 G4 LVB0P/RLV6P/RED[1] RXB0+
HSYNC1 AF3 AA25
RXB0-
COMPONENT 1/2
R194 33 H6 U4 NC_66 LVB0N/RLV6N/RED[0]

VSYNC1 LINE_OUT_0L AF14 AA24
R173 33 C220 0.047uF K5 W3 NC_76 LVB1P/RLV7P/GREEN[9] RXB1+
COMP1_Pr+ RIN1P LINE_OUT_2L AD1 AB26
R174 68 C221 0.047uF K4 W4 NC_32 LVB1N/RLV7N/GREEN[8] RXB1-
AUDIO OUT
COMP1_Pr- RIN1M LINE_OUT_3L AB25

R175 33 C222 0.047uF J4 V4 LVB2P/RLV8P/GREEN[7] RXB2+
COMP1_Y+ GIN1P LINE_OUT_0R AD13 AB24
R176 0.047uF K6 Y3 NC_44 LVB2N/RLV8N/GREEN[6] RXB2-
COMP1_Y- 68 C223
GIN1M LINE_OUT_2R N/A AE14 AC24
R177 33 C224 0.047uF H4 W5 NC_61 LVB3P/LLV1P/GREEN[3] RXB3+
COMP1_Pb+ BIN1P LINE_OUT_3R AE13 AD26
R178 68 C225 0.047uF J6 NC_60 LVB3N/LLV1N/GREEN[2] RXB3-
COMP1_Pb- BIN1M AD25
R179 0 C205 1000pF J5 R4 LVB4P/LLV0P/GREEN[1] RXB4+
SOGIN1 MIC_DET_IN AD24
T5 LVB4N/LLV0N/GREEN[0] RXB4-
MICCM AE4
R5 NC_51
MICIN AD5
H5 NC_36
HSYNC2 AF4 AD23
R180 33 C206 0.047uF N3 T4 NC_67 RLV3P/RED[7]
COMP2_Pr+ RIN2P AUCOM AD4 AE23
R181 68 C207 0.047uF N2 NC_35 RLV3N/RED[6]
COMP2_Pr- RIN2M AE26
R182 33 C208 0.047uF M2 P7 RLV0P/LVSYNC
COMP2_Y+ GIN2P VRM AE2 AE25
R183 68 C209 0.047uF M1 C248 4.7uF Close to IC NC_49 RLV0N/LHSYNC
FRC PART
COMP2_Y- GIN2M AF26
R184 33 C210 0.047uF L2 R7 C249 1uF as close as possible RLV1N/LCK
AF25
COMP2_Pb+ BIN2P VAG
R185 68 C211 0.047uF L1 P6 C250 10uF RLV2P/RED[9]
COMP2_Pb- BIN2M VRP AF8 AE24
R186 0 C212 1000pF M3 C251 0.1uF NC_71 RLV1P/LDE
SOGIN2 AD9 AF24
R1 NC_40 RLV2N/RED[8]
HP_OUT_1L AF23
R2 RLV4P/RED[5]
HP_OUT_1R AE9 AD22
TV/MNT CVBS
R154 33 C213 0.047uF N4 NC_56 RLV4N/RED[4]

TUNER_CVBS CVBS0P AF9 AE22
R155 33 C214 0.047uF N6 NC_72 RLV5P/RED[3]
CVBS1P AF22
R187 33 C226 0.047uF L4 E21 RLV5N/RED[2]
AV_CVBS_IN CVBS2P ET_RXD0 AE11
R188 33 C227 0.047uF L5 E22 NC_58
SIDE_CVBS_IN CVBS3P ET_TXD0 AF6
R189 33 C228 0.047uF L6 NC_69
CVBS4P AD19
R141 C201 R190 33 C229 0.047uF M4 D21 TCON3/OE/GOE/GCLK2
CVBS5P ET_RXD1 AE6 AE19
300 1000pF R191 33 C230 0.047uF M5 F21 NC_53 TCON15/SCAN_BLK1
READY READY CVBS6P ET_TXD1 AF11 AD21
R192 33 C231 0.047uF K7 NC_74 TCON18/CS7/GCLK5
CVBS7P AD6 AE21
E23 NC_37 TCON19/CS8/GCLK6
ET_REFCLK AD12 AF21
M6 D22 NC_43 TCON11/CS5/HCON
CVBS_OUT1 ET_TX_EN AE5 AD20
M7 F22 NC_52 TCON10/CS4/OPT_N
N/A CVBS_OUT2 ET_MDC AF12 AE20
D23 NC_75 TCON9/CS3/OPT_P
ET_MDIO AF5 AF20
R156 68 C233 0.047uF N5 F23 NC_68 TCON16/WPWM
VCOM0 ET_CRS AE12 AF19
NC_59 TCON12/DPM
AD18
TCON1/STV/GSP/VST
AE10 AE18
F8 NC_57 TCON5/TP/SOE
AVLINK AF7 AF18
G8 R242 0 READY NC_70 TCON14/SACN_BLK
IRINT IR AD11
K8 R243 0 NC_42
TESTPIN AD7
A4 NC_38
RESET SOC_RESET AD10 AB22
NC_41 TCON21/CS10/VGH_ODD
MINILV
Y17
NC_16 AE7 AB23
R273 NC_54 TCON20/CS9/VGH_EVEN
AF10 AC23
10K NC_73 TCON13/LEDON
READY AD8 AC22
NC_39 TCON17/CS6/GCLK4
AB16
NC_26
AA14
NC_19
AC15
NC_30
S7 RESET CIRCUIT Y16
NC_15
AC16
*Active High reset NC_31
AE8 AC14
NC_55 NC_29
+3.3V
Y11 AA16
NC_12 NC_21
Y19 AA15
GND_105 NC_20
C200 Y10
4.7uF NC_11
10V AA11
R145 R165 NC_17
READY 10 22
READY AB15
READY NC_25
SOC_RESET AB14
NC_24
D200 R142 C202

KDS181 62K 0.1uF
READY READY 16V
READY

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AV IN_OUT/EXPANDER 2 13

IC101
250_350
HYNIX 2GBit(8) Flash +3.3V
U22
T21
PCM_D0 TCON0/POL
N21
M21
PCM_D1 TCON2/GSP_R/GCLK1 5V_DET_HDMI_2
T22 L22
5V_DET_HDMI_4
/PF_CE0
H : Serial Flash
IC104
HY27UF082G2B-TPCB
L102 S7 IC Configuration AB18
AC18
PCM_D2
PCM_D3
TCON4/CPV/GSC/GCLK3
TCON6/FLK
L21
P21
5V_DET_HDMI_3
L : NAND Flash PCM_D4 TCON8/CS2/FLK3 SIDE_CVBS_DET

+3.3V AC19
/PF_CE1 PCM_D5
H : 16 bit NC_1 NC_29 AC20
L : 8 bit 1 48 PCM_D6
1K PCM_A[0-7] AC21 K21
READY R38 PCM_D7 GPIO36/UART3_RX
NC_2 NC_28 PWM0 L23
2 47 GPIO37/UART3_TX
PCM_A[0-7] R33 1K PCM_A[0] U21 K20
NC_3 NC_27 PCM_A0 GPIO38
3 46 READY R39 1K PCM_A[1] V21 L20 R88 100
PWM1 V4 LGD BIT SEL PCM_A1 GPIO39
NC_4 NC_26 PCM_A[2] Y22 M20
4 45 R34 1K READY PCM_A2 GPIO40
H or NC : 10 bit PCM_A[3] COMP1_DET
R16 R19 NC_5 I/O7 PCM_A[7] R40 1K AA22 G20 R89 22READY
5 44 L : 8 bit PCM_A[4] PCM_A3 GPIO41
1K 3.9K AUDIO_MASTER_CLK R22 G19 R96 22
NC_6 I/O6 PCM_A[6] R35 1K READY PCM_A[5] PCM_A4 GPIO42 MODEL_OPT_0
6 43 R21
R41 1K PCM_A[6] PCM_A5
R/B I/O5 PCM_A[5] V4 LGD LVDS SEL T23 F20 R97 33
7 42 MS_SCK PCM_A[7] PCM_A6 GPIO50/UART1_RX MOD_ROM_RX
/F_RB R36 L or NC : VESA T24 F19 R98 33
1K READY PCM_A7 GPIO51/UART1_TX MOD_ROM_TX
RE I/O4 PCM_A[4] AA23 C19
8 41 R42 1K H : JEIDA C18
/PF_OE PCM_A8 10pF READY
Y20 E7 READY 10pF
CE NC_25 MS_LRCH PCM_A9 GPIO6/PM0/INT0 USB1_OCD
/PF_CE0 9 40 R37 1K AB17 D7
NC_7 NC_24 C6 PCM_A10 GPIO7/PM1/PM_UART_TX USB1_CTL
10 39 V4 LGD OPC AA21 E11
10uF PCM_A11 GPIO8/PM2
R17 NC_8 NC_23 6.3V U23 G9 READY
C4 L or NC : DISABLE PCM_A12 GPIO9/PM3
1K 11 38 Y23 F9
READY 0.1uF H : ENABLE R101 22
VCC_1 VCC_2 PCM_A13 GPIO10/PM4 MODEL_OPT_6
12 37 W23 C5 R90 22
PCM_A14 GPIO11/PM5/PM_UART_RX/INT1 MODEL_OPT_1
VSS_1 VSS_2 C7 0 . 1 u F E8
+3.3V 13 36 BIT_SEL,LVDS_SE : LCD MODULE OPT PM_SPI_CS1/GPIO12/PM6
W22 E9
NC_9 NC_22 PCM_REG_N PM_SPI_WP1/GPIO13/PM7 /FLASH_WP
R10 14 35 <T3 CHIP Config(AUD_LRCH)> OPC: Optimal power control FOR PICTURE F7 R80 22
PM_SPI_WP2/GPIO14/PM8/INT2 MODEL_OPT_2
NC_10 NC_21 Boot from SPI flash : 1’b0 AA17 F6
1K AFLC: LED TV OPTION PCM_OE_N GPIO15/PM9 TUNER_RESET
15 34 Boot from NOR flash : 1’b1 V22 D8
READY DEMOD_RESET
CLE NC_20 <CHIP_CONF={AUBCK_OUT,AUMCK_OUT,PWM1,PWM0}> PCM_WE_N PM_SPI_CS2/GPIO16/PM10
16 33 W21 G12
/PF_CE1 1.CHIP_CONF= 4’h3:{0,0,1,1}MIPS_no_EJ_NOR8 PCM_IORD_N GPIO17/PM11/INT3 AV_CVBS_DET
R8 Y21 F10
ALE I/O3 PCM_A[3] 2.CHIP_CONF= 4’h4:{0,1,0,0}MIPS_EJ1_NOR8 PCM_IOWR_N GPIO18/PM12/INT4
10K 17 32
PF_ALE 3.CHIP_CONF= 4’h5:{0,1,0,1}MIPS_EJ2_NOR8 R92 33 /SPI_CS
WE I/O2 PCM_A[2] 4.CHIP_CONF= 4’hB:{1,0,1,1}B51_Secure_no_scramble AA20 D9
R4 18 31 R81 33 SPI_CK
/PF_WE 5.CHIP_CONF= 4’hC:{1,1,0,0}B51_Secure_scramble PCM_CE_N PM_SPI_CK/GPIO1
0 WP I/O1 PCM_A[1] V23 D11
19 30 PCM_IRQA_N GPIO0/PM_SPI_CZ
PF_WP 1.MIPS as host(8051’s reset remains until MIPS deactive it.),No EJ PAD,Byte mode NAND flash P23 E10 R82 33 SPI_DI
R12 NC_11 I/O0 PCM_A[0] 2.MIPS as host,EJ use PAD1,Byte mode NAND flash PCM_CD_N PM_SPI_DI/GPIO2
20 29 R23 D10 R83 33 SPI_DO
1K 3.MIPS as host,EJ use PAD2,Byte mode NAND flash PCM_WAIT_N PM_SPI_DO/GPIO3
R3 NC_12 NC_19 P22
4.8051 as host,Internal SPI flash secure boot,no scramble PCM_RESET
10K 21 28 5.8051 as host,Internal SPI flash secure boot with scramble AR103
READY NC_13 NC_18 AA9
22 27 TS0_CLK
NC_14 NC_17 /PF_CE0 AC17 AA5
23 26 PCM_PF_CE0Z TS0_VLD
/PF_CE1 AB20 AA10
NC_15 NC_16 PCM_PF_CE1Z TS0_SYNC
24 25 /PF_OE AA18
22 PCM_PF_OEZ
/PF_WE AR102 AB21 AB5
PCM_PF_WEZ TS0_D0
PF_ALE AB19 AC4
PCM_PF_ALE TS0_D1
PF_WP AD17 Y6
PCM_PF_AD[15] TS0_D2
NAND-2G_HYNIX /F_RB AA19 AA6
PCM_PF_RBZ TS0_D3
22 W6
TS0_D4
AA7
TS0_D5
R52 33 M23 Y9
S7_TXD UART_TX2/GPIO65 TS0_D6
R53 33 N23 AA8
1MB serial Flash PJ230 S7_RXD UART_RX2/GPIO64 TS0_D7
NAND_1G_NUMONYX_NEW NAND_1G_HYNIX I2C_SDA

R55 33 M22 AC5 R104 22
FE_TS_CLK
DDCR_DA/GPIO71
Serial FLASH MEMORY IC104-*1
IC104-*3
IC101-*1
LGE101 (S7 NON_TON/DiX/RM)
CH_2 R54 33 N22
TS1_CLK
AC6 R136 22
I2C_SCL FE_TS_VLD
NAND01GW3B2CN6E
DDCR_CK/GPIO72
for BOOT TS1_VLD
H27U1G8F2BTR-BC
+3.3V
AE1 W26
NC_48 LVACLKP/LLV6P/BLUE[3]
AB6 R18
NC_1 NC_29 AF16 W25
+3.3V 22
1 48 NC_1 NC_29 NC_78 LVACLKN/LLV6N/BLUE[2]
1 48 AF1 U26
NC_2 NC_28 NC_64 LVA0P/LLV3P/BLUE[9]
2 47 NC_2 NC_28 AE3 U25
FE_TS_SYN
2 47 NC_50 LVA0N/LLV3N/BLUE[8]
IC103 TS1_SYNC
NC_3 NC_27 AD14 U24
3 46 NC_3 NC_27 NC_45 LVA1P/LLV4P/BLUE[7]
3 46 AD3 V26
NC_4 NC_26 NC_34 LVA1N/LLV4N/BLUE[6]
A5
4 45 NC_4 NC_26 AF15 V25
4 45 NC_77 LVA2P/LLV5P/BLUE[5]
NC_5 I/O7 AF2 V24
5 44 NC_5 I/O7 NC_65 LVA2N/LLV5N/BLUE[4]
5 44 AE15 W24
RGB_DDC_SDA
NC_6 I/O6 NC_62 LVA3P/LLV7P/BLUE[1]
MX25L8005M2I-15G DDCA_DA/UART0_TX
6 43 NC_6 I/O6 AD2 Y26
6 43 NC_33 LVA3N/LLV7N/BLUE[0]
RB I/O5 AD16 Y25
7 42 R/B I/O5 NC_47 LVA4P/LLV8P
B5 AC10 R28
7 42 AD15 Y24
22
R I/O4 NC_46 LVA4N/LLV8N
CH_8
8 41 RE I/O4 AE16
8 41 NC_63
RGB_DDC_SCL
E NC_25
9 40
DDCA_CK/UART0_RX
CE NC_25
TS1_D0 FE_TS_SERIAL
9 40 AC26
NC_7 NC_24 LVBCLKP/LLV0P/GREEN[5]
10 39 NC_7 AC25
C5
NC_24
10 39 LVBCLKN/LLV0N/GREEN[4]
AB10
NC_8 NC_23 AA26
11 38
4.7K
4.7K
NC_8 NC_23 LVB0P/RLV6P/RED[1]

11 38 AF3 AA25
VDD_1 VDD_2 NC_66 LVB0N/RLV6N/RED[0]
12 37 VCC_1 VCC_2 AF14 AA24
R11
12 37 NC_76 LVB1P/RLV7P/GREEN[9]
0.1uF TS1_D1
VSS_1 VSS_2 AD1 AB26
13 36 VSS_1 VSS_2 NC_32 LVB1N/RLV7N/GREEN[8]
13 36 AB25
NC_9 NC_22
BRAZIL DEMOD OPT

LVB2P/RLV8P/GREEN[7]
R5
AC9
14 35 NC_9 NC_22 AD13 AB24
14 35 NC_44 LVB2N/RLV8N/GREEN[6]
NC_10 NC_21
16V
AE14 AC24
15 34 NC_10 NC_21 NC_61 LVB3P/LLV1P/GREEN[3]
CS# VCC
15 34 AE13 AD26
CL NC_20 NC_60 LVB3N/LLV1N/GREEN[2]
TS1_D2
16 33 CLE NC_20 AD25
16 33 LVB4P/LLV0P/GREEN[1]
AL I/O3 AD24
1 8
17 32 ALE I/O3 LVB4N/LLV0N/GREEN[0]
R56 K23 AB9

17 32 AE4
/SPI_CS 22
W I/O2 NC_51
18 31 WE I/O2 AD5
18 31 NC_36
PWM0
WP I/O1 AF4 AD23
/FLASH_WP
19 30 NC_67 RLV3P/RED[7]
PWM0/GPIO66
WP I/O1
TS1_D3
19 30 AD4 AE23
NC_11 I/O0 NC_35 RLV3N/RED[6]
20 29 AE26
+3.3V
NC_11 I/O0
20 29 RLV0P/LVSYNC
R57 K22 AC8

NC_12 NC_19 AE2 AE25
22
21 28 NC_12 NC_19 NC_49 RLV0N/LHSYNC
21 28 AF26
NC_13 NC_18 RLV1N/LCK
22 27 NC_13 NC_18 AF25
RLV2P/RED[9]
PWM1/GPIO67
22 27
PWM1 TS1_D4
NC_14 NC_17 AF8 AE24
23 26 NC_14 NC_17 NC_71 RLV1P/LDE
AD9 AF24
SO
23 26
HOLD# 22PWM2
NC_15 NC_16 NC_40 RLV2N/RED[8]
R58 G23 AB8

24 25 NC_15 NC_16 AF23
READY
24 25 RLV4P/RED[5]
AE9 AD22
NC_56 RLV4N/RED[4]
2 7
AF9 AE22
NC_72 RLV5P/RED[3]
SPI_DO PWM2/GPIO68 TS1_D5

AF22
R9
RLV5N/RED[2]
AE11
NC_58
22 G22 AC7
AF6
R129 READY
NC_69
AD19
TCON3/OE/GOE/GCLK2
AE6 AE19
10K
NC_53 TCON15/SCAN_BLK1
R1 PWM3/GPIO69 TS1_D6
AF11 AD21
AD6 AE21
22 G21 AB7
AD12 AF21
R130 READY
NC_43 TCON11/CS5/HCON
AE5 AD20
NC_52 TCON10/CS4/OPT_N
0 WP# SCLK
AF12 AE20
NAND_1G_NUMONYX_OLD
NC_75 TCON9/CS3/OPT_P
PWM4/GPIO70 TS1_D7
AF5 AF20
NC_68 TCON16/WPWM
AE12 AF19
3 6
NC_59 TCON12/DPM
AD18
SPI_CK
TCON1/STV/GSP/VST
AE10 AE18
NC_57 TCON5/TP/SOE
AF7 AF18
NC_70 TCON14/SACN_BLK
AD11
NC_42
AD7
C
NC_38
AD10 AB22
NC_41 TCON21/CS10/VGH_ODD
R2
AE7 AB23
IC104-*2 NC_54 TCON20/CS9/VGH_EVEN
NAND01GW3A2CN6E AF10 AC23
NC_73 TCON13/LEDON
AD8 AC22
0 Q101 GND SI C6 D12

NC_1 NC_29
B
1 48
AB16
NC_2 NC_28 NC_26
4 5
2 47 AA14
NC_19
SPI_DI SAR0/GPIO31 MPIF_CLK

NC_3 NC_27 AC15
KRC103S DSUB_DET
3 46 NC_30
NC_4 NC_26
B6 D14
4 45 Y16
NC_15
NC_5 I/O7 AC16
READY
5 44 NC_31
READY
AE8 AC14
NC_6 I/O6 NC_55 NC_29
SAR1/GPIO32 MPIF_CS_N
6 43
RB
MODEL_OPT_3
I/O5 Y11 AA16
R46 22
7 42 NC_12 NC_21
C8
Y19 AA15
R I/O4 GND_105 NC_20
8 41
E
E NC_25 Y10
9 40 NC_11
SAR2/GPIO33
NAND FLASH MULTI LIST
AA11
NC_7 NC_24 NC_17
10 39
C7 E14 R99 1K
NC_8 NC_23 AB15
11 38 NC_25
AB14
VDD_1 VDD_2 NC_24
12 37
SAR3/GPIO34 MPIF_BUSY
VSS_1 VSS_2
13 36
NC_9 NC_22
A6
14 35
NC_10 NC_21
15 34
CL NC_20
SAR4/GPIO35
16 33
AL I/O3
17 32
E12
W I/O2
18 31
WP I/O1
19 30
MPIF_D0
NC_11 I/O0
20 29
F12
NC_12 NC_19
21 28
NC_13 NC_18
22 27
MPIF_D1
NC_14 NC_17
23 26
NC_15 NC_16
D13
NO DIVX Model _ PJ230
24 25
MPIF_D2
E13
MPIF_D3
HDCP EEPROM +3.3V

Addr:10101--
NEC SUB MICOM R75

FLMD0 AB8;AM7
IC102 ISP Port for SUB MICOM +3.3V_NEC_ST

CAT24WC08W-T 100K
R7
4.7K +3.3V_NEC_ST
A0 1 8 VCC R126
3K
A1 WP R13 4.7K C15 C16
2 7 P101 C13 C14 22pF 27pF
R14 22 12505WS-12A00
MICOM_10MHz 12pF 12pF
A2 SCL
3 6 I2C_SCL 50V 50V RESET_NEC
RS232 DEBUG SWITCH

FOR DEBUG
VSS SDA R15 22 CH_2 1
4 5 I2C_SDA
C3 +3.3V_NEC_ST
- NEC/S7/WIRELESS
RESET_NEC
2
CHECK !! STANDBY STAUTE
0.1uF X102 HALT
NEC_ISP_TXD 3
10MHz MODE
$0.199 4
X101
32.768KHz
L103
NEC_ISP_RXD 5
R86
4.7M R118 CHECK WAKE UP BY KEY !!
P122/X2/EXCLK/OCD0B
6 120K
A/B OUTPUT +3.3V_NEC_ST
P120/INTP0/EXLVI
OCD1A 7
P124/XT2/EXCLKS
IC105 R161
LOW X0 Y0 NEC
P121/X1/OCD0A
100K
MICOM MODEL OPTION
8
MC14053BDR2G C12
HIGH X1 Y1 S7M 0ISTL00024A +3.3V_NEC_ST OCD1B 9 0.1uF
EDID_WP
EEPROM
P123/XT1
ADD_BREATHING
10K
10K
10K
10K
+3.3V
10
RED_WHITE
FLMD0
RESET
READY
4.7K
4.7K
11
READY
READY
READY
I2C : A0
REGC
FLMD0
R21
R23
0.1uF
TO HDMI JACK FOR WIRELESS Y1 VDD
VDD
R59
VSS
C11
P40
P41
1 16 C
R140
R162
S7_RXD
R44
R47
12
B Q102
10K 13
2SC3052
E
R6 Y0 Y FOR DEBUG
48
47
46
45
44
43
42
41
40
39
38
37
2 15 C8 R32 100 SUB_SCL_NEC_TEMP
4.7K IC109 NEC_RXD RS232C_RXD 0.1uF AMP_RESET_N MODEL1_OPT_0
R62 22 P60/SCL0
1 36 P140/PCL/INTP6
READY M24M01-HRMN6TP R43 100 RL_ON
16V DISP_EN MODEL1_OPT_1 R63 22 P61/SDA0 2 35 P00/TI000
Z1 X R199 100 4.7K P62/EXSCL0 P01/TI010/TO00
3 14 ERROR_DET MODEL1_OPT_2 SUB_SDA_NEC_TEMP R66 3 34
NC VCC RS232C_TXD FLMD0
4.7K
1 8 MODEL1_OPT_3 R67 P63 4 33 P130 R122 10K
C1 P33/TI51/TO51/INTP4 5 IC108 32 P20/ANI0 R198 22
0.1uF Z X1 LED_WHITE SUB_SCL
10K
10K
10K
10K
E1 WP 4 13 S7_TXD UPD78F0513AGA-GAM-AX
P75 31 ANI1/P21 R138 22
RED_ONLY
2 7 6
4.7K
4.7K
5V_ON SUB_SDA
RED_ONLY
R20
R22
+5V P74 ANI2/P22 22

READY
READY
7 30 R137
E2 SCL Z0 X0 MODEL1_OPT_3 MODEL1_OPT_2
3 6 I2C_SCL 5 12 P73/KR3 8 29 ANI3/P23
MODEL1_OPT_0 POWER_ON/OFF1 +3.3V
R115
R144
R195
NEC_TXD
R45
CH_2 R25 R61 22 P72/KR2 9 28 ANI4/P24 R123 22 READY

VSS SDA 4.7K SOC_RESET
4 5 INH A R131 22 P71/KR1 10 27 ANI5/P25 R124 10K
I2C_SDA MICOM_CEC_ON/OFF
6 11 P70/KR0 ANI6/P26
11 26 R120 22
MODEL1_OPT_1 KEY2
TO HDMI JACK FOR WIRELESS P32/INTP3/OCD1B 12 25 ANI7/P27 R121 22
VEE B OCD1B KEY1
7 10 R24
512KBIT = $0.35
13
P30/INTP1 14
P17/TI50/TO50 15
P16/TOH1/INTP5 16
17
18
19
20
21
22
23
24
47K
RED ONLY RED & WHITE ADD BREATHING
P11/SL10/RXD0
P12/SO10
P31/INTP2/OCD1A
2 2 P10/SCK10/TXD0
VSS C
P15/TOH0
P13/TXD6
+3.3V_NEC_ST
P14/RXD6
AVSS
MODEL_OPT_0
AVREF
IC109-*1
M24512-HRMN6TP
8 9 0 0 1 +3.3V_NEC_ST
E0 VCC
1 8
MODEL_OPT_3 0 1 0 IC107
E1
2 7
WP
ST_NVRAM_512K M24C16-WMN6T
E2
3 6
SCL
1 8
C17 C20
VSS SDA
R60 1 NC VCC 8
C9 0.1uF 100uF
4 5
47K 0.1uF 16V
2
2 E1 WC 7
7 16V
OCD1A
22
22
22
3 6 R69 22
3 E2 SCL6
R72 R73
+3.3V_NEC_ST
0 0 READY
R100
4 5 R70 22 R26
R77
R78
4 GND SDA 5
R93
4.7K
HDMI_CEC
0IMMRSG036B
IR
R27
LED_RED
AC_DET
4.7K
NEC_ISP_RXD READY
NEC_TXD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES NEC_ISP_TXD
NEC_RXD

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. S7/FLASH/NVRAM/GPIO 1 13

< LGIT CAN H/N TUNER >
+5V_TU
L1303
MLB-201209-0120P-N2
RF_SWITCH_CTL R1343
10K
C1302
0.1uF
16V
E R1321
Pull-up can’t be applied Q1306
2.2K
because of MODEL_OPT_2 ISA1530AC1
B
C
R1344
C 10K
Q1307 B
2SC3052 FE_BOOSTER_CTL
TU1300 C1311 E
0.01uF
TDTR-T035F 25V
+5V_TU
+5V_TU
L1302
RF_S/W_CTL R1329
470
1
C1309 C1308 C1300 C1301
BST_CTL 1200pF 4.7uF 0.1uF 22uF R1332
2 50V 10V 16V +3.3V 82
TUNER_SIF
+B1[5V] E
3 R1318 C1325
R1320
3K
NC_1[RF_AGC] 3K 100pF 50V B ISA1530AC1
4 C1305
1200pF
C1314
1200pF
100 R1315 R1325
C
Q1304
50V 50V TU_SCL 4.7K
NC_2
5 100 R1316 CH_6
SCLT TU_SDA
+5V_TU
6
C1312 C1313
SDAT 47pF 47pF
7 50V 50V
R1326
1K
NC_3 R1330
8 READY 100
SIF
9
R1334
NC_4 READY R1324 0 82
10 TUNER_CVBS
+1.2V_DE E
VIDEO
11
B Q1305
GND L1301 +3.3V R1327 ISA1530AC1
12 +3.3V 1K
C
C1307 L1300
+B2[1.2V] 4.7uF C1306 R1309 R1311 READY
13 10V 0.1uF 100
100K
C1304 TUNER_RESET
+B3[3.3V] 4.7uF C1303 C1310
14 10V 0.1uF 0.1uF
16V
RESET
15
IF/AGC R1322
16 1K
DIF_1[N] C1316 ISDB_IF_AGC

17 TUNER_IF_N
0.1uF
16V
DIF_2[P]
18 TUNER_IF_P
Close to the tuner

19
SHIELD

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LGIT CAN TUNER 13 13
AN TUNER

Great Company Great People
Brazil
Brazil Basic
Basic DTV
DTV Training
Training manual
manual
Contents
- System Design
- Trouble Shooting Guide
ATSC Group Brazil Team
Last updated 2009.11.19
1. Power-Up Boot Fail Trouble Shooting
(Front-end) (System + Scalar)

Serial_Flash NANDFlash
Serial_Flash NANDFlash DDR3
DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
ISDB-T/ SIF1 CVBS_LIVE
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
KIA7427AF HDMI CEC (Stand-by)
COMP2_LR
RGB_LR EXT_IN
(Comp1/2, RGB) Reset 24C16
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
SIDE HDMI_PORT Rear USB( SVC only PJ230)
UI_HW_PORT1
HDMI_Side (C port) Side USB
Customer Oriented R&D Breakthrough

Reset Design
Active Low TAS5709

(AMP)
KIA7029AF Active Low
(Reset) Micom
GPIO Reset GPIO Reset
Active Low Tuner
Active High
S7
(Main Soc)
GPIO Reset
Demodulator
Active Low

S7 Power Sequence Appendix
Power Up Sequence
Power Note:
3.3V_AVDD_MPLL
XTAL
(AVDD_DMPLL)
t1
3.3V 1.26V (VDDC)
AVDD_DMPLL
t2
Reset 3.3V_VDDP (VDDP)
(HI Active)
t3
1.5V/1.8V (AVDD_DDR0/1)
1.26V
t4
Other Power (AVDD_AU25,
3.3V
VDDP AVDD_AU33,
AVDD_MEMPLL,
1.5V/1.8V AVDD2P5_ADC…etc)
with
Other Power
Time

S7 Power Sequence Appendix
Power Up Timing Requirements
Time Description Min Typ. Max Unit
t1 XTAL stable to Reset falling 5 ― ― ms
t2 Reset pulse width 5 ― ― ms
t3 1.26V to Reset falling 5 ― ― ms
t4 3.3VDDP to Reset falling 5 ― ― ms

S7 Power Sequence
# t2 : Reset Pulse Width : 40ms Æ OK

S7 Power Sequence
a) AC On b) DC(Remocon) On
1 :X-tal 1 :X-tal
2 : 3.3V 2 : 3.3V
3 : 1.26V 3 : 1.26V
4 : Reset 4 : Reset
# t1 : Reset Pulse Width : 400ms Æ OK # t1 : Reset Pulse Width : 120ms Æ OK


GP2 I2C MAP
TGPIO2/I2C_CLK (R3) <TU_SCL> CH 6 +3.3V_TU
TGPIO3/I2C_SDA (T3) <TU_SDA>
TUNER
TUNER
LGIT
LGIT HN(LGT10)
HN(LGT10)
0xC2(PLL)/0x10(Analog
0xC2(PLL)/0x10(Analog Demod)
Demod)
DDCR_CK/GPIO72 (N22) <I2C-SCL> CH 2 +3.3V
DDCR_DA/GPIO71 (M22) <I2C-SDA>
NVRAM
NVRAM HDCP
HDCP EEPROM
EEPROM
0xA0
0xA0 0xA8
0xA8
TGPIO0 (U1) <SCL1> CH 5 +3.3V
TGPIO1 (U2) <SDA1> /+3.3V_NEC_ST
AMP
AMP PDP
PDP MODULE
MODULE DEMOD.(BRAZIL)
DEMOD.(BRAZIL)
SATURN 7 TAS5709
TAS5709 MN884433
MN884433
0x36
0x36 0x1C
0x1C 0xD8
0xD8
DDCDA_CK/GPIO23
DDCDA_DA/GPIO24
DDCDB_CK/GPIO25
DDCDB_DA/GPIO26
DDCDD_CK/GPIO29 (B4) <DDC_SCL3> EEPROM

EEPROM CH 12 5V_HDMI_1
DDCDD_DA/GPIO30 (C4) <DDC_SDA3> HDMI1
HDMI1 /+5.0V
0XA0
0XA0
DDCDC_CK/GPIO27 (AA4) <DDC_SCL4> EEPROM

EEPROM CH 11 5V_HDMI_Side
DDCDC_DA/GPIO28 (AB4) <DDC_SDA4> HDMI1
HDMI1 /+5.0V
0XA0
0XA0
DDCA_CK/UART0_RX (N22) <RGB_DDC_SCL> EEPROM

EEPROM CH 8 +5V_ST
DDCA_DA/UART_TX (M22) <RGB_DDC_SDA> RGB
RGB
0XA0
0XA0
I2S_IN_WS/GPIO174 (F15) <SUB_SCL_NEC_TEMP> CH 7 +3.3V

I2S_IN_BCK/GPIO175 (F14) <SUB_SDA_NEC_TEMP>
MICOM
MICOM EEPROM SUB
SUB I2C
I2C
EEPROM
UPD78F0513
UPD78F0513 M24C16 Touch
Touch Eye’
Eye’
M24C16
0x52
0x52 0x? 0x70
0x70
0x?

GPIO Structure
GPIO Signal Name Direction Description
66 PWM0 Input Chip configuration
67 PWM1 Input Chip configuration
31 DSUB_DET Input D-Sub Auto link check
32 Model_OPT_3 Input Model option 3
42 Model_OPT_0 Input Model option 0
11 Model_OPT_1 Input/Output Model option 1 /FE_BOOSTER_CTRL
14 Model_OPT_2 Input/Output Model option 2/RF_SWITCH_CTL
TCON2/GSP 5V_DET_HDMI_2 Input (HDMI3 Ready) HDMI 5V Detect

_R/GCLK1
TCON4/CPV 5V_DET_HDMI_4 Input HDMI Side 5V Detect

//GSC_R/G
CLK3
TCON6/FLK 5V_DET_HDMI_3 Input HDMI_1 5V Detect
40 COMP1_DET Input Compnent1 Auto link
50 MOD_ROM_RX Input Module Rom download UART
51 MOD_ROM_TX Output Module Rom download UART
5 USB1_OCD input USB1_OCD
7 USB1_CTRL Output USB1_5V Power Control
15 TUNER_RESET Output TUNER_RESET
16 DEMOD_RESET Output Demodulator Reset
17 AV_CVBS_DET Input AV_CVBS Auto link
176 COMP2_DET Input Compnent2 Auto link
TCON8/CS2 SIDE_CVBS_DET Input SIDE_CVBS Auto link

/FLK3

GP2 BRAZIL LOW Power Map
58mA IC105
STBY
+3.3V_ST L900 IR PART DEBUG S/W
+5V_ST (ST_BY시)
L501 IC500 R508 +3.3V_NEC_ST
(3.3V Reg) IC108
659mA L502 NEC MICOM
AP2121/0.3A :$0.048 IC900 IC107
(RS232C DRV)
Instant boot Ready MICOM EEPROM
601mA 355mA
P IC502
(DCDC) L1201
VCC_1.5V_DDR
R1201
A-MVREFDQ
A-MVREFCA
Instant Boot
IC901(RGB EEPROM) +1.5V_DDR_IN R1204
O L505 19mA
R1224
B-MVREFCA
B-MVREFDQ
IC1201,1202
(DDR3)
Multi Power
R1227
w P_17V
TU700(TAS5709)
E <TUNER 5V > L300
AVDD_DDR0_1.5
MVREF
P_17V +7V +5V_TU R300
R IC507(DCDC) IC506(LDO) TU1300(TUNER)
L301
AVDD_DDR1_1.5
+1.26V_VDDC +1.26V_MIU1VDDC
IC504 (DCDC) L321
+1.26V_MIU0VDDC
L324
P_+5V +5V VDDC
Q501 (TR) USB REAR (SVC) L323
L507 L1100
801,802,804
IC1101(USB S/W) (HDMI EEPROM)
B HDMI CEC IC504 (LDO)

+3.3V
L514
+3.3V_AVDD
L310
VDD33_DVI
AVDD_DMPLL_3.3
O IC1000(NAND GATE) L308
L318
AVDD_NODIE_3.3 IC100
Multi Power
VDD33_3.3 AU33_3.3 MSTAR (S7)
SPDIF
A L702
+3.3V_DVDD
+3.3V_AU_AVDD
IC700(TAS5709)
L309 L314
L316
FRC_LPLL_3.3
VDD33_3.3
R L703
L1300
IC700(TAS5709)
TU1300(TUNER)
D +3.3V L901 IR PART
IC102,9(EEPROM)
IC103(Serial Flash)
L102 IC104(NAND Flash)
+2.5V_AVDD AVDD2P5_2.5
IC505 (REG) L303
+3.3V_DE AVDD25_PGA_2.5
L609 IC602 L304
+1.2V_DE (MN884433) AU25_2.5
IC600(REG) L305
ADC2P5_2.5
L1301 TU1300(TUNER) L306

Trouble Shooting Guide for LG Service Man
Please check system, after power Off/On one time

2. No OSD Trouble Shooting
3. Digital TV Video Trouble Shooting
4. Analog TV Video Trouble Shooting
5. Component Video Trouble Shooting
6. RGB Video Trouble Shooting
7. AV Video Trouble Shooting
8. HDMI Video Trouble Shooting
9. All Source Audio Trouble Shooting
10. Digital TV Audio Trouble Shooting
11. Analog TV Audio Trouble Shooting
12. Component / RGB / AV Audio Trouble Shooting
13. HDMI Audio Trouble Shooting
14. USB Trouble Shooting


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

N Y
Check P500 All Voltage Level
Check Power connector Replace Power board
(17V, 5V, 3.5/5V_ST)
Check All Voltage Level N Replace one of Bead, IC500

at Bead, RL_ON, IC500 output & Recheck
N If Q501 Output is normal, N

Check Voltage Level 3.3V at IC504,
Replace of the IC504
R124(Micom)
& Recheck
N Check R527 voltage level N

Check Voltage Level 1.26V at C534 (3.3V RL_ON)
Replace one of IC501 & Recheck
Check Micom Redownload or
Y
replace
N Check R500 voltage level N
Check Voltage Level 1.5V
(ON/OFF Control)
at IC502 #7 pin
Replace one of IC502 & Recheck
N Replace one of IC505 and application N

Check Voltage Level 2.5V at C589
circuit & Recheck
N N
Check X200 Clock24MHz Replace X200
Check signal transition N Maybe Serial Flash Memory N Check S7 Main chip and Soc_Reset
at IC103 problem Signal from micom GPIO
Y
N
Check signal transition N Maybe NAND Flash Memory or S7
IC104 have troubles
Check DDR Memory
Y /Replace one


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check P500 N Check GPIO Path of Micom

5V_ON
N Y
Check 5V Voltage Level
Check Power connector Replace Power board
at P500
Check 5V Voltage Level N Replace one of L507,501

at L507, L501 & Recheck
N Replace one of Q501

Check 5V Voltage Level at Q501
& Recheck
Y
Check P903 N Maybe S7(IC101)
(TXAC-), (TXAC+), (TXBC-),
has troubles
(TXBC+), Display Enable
N
Check LVDS Cable Replace Cable
Check PDP Module Electrical Specifications

Power Supply Sequence
Check CAS
Input Signal Timing Specification
Control Signal Register
It should satisfy the Pixel Clock on CAS.

No OSD Trouble Shooting (Module Power Sequence)
Vcc
(5V)
TOn TOff TOnR
Va
TVaR TVaF
Vs
TVsR TVsF
Td_on Td_off
DISPEN Normal Display
Symbol Description Min. Max. unit

Time interval between 90% of Vcc and 10% of Vs
TOn 750 1250 msec
when Power On
Time interval between 10% of Vs and 90% of Vcc
TOff 20 - msec
when Power Off
Time interval between 10% of Vcc and 90% of Vcc
TOnR 2000 - msec
when Power On
TVaR Rising Time of Va (10% to 90%) 10 300 msec

TVaF Falling Time of Va (90% to 10%) 50 500 msec
TVsR Rising Time of Vs (10% to 90%) 100 400 msec
TVsF Falling Time of Vs (90% to 10%) 90 500 msec
Time interval between 90% of Vs
Td_on 3100 - msec
and DISPEN rising edge when Power On
Time interval between DISPEN falling edge 1500 6000 msec

Td_off
and 90% of Vs when Power Off Recommended 2sec

Module Control Trouble Shooting
“TILT” on Adjust Remocon N N

PDP Module Power is OK? Check SMPS & cable
: PDP internal pattern displays?
SCL
Y Y
Replace PDP Module
SDA
PDP Module is OK. N Check Signal N Replace Control

Check SCL,SDA line output Board
< Sample Signal >
1 9 1 8
SCL
SDA 0 0 0 1 1 1 0 W A7 A6 A1 A0
Start Chip ID Address Byte Write ACK Command Address

By (0x1C) only By Slave Addr=A[7:0]
Master
9 1 9 ACK signal Check

SCL (continue) Low : OK
High : Error
SDA (continue) D7 D6 D0
ACK Command Data ACK Stop

By Slave for Addr By Slave By Master
Master : Image Board

Slave : PDP Module


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check RF Cable
Check Tuner(TU1300) Power N Replace one of Bead

(5.0V, 3.3V, 1.2V) & Recheck
N
Check IF Signal pin #17, 18 Maybe Tuner has problems
Check Demodulator Power N

Replace L609 / IC600
(3.3V, 1.2V) L609, IC600
Check Demodulator X-TAL N

Replace X-TAL
(X602)
Check TP Clock, Data, Sync N

Maybe Demodulator has problems
R630, R631, R632
Maybe MstarS7(IC100)
has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check RF Cable
N Replace one of
Check Tuner Power
L1301/L1300/L1302
(5.0V, 3.3V, 1.2V)
& Recheck
Check CVBS Signal N

Maybe Tuner(TU1300) has problems
TU1300 #11 Pin
N Replace one of
Check CVBS Signal
R1330/Q1305/R154/C213
R1334
& Recheck
Maybe MstarS7(IC100)
has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check Signal Format

Is it supported signal?
Check Component Cable
N
Check Component Jack JK1001 Replace Jack
N Replace one of
Check Component Signal
R1020/R1021/R1022
R1020/R1021/R1022
R1005/R1012/R1013
R1005/R1012/R1013
& Recheck
Y
Check Component Signal N
R175/R173/R177 Replace it
R180/R182/R184
Maybe Mstar S7(IC100)

has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check Signal Format

Check RGB Cable
N
Check RGB Jack P901 Replace Jack
Check RGB Signal N

Replace It & Recheck
R907,R908,R909
N Replace one of R915/R916

Check Sync Signal
& Recheck
N Replace it or re-burn
Check EEPROM (IC901)
& Recheck

has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check Signal Format

Check AV Cable
N
Check Jack JK1001/JK1002 Replace Jack
N Replace one of
Check CVBS Signal
C1016/C1018
C1016/C1018
& Recheck
N Replace one of
Check CVBS Signal
R187/R188/C226/C227
R187/R188/C226/C227
& Recheck

has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check Signal Format

Check HDMI Cable
Check HDMI Jack N

Replace Jack
JK803, JK804
Y
Check I2C Signal N
R844/R845 Replace It & Recheck
/R858/R859/R848/R849/R862/R863

has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_S7
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_S7
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Make sure you can’t hear any audio
N
Check Speaker Replace Speaker
N
Check Connector P703 Replace Connector
N Replace one of N
Check Signal Maybe TAS9709 has problems.
Capacitor, Register
L700, L701 Replace It
& Recheck
Y
Check IC700 Power N
17V, 3.3V Replace It & Recheck
L702,L703
Check Mstar S7 I2S Output N

Replace It & Recheck
R724, R725, R726

has problems


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

N Follow procedure digital TV video

Check video output
trouble shooting
Follow procedure All source audio N Maybe Mster S7 internal audio DSP
trouble shooting has problems. Replace It


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

N Follow procedure analog TV video

Check video output
trouble shooting
Check Tuner Power N Replace one of L1300/L1301/L1302

(5.0V, 3.3V, 1.2V) & Recheck
Check SIF Signal N

Maybe Tuner(TU1300) has problems
TU1300 #9 Pin
N Replace one of
Check SIF Signal C252/R246/R1332/Q1304/R1325
IC501 & Recheck
Follow procedure All source audio N Maybe Mstar S7 audio block has
trouble shooting problems. Replace It
< SIF waveform – sample >

- Defend on the input signal.


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

N Follow procedure external input

Check Video Output
video trouble shooting
N
Check Jack JK1001/JK1002/P900 Replace Jack
Check Signal Replace one of

C206/C207/C208/C209/C210/C211 C206/C207/C208/C209/C210/C211
C212/C220/C221/C222/C223/C224 N C212/C220/C221/C222/C223/C224
C225/C205/R166/R167/R168/R169 C225/C205/R166/R167/R168/R169
R170/R171/R127/C215/C216/C203 R170/R171/R127/C215/C216/C203
C217/C218/C219/C204/R187/R188 C217/C218/C219/C204/R187/R188
C226/C227 C226/C227 & Recheck
trouble shooting problems. Replace It


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

N
Follow procedure HDMI video
Check video output
trouble shooting
N
Re-download EDID data Replace IC802, IC804
trouble shooting problems. Replace it


DDR3
1MB
1MB 256MB
256MB 256MB(128*2)
256MB(128*2)
WXGA/XGA
Cable
CVBS_LIVE LVDS
PAL/NTSC SPDIF
IF TP1
SIF_LIVE
Demodulator TP1 S7
S7
MN884433 I2S_BCM
EXT_IN
HDMI_D
Rear(0)
USB2.0
HDMI_C Side(1)
(External Input)
(Audio Out) (Micom)
AV1
AV1_LR
AV2
AV2_LR I2S_BCM
TAS9709
TAS9709
COMP1_LR
COMP2_LR
RGB_LR EXT_IN
NEC
I2C Micom
(USB) Local
KEY
IR
HDMI_Rear(D port)
UI_HW_PORT1

Check USB 2.0 Cable
Y
Check USB device
If device is 2.5 inch HDD,
Check power adaptor
Check P1102 (250/350 tool) N

Replace Jack
P1100 (230 tool)
Y
Check 5V voltage level N Replace one of
IC1101 #2 (250/350 tool)
IC1101,L1100 & Recheck
L1100 (230 tool)
MaybeMstar S7 (IC101)
has problems. Replace It.
• Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)

LG 42PJ250-SA Chassis PB02A

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LG 42PJ250-SA Chassis PB02A

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Available Formats

Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 42PJ250 42PJ250-SA

P/NO : MFL63140201(1004-REV00) Printed in Korea

SAFETY PRECAUTIONS ...........................................................................................................3

ADJUSTMENT INSTRUCTION ..................................................................................................8

BLOCK DIAGRAM ...................................................................................................................15

EXPLODED VIEW ...................................................................................................................16

SVC. SHEET ................................................................................................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Good Earth Ground

Model Name Market Brand

Model Name Market Appliance

6. RGB Input (PC)

1. Application Range 4. PCB Assembly Adjustment

4-1. Using RS-232C

V After Receive 100% Full white pattern (06CH) then

(3) Adjustment sequence

3-1. PCB Assembly adjustment O ad 00 10: Adjust 1080p comp

3-2. Set Assembly Adjustment

5-1. Auto Adjust Component

Caution : Set Volume 0 after adjustment

5-2. Use Internal ADC(S7)

5-5. Manual Download

- EDID data (Model name = LG TV)

- In manual Adjust case, if you press ADJ button of service

O Connect all cables and equipments like Pic.5)

5-6. Adjustment Color Temperature

O wb 00 00”: Start Auto-adjustment of white balance.

< Connection Diagram for Adjustment White balance >

10. Default Service option.

10-3. Temperature Threshold

< fig.1 : 42HD Power PCB Assy Voltage adjustment >

V After download is finished, remove the USB stick.

V Press “IN-START” key of ADJ remote control, check the

V Select download file (epk file)

DDR3 1.5V By CAP - Place these Caps near Memory

CLose to DDR3 CLose to Saturn7M IC CLose to Saturn7M IC CLose to DDR3

BA1 A-MBA1 A_DDR3_A12/DDR2_A0 B_DDR3_A12/DDR2_A0 J7 A8

A-MBA2 R1206 A-TMA13 A_DDR3_A13/DDR2_A7 B_DDR3_A13/DDR2_A7 B-TMA13 0.01uF K7 C1

C1 K7 A-MCKB A-TMCKB B-TMRASB B-MRASB VDDQ_5

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C1122 C1116 250_350 250_350

10mm READY READY

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5A [YL1]O-SPRING 5.6V 100pF

5E [BL2]O-SPRING 1/16W VCC

7E [BL2]E-LUG-S 30V 10pF READY VINPUT

5N [RD3]O-SPRING_2 R1029 10K

6J [GN3]E-LUG 30V 75 10pF

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ROM DOWNLOAD FOR PDP 250_350

SUB Board I/F

12K +3.3V_ST 4.7K

R900 R901 50V R927 R938 R941 L903

R904 ADUC30S03010L_AMODIODE R937

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CEC_REMOTE HDMI_CEC_S7 CEC_REMOTE HDMI_CEC

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Power Up Timing Requirements