Assembly Process Induced Stress Analysis for New

FLMP Packages by 3D FEA

Yong Liu, Scott Irving, Margie Tumulak and Elsie A. Cabahug

Fairchild Semiconductor Corp.

South Portland, ME 04106

 Outline of Presentation

• Motivation
• FEA Framework-Concept to Product
• Problems Defined
• Material Constitutive Relations
• Simulation Strategies
• Results of Flip Chip Attach and Clamping
• Conclusions and Further Work
 Motivation
 “Try-out” process by simulation first
 To improve quality
 To reduce time to market
 To reduce manufacturing costs

Flip Chip Attach

Degating and testing

Clamping and Molding

Sawing and TNR

FEA Framework - Concept to Product
Early design phase
- fast analytic models
Concept
- guide for geometry and material selection
- short loops for optimization

Virtual characterization
Detailed - full models for accuracy
Package
- thermal analysis (Ja, Jc, heat dissipation)
Design
- moisture absorption and diffusion
- electrical analysis

Assembly Process Simulation

Process
Modeling - isolate process issues
- predict process induced stress
- optimize process steps
Reliability
- design and process verification
Verification
Assembly Level Reliability
- utilize full package and process models
- advanced prediction of failure mechanisms
- mimic reliability qualification tests
- solder joint fatigue, delamination/adhesion, warpage
- corrosion, electromigration
Virtual Release
 Problems we are modeling
• Flip chip attach processing with reflow
• Clamping processing before molding

Clamping pressure

Flip Chip Attach Clamping Process

Note: The trade mark of FLMP in Fairchild Semiconductor

is BottomlessTM
 Problems we are modeling
• Both flip chip attach and clamping processes are very
non- linear both in geometry and material.
• It is very hard to get converged simulation results.

How to target this modeling work and get the correct

solution?

• Materials models
Assume that solder joint is non-linear, all others are elastic
• Numerical algorithms
 Material Constitutive Relations

BKA model (Brown, Kim and Anand, 1989)

 ε&vp
m
s  Q 
f ANAND = σ = sinh  exp  
−1

ξ  A  kT  
With the evolution equation

s dε vp
a
ds   s 
= h0  1 − ∗  sign(1 − ∗ )
dt   s  s dt

 dε vp dt
n
∗  Q 
s = s
ˆ exp 
 A  kT 
 Material Constitutive Relations

Elastic plastic stress and strain relations

σ = f(ε&, ε&pl , T) (examples are bi-linear or multi-linear)
ε&= ε&e + ε&pl

Solder ball Paste

Multi-linear plastic stress-strain relation

 Material Constitutive Relations

Elastic Plastic and Creep Model:

This model includes both plastic and creep properties.

ε&= ε&e + ε&pl + ε&creep

With the creep equation

 −Q n
ε&creep = c exp σ
 kT 

(Norton’s law)
 Numerical Strategies
Numerical Strategies
• Simple Progressive solution
• Implicit algorithm
• Solver Technology

Simple Progressive solution

Newton-Raphson convergence radius ( see Eggert et al, 1991)

F (t ) = (1. − ) exp( β t ) f trial +

t
tL tL
t
[1. − (1. − ) exp( β t )] f ANAND
tL tL
For incremental theory, tL is taken as very small local time.
For field theory, tL can be taken as the whole action time.
A simple example: ftrial is selected as a linear elastic solution
in a very short time as the initial guess
 Numerical Strategies
Examples of numerical strategies

Power law (m=0.05) BKA model

Progressive stress-strain relations in a field FEM (Antoinette and Yong, 2001)

 Numerical Strategies
Implicit Algorithm

∆ε n
vp [(
= ∆t n 1 − α ε& + α ε&
*
) n
vp
* n +1
vp ]
α∗ is in the range of [0,1]
α∗ = 1, fully implicit algorithm
α∗ = 0, explicit algorithm
Solver Technology
DOFs within 500K use direct solver (e.g.,sparse solver)

DOFs more than 500K use iterative solver

Pre-conditioned Conjugate Gradient (PCG)
Algebraic Multigrid (AMG)
Distributed Domain Solver (DDS)
Flip Chip Attach Modeling

C3

C2 C4

C1

Reflow loading
max: 285C
 Flip Chip Attach Modeling

Assume:
• Chip placement is done perfectly by the machine

• No chip floating before reflow process

• Initial stresses induced before reflow are too small to be

considered.

• The solder paste stress is free from room temp to reflow temp
285C (it almost fully melts at this temp).
Results of Flip Chip Attach

Die and joint stress

L/F stress

Die and joint deformation

 Results of Flip Chip Attach
Solder Ball Stress
30 300

25 250

Max Von-Mises Stress (MPa)

20 200

Temperature (C)
Elastic plastic model
Anand viscoplastic model
15 150
Plastic with creep model
Max shear stress Sxz (Mpa) Temperature

10 100

5 50

0 0
0 50 100 150 200
t (secs)

Max von-Mises stress versus

time in three material models
Von-Mises Stress (Mpa)
Results of Flip Chip Attach
Solder paste stress

30 300

25 250

Von-Mises Stress (MPa)

20 200

Temperature (C)
Elastic Plastic Model
Anand Viscoplastic Model
15 150
Max shear stress (Mpa) Plastic with Creep Model
Temperature

10 100

5 50

0 0
90 100 110 120 130 140 150 160 170 180
t (secs)

Max von-Mises stress versus

time in three material models
Von-Mises stress (Mpa)
 Results of Flip Chip Attach
Solder paste stress
30

25
Max Von-Mises Stress (MPa)

20

Continuum Model
15
Elements Birth and Dead Model

10

0
0 50 100 150 200
t (secs)

• Element Birth and Death Model

• Continuum Model
 Clamping Modeling

• Pre-heating 175C
• Clamping 3 mils
• Die thickness 8 mils
Results of Clamping
Solder Joint Deformation

• Solder joint highly deformed

• Gate lead goes down 9 microns
 Results of Clamping
Solder Joint Stress
30

25

Max von-Mises Stresses (MPa)

20

Elastic Plastic Model

15 Anand Viscoplastic Model
Plastic and Creep Model

10

0
0 10 20 30 40 50 60 70
t (secs)

Solder Joint Von-Mises Stress Von-Mises Stress versus time with

three material models
Results of Clamping
Package system stress

Max stress appeared at the gate lead

 Conclusions and Further works

• A FEA framework is developed for manufacturing process

(which can be applied to all the manufacturing procedures)
• Numerical strategies are presented for convergence
• Three material models are investigated and compared

Further work:
• Modeling work needs to be further validated by test results
• Material behavior is the function of both time and temp
• New methodologies such as stabilized FEA (see next page)
 Numerical Example of Stabilized FEA

∇s ⋅ v − g (ε&, s, Θ ) = 0 where τ =
βh
2v
[ ]
T( v , s ) ( s * ) = ∫ ∇s ⋅ v − g (ε&, s, Θ ) s *dV + Sτ = 0
∆

B
(See Franca, Frey and Hughes, 1992)
[ ](
Sτ = ∑ ∫ τ ∇s ⋅ v − g (ε&, s, Θ ) v ⋅ ∇s * dV )
N el

B
e =1

Case (1) Pressure with stabilization Case (2) Pressure without stabilization
Acknowledgments

Thanks for the support from Fairchild Semiconductor

Automation Dept and Fairchild Semiconductor Cebu
site.