Tutorial -4

1. What is Boundary Scan? Explain JTAG architecture and its different modes.
2. Find the test vector for SA1 at α for the circuit shown in FIGURE 4B using i) path
sensitization. ii) D algorithm.

3. Find the test vector for the circuit shown in FIGURE 5A using ITG method.
4. Find the observability of a full adder. Consider observability of primary output is 0
and controllability of each primary input is 1:1(CC0:CC1).

5. Why do faults occur in VLSI circuits? How they can be mapped into logical faults?
6. Explain the state verification experiment. Find the all possible Homing sequence and
Distinguishing sequence for the state table shown in FIGURE 6B.

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FIGURE 4B

PS NS
X=0 x=1

A C,0 A,0
B D,0 C,0
C D,1 B,0
D B,0 D,0

FIGURE 5A FIGURE 6B