ARM 7 TDM1 Thumb Delay Multiplier Embedded K

Macro Cell

Risfesign Philosophy

ARM Processor with ARM instr 32 bit

Thumb Instr i 16 bit
J lns Higher Code Density
Helps in good memory management

It is a RISC aid
lns.I.ms execute in
single dock cycle
not all
It reduces complexity of in.st.ms performed by hardware
ARM System on Chipa.ro
J 0ur esignRues ARM system AndrewStrau
Instructions Fixed length
Reduced in h
Shingle 4k execution
Pipelining Multiple instr's executed in 11
Regiters GPR Set General Purpose Registers Set
Local memory storage for all data processing
Operations
Local Store A.rc.tn Processor operates on
registers
Load store insta transfer data b w register and
memory Data items held in register bank can be used
 a 1 held ler band can be used
rg i
leg
multiple times without needing multiple memory access

Physical Features
Reduced Pconsumption extended battery operations

High Code Density

Reduced area
of die
Hardware view while
debug t.ec asothats wen.gg can
processor is executing the code
Barrel Shifter is mainly used for pre processing purpose
mainly used for shift operation
Thumb h trn
Conditional Execution it executes when condition is
satisfied
v Enhanced lns.tn SP processor instr can be added
to ARM processors

Memory
8bit men 16 bit 32 bit
ARM 32 bit cycles 2 I
Thumb 16 bit 2 I 1

Priming Model Dataflow Model ARMCore

fistinit a
 lead
I
kGesUt
s Reg.tiiecro.mg
Pc

to
y l
It is Von Neumann architecture
Irish decoder decodes in.tk before execution

Features
Uses load store instf
No data processing ins.IT manipulate
memory
Register File ro rs
Each register can hold 31 bits of data can be
stored
Rn Rm Ra where 0C ncis
O MC 15
 OC das
Sign Extend converts signed 8 bit 16 bit noes
to 32 bit values and places it in the
registers
Alternately Rm can be preprocessed in Barnet shifter
before sent to ALU
Incrementor increments A.d.dnr.e.ge before core R w
next register value from Ito next sequential memory
location

Register File GPRS General PurposeRegisters

Codel Data

roiaaieiaardiza.fi remgois7e
s

16 registers
f
f
processor status register
Riz tack Pointer head
of the IkRegister
stack in current processor mode b Pc
Rice Link Register holds return address sad a.d.de
v of is ins.INnext
Rig Program Counter holds adder of next ins.tn whenthere
ajump
Current ProgramStatusR.e.gg

Riz and Ria also be used as GPR They are

can
also called Orthogonal Any ins.tn applied to ro can
be applied to
any other register
 e
appld Ihr
ny regisle
Current Programdtatus Register
Mainly to monitor and control internal operations

kFIags S
µcontro
31 30 29 28 27 7 6 5 4 O

H IH b
t Fou
N Bit 31 f
L Ve
t Thumb of
Z ZeroFlag Java Interrupt o.p.ee

5 151 0
C Bit IGF Hardware
carry
V Overflow
Interrupts
I
SaturationCHappenisns.in0sP Interrupt pin
F Fast InterruptPin

Professor Medes The registers that are active and

CPSR register is
given by processor modes
modes
Privileged Mode Full r and w access to all
of CPSR
Non privilage Mode r access to controlfieldand
r and w to condition
flags
1 1 2020
privileged Mode

Modes
L Non privilaged Mode User Mode
 Privileged Mode

I
edin.at ientosa
a
a

Supervisor Processor is in
after reset and OS kernel
operates in

System Special version of user mode Fullaccess

to 121W CPSR
Undefined Whenever processor encounters an Undefine
in.s.IN cannot decode the OPCODE

Banked RegisterLLhadow Registers

FIB 1120 Svc

re

THE tests
Und ABT

re
Meet i Ii IEEE't
ftp.OND
ABs.w
Total 37 registers 16 1 CPS R G P R set
Reg
 20 Banked had

Mode
changing happens by writing mode bits in CPSR
Except for system mode all modes have set of banke
register that are subset of main 16 registers
One to one b w Banked and Main registers
mapping

mode is changed by a
Processor writes
program that
directly to CPSR
by hardware when it responds to interra
Ex External device rises an 112g and user mode
registers r13 and 14 are jumped to rl3 IRD r14 IRD
r
and CPSR is stored in SPSR

pecialreturnins.I.n is used to instruct the core

to restore CPSR

Processing Modes
4 3 2 I 0
Mode Abbrevation Mode Bits
Priyvilage
0Abort abt 10 l l l
0 FIG fig Y 1000 I
O IRD Y l O O I 0
Supervisor
irq
Svc Y l O 01 I
0 System 4 l l l l l
Sys
Undefined undf Y 1 1 01 I
OU d u f
0 User Usr N l O 00 0

The CPSR to SPSR doesn't take place

copy of
when mode is forced
change by program writing
State and Instruction Get
When processor is in ARM state 32 bit
Thumb slate 16 bit
Jazelle state 8 bit
j p FO
GOI of the set is in
java implemented codes
in hardware 401 in software it is closed i.ns.IN set

No sequential operations aren't possible.ie the code

can't jump b w ARM Thumb J in one code

ARM Thumb
CPSR 1 0 CPSR 1 1
Instruction Size 32 bit lb bit
core InstI 58 30
Most Only with
Condition Exe of the
insta branch
Data processing Access to barrel Separate in n
Instrn shifterand ALU for BarrelShifterGAL
 I 1
Program Status 121W in No direct
mode access
Register privileged
IS GPRTPC 8GPR 17HighEeg
Register Usage
f PC

Instruction Masks CPSR I 1 IRD is blocked

F l i F is blocked
IS
condition