Tutorial -3

1. Find out the reduced number of test vectors for i) Three input AND gate ii) two input
NOR gate ii) inverter.

2. How to reduce the number of test vectors for a combinational circuit with a, b, c, d, e,
f, g inputs and V(a,b,e),W(b,c,g),X(a,d,e),Y(c,d,e) and Z(e,f) outputs. List the reduced
test vectors.

3. What are the different types of output compression techniques? For the function
Z =AB+BC +CA , if there is a SA0 fault at the output of second AND gate (BC)
then find signature of faulty and fault free circuit.

4. Find test vector for SA0 and SA1 at W, X, Y and Z in the circuit Z = XY +WY
´ .

5. Find the test vector for SA0 in the circuit shown in FIGURE 3B. using Boolean
difference method w.r.t k-p-z path and w.r.t k-q-z path.

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FIGURE 3B