DEPARTMENT DOCUMENT DOC.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION
Dr.N.G.P.Institute of Technology ENGINEERING DATE : 04.08.221
Coimbatore - 48
COURSE PLAN
Academic Year 2019-2020
Semester : V
Hours/Week
EC8552 Computer Architecture and Organization L T P C
3 0 0 3
BATCH: 2019-2023 BRANCH: ECE - B YEAR: III
ECE Department
Mr.C.MAKESH Assistant Professor
Sl.No. Topics to be covered Planned Resources Teaching aids : ICT/ Conventional Executed Date and Reason for
No. of (T1, T2, R1, & Pedagogy Techniques, Role No. of Period deviation
Hours R2, W1, W2, Play, GD, Seminar, Analogy, Case Hours
W3) Study, Quiz, Problem Solving,
Puzzles, etc.,

UNIT- I TITLE : COMPUTER ORGANIZATION & INSTRUCTIONS HOURS :9+1

1. Introduction 1 R1, T1

Basics of a computer system: Evolution, 1 T1

2.
Ideas

3. Technology 1 R1

4. Performance, Power wall 1 R1

5. Uniprocessors to Multiprocessors 1 R1
 6. Addressing and addressing modes 2 R1 HoD

7. Instructions 1 R1

Operations and Operands, Representing 1 T1 HoD

8.
instructions

9. Logical operations, control operations 1 R1, T1

HoD
UNIT- II TITLE : ARITHMETIC HOURS :9

1. Fixed point Addition 1 T1

2. Subtraction 2 T1, R1

3. Multiplication 2 T1, R1

4. Division 1 T1, R1

5. Floating Point arithmetic 1 T1

6. High performance arithmetic 1 T1

7. Subword parallelism 1 T1, R1

UNIT- III TITLE : THE PROCESSOR HOURS :9

1. Introduction, Logic Design Conventions 1 T1

2. Building a Datapath 1 T1

3. A Simple Implementation scheme 1 T1

4. An Overview of Pipelining 1 T1

5. Pipelined Datapath and Control 1 T1

 6. Data Hazards: Forwarding versus Stalling 1 T1 HoD

7. Control Hazards 1 T1

8. Exceptions 1 T1

9. Parallelism via Instructions 1 T1

HoD
UNIT- IV TITLE : MEMORY AND I/O ORGANIZATION HOURS :9

1. Memory hierarchy 1 T1, R3

2. Memory Chip Organization 1 T1

3. Cache memory 1 T1

4. Virtual memory 1 T1

5. Parallel Bus Architectures 1 T1

6. Internal Communication Methodologies 1 T1

7. Serial Bus Architectures 1 T1, R3

8. Mass storage 1 T1, R3

9. Input and Output Devices 1 T1 HoD

UNIT- V TITLE : ADVANCED COMPUTER ARCHITECTURE HOURS :9

1. Parallel processing architectures and 1 T2, R2

challenges

2. Hardware multithreading 2 T2, R2

3. Multicore and shared memory 1 T2

 multiprocessors

4. Introduction to Graphics Processing Units 1 T2 HoD

5. Clusters and Warehouse scale computers 2 T2

6. Introduction to Multiprocessor network 2 T2, R2

topologies

CONTENT BEYOND THE SYLLABI

HoD

Text Book

1. David A. Patterson and John L. Hennessey, ―Computer Organization and Design‖, Fifth edition, Morgan Kauffman / Elsevier, 2014.
(UNIT I-V)
2. Miles J. Murdocca and Vincent P. Heuring, ―Computer Architecture and Organization: An Integrated approach‖, Second edition,
Wiley India Pvt Ltd, 2015 (UNIT IV,V)

Reference Books :

1. V. Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, ―Computer Organization―, Fifth edition, Mc Graw-Hill Education
India Pvt Ltd, 2014.
2. William Stallings ―Computer Organization and Architecture‖, Seventh Edition, Pearson Education, 2006. 65
3. Govindarajalu, ―Computer Architecture and Organization, Design Principles and Applications", Second edition, McGraw-Hill
Education India Pvt Ltd, 2014.
Web Links / Other Resources :

W1 : http://www.seas.gwu.edu/~narahari/cs211/materials/lectures/lectures.html

W2 : http://engineeringppt.net/tag/computer-organization-and-architecture-notes/

W3: http://nptel.ac.in/

1. No. of hours conducted using ICT enabled Teaching :

2. No. of hours conducted using Conventional Methods :

3. No. of Tutorial hours conducted :

4. No. of case studies discussed :

Faculty Signature Head of the Department