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Fabrication and Manufacturing (Basics) : - Batch Processes - Silicon Is Neat Stuff
Fabrication and Manufacturing (Basics) : - Batch Processes - Silicon Is Neat Stuff
Manufacturing (Basics)
• Batch processes • Silicon is neat stuff
– Fabrication time independent – Oxide protects things from
of design complexity impurities
• Standard process – Can be etched selectively on
– Customization by masks silicon or metal
– Each mask defines geometry • Can be doped
on one layer – Add P or As impurities
– Lower-level masks define
transistors
– Higher-level masks define
wiring
Processed
Chemicals Processing wafer Chips
Wafers
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
p+ n+ n+ p+ p+ n+
n well
p substrate
GND VDD
• Six masks
– n-well Polysilicon
– Polysilicon
– n+ diffusion n+ Diffusion
– p+ diffusion p+ Diffusion
– Contact Contact
– Metal
Metal
p substrate
SiO2
p substrate
Photoresist
SiO2
p substrate
Photoresist
SiO2
p substrate
Photoresist
SiO2
p substrate
SiO2
p substrate
n well
n well
p substrate
n well
p substrate
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
n well
p substrate
n+ Diffusion
n well
p substrate
n+ n+ n+
n well
p substrate
n+ n+ n+
n well
p substrate
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
Contact
M etal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
Designer Foundry
Design Rules
Process Parameters
• Resolution
– Width and spacing of lines on one layer
• Alignment
– make sure interacting layers overlap (or don’t)
– Contact surround
– Poly overlap of diffusion
– Well surround of diffusion
VD D
VDD
Rnwell
p-source
+ + + +
p n n+ p p n+
n-well Rnwell
Metal 1 (blue)
a
a a Poly (red)
n-type
diffusion
Gnd (green) VSS (Gnd)
a b p-diffusion
a
z b
a
b
Poly
Gnd
n-diffusion
Metal 1 Gnd
b c F
F
a
x x x x x x x
b e
a b c d
d e c Gnd
Two n-diff gaps, zero p-diff gaps
EE 261 James Morizio 52
e b
VDD
a a
e d
d e c
a
d b c
b c
pMOS graph nMOS graph
a
b
d e c
Gnd
• For example: d, e, a, b, c
• If no such path exists, then break diffusion into strips
e d
a d e c
d b c
b c
nMOS graph
VDD
F x x x x x
a
b
e c
F
d
Gnd
Ordering: d, e, a, b, c: x x x x x
Zero n-diff gaps, zero p-diff gaps Gnd d e a b c