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IRFI4212H-117P: Description
IRFI4212H-117P: Description
IRFI4212H-117P
Features Key Parameters g
Integrated half-bridge package VDS 100 V
Reduces the part count by half RDS(ON) typ. @ 10V 58 m:
Facilitates better PCB layout Qg typ. 12 nC
Key parameters optimized for Class-D Qsw typ. 6.9 nC
audio amplifier applications RG(int) typ. 3.4 Ω
Low RDS(ON) for improved efficiency TJ max 150 °C
Low Qg and Qsw for better THD and
improved efficiency
Low Qrr for better THD and lower EMI
Can delivery up to 150W per channel into
4Ω load in half-bridge configuration
amplifier
Lead-free package
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08/21/06
IRFI4212H-117P
Electrical Characteristics @ TJ = 25°C (unless otherwise specified) g
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.09 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 58 72.5 mΩ VGS = 10V, ID = 6.6A e
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 100V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
gfs Forward Transconductance 11 ––– ––– S VDS = 50V, ID = 6.6A
Qg Total Gate Charge ––– 12 18
Qgs1 Pre-Vth Gate-to-Source Charge ––– 1.6 ––– VDS = 80V
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.71 ––– nC VGS = 10V
Qgd Gate-to-Drain Charge ––– 6.2 ––– ID = 6.6A
Qgodr Gate Charge Overdrive ––– 3.5 ––– See Fig. 6 and 15
Qsw Switch Charge (Qgs2 + Qgd) ––– 6.9 –––
RG(int) Internal Gate Resistance ––– 3.4 ––– Ω
td(on) Turn-On Delay Time ––– 4.7 ––– VDD = 50V, VGS = 10Ve
tr Rise Time ––– 8.3 ––– ID = 6.6A
td(off) Turn-Off Delay Time ––– 9.5 ––– ns RG = 2.5Ω
tf Fall Time ––– 4.3 –––
Ciss Input Capacitance ––– 490 ––– VGS = 0V
Coss Output Capacitance ––– 64 ––– pF VDS = 50V
Crss Reverse Transfer Capacitance ––– 34 ––– ƒ = 1.0MHz, See Fig.5
Coss eff. Effective Output Capacitance ––– 110 ––– VGS = 0V, VDS = 0V to 80V
LD Internal Drain Inductance ––– 4.5 ––– Between lead, D
nH 6mm (0.25in.)
G
LS Internal Source Inductance ––– 7.5 ––– from package
S
and center of die contact
Diode Characteristics g
Parameter Min. Typ. Max. Units Conditions
IS @ TC = 25°C Continuous Source Current ––– ––– 11 MOSFET symbol
(Body Diode) A showing the
ISM Pulsed Source Current ––– ––– 44 integral reverse
(Body Diode)c p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 6.6A, VGS = 0V e
trr Reverse Recovery Time ––– 36 54 ns TJ = 25°C, IF = 6.6A
Qrr Reverse Recovery Charge ––– 56 84 nC di/dt = 100A/µs e
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 1.9mH, RG = 25Ω, IAS = 6.6A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Rθ is measured at TJ of approximately 90°C.
Specifications refer to single MosFET.
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IRFI4212H-117P
100 100
VGS VGS
TOP 15V TOP 15V
12V 12V
10V 10V
ID, Drain-to-Source Current (A)
6.0V
10 10
6.0V
100 2.5
ID = 6.6A
R DS(on) , Drain-to-Source On Resistance VGS = 10V
ID, Drain-to-Source Current (A)
2.0
10
(Normalized)
T J = 150°C
1.5
T J = 25°C
1
1.0
VDS = 50V
≤60µs PULSE WIDTH
0.1 0.5
3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100 120 140 160
10000 12.0
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
ID= 6.6A
C rss = C gd 10.0 VDS= 80V
VGS, Gate-to-Source Voltage (V)
1000 8.0
Ciss
6.0
Coss
100 4.0
Crss
2.0
10 0.0
1 10 100 0 2 4 6 8 10 12 14
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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IRFI4212H-117P
100 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 150°C
10 10
100µsec
1
T J = 25°C
1 0.1 1msec
10msec
0.01 Tc = 25°C
Tj = 150°C
VGS = 0V Single Pulse DC
0.1 0.001
0.0 0.5 1.0 1.5 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area
12 4.5
8 3.5
ID = 250µA
6 3.0
4 2.5
2 2.0
0 1.5
25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
T J , Junction Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Junction Temperature Fig 10. Threshold Voltage vs. Temperature
10
D = 0.50
0.20
Thermal Response ( Z thJC )
1 0.10
0.05
0.02
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.1 0.01 τJ τC 0.7942 0.000208
τJ τ
τ1 τ2
1.3536 0.001434
τ3 τ4
τ1 τ2 τ3 τ4 2.2345 0.100647
Ci= τi/Ri 2.7177 1.9398
SINGLE PULSE Ci i/Ri
0.01 ( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100
t1 , Rectangular Pulse Duration (sec)
T J = 125°C 100
125
75
100
50
75 T J = 25°C
25
50 0
4 5 6 7 8 9 10 11 12 13 14 15 16 25 50 75 100 125 150
VGS, Gate -to -Source Voltage (V) Starting T J , Junction Temperature (°C)
Fig 13a. Maximum Avalanche Energy vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 13b. Unclamped Inductive Test Circuit Fig 13c. Unclamped Inductive Waveforms
LD
VDS VDS
90%
+
VDD -
D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf
Fig 14a. Switching Time Test Circuit Fig 14b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT Vgs(th)
0
1K
Fig 15a. Gate Charge Test Circuit Fig 15b Gate Charge Waveform
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IRFI4212H-117P
TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))
14
TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/06
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