CLOUD COMPUTING

SUBJECT:

CLOUD COMPUTING
ASSIGNMENT NO. 2

COURSE INSTRUCTOR:
DR. HUMAIRA IJAZ
COURSE CODE:
IT-4544

PREPARED BY:
WALEED AHMED
BSEF17E05
BSSE (7TH- SELF)
2017-2021

DATE:
WEDNESDAY, NOVEMBER 18, 2020.

DEPARTMENT OF CS & IT
UNIVERSITY OF SARGODHA
SARGODHA, 40100

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Q.No.1: Differentiate between Simulation, Emulation and Virtualization? _______________ 4

Q.No.2: Where Simulation, Emulation and Virtualization is usually preferred? ____________ 5
Emulation: _______________________________________________________________________ 5
Simulation: _______________________________________________________________________ 5
Virtualization: _____________________________________________________________________ 5
Q.No.3: What is Instruction Set Architecture (ISA)? __________________________________ 6
The 3 most common types of ISAs are: ____________________________________________ 6
1) Stack ________________________________________________________________________ 6
2) Accumulator __________________________________________________________________ 6
3) GPR _________________________________________________________________________ 6
Popular ISAs:______________________________________________________________________ 7
Q.No.4: What are privilege levels (rings) in OS and different types of instructions? ________ 7
PRIVILEGE LEVEL: _____________________________________________________________ 7
TYPES OF INSTRUCTIONS: ______________________________________________________ 8
Non-Privileged Instructions: _________________________________________________________ 8
Examples of Non-Privileged Instructions: ______________________________________________________9

Privileged Instructions: _____________________________________________________________ 9

Examples of Privileged Instructions: __________________________________________________________ 9

Q.No.5: What are different types of interrupts? ____________________________________ 10

Types of Interrupts: __________________________________________________________ 10
1. Hardware Interrupts: __________________________________________________________ 10
 Maskable Interrupt: _________________________________________________________________10
 Non-Maskable Interrupt: _____________________________________________________________ 10

2. Software Interrupts: ___________________________________________________________ 10

 Normal Interrupts: __________________________________________________________________10
 Exception: _________________________________________________________________________10

Classification of Interrupts According to Periodicity of Occurrence: _________________________ 10

1. Periodic Interrupt: ___________________________________________________________________10
2. Aperiodic Interrupt:__________________________________________________________________10

Classification of Interrupts According to the Temporal Relationship with System Clock: ________ 10
1. Synchronous Interrupt: _______________________________________________________________ 10
2. Asynchronous Interrupts: _____________________________________________________________ 10

Q.No.6: What is interrupt handling in OS? ________________________________________ 11

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Interrupt Handling:________________________________________________________________ 11
Type of Interrupt Handlers: _________________________________________________________ 11
1. First Level Interrupt Handler (FLIH) ______________________________________________________ 11
2. Second Level Interrupt Handler (SLIH) ___________________________________________________11

Q.No.7: What is Vector Table?__________________________________________________ 12

The Interrupt Vector Table__________________________________________________________ 12
RESET in 8051: __________________________________________________________________________12

Methods of Using Interrupt Vector Table: _____________________________________________ 13

PREDEFINED: ___________________________________________________________________________13
FETCH: ________________________________________________________________________________13
INTERRUPT ACKNOWLEDGE: _______________________________________________________________ 14

Q.No.8: What is Program Counter? ______________________________________________ 14

Program Counter: _________________________________________________________________ 14
Q.No.9: What is Context Switching? _____________________________________________ 15
Context Switching: ________________________________________________________________ 15
MULTITASKING _________________________________________________________________________15
INTERRUPT HANDLING____________________________________________________________________15
USER AND KERNEL MODE SWITCHING _______________________________________________________ 15

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CLOUD COMPUTING
ASSIGNMENT NO.2
Q.No.1: Differentiate between Simulation, Emulation and Virtualization?
ANS:
EMULATION VIRTUALIZATION SIMULATION
Emulation, in a software Virtualization is the creation A simulation is an
context, is the use of an of virtual servers, approximate imitation of the
application program or infrastructures, devices and operation of a process or
device to imitate the computing resources. system that represents its
behavior of another program Virtualization changes the operation over time. A
or device. Common uses of hardware-software relations computer simulation is an
emulation include: Running and is one of the attempt to model a real-life
an operating system on a foundational elements of or hypothetical situation on a
hardware platform for which cloud computing technology computer so that it can be
it was not originally that helps utilize the studied to see how the
engineered. capabilities of cloud system works.
computing to the full.
In case of Emulation, you’d In virtualization, hardware In simulation, the hardware
need a software connector to can be accessed directly. is accessed both directly to
access hardware. test functionality and
indirectly to control the
environment.
Emulator requires an Virtual machine can run the An instruction set simulator
interpreter to translate the code directly, which is (ISS) is a simulation model,
source code. available in different usually coded in a high-level
languages. programming language,
which works by "reading"
instructions and maintaining
internal variables which
represent the processor's
registers.
Emulators are relatively Virtual machines are Simulators are faster than
slower. Since it involves relatively faster in its emulators but could be
binary translation which can operations. slower than virtual machines.
cause latency.
Emulation is comparatively VM solutions are costlier Simulator are the most costly
cheaper. than Emulation. of the three techniques as it
builds real time environment
to execute the code (system).

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Internal structure of Virtual machine can run the Internal structure of

emulation is written in
machine-level assembly
language.
Emulation falls short of
virtualization as far as backup
and recovery is considered.
Types of Emulation:
 CLI
 ANSI Emulation
 Digital Emulation
And many more.
code directly, which is
available in different
language.
Virtualization provides better
backup solutions.
Types of Virtualization:
 Server Virtualization.
 Application Virtualization.
 Network Virtualization.
 Desktop Virtualization.
 Storage Virtualization.
simulation is written in high-
level language.
Simulation can also backup
or record data impressively.
Types of Simulation:
 Live: Real people and
Real System
 Virtual: Real people but
Simulated System
 Constructive: Simulated
People and Simulated
System

Q.No.2: Where Simulation, Emulation and Virtualization is usually preferred?

ANS:
The preferred use of all three of these techniques are written below.
EMULATION:
Emulation is preferably used where we want:
 To run operating system on a hardware platform for which it was not originally engineered.
 To run arcade or console-based games upon desktop computers.
 To run legacy applications on devices other than the ones for which they were developed.

SIMULATION:
Simulation is preferred where want to:
 Avoid danger and loss of life.
 Where conditions can be varied and outcomes investigated.
 Investigate critical situations without risk.
 Have effective cost control.
 Have speedy behavior needed to be studied easily over a long period of time.

VIRTUALIZATION:
Virtualization is preferred where we want:
 To reduced capital and operating costs.
 Minimized or eliminated downtime.
 Increased it productivity, efficiency, agility and responsiveness.
 Faster provisioning of applications and resources.
 Greater business continuity and disaster recovery.

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 Simplified data center management.

 Availability of a true software-defined data center

Q.No.3: What is Instruction Set Architecture (ISA)?

ANS:
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between software and hardware.
We will briefly describe the instruction sets found in many of the microprocessors used today.
In general, an ISA defines the supported data types, the registers, the hardware support for
managing main memory, fundamental features (such as the memory consistency, addressing
modes, virtual memory), and the input/output model of a family of implementations of the ISA.
The ISA of a processor can be described using 5 categories:
1. Operand Storage in the CPU: Where are the operands kept other than in memory?
2. Number of explicit named operands: How many operands are named in a typical instruction?
3. Operand location: Can any ALU instruction operand be located in memory?
4. Operations: What operations are provided in the ISA?
5. Type and size of operands: What is the type and size of each operand and how is it specified?
Of all the above the most distinguishing factor is the first.

The 3 most common types of ISAs are:

1. Stack - The operands are implicitly on top of the stack.
2. Accumulator - One operand is implicitly the accumulator.
3. General Purpose Register (GPR) - All operands are explicitly mentioned, they are either
registers or memory locations.
The advantages and disadvantages of each of these approaches are as follows:
1) STACK
Advantages: Simple Model of expression evaluation (reverse polish). Short instructions.
Disadvantages: A stack can't be randomly accessed this makes it hard to generate efficient code.
The stack itself is accessed every operation and becomes a bottleneck.
2) ACCUMULATOR
Advantages: Short instructions.
Disadvantages: The accumulator is only temporary storage so memory traffic is the highest for
this approach.
3) GPR
Advantages: Makes code generation easy. Data can be stored for long periods in registers.
Disadvantages: All operands must be named leading to longer instructions.

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POPULAR ISAS:
There are various popular instruction sets that are used in the industry and are of theoretical
importance. Each one has its own usage and advantages.

Following are the instruction set architectures:

 Reduced Instruction Set Computer (RISC)
RISC is an instruction set architecture (ISA) which has fewer cycles per instruction (CPI) than
a Complex Instruction Set Computer (CISC).
 Complex Instruction Set Computer (CISC)
CISC is an instruction set architecture (ISA) which has fewer instructions per program than a
Reduced Instruction Set Computer (RISC).
 Minimal Instruction Set Computers (MISC)
MISC is a processor architecture with a very small number of basic instruction operations and
corresponding opcodes.
 Very Long Instruction Word (VLIW)
VLIW is an instruction set architectures designed to exploit Instruction Level Parallelism (ILP).
 Explicitly Parallel Instruction Computing (EPIC)
EPIC is an instruction set that permits microprocessors to execute software instructions in
parallel by using the compiler, rather than complex on-die circuitry, to control parallel
instruction execution.
 One Instruction Set Computer (OISC)
OISC is an abstract machine that uses only one instruction obviating the need for a machine
language opcode.
 Zero Instruction Set Computer (ZISC)
ZISC is a computer architecture based on pattern matching and absence of micro-instructions
in the classical sense.

Q.No.4: What are privilege levels (rings) in OS and different types of instructions?
ANS:

PRIVILEGE LEVEL:
A privilege level in the x86 instruction set controls the access of the program currently running
on the processor to resources such as memory regions, I/O ports, and special instructions. There
are 4 privilege levels ranging from 0 which is the most privileged, to 3 which is least privileged.
Most modern operating systems use level 0 for the kernel/executive, and use level 3 for
application programs. Any resource available to level n is also available to levels 0 to n, so the
privilege levels are rings. When a lesser privileged process tries to access a higher privileged
process, a general protection fault exception is reported to the OS.

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Computer operating systems provide different levels of access to resources. A protection ring is
one of two or more hierarchical levels or layers of privilege within the architecture of a computer
system. This is generally hardware-enforced by some CPU architectures that provide different
CPU modes at the hardware or microcode level. Rings are arranged in a hierarchy from most
privileged (most trusted, usually numbered zero) to least privileged (least trusted, usually with
the highest ring number). On most operating systems, Ring 0 is the level with the most privileges
and interacts most directly with the physical hardware such as the CPU and memory.

Figure 1: Privilege Levels (Rings) in OS

In the inner most ring are the most protected instructions; those that only the kernel should be allowed
to call. For example, the HLT instruction to halt the processor should not be allowed to be run by a user
application, since it would stop the entire computer from working. However, the kernel needs to be able
to call this instruction when the computer is legitimately shut down.

Each inner ring can access any instructions protected by a further out ring, but not any protected by a
further in ring. Not all architectures have multiple levels of rings as above, but most will either provide
for at least a "kernel" and "user" level.

TYPES OF INSTRUCTIONS:
Instructions are divided into two categories:
 Non-Privileged Instructions
 Privileged Instructions.
NON-PRIVILEGED INSTRUCTIONS:
A Non-Privileged instruction is an instruction that any application or user can execute.
(OR)
The Instructions that can run only in User Mode are called Non-Privileged Instructions.
Various examples of Non-Privileged Instructions include:

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 Reading the status of Processor

 Reading the System Time
 Generate any Trap Instruction
 Sending the final printout of Printer
Also, it is important to note that in order to change the mode from Privileged to Non-Privileged,
we require a Non-privileged Instruction that does not generate any interrupt.
Examples of Non-Privileged Instructions:
I. movl
II. addl
III. call
IV. ret
PRIVILEGED INSTRUCTIONS:
A Privileged instruction, on the other hand, is an instruction that can only be executed in kernel
mode.
(OR)
The Instructions that can run only in Kernel Mode are called Privileged Instructions.
Instructions are divided in this manner because privileged instructions could harm the kernel.
Privileged Instructions possess the following characteristics:
1) If any attempt is made to execute a Privileged Instruction in User Mode, then it will not be
executed and treated as an illegal instruction. The Hardware traps it to the Operating System.
2) Before transferring the control to any User Program, it is the responsibility of the Operating
System to ensure that the Timer is set to interrupt. Thus, if the timer interrupts then the
Operating System regains the control.
Thus, any instruction which can modify the contents of the Timer is a Privileged Instruction.
3) Privileged Instructions are used by the Operating System in order to achieve correct
operation.
4) Various examples of Privileged Instructions include:
 I/O instructions and Halt instructions
 Turn off all Interrupts
 Set the Timer
 Context Switching
 Clear the Memory or Remove a process from the Memory
 Modify entries in Device-status table
Examples of Privileged Instructions:
I. insl
II. outb
III. inb
IV. int
A program that tries to run a system call the kernel does not consider to be allowed will be
terminated.

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Q.No.5: What are different types of interrupts?

ANS:
Interrupt is a signal which has highest priority from hardware or software which processor should
process its signal immediately.

Types of Interrupts:
Although interrupts have highest priority than other signals, there are many type of interrupts
but basic type of interrupts are
1. HARDWARE INTERRUPTS: If the signal for the processor is from external device or
hardware is called hardware interrupts. Example: from keyboard we will press the key to
do some action this pressing of key in keyboard will generate a signal which is given to
the processor to do action, such interrupts are called hardware interrupts. Hardware
interrupts can be classified into two types they are
 Maskable Interrupt: The hardware interrupts which can be delayed when a much
highest priority interrupt has occurred to the processor.
 Non-Maskable Interrupt: The hardware which cannot be delayed and should
process by the processor immediately.
2. SOFTWARE INTERRUPTS: Software interrupt can also divided in to two types. They are
 Normal Interrupts: the interrupts which are caused by the software instructions
are called software instructions.
 Exception: Unplanned interrupts while executing a program is called Exception.
For example: while executing a program if we got a value which should be divided
by zero is called a exception.
CLASSIFICATION OF INTERRUPTS ACCORDING TO PERIODICITY OF OCCURRENCE:
1. Periodic Interrupt: If the interrupts occurred at fixed interval in timeline then that
interrupts are called periodic interrupts
2. Aperiodic Interrupt: If the occurrence of interrupt cannot be predicted then that interrupt
is called aperiodic interrupt.
CLASSIFICATION OF INTERRUPTS ACCORDING TO THE TEMPORAL RELATIONSHIP WITH
SYSTEM CLOCK:
1. Synchronous Interrupt: The source of interrupt is in phase to the system clock is called
synchronous interrupt. In other words interrupts which are dependent on the system
clock. Example: timer service that uses the system clock.
2. Asynchronous Interrupts: If the interrupts are independent or not in phase to the system
clock is called asynchronous interrupt.

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Q.No.6: What is interrupt handling in OS?

INTERRUPT HANDLING:
An operating system usually has some code that is called an Interrupt Handler. The interrupt
handler prioritizes the interrupts and saves them in a queue if more than one is waiting to be
handled.
Interrupt handlers, also commonly known as Interrupt Service Routine (ISR), is a block of code
that is associated with a specific interrupt condition.
If there is an interrupt present then it will trigger the interrupt handler, the handler will stop the
present instruction which is processing and save its configuration in a register and load the
program counter of the interrupt from a location which is given by the Interrupt Vector Table
(IVT).
After processing the interrupt by the processor interrupt handler will load the instruction and its
configuration from the saved register, process will start its processing where it’s left. This saving
the old instruction processing configuration and loading the new interrupt configuration is also
called as context switching.
The interrupt handler is also called as Interrupt service routine (ISR). There are different types of
interrupt handler which will handle different interrupts. For example for the clock in a system
will have its interrupt handler, keyboard it will have its interrupt handler for every device it will
have its interrupt handler.
The main features of the ISR are:
 Interrupts can occur at any time they are asynchronous. ISR’s can call for asynchronous
interrupts.
 Interrupt service mechanism can call the ISR’s from multiple sources.
 ISR’s can handle both maskable and non maskable interrupts. An instruction in a program
can disable or enable an interrupt handler call.
 ISR on beginning of execution it will disable other devices interrupt services. After
completion of the ISR execution it will re initialize the interrupt services.
 The nested interrupts are allowed in ISR for diversion to other ISR.

TYPE OF INTERRUPT HANDLERS:

1. First Level Interrupt Handler (FLIH) is hard interrupt handler or fast interrupt handler.
These interrupt handlers have more jitter while process execution and they are mainly
maskable interrupts
2. Second Level Interrupt Handler (SLIH) is soft interrupt handler and slow interrupt handler.
These interrupt handlers are having less jitter.

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Figure 2: Interrupt and Interrupt Handler

Q.No.7: What is Vector Table?

THE INTERRUPT VECTOR TABLE
An interrupt vector is the memory location of an interrupt handler, which prioritizes interrupts
and saves them.
(OR)
The interrupt vector table, often abbreviated to IVT or simply IV, is an array of pointers to
functions, associated by the CPU to handle specific exceptions, such as faults, system service
requests from the application, and interrupt requests from peripherals. The IVT is usually located
at the beginning of the binary image, and thus stored starting from the lowest address in the
flash memory.

An example for the vector table is given by:

RESET in 8051:
There are six interrupts including RESET in 8051.

INTERRUPTS ROM LOCATION (HEX) PIN

Serial COM (RI and TI) 0023
Timer 1 interrupts(TF1) 001B
External HW interrupt 1 (INT1) 0013 P3.3 (13)
External HW interrupt 0 (INT0) 0003 P3.2 (12)
Timer 0 (TF0) 000B
Reset 0000 9

1. When the reset pin is activated, the 8051 jumps to the address location 0000. This is power-
up reset.

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2. Two interrupts are set aside for the timers: one for timer 0 and one for timer 1. Memory
locations are 000BH and 001BH respectively in the interrupt vector table.
3. Two interrupts are set aside for hardware external interrupts. Pin no. 12 and Pin no. 13 in
Port 3 are for the external hardware interrupts INT0 and INT1, respectively. Memory locations
are 0003H and 0013H respectively in the interrupt vector table.
4. Serial communication has a single interrupt that belongs to both receive and transmit.
Memory location 0023H belongs to this interrupt.

Figure 3: Shows a typical vector table of a real system. The undefined instruction handler is located so that a simple branch is
adequate, whereas the other vectors require an indirect address using assembler instructions specific for loading.

METHODS OF USING INTERRUPT VECTOR TABLE:

An interrupt vector table is used in the three most popular methods of finding the starting
address of the interrupt service routine:
PREDEFINED:
The "predefined" method loads the program counter (PC) directly with the address of some entry
inside the interrupt vector table. The jump table itself contains executable code. While in
principle an extremely short interrupt handler could be stored entirely inside the interrupt vector
table, in practice the code at each entry is a single jump instruction that jumps to the full interrupt
service routine (ISR) for that interrupt. The Intel 8080[5], Atmel AVR and all 8051 and Microchip
microcontrollers use the predefined approach.

FETCH:
The "fetch" method loads the PC indirectly, using the address of some entry inside the interrupt
vector table to pull an address out of that table, and then loading the PC with that address. Each
and every entry of the IVT is the address of an interrupt service routine. All Motorola/Freescale
microcontrollers use the fetch method.

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INTERRUPT ACKNOWLEDGE:
For the "interrupt acknowledge" method, the external device gives the CPU an interrupt handler
number. The interrupt acknowledge method is used by the Intel Pentium and many older
microprocessors.

Q.No.8: What is Program Counter?

Ans:
PROGRAM COUNTER:
The program counter is commonly known as the instruction address register or instruction
pointer in Intel x86 micro processing code. The program counter keeps track of the next memory
address of instructions that are to be executed. Once the current instruction is completed, the
program counter holds the address of the next location of instruction that needs to be executed
by the processor.

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Q.No.9: What is Context Switching?

Ans:
CONTEXT SWITCHING:
A context switch is a procedure that a computer's CPU (central processing unit) follows to change
from one task (or process) to another while ensuring that the tasks do not conflict. Effective
context switching is critical if a computer is to provide user-friendly multitasking.
In computing, a context switching is the process of storing the state of a process or thread, so
that it can be restored and resume execution at a later point. This allows multiple processes to
share a single central processing unit (CPU), and is an essential feature of a multitasking operating
system.
There are three potential triggers for a context switch:
MULTITASKING
Most commonly, within some scheduling scheme, one process must be switched out of the CPU
so another process can run. This context switch can be triggered by the process making itself
unrunnable, such as by waiting for an I/O or synchronization operation to complete.
On a pre-emptive multitasking system, the scheduler may also switch out processes that are still
runnable. To prevent other processes from being starved of CPU time, preemptive schedulers
often configure a timer interrupt to fire when a process exceeds its time slice. This interrupt
ensures that the scheduler will gain control to perform a context switch.

INTERRUPT HANDLING
When an interrupt occurs, the hardware automatically switches a part of the context (at least
enough to allow the handler to return to the interrupted code). The handler may save additional
context, depending on details of the particular hardware and software designs. Often only a
minimal part of the context is changed in order to minimize the amount of time spent handling
the interrupt. The kernel does not spawn or schedule a special process to handle interrupts, but
instead the handler executes in the (often partial) context established at the beginning of
interrupt handling. Once interrupt servicing is complete, the context in effect before the interrupt
occurred is restored so that the interrupted process can resume execution in its proper state.

USER AND KERNEL MODE SWITCHING

When the system transitions between user mode and kernel mode, a context switch is not
necessary; a mode transition is not by itself a context switch. However, depending on the
operating system, a context switch may also take place at this time.

THANK YOU
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