MICROPROCESSOR (KCS 403)

1) Which is the microprocessor comprises:

a) Register section
b) One or more ALU
c) Control unit
d) All of these
2) What is the store by register?
a) Data
b) Operands
c) Memory
d) None of these
3) Accumulator based microprocessor examples are:
a) Intel 8085
b) Intel 8086
c) a and b both
d) None of these
4) A set of register which contain are:
a) Data
b) memory addresses
c) result
d) all of these
5) There are primarily two types of register
a) General purpose register
b) Dedicated register
c) A and B
d) none of these
6) Name of typical dedicated register is
a) PC
b) IR
c) SP
d) All of these
7) BCD stands for
a) Binary coded decimal
b) Binary coded decoded
c) Both a
&b
d) None of
these
8) The processor 80386/ 80486 and Pentium processor uses ____ bits address bus
a) 16
b) 32
c) 36
d) 64
9) Which is not the control bus signal:
a) READ
b) WRITE
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c) RESET
d) None of these
10) PROM stands for:
a) Programmable read-only memory
b) Programmable read write memory
c) Programmer read and write memory
d) None of these

11) EPROM stands for:

a) Erasable Programmable read-only memory
b) Electrically Programmable read write memory
c) Electrically Programmable read-only memory
d) None of these
12) Each memory register has
a) Address
b) Contents
c) Both a and b
d) None of these
13) Customized ROMS are called
a) Mask ROM
b) Flash ROM
c) EPROM
d) None of these
14) A microprocessor retrieves instructions from
a) Control memory
b) Cache memory
c) Main memory
d) Virtual memory
15) Which causes the microprocessor to immediately terminate its present activity
a) RESET signal
b) INTERUPT signal
c) Both
d) None of these
16) INTR : it implies the signal:
a) INTRRUPT REQUEST
b) INTRRUPT RIGHT
c) INTRRUPT WRONG
d) INTRRUPT RESET

17) Which of the following are the two main components of the CPU?
a) Control Unit and Registers
b) Registers and Main Memory
c) Control unit and ALU
d) ALU and Bus
18) The language that the computer can understand and execute is called
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a) Machine language
b) Application software
c) System program
d) All of the above
19) Which of the following memories needs refresh?
a) SRAM
b) DRAM
c) ROM
d) ALL of the above
20) The memory which is programmed at the time it is manufactured
a) PROM
b) RAM
c) PPROM
d) EPROM
21) The first microprocessor built by the Intel Corporation was called

a) 8008
b) 8080
c) 4004
d) 8800
22) Which is the type of memory for information that does not change on
your computer?
a) RAM
b) ROM
c) ERAM
d) RW/RAM
23) Which company is the biggest player in the microprocessor industry?
a) Motorola
b) IBM
c) INTEL
d) AMD
24) The term giga byte refers to
a) 1024 bytes
b) 1024 kilobytes
c) 1024 megabytes
d) 1024 gigabytes
25) 4GB ROM consist of
a) 12 Address lines
b) 32 Address lines
c) 4 Address lines
d) 10 Address lines
26) Which 3x8 decoder IC used for interfacing
a) 74HS13
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b) 74LS17
c) 74LS138
d) 9955
27) FFH equivalent to in binary
a) 00001111
b) 11001100
c) 11001111
d) 11111111
28) Universal logic gates are
a) AND, OR
b) OR, NOT
c) NAND, NOR
d) NAND, OR
29) C and C++ is
a) Low level language
b) High level language
c) Assembly level language
d) None of these
30) 32-bit microprocessor consist
of
a) 32 data lines
b) 16 data lines
c) 32 address lines
d) 16 address lines
31. 8085 microprocessor Instruction LHLD 1234H is having following Addressing Mode:

a) Register addressing mode

b) Direct addressing mode

c) Indirect addressing mode

d) Implied addressing mode

32. What is the purpose of the READY signal in 8085

a) It is used to provide WAIT states when the 8085 is communicating with a slow
peripheral device.

b)It indicates that the 8085 is ready to receive inputs

c) It indicates that the 8085 is ready to provide Direct Memory Access

d) It indicates that the 8085 is ready to send outputs

33. Number of machine cycles required to execute LXI H, 7835H instruction in 8085 will
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be:

a) 1 machine cycle

b) 3 machine cycles

c) 5 machine cycles

d) 2 machine cycles
34. Number of T states required to execute JMP 5012H instruction is:

a) 10

b) 16

c) 13

d) 7
35. If Register A=59H and Register D= 4DH then after execution of ADD D value of Carry
and Zero flag will be:

a)CF= 0, ZF=0

b) CF= 0, ZF=1

c) CF= 1, ZF=0

d) CF= 1, ZF=1
36. In memory read machine cycle in 8085 , values of status signals are :

a) S0= 0, S1=0

b) S0= 1, S1=0

c) S0= 0, S1=1

d) S0= 1, S1=1
37. Memory handling capacity of 8085 microprocessor is:

a) 64 KB

b) 1MB

c) 16 MB
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d) 4 MB

38. A programming model of a microprocessor is ____.

a) list of all I/O devices that can be connected

b) diagrams of the internal bus architecture

c) part of the block diagram that a programmer can affect using the instruction set

d) the entire block diagram

39. The frequency of 8085 microprocessor is

a) 3MHz

b) 1Hz

c) 2Hz

d) 3KHz
40. The vector address of TRAP is

a) 0024H

b) 0038H

c) 002AH

d) 0020H
41. Non-Maskable Interrupt is

a) RST 7.5

b) RST 5.5

c) INTR

d) TRAP
42. Which pin is used for de-multiplexing of buses

a) ALE

b) BHE
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c) RD

d) WR
43. The instruction size of LDA 3000H is

a) 3 Byte

b) 2 Byte

c) 1 Byte

d) 4 Byte
44. Example of Immediate addressing mode is

a) STA 3000H

b) LDA 3000H

c) MVI A, 32H

d) HLT
45. 8085 consist of I/O ports:

a) 256

b) 128

c) 32

d) 8
46. 8085 consist of address lines:

a) 24

b) 16

c) 8

d) 32
47. SP and PC are known as

a) Stack program and Program coin

b) Stack pointer and Program counter

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c) Static pointer and Permanent counter

d) Stack Program and Programmable counter

48. Which flag is used for checking number of 1’s in data

a) Carry

b) Sign

c) Zero

d) Parity
49. INR A is used for

a) Checking accumulator content

b) Increment accumulator content by one

c) Increment accumulator content by two

d) Decrement accumulator
50. Temp. registers in 8085 are

a) W and Z

b) X and Y

c) A and B

d) Y and Z
51. For 8085, the size of accumulator is

a) 4-bit

b) 8-bit

c) 16-bit

d) 24-bit
52. For 8085, the size of PC is

a) 4-bit

b) 8-bit
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c) 16-bit

d) 24-bit
53. Which is not flag in 8085

a) Carry

b) Sign

c) Direction

d) Zero

54. ADD M is type of

a) Register addressing mode

b) Immediate addressing mode

c) Implied addressing mode

d) Indirect addressing mode

55. Which register pair has been used as by default memory pointer in 8085

a) H and L

b) W and Z

c) B and C

d) D and E
56. 8085 operating voltage is

a) +5V

b) -5V

c) +10V

d) -3V
57. HOLD and HLDA pins are related to

a) Serial data transfer

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b) Parallel data transfer

c) DMA

d) None of these
58. Which machine cycle is used for fetching the data from input location:

a) Opcode fetch

b) I/O Read

c) I/O write

d) I/O fetch
59. Memory read consist of

a) 3T

b) 4T

c) 5T

d) 6T
60. After execution of MVI A, 00H, accumulator consist of

a) 32H

b) 00H

c) 24H

d) None of these
61. To execute one instruction at a time (single stepping execution) following flag bit is
used in 8086 microprocessor

a) Trap Flag

b) Interrupt Flag

c) Direction Flag

d) Overflow Flag
62. The maximum size of each segment in memory segmentation of 8086 is:
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a) 16 KB

b) 32 KB

c) 48 KB

d) 64 KB
63. In 8086 one of the following statement is not true:

a) Coprocessor is interfaced in MIN mode.

b) Coprocessor is interfaced in MAX mode.

c) I/O can be interfaced in MIN/MAX mode.

d) Supports pipeline architecture

64. For Direction Flag(DF)=1, if starting address of string is 51004H then second string
element address will be:

a) 51003H

b) 51004H

c) 51005H

d) 51003H or 51005H.
65. In 8086 Microprocessor Overflow flag will set when

a) The sum is more than 16 bit.

b) Sign and Carry flag bits are set

c) Only sign flag is set.

d) Signed numbers go out of their range after arithmetic operation.

66. BIU in 8086 contains an instruction queue of size

a) 2 Bytes.

b) 4Bytes

c) 6 Bytes.

d) 8 Bytes.
67. EU in 8086 stands for
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a) Extended unit.

b) End unit

c) Execution unit.

d) Encapsulation unit.
68. Which statement is false about EU in 8086 Microprocessor

a) It decodes various instructions.

b) It generates necessary control signals

c) It fetches instructions from memory.

d) It performs various arithmetic operations using ALU.

69. For CS= 1234H and IP= ABCDH, 20 bit physical address of the instruction will be:

a) 0BE01H.

b) 1FC0DH

c) 1CF0DH .

d) ACE04H.
70. For DS=1234H, Maximum Possible physical Address for an element in data segment
will be:

a) 2323F H

b) 21223F H

c) 2233F H

d) 2212F H
71. Which of the following index/pointer register cannot be used to provide offset address
with DS register to locate an element in data segment:

a) BX

b) IP

c) SI
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d) DI
72. Memory handling capacity of 8086 microprocessor is:

a) 64 KB

b) 1MB

c) 16 MB

d) 4 MB
73. For 8086 microprocessor, following statement is false:

a) It supports memory segmentation.

b) It supports pipelined architecture

c) It supports multiprogramming.

d) It has a 20 bit data bus.

74. The number of segment registers available in 8086 microprocessor are:

a) 3

b) 4

c) 5

d) 6
75. 8086 microprocessor supports ______ number of flag bits.

a) 5

b) 7

c) 9

d) 11
76. 8086 consist of address lines:

a) 20

b) 16

c) 8
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d) 24
77. 8086 microprocessor supports ______ number of software interrupts

a) 8

b) 16

c) 128

d) 256
78. Software interrupt which corresponds to division by zero error is:

a) TYPE 0

b) TYPE 1

c) TYPE 2

d) TYPE 3
79. INC instruction increases the content of destination register by:

a) 1

b) 2

c) 4

d) 8
80. Software interrupt which represents a break-point interrupt is:

a) TYPE 0

b) TYPE 1

c) TYPE 2

d) TYPE 3
81. in 8086 microprocessor, IP register is ____ bits length

a) 4-bit

b) 8-bit

c) 16-bit
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d) 24-bit
82. For 8086, IF flag bit is recognized as:

a) Indicate flag

b) Inter flag

c) Interrupt flag

d) Initial flag
83. Which is true about hardware interrupts in 8086 microprocessor:

a) It supports only one hardware interrupt NMI

b) It supports two hardware interrupts NMI and INTR

c) It supports three hardware interrupts NMI, INTR and TRAP

d) It supports only one hardware interrupt INTR

84. Offset address is not provided by following____ register in 8086 microprocessor:

a) CS

b) SP

c) BP

d) IP
85. In 8086, ____Register is used to provide offset address in calculation of physical
address of next instruction is:

a) IP

b) BP

c) BX

d) SP
86. STC instruction is having following addressing mode:

a) Register addressing mode

b) Direct addressing mode

 MICROPROCESSOR (KCS 403)

c) Indirect addressing mode

d) Implied addressing mode

87. MOV CL, DH instruction is having following addressing mode:

a) Register addressing mode

b) Direct addressing mode

c) Indirect addressing mode

d) Implied addressing mode

88. To clear the carry flag in 8086 microprocessor, following instruction is used:

a) STC

b) CLC

c) CMC

d) CLD
89. To set the direction flag in 8086 microprocessor, following instruction is used:

a) STC

b) STD

c) SETD

d) OLD
90. Software interrupt used for single step execution of program is:

a) TYPE 0

b) TYPE 1

c) TYPE 2

d) TYPE 3
91. A sequence of two register that multiplies the content of DE register pair by two and store
the result in HL register pair is
(a) XCHG and DAD B
(b) XTHL and DAD H
(c) PCHL and DAD B
(d) XCHG and DAD H
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92. Consider the sequence of 8085 instruction given below.

LXI H, 9258H
MOV A,M
CMA
MOV M,A
Which one of the following is performed by this sequence?
(a) Contents of location 9258H are moved to accumulator
(b) Contents of location 9258H are compared with the contents of the accumulator
(c) Contents of location 9258H are complemented and stored in location 9258H
(d) Contents of location 5892H are complemented and stored in location 5892H
93. It is desired to multiply the numbers 0AH by 0BH and store the result in the accumulator.
The numbers are available in register B and C respectively. A part of the 8085 program
for this purpose is given below:
MVI A, 00H
Loop:_____________
___________________

HLT
END
The sequence of instructions to complete the program would be
(a) JNZ LOOP, ADD B, DCR C
(b) ADD B, JNZ LOOP, DCR C
(c) DCR C, JNZ LOOP, ADD B
(d) ADD B, DCR C, JNZ LOOP
94. The following program starts at location 0100H.
LXI SP, 00FFH
LXI H, 0107H
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109H is
(a) 20H
(b) 02H
(c) 00H
(d) FFH
95. For 8085 microprocessor, the following program is executed.
MVI A, 05H;
MVI B, 05H;
PTR: ADD B;
DCR B;
JNZ PTR;
ADI 03H;
HLT;
At the end of program, accumulator contains
(a) 17H
(b) 20H
(c) 23H
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(d) 05H
96. An 8085 assembly language program is given below. Assume that the carry flag is
initially unset. The content of the accumulator after the execution of the program is
MVI A, 07H
RLC
MOV B,A
RLC
RLC
ADD B
RRC
(a) 8CH
(b) 64H
(c) 23H
(d) 15H
97. For the 8085 assembly language program given below, the content of the accumulator
after the execution of the program is
3000 MVI A, 45H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
(a) 00H (b) 45H (c) 67H (d) E7H
98. An 8085 executes the following instructions
2710 LXI H, 30A0 H
2713 DAD H
2714 PCHL
All address and constants are in Hex. Let PC be the contents of the program counter and
HL be the contents of the HL register pair just after executing PCHL. Which of the
following statements is correct?
(a) PC=2715H HL=30A0H
(b) PC=30A0H HL=2715H
(c) PC=6140H HL=6140H
(d) PC=6140H HL=2715H
99. An 8085 assembly language program is given below.
MVI A, B5H
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
HLT
The contents of the accumulator just execution of ADD instruction in line 4 will be
(a) C3H (b) EAH (c) DCH
(d) 69H
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100. From question no. 9, after execution of line 7 of the program, the status of the CY
and Z flags will be
(a) CY=0, Z=0
(b) CY=0, Z=1
(c) CY=1, Z=0
(d) CY=1, Z=1
101. Following is the segment of a 8085 assembly language program
LXI SP, EFFFH
CALL 3000H
-
-
-
3000H: LXI H, 3CF4H
PUSH PSW
SPHL
POP PSW
RET
On completion of RET execution, the contents of SP is
(a) 3CF0 H (b) 3CF8 H (c) EFFD H (d) EFFF H
102. The following program starts at location 0100H.
LXI SP, 00FF
LXI H, 0701
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109 H is
(a) 20 H (b) 02 H (c) 00 H (d) FF H
103. Continuation of question no. 12, if in addition following code exists from 019H
onwards,
ORI 40 H
ADD M
What will be the result in the accumulator after the last instruction is executed
(a) 40 H (b) 20 H (c) 60 H (d) 42H
104. Consider the following assembly language program
MVI B, 87H
MOV A, B
START: JMP NEXT
MVI B, 00H
XRA B
OUT PORT1
HLT
NEXT: XRA B
JP START
OUT PORT2
HLT
The execution of above program in an 8085 microprocessor will result in
(a) an output of 87H at PORT1
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(b) an output of 87H at PORT2

(c) infinite looping of the program execution with accumulator data remaining at 00H
(d) infinite looping of the program execution with accumulator data alternating between
00H and 87H
105. The contents of register (B) and accumulator (A) of 8085 microprocessor are 49J
are 3AH respectively. The contents of A and status of carry (CY) and sign (S) after
execution SUB B instructions are
(a) A = F1, CY = 1, S = 1
(b) A = 0F, CY = 1, S = 1
(c) A = F0, CY = 0, S = 0
(d) A = 1F, CY = 1, S = 1
106. The following instructions have been executed by an 8085 MP
ADDRESS (HEX) INSTRUCTION
6010 LXI H, 8 A 79 H
6013 MOV A, L
6015 ADDH
6016 DAA
6017 MOV H, A
6018 PCHL
From which address will the next instruction be fetched?
(a) 6019 (b) 6379 (c) 6979 (d) None of the above
107. The following sequence of instructions are executed by an 8085 microprocessor:
1000 LXI SP, 27 FF
1003 CALL 1006
1006 POP H
The contents of the stack pointer (SP) and the HL, register pair on completion of
execution of these instruction are
(a) SP = 27 FF, HL = 1003
(b) SP = 27 FD, HL = 1003
(c) SP = 27 FF, HL = 1006
(d) SP = 27 FD, HL = 1006
108. In a microprocessor system, the stack is a used for
(a) Storing the program return address whenever a subroutine jump instruction is
executed
(b) Transmitting and receiving input output data
(c) Storing all important CPU register contents whenever an interrupt is to be serviced
(d) Storing program instructions for interrupt service routine
109. In a microprocessor , the register which holds the address of the next instruction
to be fetched is
(a) Accumulator (b) Program Counter (c) Stack pointer (d) Instruction register
110. In an 8085 microprocessor , which one of the following instruction changes the
contents of accumulator?
(a) MOV B,M (b) PCHL (c) RNZ (d) SBI BEH
111. In an 8085 microprocessor, the contents of the accumulator and the carry flag are
A7H and 0 respectively. If the instruction RLC is executed, the nt contents of
accumulator and the carry flag respectively , will be
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(a) 4EH and 0 (b) 4EH and 1 (c) 4F and 0 (d) 4F and 1
112. The following program is run on an 8085 microprocessor
Memory address Instruction
2000H LXI SP,1000H
2003H PUSH H
2004H PUSH D
2005H CALL 2050H
2008H POP H
2009H HLT
At the completion of execution of the program, contents of PC and SP is
(a) PC=200A, SP=1000H (b) PC=200A, SP=0FFEH (c) none (d) All
113. An 8085 microprocessor executes “STA 1234H” with starting address location
1FFEH. While the instruction is fetched and executed, the sequence of values written at
the address pin A15-A8 is
(a) 1FH,1FH,20H,12H (b) 1FH,1FH,12H,12H (c) both (d) none
114. Which one of the following 8085 microprocessor programs correctly calculates
the product of two 8 bit number stored in register B and C?
(a) MVI A,00H (C) both
CMP C
LOOP DCR B
HLT
(b) MVI A, 00H (d) None
LOOP ADD C
DCR B
JNZ LOOP
HLT
115. In an 8085 system, a PUSH operation requires more clock cycle than a POP
operation. Which one of the following options is the correct reason for this
(a) Memory write operations are slower than memory read operations in 8085 based
system
(b) The stack pointer needs to be pre decremented before writing registers in a PUSH,
whereas a POP operation uses the address already in stack pointer
(c) Both
(d) None
116. Which assembler are used to convert 8086 assembly language program into
machine language program
(a) MASM (b) TASM (c) DOS (d) All
117. Meaning of inter-segment jump in 8086 is
(a) Operation of jumping from one code segment to another
(b) Operation of jumping within same code segment
(c) Both
(d) None
118. Meaning of intra-segment jump in 8086 is
(a) Operation of jumping from one code segment to another
(b) Operation of jumping within same code segment
(c) Both
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(d) None
119. Write an instruction set to initialize DS with the value 3000H
(a) MOV DS, AX (C) both
MOV AX, 3000H
(b) MOV AX,3000H (d) none
MOV DS, AX
120. What is full form of MASM
(a) Macro assembler (b) Micro assembler (c) both (d) none
121. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) Timing and control block
b) Program command control block
c) Priority block
d) None of the mentioned
122. The priority between the DMA channels requesting the services can be resolved by
a) Timing and control block
b) Program command control block
c) Priority block
d) None of the mentioned
123. The register that holds the current memory address is
a) Current word registers
b) Current address registers
c) Base address register
d) Command register
124. The register that holds the data byte transfers to be carried out is
a) Current word register
b) Current address register
c) Base address register
d) Command register
125. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
126. The current address register is programmed by the CPU as
a) Bit-wise
b) Byte-wise
c) Bit-wise and byte-wise
d) None of the mentioned
127. Which of these register’s contents is used for auto-initialization (internally)?
a) Current word register
b) Current address register
c) Base address register
d) Command register
128. The register that maintains an original copy of the respective initial current address register
and current word register is
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a) mode register
b) Base address register
c) Command register
d) Mask register
129. The register that can be automatically incremented or decremented, after each DMA
transfer is
a) Mask register
b) Mode register
c) Command register
d) Current address register
130. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
131. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
132. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
133. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned

134. The data bus buffer is controlled by

a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
135. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR (ACTIVE LOW)
d) All of the mentioned
136. How many pins does the 8255 PPI IC contains?
a) 24
b) 20
c) 32
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d) 40
137. In which mode do all the Ports of the 8255 PPI work as Input-Output units for data transfer?
a) BSR mode
b) Mode 0 of I/O mode
c) Mode 1 of I/O mode
d) Mode 2 of I/O mode
138. Which of the following pins are responsible for handling the on the Read Write control
Logic unit of the 8255 PPI?
a) CS'
b) RD'
c) WR'
d) ALL of the above
139. In which of the following modes is the 8255 PPI capable of transferring data while
handshaking with the interfaced device?
a) BSR mode
b) Mode 0 of I/O mode
c) Mode 1 of I/O mode
d) Mode 2 of I/O mode
140. How many bits of data can be transferred between the 8255 PPI and the interfaced device at
a time? or What is the size of internal bus of the 8255 PPI?
a) 16 bits
b) 12 bits
c) 8 bits
d) None of the above

141. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7

142. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
143. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
144. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
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d) all of the mentioned

145. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
146. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
147. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
148. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) Mode 1
c) Mode 2
d) Mode 3
149. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low
for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
150. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4

Answers

1. D
2. A
3. C
4. D
5. C
6. D
7. A
8. B
9. C
10. A
11. A
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12. C
13. A
14. C
15. B
16. A
17. C
18. A
19. B
20. A
21. C
22. B
23. C
24. C
25. B
26. C
27. D
28. C
29. B
30. A

31. B
32. A
33. B
34. A
35. A
36. C
37. A
38. C
39. A
40. A
41. D
42. A
43. A
44. C
45. A
46. B
47. B
48. D
49. B
50. A
51. B
52. C
53. C
54. D
55. A
56. A
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57. C
58. B
59. A
60. A
61. A
62. D
63. A
64. A
65. D
66. C
67. C
68. C
69. C
70. C
71. B
72. B
73. D
74. B
75. C
76. A
77. D
78. A
79. A
80. D
81. C
82. C
83. B
84. A
85. A
86. D
87. A
88. B
89. B
90. B
91. D
92. C
93. D
94. C
95. A
96. C
97. C
98. C
99. B
100. C
101. B
102. C
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103. C
104. B
105. A
106. C
107. C
108. C
109. B
110. D
111. D
112. A
113. A
114. B
115. B
116. D
117. A
118. B
119. B
120. A
121. B
122. C
123. B
124. A
125. C
126. B
127. C
128. B
129. D
130. D
131. B
132. C
133. C
134. B
135. D
136. D
137. B
138. D
139. C
140. C
141. C
142. A
143. C
144. D
145. D
146. C
147. B
148. A
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149. A
150. C