NR PCS-978 - Instruction - Manual - EN - General - X (NR)

PCS-978
Transformer Protection
Instruction Manual
NR Electric Co., Ltd.

PCS-978 Transformer Protection
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment the user should be familiar with the contents of this
manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety
The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
NR ELECTRIC CO., LTD. i

Instructions and Warnings
The following indicators and standard definitions are used:
DANGER means that dearth, severe personal injury, or considerable equipment damage will
occur if safety precautions are disregarded.
WARNING means that dearth, severe personal, or considerable equipment damage could occur
if safety precautions are disregarded.
CAUTION means that light personal injury or equipment damage may occur if safety
precautions are disregarded. This particularly applies to damage to the device and to
resulting damage of the protected equipment.
WARNING!
The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.
WARNING!
During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.
Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.
In particular, the general facility and safety regulations for work with high -voltage equipment must
be observed. Noncompliance may result in dearth, injury, or significant equipment damage.
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.
WARNING!
 Exposed terminals
Do not touch the exposed terminals of this equipment while the power is on, as the high voltage
generated is dangerous
 Residual voltage
Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. It
takes a few seconds for the voltage to discharge.
ii NR ELECTRIC CO., LTD

CAUTION!
 Earth
The earthing terminal of the equipment must be securely earthed
 Operating environment
The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.
 Ratings
Before applying AC voltage and current or the DC power supply to the equipment, check that they
conform to the equipment ratings.
 Printed circuit board
Do not attach and remove printed circuit boards when DC power to the equipment is on, as this
may cause the equipment to malfunction.
 External circuit
When connecting the output contacts of the equipment to an external circuit, carefully check the
supply voltage used in order to prevent the connected circuit from overheating.
 Connection cable
Carefully handle the connection cable without applying excessive force.
Copyright
Release: R1.01 NR ELECTRIC CO., LTD.
P/N: EN_YJBH5100.0086.0002 69 Suyuan Avenue, Jiangning, Nanjing 211102, China
Copyright © NR 200 9. All rights reserved Tel: 86-25-87178185, Fax: 86-25-87178208
We reserve all rights to this document and to the information Website: www.nari-relays.com
contained herein. Improper use in particular reproduction and Email: nr_techsupport@nari-relays.com
dissemination to third parties is strictly forbidden except where
expressly authorized.
The information in this manual is carefully checked periodically,
and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or
improvement are greatly appreciated.
We reserve the rights to make technical improvements without
notice.
NR ELECTRIC CO., LTD. iii

iv NR ELECTRIC CO., LTD

Table of Contents
Preface.............................................................................................................................................. i
Introduction .............................................................................................................................. i
Health and Safety ..................................................................................................................... i
Instructions and Warnings..................................................................................................... ii
Table of Contents ........................................................................................................................... v
Chapter 1 Introduction ................................................................................................................... 1
1.1 Application ......................................................................................................................... 1
1.2 Functions ........................................................................................................................... 2
1.3 Features ............................................................................................................................. 5
1.4 Ordering Options .............................................................................................................. 8
Chapter 2 Technical Data..............................................................................................................11
2.1 Electrical Specifications..................................................................................................11
2.1.1 Alternating Current Input ......................................................................................11
2.1.2 Alternating Voltage Input ......................................................................................11
2.1.3 Power Supply .........................................................................................................11
2.1.4 Binary Input ........................................................................................................... 12
2.1.5 Binary Output ........................................................................................................ 12
2.1.6 Power Supply Output for Opto-coupler ............................................................. 12
2.2 Mechanical Specifications ............................................................................................. 12
2.3 Ambient Temperature and Humidity Range ................................................................. 13
2.4 Communication Port....................................................................................................... 13
2.4.1 Communication Port for RTU/SCADA ................................................................ 13
2.4.2 Communication Port for Print ............................................................................. 14
2.4.3 RS-485 for Clock Synchronization...................................................................... 14
2.5 Type Tests ........................................................................................................................ 15
2.5.1 Environmental Tests............................................................................................. 15
2.5.2 Mechanical Tests .................................................................................................. 15
NR ELECTRIC CO., LTD. v

2.5.3 Electrical Tests ...................................................................................................... 15
2.5.4 Electromagnetic Compatibility............................................................................ 15
2.6 Certifications ................................................................................................................... 16
2.7 Protective Functions ...................................................................................................... 16
2.7.1 Conventional Current Differential Protection .................................................... 16
2.7.2 DPFC Current Differential Protection ................................................................. 17
2.7.3 Restricted Earth Fault Protection ....................................................................... 17
2.7.4 Winding Differential Protection........................................................................... 17
2.7.5 Overexcitation Protection .................................................................................... 17
2.7.6 Frequency Protection........................................................................................... 18
2.7.7 Mechanical Protection.......................................................................................... 18
2.7.8 Impedance Protection .......................................................................................... 18
2.7.9 Phase Overcurrent protection ............................................................................. 18
2.7.10 Zero-sequence Overcurrent Protection ........................................................... 19
2.7.11 Phase Overvoltage Protection........................................................................... 19
2.7.12 Zero-sequence Overvoltage Protection ........................................................... 19
2.7.13 Phase Undervoltage Protection ........................................................................ 20
2.7.14 Thermal Overload Protection ............................................................................ 20
2.7.15 Breaker Failure Initiation ................................................................................... 20
2.7.16 Overload Alarm Element .................................................................................... 20
2.7.17 Initiating Cooler Element ................................................................................... 21
2.7.18 Blocking On-Load Tap Change Element.......................................................... 21
2.7.19 Zero-Sequence Overvoltage Alarm Element ................................................... 21
2.7.20 Zero-Sequence Overcurrent Alarm Element.................................................... 21
Chapter 3 Description of Operation Theory .............................................................................. 23
3.1 General Description ........................................................................................................ 23
3.2 Current Differential Protection ...................................................................................... 23
3.2.1 Features ................................................................................................................. 23
3.2.2 Fault Detector........................................................................................................ 24
3.2.3 Protection Principle .............................................................................................. 25
vi NR ELECTRIC CO., LTD

3.2.4 Logic Scheme ....................................................................................................... 40
3.2.5 Setting .................................................................................................................... 42
3.2.6 Input and Output................................................................................................... 49
3.3 Restricted Earth Fault Protection (REF) ....................................................................... 50
3.3.1 Fault Detector ........................................................................................................ 50
3.3.3 Logic Scheme ....................................................................................................... 57
3.3.4 Setting .................................................................................................................... 58
3.3.5 Input and Output................................................................................................... 60
3.4 Winding Differential Protection ..................................................................................... 63
3.4.1 Fault Detector ........................................................................................................ 63
3.4.3 Logic Scheme ....................................................................................................... 69
3.4.4 Setting .................................................................................................................... 69
3.4.5 Input and Output................................................................................................... 72
3.5 Overexcitation Protection .............................................................................................. 76
3.5.1 Fault Detector ........................................................................................................ 76
3.5.3 Logic Scheme ....................................................................................................... 79
3.5.4 Setting .................................................................................................................... 80
3.5.5 Input and Output................................................................................................... 84
3.6 Frequency Protection ..................................................................................................... 85
3.6.1 Fault Detector ........................................................................................................ 85
3.6.3 Logic Scheme ....................................................................................................... 87
3.6.4 Setting .................................................................................................................... 88
3.6.5 Input and Output................................................................................................... 91
3.7 Mechanical Protection .................................................................................................... 91
3.7.2 Logic Scheme ....................................................................................................... 92
NR ELECTRIC CO., LTD. vii

3.7.3 Setting .................................................................................................................... 92
3.7.4 Input and Output................................................................................................... 93
3.8 Impedance Protection .................................................................................................... 94
3.8.1 Fault Detector ........................................................................................................ 94
3.8.3 Logic Scheme ....................................................................................................... 98
3.8.4 Setting .................................................................................................................... 99
3.8.5 Input and Output................................................................................................. 102
3.9 Phase Overcurrent Protection (OC) ............................................................................ 103
3.9.1 Fault Detector ...................................................................................................... 103
3.9.2 Protection Principle ............................................................................................ 104
3.9.3 Logic Scheme ..................................................................................................... 107
3.9.4 Setting ...................................................................................................................110
3.9.5 Input and Output................................................................................................. 120
3.10 Zero-Sequence Overcurrent protection (ROC) ........................................................ 121
3.10.1 Fault Detector .................................................................................................... 121
3.10.2 Protection Principle.......................................................................................... 122
3.10.3 Logic Scheme ................................................................................................... 125
3.10.4 Setting ................................................................................................................ 127
3.10.5 Input and output ............................................................................................... 134
3.11 Phase Overvoltage Protection (OV) .......................................................................... 136
3.11.1 Fault Detector .................................................................................................... 136
3.11.2 Protection Principle .......................................................................................... 136
3.11.3 Logic Scheme .................................................................................................... 138
3.11.4 Setting ................................................................................................................ 139
3.11.5 Input and Output ............................................................................................... 143
3.12 Zero-Sequence Overvoltage Protection (ROV)........................................................ 144
3.12.1 Fault Detector.................................................................................................... 144
3.12.3 Logic Scheme ................................................................................................... 145
viii NR ELECTRIC CO., LTD

3.12.4 Setting ................................................................................................................ 147
3.12.5 Input and Output ............................................................................................... 149
3.13 Undervoltage Protection (UV) .................................................................................... 150
3.13.1 Fault Detector .................................................................................................... 150
3.13.3 Logic Scheme ................................................................................................... 151
3.13.4 Setting ................................................................................................................ 153
3.13.5 Input and Output ............................................................................................... 154
3.14 Thermal Overload Protection .................................................................................... 155
3.14.1 Fault Detector .................................................................................................... 155
3.14.3 Logic Scheme ................................................................................................... 156
3.14.4 Setting ................................................................................................................ 157
3.14.5 Input and Output ............................................................................................... 159
3.15 Breaker Failure Protection (BFP) .............................................................................. 160
3.15.1 Fault Detector .................................................................................................... 160
3.15.2 Protection Theory ............................................................................................. 160
3.15.3 Logic Scheme ................................................................................................... 161
3.15.4 Setting ................................................................................................................ 163
3.15.5 Input and Output ............................................................................................... 165
3.16 Overload Alarm Element ............................................................................................ 166
3.16.1 Principle ............................................................................................................. 166
3.16.2 Logic Scheme ................................................................................................... 166
3.16.3 Setting ................................................................................................................ 167
3.16.4 Input and Output ............................................................................................... 168
3.17 Initiating Cooler Element............................................................................................ 168
3.17.1 Principle ............................................................................................................. 168
3.17.2 Logic Scheme ................................................................................................... 169
3.17.3 Setting ................................................................................................................ 169
3.17.4 Input and Output ............................................................................................... 170
NR ELECTRIC CO., LTD. ix

3.18 Blocking On-load Tap Change Element.................................................................... 171
3.18.1 Principle ............................................................................................................. 171
3.18.2 Logic Scheme ................................................................................................... 171
3.18.3 Setting ................................................................................................................ 172
3.18.4 Input and Output ............................................................................................... 172
3.19 Zero-sequence Overvoltage Alarm Element ............................................................ 173
3.19.1 Principle ............................................................................................................. 173
3.19.2 Logic Scheme ................................................................................................... 173
3.19.3 Setting ................................................................................................................ 174
3.19.4 Input and Output ............................................................................................... 174
3.20 Zero-sequence Overcurrent Alarm Element ............................................................ 175
3.20.1 Principle ............................................................................................................. 175
3.20.2 Logic Scheme ................................................................................................... 175
3.20.3 Setting ................................................................................................................ 175
3.20.4 Input and Output ............................................................................................... 176
3.21 Voltage Element........................................................................................................... 177
3.21.1 Principle ............................................................................................................. 177
3.21.2 Input and Output ............................................................................................... 177
3.22 Current Element .......................................................................................................... 180
3.22.1 Principle ............................................................................................................. 180
3.22.2 Input and Output ............................................................................................... 181
3.23 Tripping Output Element ............................................................................................ 182
3.23.1 General Description.......................................................................................... 182
3.23.2 Tripping Matrix of Protection Element ........................................................... 183
3.23.3 Programmable Tripping Output Element ....................................................... 184
3.23.4 Setting ................................................................................................................ 184
3.23.5 Input and Output ............................................................................................... 185
3.24 Intermediate Variable Element................................................................................... 186
3.24.1 Principle ............................................................................................................. 186
3.24.2 Input and Output ............................................................................................... 186
x NR ELECTRIC CO., LTD

3.25 GOOSE Function......................................................................................................... 188
3.25.1 General Description.......................................................................................... 188
3.25.2 Setting ................................................................................................................ 188
3.25.3 Input and Output ............................................................................................... 189
Chapter 4 Automatic Supervision ............................................................................................ 193
4.1 General Description ...................................................................................................... 193
4.2 Relay Self-supervision ................................................................................................. 193
4.2.1 Relay Hardware Supervision ............................................................................. 193
4.2.2 Output Tripping Circuit Supervision ................................................................ 193
4.2.3 Setting Checking ................................................................................................ 193
4.2.4 Opto-coupler Power Supervision ..................................................................... 194
4.2.5 Fault Detector Element Supervision................................................................. 194
4.2.6 Voltage and Current Drift Monitoring and Auto Adjustment .......................... 194
4.2.7 Test Mode Supervision....................................................................................... 194
4.2.8 Hardware Configuration Supervision............................................................... 194
4.3 Secondary Circuit Supervision ................................................................................... 194
4.3.1 Voltage Transformer Supervision (VTS) ........................................................... 194
4.3.2 Current Transformer Supervision (CTS) .......................................................... 195
4.4 Failure and Abnormality Alarms.................................................................................. 195
4.4.1 Hardware Self-supervision Alarms ................................................................... 195
4.4.2 Equipment Operation Alarms ............................................................................ 197
Chapter 5 Metering and Recording .......................................................................................... 201
5.2 Metering ......................................................................................................................... 201
5.3 Event & fault Records................................................................................................... 202
5.3.1 Introduction ......................................................................................................... 202
5.3.2 Event Recording ................................................................................................. 202
5.3.3 Disturbance and Fault Recording ..................................................................... 202
5.3.4 Present Recording .............................................................................................. 204
Chapter 6 Hardware Description .............................................................................................. 205
NR ELECTRIC CO., LTD. xi

6.2 Plug-in Module Configuration ..................................................................................... 208
6.2.1 Configuration Principle ...................................................................................... 208
6.2.2 Typical Configuration ......................................................................................... 210
6.3 Plug-in Module Terminal Definition..............................................................................211
6.3.1 PWR Module (NR1301) ........................................................................................211
6.3.2 MON Module (NR 1102) ...................................................................................... 213
6.3.3 DSP Module 1 (Protection Calculation) ............................................................ 215
6.3.4 DSP Module 2 (Fault Detector Calculation) ..................................................... 215
6.3.5 Binary Input Module (NR1504) .......................................................................... 216
6.3.6 Binary Output Module ........................................................................................ 219
6.3.7 Analog Input Module .......................................................................................... 221
6.3.8 GOOSE Module (Optional) ................................................................................. 224
6.4 Tripping Matrix .............................................................................................................. 224
6.5 Output Contact .............................................................................................................. 225
6.5.1 Tripping Output Contact .................................................................................... 225
6.5.2 Signal Output Contact ........................................................................................ 226
Chapter 7 Common Settings ..................................................................................................... 227
7.1 Equipment Settings ...................................................................................................... 227
7.2 Communication Settings.............................................................................................. 228
7.3 System Settings ............................................................................................................ 230
7.4 Equipment Description Settings ................................................................................. 233
7.5 SLD Settings .................................................................................................................. 234
7.6 Equipment VEBI Settings ............................................................................................. 235
Chapter 8 Configurable Function ............................................................................................. 239
8.2 Introduction on PCS-PC software ............................................................................... 239
8.3 Protective Equipment Configuration .......................................................................... 239
8.3.1 System Configuration ........................................................................................ 239
8.3.2 Function Configuration ...................................................................................... 248
xii NR ELECTRIC CO., LTD

8.3.3 Configuration of LED Indicators ....................................................................... 248
8.3.4 Configuration of Binary Input............................................................................ 249
8.3.5 Configuration of Binary Output......................................................................... 250
8.3.6 Setting configuration.......................................................................................... 251
Chapter 9 HMI Operation Instruction ....................................................................................... 253
9.1 Human Machine Interface Overview ........................................................................... 253
9.1.1 Functionality........................................................................................................ 254
9.1.2 Keypad and Keys ................................................................................................ 254
9.1.3 LED Indications................................................................................................... 255
9.1.4 Communication Port .......................................................................................... 256
9.1.5 Communication................................................................................................... 256
9.2 Understand the HMI Menu Tree ................................................................................... 257
9.2.1 Overview .............................................................................................................. 257
9.2.2 VALUES................................................................................................................ 259
9.2.3 REPORT ............................................................................................................... 262
9.2.4 PRINT ................................................................................................................... 262
9.2.5 SETTINGS ............................................................................................................ 264
9.2.6 LOCAL_CTRL ...................................................................................................... 265
9.2.7 CLOCK ................................................................................................................. 265
9.2.8 VERSION .............................................................................................................. 265
9.2.9 TEST MODE ......................................................................................................... 265
9.2.10 INTERFACE ....................................................................................................... 266
9.3 Understand the LCD Display ....................................................................................... 266
9.3.1 Overview .............................................................................................................. 266
9.3.2 Display during Normal Operation ..................................................................... 266
9.3.3 Display When Tripping ....................................................................................... 267
9.3.4 Display under Abnormal condition ................................................................... 269
9.3.5 Display When Binary Input Changes Status.................................................... 270
9.3.6 Display Control Report ...................................................................................... 271
9.4 Keypad Operation ......................................................................................................... 272
NR ELECTRIC CO., LTD. xiii

9.4.1 View Device Status ............................................................................................. 272
9.4.2 View Device Report ............................................................................................ 273
9.4.3 View Module Information ................................................................................... 273
9.4.4 Print Device Report ............................................................................................ 274
9.4.5 View Device Setting ............................................................................................ 275
9.4.6 Modify Device Setting ........................................................................................ 275
9.4.7 Copy Device Setting ........................................................................................... 278
9.4.8 Switch Setting Group ......................................................................................... 279
9.4.9 Delete Report ...................................................................................................... 280
9.4.10 Modify Device Clock......................................................................................... 281
9.4.11 Check Software Version ................................................................................... 282
9.4.12 Communication Test ........................................................................................ 282
9.4.13 Select Language ............................................................................................... 284
Chapter 10 Communications .................................................................................................... 285
10.1 General Description .................................................................................................... 285
10.2 Rear Communication Port Information .................................................................... 285
10.2.1 RS-485 Interface................................................................................................ 285
10.2.2 Ethernet Interface ............................................................................................. 287
10.2.3 IEC60870-5-103 Communication ..................................................................... 288
10.3 IEC60870-5-103 Interface over Serial Port................................................................ 288
10.3.1 Physical Connection and Link Layer.............................................................. 289
10.3.2 Initialization ....................................................................................................... 289
10.3.3 Time Synchronization ...................................................................................... 289
10.3.4 Spontaneous Events ........................................................................................ 289
10.3.5 General Interrogation ....................................................................................... 292
10.3.6 General Functions ............................................................................................ 292
10.3.7 Disturbance Records ....................................................................................... 294
10.4 IEC60870-5-103 Interface over Ethernet ................................................................... 295
10.5 Messages Description for IEC61850 Protocol ......................................................... 295
10.5.1 Overview ............................................................................................................ 295
xiv NR ELECTRIC CO., LTD

10.5.2 Communication Profiles .................................................................................. 296
10.5.3 Server Data Organization................................................................................. 296
10.5.4 Server Features and Configuration ................................................................ 299
10.5.5 ACSI conformance ............................................................................................ 301
10.5.6 Logical Nodes ................................................................................................... 305
10.6 GOOSE Service ........................................................................................................... 308
10.6.1 GOOSE Introduction......................................................................................... 308
10.6.2 GOOSE Function .............................................................................................. 308
Chapter 11 Installation and Commissiong ...............................................................................311
11.1 Introduction ..................................................................................................................311
11.2 Safety Information....................................................................................................... 312
11.3 Overview ...................................................................................................................... 313
11.4 Unpacking and Checking The Protection Equipment ............................................. 313
11.5 Installing the Protection Equipment ......................................................................... 314
11.5.1 Overview ............................................................................................................ 314
11.5.2 Dimensions........................................................................................................ 315
11.5.3 Grounding Guidelines ...................................................................................... 316
11.5.4 Cubicle Grounding............................................................................................ 317
11.5.5 Ground Connection on the Device ................................................................. 317
11.5.6 Grounding Strips and Their Installation......................................................... 318
11.5.7 Making the Electrical Connections ................................................................. 318
11.6 Check the External Circuitry ...................................................................................... 320
11.7 Energizing the Protection Equipment....................................................................... 321
11.8 Setting the Protection Equipment ............................................................................. 322
11.9 Establishing Connection and Verifying Communication........................................ 322
11.10 Verifying Settings by Secondary Injection ............................................................. 322
11.10.1 Insulation Test (if required)............................................................................ 323
11.10.2 Current Measurement Check......................................................................... 324
11.10.3 Voltage Measurement ..................................................................................... 324
11.10.4 Testing the Binary Inputs ............................................................................... 325
NR ELECTRIC CO., LTD. xv

11.10.5 Print Fault Report............................................................................................ 326
11.10.6 Final Check ...................................................................................................... 326
Chapter 12 Maintenance ............................................................................................................ 327
12.1 Appearance Check ...................................................................................................... 327
12.2 Failure Tracing and Repair......................................................................................... 327
12.3 Replace Failed Modules ............................................................................................. 328
12.4 Replace Button Battery .............................................................................................. 329
12.5 Cleaning ....................................................................................................................... 329
12.6 Storage ......................................................................................................................... 329
Chapter 13 Decommissioning and Disposal ........................................................................... 331
13.1 Decommissioning ....................................................................................................... 331
13.1.1 Switching off ..................................................................................................... 331
13.1.2 Disconnecting Cables ...................................................................................... 331
13.1.3 Dismantling ....................................................................................................... 331
13.2 Disposal ....................................................................................................................... 331
Chapter 14 Manual Release History ......................................................................................... 333
xvi NR ELECTRIC CO., LTD

NR ELECTRIC CO., LTD. xvii

Chapter 1 Introduction
1.1 Application
The PCS-978 is a microprocessor-based relay designed for the protection of a two-winding or

three-winding power transformer or an autotransformer in any voltage level, which can provide six
CT inputs at most and support various connection groups. PCS-978 can be configured to
independent main protection or backup protective equipment, or protective equipment integrating
main protection with backup protection. Besides protective functions, fault diagnostic, fault &
disturbance recording, and uplink communication functions are also supported in this relay.
PCS-978 is supplied for two-winding applications and three-winding applications as indicated

below, PCS-978 is also for an autotransformer application.
NR ELECTRIC CO., LTD. 1

Figure 1.1-1 2-winding and 3-winding applications
1.2 Functions
Protective functions of PCS-978 are listed in the following table and function diagram is also
shown below.
Table 1.2-1 Protective functions of PCS-978
Protective function overview Function No. Module

Conventional percent differential protection 87T 1
Unrestrained instantaneous differential protection 50/87UT 1
DPFC current differential protection. 7/87DT 1
2 NR ELECTRIC CO., LTD

Protective function overview Function No. Module

Restricted earth fault protection 64REF 3
Winding differential protection 87WT 3
Overexciation protection 24 1
Frequency protection 86 1
Mechanical protection (4 mechanical signal input) 26,63,71 1
Phase-to-phase impedance protection 21P
3
Phase-to-earth impedance protection 21G
Definite-time overcurrent protection
50P,51P,67P 4
Inverse-time overcurrent protection
Definite-time zero-sequence overcurrent protection
51G,67G 4
Inverse-time zero-sequence overcurrent protection
Definite-time zero-sequence overvoltage protection
59G 3
Inverse-time zero-sequence overvoltage protection
Definite-time phase overvoltage protection
59P 3
Inverse-time phase overvoltage protection
Phase undervoltage protection 51G 3
Thermal overload protection 49 3
Breaker failure protection 50BF 4
Overload alarm element 49 3
Overload for initiating cooler element 49 3
Blocking on-load tap change during overload element 49 3
Zero-sequence overvoltage alarm element 59G 3
Zero-sequence overcurrent alarm element 51G 3
Voltage element 3
Current element 10
CT saturation detection
Inrush current detection
Overexcitation detection
Harmonic blocking function
Power swing blocking releasing function PSBR
VT circuit failure supervision VTS
CT circuit failure supervision CTS
NOTE: DPFC is the abbreviation of “Deviation of Power Frequency Component”. In case
of a fault in the power system, the fault current consists of three parts: the power
frequency components before the fault, the power frequency variables during the fault
and the transient variables during the fault. DPFC is the power frequency variables

during the fault.
The function diagrams for protecting a three-winding transformer and an autotransformer are
shown below.
*
*
*
U * / f* 
Figure 1.2-1 Function diagram 1 for a three-winding transformer

*
*
*
*
*
U * / f* 
Figure 1.2-2 Function diagram 2 for an autotransformer
Miscellaneous functions are list in the following table, such as metering, self-supervision and
oscillography, communication functions, and etc.

Table 1.2-2 Miscellaneous functions of PCS-978
Miscellaneous functions overview

Programmable tripping output matrix
Programmable binary input
Configurable function Programmable binary output
Programmable LED indicators
Configurable protection function
Relay hardware supervision and secondary circuit
Automatic self-supervision
supervision
Metering 24 samples per cycle
Fault recording 64 latest fault reports, 64 latest fault waveforms
(1) Fault recording is trigger by pickup of protection
Oscillography
(2)Present recording is triggered manually on keypad.
function Trigger mode
(3)Present recording triggered remotely through
PCS-PC
1024 latest abnormality reports
Event recording 1024 latest binary status input change reports
1024 latest user operation reports
Loacal HMI LCD and keypad
PCS-PC software or substation automation system
Remote HMI
software
Two RS-485 ports and two Ethernet ports, or four
Rear Ports type
Ethernet ports
communication
IEC 60870-5-103
ports to host Protocol type
IEC 61850-8-1
Rear communication port to printer One RS-485 or RS-232
Pulse per second/minute (PPS/PMS) via binary input
Time synchronisation Clock message via communication ports
IRIG-B via RS-485 differential level
Binary input
Input and output Analog input
Binary output
Multiple setting groups
Voltage and current drift auto-adjustment
1.3 Features
 Configurable Function

Modules of PCS-978 equipment adopt intelligent design, amount of input and output modules and
module slot position are configurable. User can increase or decrease the amount of AC input
module, binary input module and binary output module, and terminals of those modules can be
defined according to actual requirement. Besides, configurability is also reflected in software
design of equipment, which means that user can hide the protective element not used or add new
protective module not in standard configuration.
 Parallel Calculation of Double DSP system
The hardware of equipment comprises a 64-bit microprocessor and two 32-bit digital signal
processors (DSP). Those processor can operate in parallel companied by fast A/D converter. The
64-bit microprocessor performs logic calculation and the DSP performs the protection calculation.
High performance hardware ensures real time calculation of all protection relays within a sampling
interval.
On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection logic
calculation are completed simultaneously.
 Independent Fault Detector
Independent fault detectors in fault detector DSP module for connecting power supply of output
relays. The relay can drive a tripping output only when protection element on protection DSP
module operates with the fault detector in the fault detector DSP module operating simultaneously.
This kind of independent supervision of tripping outputs using fault detectors can avoid any
maloperation possibly caused by any hardware component faulure. This highly increases the
security.
 Integration of Main and Backup Protection (Recommended)
Main and backup protection can be integrated in one set of protection equipment. Protection
information such as sampled data and binary inputs is shared by all elements. The equipment can
record all relevant waveforms of any fault.
 Reliable Percent Differential Protection
Characteristic of percent differential with initial restraint is used and criteria for current transformer
saturation are accompanied.
 Distinct Method of Phase Shifting
△ → Y transfer method is used to adjust phase angle of secondary current on each side of the
transformer, and thus the faulty and healthy phase can possess its characteristic. Therefore,
restraint current and differential current can be phase-segregated, which can distinguish the faulty
phase from phase only with inrush current characteristic when transformer is energized.
 Provide two Inrush Current Distinguishing Methods
Two discrimination principles for inrush current are provided: harmonics restraint and waveform
distortion restraint.

 High Sensitive and Securable DPFC Differential Protection
DPFC percent differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good.
 Practical Restricted Earth Fault Protections of Each Side
Positive sequence current restraint element is adopted to eliminate the influence of difference of
transient characteristic and saturation of various CT to zero-sequence percent differential
protection.
 Reliable Differential CT Circuit Failure Detection
Distinguish of open and short circuit of CT against fault is more reliable due to combination of
voltage and current value method adopted
 Flexible Backup Protection
Maximum requirements to backup protection of all sides of the transformer are provided. The
tripping output circuit can be configured by tripping matrix and suitable to any mode of tripping.
 Perfect Fault Recording Function
 Event Recorder including 1024 status change of binary input reports and 1024 alarm
reports
 Disturbance recorder including 64 fault reports, and 64 waveforms, and file format of
waveform is compatible with international COMTRADE91 and COMTRADE99 file. Up to
80 analog inputs and 200 binary inputs can be recorded, and three oscillograph
triggering mode are supported, which are protection triggering, manual triggering,
remote triggering through PCS-PC software.
 Friendly HMI Interface
The HMI interface with a LCD and a 9-button keypad on the front panel is very friendly to the user.
 Communication Ports
 One front RS-232 port
 Two rear RS-485 ports and two Ethernet ports supporting or four Ethernet ports
(optional) with IEC 60870-5-103 or IEC 61850-8-1 protocol.
 One rear RS-485 with clock synchronization.
 One rear RS-232 or RS-485 with printer.
 GOOSE communication function (optional module)
 Various Clock Synchronizations
Various GPS clock synchronizations: second/minute pulse via binary input or RS -485, message
via communication ports and IRIG-B synchronization.

1.4 Ordering Options
Description and Option PCS-978- * * * * * * * * *

Functions
Standard A
Quantity of AC Current/Voltage Inputs

12 current inputs A
6 current inputs/6 voltage inputs B
9 current inputs/3 voltage inputs C
12 current inputs/12 voltage inputs D
18 current inputs/6 voltage inputs E
24 current inputs/12 voltage inputs F
Quantity of Binary Inputs/Outputs

Non available 0
18 inputs/11 tripping outputs 1
18 inputs/11 tripping outputs/11 signal outputs 2
Secondary AC Voltage Input;

Current Input; Frequency
100V Phase; 1 Amp Phase; 50 Hz 1
100V Phase ; 5 Amp Phase; 50 Hz 3
Support of electronic/optical CT/VT 9
Auxiliary Power Supply

110Vdc 1
125Vdc 2
220Vdc 3
250Vdc 4

Description and Option PCS-978- * * * * * * * * *

Communication Ports for Integration
2 x EIA-485 + 2 x 100Base-TX A
4x 100Base-TX B
2 x 100Base-TX + 2 x 100BaseFX C
Protocol
IEC 60870-5-103 (Only for EIA-485) S
IEC 61850 (Only for 100BaseTX and 100BaseFX)* E
Support to GOOSE
Non Available 0
GOOSE Module 1
Connector Type
Plug In/Out Terminal P
Screw terminal S
*: The items marked with '*" are not included in the basic price and have an additional cost.


Chapter 2 Technical Data
2.1 Electrical Specifications

2.1.1 Alternating Current Input
Standard IEC 60255-27:2005

Phase rotation ABC
Nominal frequency 50±5Hz, 60±5Hz
Rated Current 1A 5A
Linear to 0.05In~40In 0.05In~40In
Thermal withstand
-continuously 4In 4In
-for 10s 30In 30In
-for 1s 100In 100In
-for half a cycle 250In 250In
Burden < 0.2VA/phase @In < 0.25VA/phase @ In
2.1.2 Alternating Voltage Input

Rated Voltage (Un) 100V, 110V 200V
Linear to 0.01Un~1.7Un 0.01Un~1.7Un
Thermal withstand
-continuously 2Un 1.1Un
-10s 2.6Un 1.9Un
-1s 3Un 2.1Un
Burden at rated < 0.25VA/phase @Un
2.1.3 Power Supply

Rated Voltage 110V/125V, 220V/250V
Variation 80%Un~120%Un
Permissible AC ripple
≤15% of the nominal auxiliary voltage
voltage
Voltage short
100ms for interruption without de-energizing
interruptions
Voltage dips Up to 10s for dips 40%Un without reset

Burden
Quiescent condition <30W
Operating condition <45W
2.1.4 Binary Input
Rated Voltage (Un) 24V, 48V, 110V, 125V, 220V, 250V

Maximal pickup voltage 70%Un
Minimum dropout
55%Un
voltage
Maximum permissible
120%Un
voltage
Withstand 2000VAC, 3000VDC
Resolving time for logic
<1ms
input
2.1.5 Binary Output
Item Tripping contact Signal contact

Output mode Potential free contact
8A@250V AC
Continuous carry 8A
5A@30V DC
Pickup time <5ms <10ms
Breaking capacity 0.05A@110V DC resistance 0.2A@220V DC resistance
Making capacity
2000VA 3040VA
(L/R=40ms)
Maximal system 250V AC 380V AC
voltage 30V DC 250V DC
Test voltage across
1000V RMS for 1min 1200V RMS for 1min
open contact
Short duration current 30A@0.5S 35A@0.5S
2.1.6 Power Supply Output for Opto-coupler
Standard IEC 60255-1

Rated Voltage 24V
Rated Current 200mA
Maximal current 500mA
2.2 Mechanical Specifications
Enclosure dimensions 482.6mm×177mm×291mm(4U),

(W×H×D) 482.6mm×354.8mm×285mm (8U)

Mounting Way Flush mounted

Trepanning dimensions 450mm×179mm(4U), M6 screw
(W×H) 451.1mm×356.8mm(8U), M6 screw
Housing color Silver grey
Weight per device Approx. 20kg(4U), Approx.40kg(8U)
Display language Chinese, English
Housing material Aluminum
Location of terminal Rear panel of the device
Protection class
Front side IP40, up to IP51 (Flush mounted)
Other sides IP30
Rear side, connection
IP20
terminals
2.3 Ambient Temperature and Humidity Range

Operating temperature -25°C to +55°C
Transport and storage
-40°C to +70°C
temperature range
Permissible humidity 5%-95%, condensation not permissible
2.4 Communication Port

2.4.1 Communication Port for RTU/SCADA
Port number 2
Baud rate 4800,9600,19200,38400,57600,115200
Transmission distance <1000m@4800bps
Electrical Maximal capacity 32
Twisted pair Screened twisted pair cable
RS-485 Protocol IEC 60870-5-103: 1997
(EIA) Safety level Isolation to ELV level
Port number 2
Connector type ST
Optical
Baud rate 4800,9600,19200,38400,57600,115200
(Optional)
Transmission standard 100Base-FX
Transmission distance <1500m

Optical fibre type Multi-mode fibre

Wave length 850/820nm
Fibre size 62.5/125μm (core DIA/cladding DIA)
Protocol IEC 60870-5-103: 1997
Safety level Isolation to ELV level
Port number 2
Connector type RJ-45
Transmission rate 100Mbits/s
Electrical Transmission standard 100Base-TX
Protocol IEC 60870-5-103: 1997 or IEC 61850
Port number 2
Connector type SC
Ethernet
Transmission rate 100Mbits
Transmission standard 100Base-TX
Optical
Optical fibre type Multi-mode or single-mode
(Optional)
853/1310nm for multi-mode
Wave length
1310/1550nm for single-mode
Fibre size 62.5/125μm (core DIA/cladding DIA)
Protocol IEC 60870-5-103: 1997 or IEC 61850
2.4.2 Communication Port for Print
Prot number 1
Baud Rate 4800, 9600, 19200, 38400
RS-232 (EIA)
Printer type EPSON® 300K printer
2.4.3 RS-485 for Clock Synchronization
Port number 1
RS-485 (EIA) Maximal capacity 32
Timing standard PPS, IRIG-B

2.5 Type Tests

2.5.1 Environmental Tests
Dry cold test Per IEC60068-2-1:2007

Dry heat test Per IEC60068-2-2:2007
Damp heat test, cyclic Per IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration Per IEC 60255-21-1:1988 Class I

Shock and bump Per IEC 60255-21-2:1988 Class I
2.5.3 Electrical Tests

Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Insulation resistance
Isolation resistance >100MΩ@500VDC
measurements
2.5.4 Electromagnetic Compatibility
1MHz burst Per IEC 60255-22-1:2007

disturbance test Common mode: class III 2.5KV
Differential mode: class III 1.0KV
Electrostatic discharge Per IEC60255-22-2:2008 class IV
test For contact discharge: 8kV
For air discharge: 15kV
Radio frequency Per IEC 60255-22-3:2007 class III
interference tests Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80… 1000MHz
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
Fast transient Per IEC 60255-22-4:2008
disturbance tests Power supply, I/O, Earth: class IV, 4kV, 2.5kHz, 5/50ns
Communication terminals: class IV, 2kV, 5kHz, 5/50ns
Surge immunity test Per IEC 60255-22-5:2008

Power supply, AC input, I/O port: class IV, 1.2/50us

Common mode: 2kV
Differential mode: 1kV
Conducted RF Per IEC 60255-22-6:2001
Electromagnetic Power supply, AC, I/O, Comm. Terminal: Class III, 10Vrms, 150
Disturbance kHz~80MHz
Power Frequency Per IEC 61000-4-8:2001
Magnetic Field
class V, 100A/m for 1min, 1000A/m for 3s
Immunity
Pulse Magnetic Field Per IEC 61000-4-9:2001
Immunity class V, 6.4/16μs, 1000A/m for 3s
Damped oscillatory IEC 61000-4-10:2001
magnetic field immunity class V, 100kHz & 1MHz–100A/m
2.6 Certifications
 ISO9001: 2000
 ISO14001:2004
 OHSAS18001: 1999
 ISO10012:2003
 CMMI L3
 EMC: 89/336/EEC, EN50263:2000
 Products safety(PS): 73/23/EEC, EN61010-1: 2001, EN60950: 2002
2.7 Protective Functions
NOTE: There are some symbols mentioned in the following sections and the meaning of
them is given here.
In -- rated secondary current of CT
Ie –rated secondary current of transformer
Id -- differential current
[I_Pkp_PcntDiff] -- setting of percent differential protection
2.7.1 Conventional Current Differential Protection
Pickup setting of percent differential protection 0.05 ~ 5Ie

Setting of instantaneous differential protection 0.05 ~ 20Ie

Tolerance of current setting ≤2.5%xSetting or 0.02×Ie, whichever is greater

Restraint factor setting 0.20~0.75
Second harmonic restraint coefficient setting 0.05~0.3
Third harmonic restraint coefficient setting 0.05~0.3
≤ 30ms( Id>2[I_Pkp_PcntDiff])
Operating time of percent differential element
Without harmonic blocking
Operating time of unrestrained instantaneous
≤ 15ms( Id>1.5[I_InstDiff])
differential element
2.7.2 DPFC Current Differential Protection
Pickup setting of DPFC differential current fault

0.2Ie
detector
Tolerance of current setting ≤10%
Operating time ≤30ms (2×[I_Pkp_PcntDiff])
2.7.3 Restricted Earth Fault Protection
Pickup setting of restricted earth fault protection 0.05 ~ 5In

Tolerance of current setting ≤2.5%xSetting or 0.02×In, whichever is greater
Operating time ≤30ms (2×[I_Pkp_PcntREF])
2.7.4 Winding Differential Protection
Pickup setting of winding differential protection 0.05 ~ 5In

Tolerance of current setting ≤2.5%xSetting or 0.02×In, whichever is greater
Operating time ≤30ms (2×[I_Pkp_PcntWdgDiff])
2.7.5 Overexcitation Protection
Definite time U * / f* setting 1.0～1.7 pu
Definite time delay setting 0.1 s～9999 s
Inverse time U * / f * setting 1.0～1.7 pu
Inverse time delay setting 0.1 s～9999 s
Tolerance of U * / f * setting ≤2.5%×Setting or 0.01 whichever is greater
Tolerance of operating time of definite-time

≤1%xSetting + 40ms
overexciation protection

Tolerance of operating time of inverse-time

≤2.5% related to U * / f* ±40 ms,
overexcitation protection
2.7.6 Frequency Protection
Underfrequency setting 40~70Hz

Overfrequency setting 40~70Hz
Time delay setting 0.1~6000s
Tolerance of frequency setting ≤0.02Hz
Tolerance of time delay ≤1%xSetting + 40ms
2.7.7 Mechanical Protection
Time setting range 0min ~6000s

Time setting tolerance ≤1% + 40ms
2.7.8 Impedance Protection
Impedance setting 0~200Ω

Time setting 0 ~ 20s
Tolerance of impedance setting ≤2.5%xSetting or 0.5Ω/In, whichever is greater
Tolerance of time setting ≤1%xsetting + 40ms
2.7.9 Phase Overcurrent protection
Current setting 0.05~150A

Time setting of definite-time OC 0~20s
Base time ( T p ) of inverse-time OC 0~20s
Minimum delay of inverse-time OC 0~20s
Time multiplier ( Kt ) of inverse-time OC 0.01~200
Exponent ( ) of inverse-time OC 0.01~10

Tolerance of current setting of definite-time OC ≤2.5%xSetting or 0.02In, whichever is greater
Tolerance of time setting of definite-time OC ≤1%xSetting + 40ms
Tolerance of trip time for 1.2< I / I p <20 of ≤ 5% of reference (calculated) value + 2%

current tolerance, respectively 40ms
inverse-time OC
Undervoltage element setting 2~110V
Negative overvoltage element setting 2~110V
Tolerance of voltage setting ≤2.5%xSetting or 0.1V, whichever is greater
Tolerance of angle of directional element ≤3º

2.7.10 Zero-sequence Overcurrent Protection

Time setting of definite-time ROC 0~20s
Base time ( T p ) of inverse-time ROC 0~20s
Minimum delay of inverse-time ROC protection 0~20s
Time multiplier ( Kt ) of inverse-time ROC 0.01~200
Exponent ( ) of inverse-time ROC protection 0.01~10

Tolerance of current setting of definite-time ≤2.5%xSetting or 0.02In, whichever is greater
ROC
Tolerance of time setting of definite-time ROC ≤1%xSetting + 40ms
Tolerance of trip time for 1.2< I / I p <20 of ≤ 5% of reference (calculated) value + 2%

inverse-time ROC
Tolerance of angle of directional element ≤3º
2.7.11 Phase Overvoltage Protection
Voltage setting 0.05~150V

Time setting of definite-time OV 0~20s
Base time ( T p ) of inverse-time OV 0~20s
Minimum delay of inverse-time OV 0~20s
Time multiplier ( Kt ) of inverse-time OV 0.01~200
Exponent ( ) of inverse-time OV 0.01~10

Tolerance of voltage setting of definite-time OV ≤2.5%xSetting or 0.1V, whichever is greater
Tolerance of time setting of definite-time OV ≤1%xSetting + 40ms
Tolerance of trip time for 1.2< U / U p <20 of ≤ 5% of reference (calculated) value + 2%

Voltage tolerance, respectively 40ms
inverse-time OV
2.7.12 Zero-sequence Overvoltage Protection
Voltage setting of ROV 0.05~300V

Time setting of definite-time ROV 0~20s
Base time ( T p ) of inverse-time ROV 0~20s
Minimum delay of inverse-time ROV 0~20s

Time multiplier ( Kt ) of inverse-time ROV 0.01~200
Exponent () of inverse-time ROV 0.01~10

Tolerance of voltage setting of definite-time ≤2.5%xSetting or 0.1V, whichever is greater
ROV
Tolerance of time setting of definite-time ROV ≤1%xSetting + 40ms
Tolerance of trip time for 1.2< U / U p <20 of ≤ 5% of reference (calculated) value + 2%

Voltage tolerance, respectively 40ms
inverse-time ROV
2.7.13 Phase Undervoltage Protection
Voltage setting 0.05~150V

Time setting 0~20s
Tolerance of voltage ≤2.5%xSetting or 0.1V, whichever is greater
Tolerance of time setting ≤1%xsetting + 40ms
2.7.14 Thermal Overload Protection
Base current range( I B ) 0.05~150A
Transformer thermal time constant ( ) 0~200min
0.01~200
Thermal overload coefficient ( k ) for tripping.
0.01~200
Thermal overload coefficient ( k ) for alarming.
≤ 5% of reference (calculated) value + 2%

Tolerance of trip time for 1.2< I / k 
I B <20
2.7.15 Breaker Failure Initiation
Range of phase current setting 0.05~150A

Range of zero sequence current setting 0.05~150A
Range of negative sequence current setting 0.05~150A
Time setting range 0s ~20s
Current setting tolerance ≤2.5% or 0.02×In, whichever is greater
Time setting tolerance ≤1% + 40ms
2.7.16 Overload Alarm Element

Tolerance of current setting ≤2.5%xSetting or 0.02In, whichever is greater
Time setting 0s ~ 20s

Tolerance of time setting ≤1%xSetting + 40ms
2.7.17 Initiating Cooler Element

2.7.18 Blocking On-Load Tap Change Element

2.7.19 Zero-Sequence Overvoltage Alarm Element
Current setting 0.05~300V

Tolerance of current setting ≤2.5%xSetting or 0.1V, whichever is greater
2.7.20 Zero-Sequence Overcurrent Alarm Element



Chapter 3 Description of Operation Theory
3.1 General Description
Main protection of protection equipment consists of current differential protection, restricted earth
fault protection, winding differential protection and overexcitation protection and backup protection
consists of voltage controlled directional overcurrent protection, directional zero-sequence
overcurrent protection, impedance protection, overvoltage protection, undervoltage protection,
zero-sequence overvoltage protection, thermal overload protection, frequency protection,
mechanical protection and breaker failure protection. Besides, current transformer and voltage
transformer supervision functions also included.
The equipment has 2 plug-in modules (i.e. protection DSP module and fault detector DSP module)
for protection calculation. Protection DSP module is responsible for calculation of protection
element, and fault detector DSP module is responsible for calculation of fault detector of protection.
Fault detectors on fault detector DSP module picks up to connect positive pole of power supply of
output relays. The equipment output relays can operate to trip only if the fault detector on fault
detector DSP module picks up and the corresponding protection element on protection DSP
module operates simultaneously. Otherwise, the output relays can’
t operate to trip. An alarm
message will be issued with blocking tripping output if a protection element on protection DSP
module operates while the corresponding fault detector on fault detector element does not
operates.
The Fault detector of fault detector DSP module consists of several independent fault detectors,
which can monitor corresponding protection elements without influence to other protection
elements. For example, conventional percent differential protection will not operate to send trip
command until protection element of protection DSP module and the corresponding fault detector
of fault detector DSP module operate at the same time.
3.2 Current Differential Protection
3.2.1 Features
Differential protection characteristics of PCS-978 are as follows:
 Maximum six CT inputs for differential protection.
 Protecting 2-winding and 3-winding transformers and auto-transformer.
 24 connection groups available for two-winding transformer.
 288 connection groups available for 3-winding transformer.
 Optional inrush current distinguished principles: harmonic criterion or waveform distortion.

 Self-adaptive inrush current blocking criterion can enhance ability of differential protection to
avoid maloperation during transformer energization effectively and ensure high speed of
differential protection during normal operation if there is any fault.
 Fifth harmonic criterion applied continuously to detect overexciation condition.
 Distinct method of phase shifting of secondary currents for differential protection.
△ → Y transfer method is adopted to adjust phase angle of secondary currents on each side of
the transformer, and thus the faulty and healthy phase can possess its characteristic.
Therefore, restraint current and differential current can be phase-segregated, which can
distinguish the faulty phase from phase only with inrush current characteristic when
transformer is energized.
 High sensitive and securable DPFC percent differential protection
DPFC percent differential protection which consists of power frequency fault component is
regardless of the load current and is sensitive to sm all internal fault current within the
transformer and has the strong ability of anti-CT saturation.
 Reliable percent differential protection
Percent differential protection with initial restraint slope consists of sensitive and insensitive
percent differential elements as well as independent CT saturation criterion.
 Reliable differential CT circuit failure detection
Multi-phase CT broken circuit, multi-side CT broken circuit and CT short circuit can be
distinguished by combination of voltage and current.
3.2.2 Fault Detector
3.2.2.1 Fault Detector of Differential Current
The pickup of this fault detector will enable the percent current differential protection and
unrestraint differential protection.
I d I cdqd (Equation 3.2-1)
Where：
I d is the differential current of any phase.
I cdqd is the setting threshold of phase differential currents, i.e. setting [I_Pkp_PcntDiff].
3.2.2.2 Fault Detector of DPFC Differential Current
Criteria of this fault detector:

I d 1.25Idt I dth
  
(Equation 3.2-2)
I d I 1 I 2 ... I m
Where:
I dt is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold value of voltage
is slightly greater than the unbalance output, multiple 1.25 of the deviation component is
reasonable.
 
I 1 … . I m are the DPFC current of each side of transformer representatively.
I d is the half-cycle integrated value of differential current.
I dth is the fixed threshold and the value is 0.2In.
This fault detector is regardless of direction of power flow and very sensitive. It has been set in
factory and does not need to be set on site. The pickup of this fault detector will enable DPFC
percent differential protection.
3.2.3 Protection Principle

Current differential protection includes percent differential protection, unrestrained differential
protection, DPFC percent differential protection. Percent differential protection is three-slope
differential protection with restraint characteristic. Unrestrained differential protection is to
accelerate the trip speed for transformer’
s serious internal faults without restraint characteristics
and blocking elements. DPFC percent differential protection calculated by current variation has
high sensitivity to slight fault under heavy load. Above three differential protection elements work
coordinately to form the high-speed current differential protection with high sensitivity.
3.2.3.1 Current compensation
During the normal operation, the magnitude and angle of secondary currents of each side of
transformer are different due to the mismatch between the CT ratios and the power transformer
ratio, different voltage levels of each side, and transformer delta-wye connection. The current
difference between each side shall be eliminated before do the calculation of current differential
protection, which is realized by magnitude compensation (i.e. CT ration correction), phase shift
compensation and residual current elimination (i.e. Δ→ Y transforming).
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current （ i.e.
I d I 
_ H I 
_ L ）should be zero during the normal operation of the transformer or an external
fault occurring.

Figure 3.2-1 Current compensation calculation process
Where:
Ip_H, Ip_L are primary currents of HV and LV sides respectively.
I_H, I_L are secondary currents of HV and LV sides respectively.
I’
_H, I’
_L are secondary corrected currents of HV and LV sides respectively.
M1, M2 are matrixes of phase shifting and residual current elimination of HV and LV sides
respectively.
Kph1, Kph2 are corrected coefficients of HV and LV sides for magnitude compensation
respectively.
3.2.3.1.1 Calculations of Differential and Restraint Currents
The equation of calculating differential current is as follows.

I dA  
I A1 I A2  I A3 I A4 
    / I    / I   / I  I B4 / I 2e _ 4 

I dB  M 1 
I B1 2e _ 1 M 2 I B2  2e _ 2 M 3 I B3 2e _ 3 M 4  

  
I 1 I 2    
I
  
dC 
C   
C     
IC3
   
I C
4 
1 2 3 4 5

I A5  
I A6 
  
I B6 
M 5 
I B5 / I 2e _ 5 M 6  / I 2e _ 6

I 5
 
I 6
 C    
C 
 
6 7
(Equation 3.2-3)
The above equation can be simplified to the following equation:

I dA I 
A1 I 
A2 I A3 I 
A4 I 
A 5 I 
A6

I dB I B1 I B 2 I B3 B 4 B 5 B
      I  I  I 6 (Equation 3.2-4)
    
I dC I C1 I 
C 2 I 
C3 IC 4 IC5 IC 6
Where:
I An , I Bn , I Cn are secondary values of three-phase current of branch n (n=1, 2, 3, 4, 5, 6).
I dA , I dB , I dC are three-phase differential current values.
I
An , I 
Bn , I 
Cn are secondary values of corrected three-phase current of branch n (n=1, 2, 3, 4, 5,
6).
M 1 , M 2 , M 3 , M 4 , M 5 , M 6 are matrixes of phase shifting of each branch of transformer respectively. Its

value is decided according to the connection group of transformer and please refers to section
3.2.3.1.2 for details.
I2 e _ 1 , I 2 e _ 2 , I 2 e _ 3 , I 2e _ 4 , I 2e _ 5 , I2 e _ 6 are secondary rated values of each branch of transformer
respectively.
The equation of calculating restraint current is:
 1
I rA  I 
A1 I 
A 2 I 
A 3 I 
A 4 I 
A 5 I 
A6 
 2
 1
I rB  I 
B1 I 
B 2 I 
B 3 I 
B 4 I 
B 5 I 
B6  (Equation 3.2-5)
 2
 1
I rC  I 
C1 I 
C2 I C 3 I 
C 4 I C5 I C6 
 2
Where:
I rA , I rB , I rC are three-phase restraint current values.
3.2.3.1.2 Phase Shift Compensation
The following transforming method is based on the assumptions listed here:
 Each side three-phase CT of transformer shall be connected in star type.
 Secondary currents of each side three-phase CT shall be connected to the equipment directly.
 The positive polarity of each side three-phase CT shall be at busbar side.
The secondary current phases of CTs at each side are adjusted by software and phase shift is
realized by Δ→ Y transform method. Thus the inrush current and fault current can be discriminated
definitely, and the operating speed of protection can be accelerated. For transformer connection
group Y/Δ-11, the phase shifting equations are as follows:
At wye (Y) side:

  
I ' A ( I A I 0 )
  
( I B I 0 ) (Equation 3.2-6)
'
I B
  
I ' C (I C I 0 )
At delta (Δ) side :
  
I ' a ( I a I c ) / 3
  
(I b I a ) / 3 (Equation 3.2-7)
'
I b
  
I ' c ( I c I b ) / 3
Where:
  
I a , I b , I c are the secondary currents of CT at Δ side.
  
I ' a , I ' b , I ' c are the corrected currents of CT at Δ side.
  
I A , I B , I C are the secondary currents of CT at Y side.
  
I ' A , I ' B , I ' C are the corrected current of CT at Y side.
For other connection groups, phase shit process is similarly.
Protection equipment can select suitable phase sift matrixes automatically to complete phase shift
compensation according to three system settings [WdgConn_HVS], [Clk_MVS_WRT_HVS] and
[Clk_LVS_WRT_HVS]. [WdgConn_HVS] is to select the connection type of HV side winding, “0”
for wye winding and “1”for delta winding. [Clk_MVS_WRT_HVS] and [Clk_LVS_WRT_HVS] are
respectively to set the actual o’
clock of MV and LV side windings.
Two examples are given below.
For connection group Y0/Y0/Δ11, [WdgConn_HVS] is set as “0”, [Clk_MVS_WRT_HVS] is set as

“0”, and [Clk_LVS_WRT_HVS] is set as “11”.
For connection group Y0/Y0/Δ1, [WdgConn_HVS] is set as “0”, [Clk_MVS_WRT_HVS] is set as

“0”, and [Clk_LVS_WRT_HVS] is set as “1”.
Phase shift matrixes are listed in the following table. For example, a transformer with connection
group YNd11y10, for HV side is taken as the reference side, the relative o’ clock of HV side is “0”.
The leading phase of MV side to HV side is 30°(its relative o’
clock is 11), and the leading phase of
clock is 10). Therefore, in the Table 3.2-1 M 1, M 2 , M 3

LV side to HV side is 60°(i.e. its relative o’

of three sides represent the matrix of relative o’

clock 0, 11 and 10 respectively. Here, M1, M2 and
M3 represent phase shift matrixes of HV, MV and LV sides.
Table 3.2-1 Phase shift matrix value
Relative o’clock Matrix Value
2 1 1
1 
0（12） 1 2 1
3  

1 1
 2

1 1 0
1 
1 
 0 1 1

3

1 0 1

1 2 1
1 
2  1 1 2 
3  


 2 1 1 

0 1 1
1 
3  1 0 1
3  

1 1 0 

1 1 2
1 
4  2 1 1
3  

1 2 1

1 0 1
1 
5  1 1 0
3  

 0 1 1

2 1 1
1 
6  1 2 1
3  

 1 1 2 

1 1 0
1 
7  0 1 1
3  

1 0 1

1 2 1 

1 
8  1 1 2 
3  

 2 1 1


Relative o’clock Matrix Value
0 1 1
1 
9 1 0 1
3  

 1 1 0 

1 1 2 
1 
10 2 1 1
3  

1 2 1 

1 0 1
1 
11 1 1 0
3  

 0 1 1

3.2.3.1.3 Magnitude Compensation
 Calculate rated primary current at each side
Sn
I1 e  (Equation 3.2-8)
3U1 n
Where:
S n is the maximum rated capacity (i.e. the setting [Sn]).
U1 n is rated voltage at calculated side of the transformer (i.e. the setting [U1n_HVS]).
 Calculate rated secondary current at each side
I1n
I2 e  (Equation 3.2-9)
nCT
Where:
I 2 e is rated secondary current at the calculated side of transformer.
I1e is rated primary current at the calculated side of transformer.
n CT is the ratio of CT at the calculated side of transformer.
When viewing settings and values of conventional current differential protection in the relay, user
will find the unit “Ie”(transformer secondary rated current). The current in differential protection
calculation is not actual secondary value but per unit value which can be got by actual secondary
value of each side of transformer divided by transformer secondary current of each side.
3.2.3.2 Sensitive Percent Differential Protection Element
The currents used in this section analysis and the following analysis have been corrected, that
means the currents for following calculation are the products of the actual secondary current of

each side multiplying its own correction coefficient
The Low setting percent differential protection with low pickup setting and restraint slope is also
called sensitive percent differential protection and is much more sensitive to operate when a slight
internal fault occurs. Three blocking elements, CT saturation, inrush current, CT circuit failure
(optional) and overexcitation (optional) have also been included for the protection in order to
prevent it from the unwanted operation during an external fault.
I d 0.2 I r I cdqd I r 0.5 I e

I K 
d b1 I r 0.5I e  0.1I e I cdqd 0.5I e I r 6I e
I d 0.75 I r 6I e 
Kb 1 
5.5I e 
0.1I e I cdqd I r 6 I e

 1 m
(Equation 3.2-10)
I r 2 Ii
 m
i1
I  I
 d  i
 i1
Where:
I e is a unit of current, i.e. the rated secondary current of transformer.
I i (i = 1 … m) are the phase currents of each branch (from 1 to m) of a transformer respectively.
I cdqd is the pickup value of percent differential protection (i.e. [I_Pkp_PcntDiff]).
I d is the differential current.
I r is the restraint current.
kbl is the percent restraint coefficient (i.e. [Slope_PcntDiff]) with setting range 0.2 ~ 0.75, and 0.5
is recommended usually.
3.2.3.3 Insensitive Percent Differential Protection Element
A percent differential protection with high slope and high setting is equipped with the equipment.
This protection, also called an insensitive differential protection, is blocked only by an inrush
current criterion.
High setting percent differential protection can accelerate the trip when serious inner faults occur.
Operation criterion of this high setting percent differential protection is:
I d 0.6[ I r 0.8I e ] 1.2 I e


 (Equation 3.2-11)
I r 0.8I e


Where:
Id I r I
, and e have same meaning as mentioned above.
NOTE: Parameters of this protection have been fixed in the program and do not need to
be configured by user.
3.2.3.4 Unrestrained Instantaneous Differential Protection Element
The aim of unrestrained instantaneous differential protection for transformer is to accelerate the
trip speed for transformer’
s inner fault. Therefore the element does not need any blocking element,
but the setting should be greater than the maximum inrush current.
Unrestrained differential element shall operate to trip breakers at all sides of transformer when any
phase differential current is higher than its setting. Its operation criterion is:
I d I cdsd (Equation 3.2-12)
Where:
Id
is the maximum value of three-phase differential current.
I cdsd is the setting of the unrestrained instantaneous differential protection(i.e. the setting
[I_InstDiff]).
3.2.3.5 DPFC Percent Differential Protection Element
DPFC (Deviation of Power Frequency Component) percent differential protection reflects deviation
of load condition which can perform a sensitive protection for the transformer. Lab test shows that
it is more sensitive in the heavy load condition than the conventional percent differential relay.
The operation criteria of DPFC percent differential are as follows:

I d 1.25 I dt I dth

I d 0.6 I r
 I r 2I e

I d 0.75 I r 0.3 I e I r 2I e

(Equation 3.2-13)
I r max{ I1 I2  .... I m }
  
I d I 1 I 2 .... I m
Where:
I dt is the floating threshold value which will arise automatically and gradually according to

increasing of output of deviation component. In order to ensure the threshold value is slightly
greater than the unbalance output, multiple 1.25 of the deviation component is reasonable and the
unwanted operation of relays will not occur during power swing or power frequency deviating.
 
I 1 … I m are DPFC currents of each branch (from 1 to m) of a transformer respectively.

I 1 is the DPFC differential current.
I dth is the fixed threshold value of current.
I r is the DPFC restraint current, it is the maximum current among the restraint current of three
phases.
NOTE: Calculation of restraint current of DPFC percent differential protection is different
with the percent differential protection, it is difficult to test the function on site, so we
recommend qualitative function test only on site.
Calculation of DPFC restraint current and differential current is phase-segregated. DPFC percent
differential protection is always blocked by inrush current, overexciation and CT circuit failure.
Due to high slope of DPFC percent differential protection, the protection has higher ability of
anti-CT saturation and can improve the sensitivity to slight inter-turn fault during normal operation
of transformer

3.2.3.6 Operation Characteristic Curve
Figure 3.2-2 Operation characteristic curve of conventional current differential protection
1) Insensitive percent differential protection element will send tripping signal with blocking of CT
saturation, overexcitation, inrush current and CT circuit failure (optional). It can ensure
sensitivity of protection and avoid the unwanted operation when CT is saturated during an
external fault. Its operation area is the tint shadow area in the figure above.
2) Insensitive percent differential protection element will send tripping signal with blocking of
inrush current. It eliminates the influence of transient and steady saturations of CT during an
external fault and ensures reliable operation even if CT is in saturation condition during an
internal fault by means of its percent restraint characteristic. Its operation area is the deeper
shadow area in the figure above.
NOTE: Only the secondary harmonic criterion is adopted to distinguishing inrush current
for blocking insensitive percent differential protection.
3) Unrestrained instantaneous differential protection element will send tripping signal without any
blocking if differential current of any phase reaches its setting. Its operation area is over the
above two areas with the deepest dark shadow.

differential current
m
K= K=0.75
0.2 Ie K=0.6
restraint current
2 Ie
Figure 3.2-3 Operating characteristic curve of DPFC percent differential protection
Where:
The value of m is defined by the branch number for DPFC percent differential protection
calculation.
3.2.3.7 Inrush Current Detection
In this protection equipment, the logic setting [Opt_Inrush_Ident] is provided for user to select the
restraint blocking principle. If the logic setting is set as “0”, discrimination by harmonics is
enabled, and if it is set as “1”, discrimination by waveform dist ortion is enabled.
3.2.3.7.1 Distinguishing by Harmonics
In PCS-978 series protection equipment, the second and third harmonics of differential current can
be used to distinguish inrush current. Its criteria are:

I d _ 2 nd K 2 xb I d _ 1st
I K 3 xb I d _ 1 st
d _ 3 rd
Where:
I d _ 2 nd I d _ 3 rd
and are the second and third harmonics of phase differential current
respectively.
I d _ 1st
is the fundamental component of the differential current of the corresponding phase.
k 2 xb and k3 xb are the setting values of restraint coefficient of second and third harmonics

k 2 xb = 0.15 and k3 xb = 0.2 is recommended. In main protection setting table, they are
respectively,
[k_2ndHarm_PcntDiff] and [k_3rdHarm_PcntDiff] respectively.
When one of three phases current is distinguished as inrush current, the percent differential
protection of this phase and only this phase will be blocked.
3.2.3.7.2 Distinguishing by Wave Distortion
The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized plentiful harmonics will appear, the waveform will be distorted, interrupted
and unsymmetrical. A special algorithm can be used for discrimination of the inrush current.
Following expression is applicable to fault condition:
S k b S 
S S t
Where:
S is the full cycle integrated value of differential current.
S  is full cycle integrated value of the instantaneous value of differential current plus the
instantaneous value half cycle (10 ms) before.
kb is a fixed constant.
S t is the threshold value which can be represented as follows:
St * I d 0.1* Ie (Equation 3.2-16)
Where:
I d is the full cycle integrated value of differential current.
 is a proportional constant.
If any one phase can not meet above equation, the current can be considered as inrush current
and only percent differential relay will be blocked..
3.2.3.7.3 Self-adaptive Measures
The equipment has the special energizing detection element for checking whether transformer is
in the process of being energized with no load or not automatically only by current criterion
(without additional breaker position signal). Once transformer in the process of being energized
with no load is detected, following self-adaptive measures are adopted to improve the ability to
avoid inrush current.

1) Protection equipment automatically decreases the restraint coefficient values of harmonics

during the initial stage of transformer energization, and with the passage of time automatically
increases those values which shall be not greater than corresponding values of settings
[k_2ndHarm_PcntDiff] and [k_3rdHarm_PcntDiff]. Not only the ability that inrush current
blocks percent differential protection is provided, but also the operation speed of percent
differential protection can be ensured when no-load transformer is energized with a fault.
2) Protection equipment can be self-adaptive to enable the crossing block mode according to the
comprehensive characteristics of three-phase differential current. If inrush current is
distinguished, equipment enables crossing block mode for short time, and then switches to
phase-segregated blocking mode after a period.
3) f the secondary harmonic percent of differential current used as auxiliary criteria continues to
rise, then percent differential protection is kept being blocked
3.2.3.8 CT Saturation Detection
In order to prevent an unwanted operation of low setting differential protection caused by transient
or steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of CT are used for the protection equipment to discriminate saturation of
three-phase CT. The criteria expression is as following:
I _ 2nd K sat _ 2xb I _ 1st



I _ 3rd K sat _ 3xb I _ 1st


Where:
I _ 1st
is the fundamental component of one phase current of some side.
I_ 2 nd
is the secondary harmonic of the same phase current.
I_ 3 rd
is the third harmonic of the same phase current.
K sat _ 2 xb , Ksat _ 3xb

are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and sensitive percent differential element will be
blocked.
3.2.3.9 Overexciation Detection
When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The fifth harmonic of differential current is used as the
criterion of overexcitation discrimination.

I d _ 5th k 5xb I d _1st (Equation 3.2-18)
Where:
I d _ 1st
is the fundamental component of differential current.
I d _ 5th
is the fifth harmonics of differential current.
k 5 xb is the constant of the fifth harmonics restraint coefficient and it is fixed at 0.25.
Degree of overexcitation can be evaluated by following overexcitation multiple:
n U* / f * (Equation 3.2-19)
Where:
U * and f * are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is secondary rated voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
If overexciation factor is less than 1.4, percent differential protection is blocked when the fifth
harmonics restraint coefficient is greater than 0.25. If overexciation factor is greater than 1.4,
perent differential protection is no longer being blocked by overexciation.
3.2.3.10 CT Supervision for Differential Protection
3.2.3.10.1 CT Circuit Abnormality of Differential Protection
If the differential current in any phase is greater than the alarm setting [I_Alm_Diff] without fault
detector of differential protection pickup and the state is keeping over 10s, differential current
abnormality alarm will be issued without blocking the protection.
3.2.3.10.2 CT Circuit Failure
 Criteria
There are following two cases will be discriminated a CT circuit failure but not an internal fault, and
the protection relay can descrimiate which side the CT circuit failure ocurrs by the unbalcned
currents of each side.
First case, if none of following four conditions is satisfied after the fault detector of differential
current or zero-sequence differential current pickus up, it will be judged as CT circuit failure and
CT circuit failure alarm will be issued.
Negative-sequence voltage at any side is greater than 6V.

Any phase current of any side increases than that before the fault detector picks up.
The maximum phase current is greater than 1.1 Ie (Ie is secondary calculated rated current of
transformer) after the fault detector picks up.
DPFC element of any phase-to-phase voltage of any side picks up.
Second case, if CT circuit abnormality of differential protection alarm (i.e. [Alm_Diff]) is issued and
negative-sequence current of one side is greater than 0.2 times maximum phase current of the
corresponding side, and then CT circuit failure will be judged.
Broken circuit and short circuit of differential CT secondary circuit can be judged more accurately
and reliably by adopting combined method of voltage and current.
 the influence of CT circuit failure on differential protections
By configuring different logic settings, user can gent following blocking functions to differential
protections after CT circuit failure alarm is issued. Once the alarm signal of differential CT circuit
failure is issued, it can be reset only when the failure is removed and equipment is reset (i.e the
binary input [BI_RstTarg] is energized).
1) The DPFC percent differential relay is always blocked during CT circuit failure.
2) Percent differential protection can be blocked when CT circuit failure is detected by configuring
the logic setting [En_CTS_Blk_Diff].
 If this logic setting is set as “0”, percent differential protection is not blocked by with the
alarm signal being issued.
 If this logic setting is set as “1”, only sensitive percent differential protection is blocked by
with the alarm signal being issued.
NOTE: CT circuit abnormality and failure alarms indicate there is an abnormality in
differential CT circuit or settings. Both shall be paid attention on site. For example,
differential circuits open can not cause protection pickup in case of light load but alarm will
be issued. If user treats this abnormality in time, the unwanted operation of percent
differential protection not blocked by CT circuit failure can be avoided when the load
increases or an external fault occurs.
NOTE: The operation time of percent differential protection with CT circuit failure being
distinguished is a littler greater than that of percent differential protection without CT circuit
failure.

3.2.4 Logic Scheme
3.2.4.1 Logic Scheme of Conventional Current Differential Protection
Id_max>[I_InstDiff]
[EBI_Diff]
&
[VEBI_Diff] & [Op_InstDiff]
[En_InstDiff]
Flg_FD_Diff
Flg_Op_InsensPcntDiff
[EBI_Diff]
&
[VEBI_Diff] &
&
[En_PcntDiff]
Flg_Inrush_2ndHarm
Flg_Op_FD_Diff
Flg_Op_SensPcntDiff
[EBI_Diff]
&
[VEBI_Diff] ≥1 [Op_PcntDiff]
[En_PcntDiff]
Flg_CT_Sat
Flg_Inrush_2ndHarm
Flg_Inrush_3rdHarm
& &
[En_3rdHarm_Blk_Diff] &
Flg_CTS
&
[Opt_CTS_Blk_Diff]
Flg_OvExc_5thHarm
≥1
U * / f * >1.4
Flg_FD_Diff
Figure 3.2-4 Logic diagram of conventional current differential protection
Where：
Id_max is the maximum value of three-phase differential current.
U* / f * is the overexciation multiple indicating the degree of overexcitation of transformer.
[EBI_Diff] is the binary input of enabling conventional and DPFC current differential of differential
protections.
[VEBI_Diff] is the VEBI setting of enabling conventional and DPFC current differential of
differential protections.
[En_PcntDiff] is the logic setting of enabling percent differential protection.
[En_InstDiff] is the logic setting of enabling unrestrained instantaneous differential protection.

Flg_FD_Diff is the internal flag indicating that the fault detector of differential current picks up.
Flg_Op_InsensPcntDiff is the internal flag indicating that operation criteria of insensitive percent
differential protection are satisfied.
Flg_Op_SensPcntDiff is the internal flag indicating that operation criteria of sensitive percent
differential protection are satisfied.
Flg_CTS is the internal flag indicating that CT circuit failure is distinguished
Flg_CT_Sat is the internal flag indicating CT saturation is distinguished.
Flg_Inrush_2ndHarm is the internal flag indicating inrush current is distinguished by the secondary
harmonic criterion.
Flg_Inrush_3rdHarm is the internal flag indicating inrush current is distinguished by the third
harmonic criterion.
Flg_OvExc_5thHarm is the internal flag indicating overexcitation of transformer is distinguished by

the fifth harmonic criterion
[En_3rdHarm_Blk_Diff] is the logic setting of enabling the third harmonic criterion used to
distinguish inrush current.
[Opt_CTS_Blk_Diff] is the logic setting of selecting whether percent differential protection is

blocked during CT circuit failure being distinguished.
[Op_InstDiff] is the operation of unrestrained instant differential protection.
[Op_PcntDiff] is the operation of percent differential protection.
3.2.4.2 Logic Scheme of DPFC Percent Differential Protection
U * / f*
Figure 3.2-5 Logic diagram of DPFC differential protection
Where:
U* / f * is the value indicating the degree of overexcitation of transformer.
Flg_Op_DPFC_Diff is the internal flag indicating that operation criteria of DPFC differential

protection are satisfied.
[EBI_Diff] is the binary input of enabling current differential protection including conventional
differential protection and DPFC differential protection.
[En_Diff] is the logic setting of enabling all kinds of differential protection.
[En_DPFC_Diff] is the logic setting of enabling DPFC differential protection.
Flg_FD_DPFC_Diff is the internal flag indicating the fault detector of DPFC differential current
picks up.
Flg_CT_Sat is the internal flag indicating CT saturation is distinguished.
Flg_Inrush_2ndHarm is the internal flag indicating inrush current is distinguished by the secondary
harmonic criterion.
Flg_OvExc_5thHarm is the internal flag indicating overexcitation of transformer is distinguished by

the fifth harmonic criterion
[Op_DPFC_Diff] is the operation of DPFC differential protection.
3.2.5 Setting
Table 3.2-2 Setting list of current differential protection
No. Setting Item Range Step Description

Pickup setting of percent differential
1 I_Pkp_PcntDiff 0.05~5Ie 0.01Ie
protection.
Setting of unrestrained instant differential
2 I_InstDiff 0.05~20Ie 0.01Ie
protection
Percent restraint coefficient of percent
3 Slope_PcntDiff 0.2~0.75 0.01
differential protection.
Restraint coefficient of second harmonics
4 k_2ndHarm_PcntDiff 0.05~0.3 0.01
for percent differential protection.
Restraint coefficient of the third harmonic
5 k_3rdHarm_PcntDif 0.05~0.3 0.01
for percent differential protection.
Setting of differential current abnormality
6 I_Alm_Diff 0.1~1.5 Ie 0.01
alarm.
Logic setting of enabling/disabling
0: disable
7 En_InstDiff unrestrained instant differential
1: enable
protection.
0: disable
8 En_PcntDiff conventional percent differential
1: enable
protection.
0: disable Logic setting of enabling/disabling DPFC
9 En_DPFC_Diff
1: enable current differential protection.


Logic setting of selecting the method of
distinguishing inrush current:
10 Opt_Inrush_Ident 0, 1
0: Waveform distortion principle
1: Harmonics principle
Logic setting of enabling/disabling the
0: disable third harmonic blocking function, i.e.
11 En_3rdHarm_Blk_Diff
1: enable enable/disable the third harmonic criteria
to distinguish inrush current.
0: disable
12 En_CTS_Blk_Diff blocking percent differential protecting
1: enable
during CT circuit failure.
0000~ Tripping logic setting of current
13 TrpLog_Diff
FFFF differential protection.
VEBI setting of enabling/disabling current
0: disable
14 VEBI_Diff differential protection and DPFC current
1: enable
differential protection.
 Setting explanation
1. [I_Pkp_PcntDiff]
Current setting of differential current is the minimum operating current of differential protection. It
shall be greater than the maximum unbalance current while transformer operates on normal rated
load, i.e.
I cdqd K rel ( K er U m) I e (Equation 3.2-20)
Where:
I cdqd is the setting [I_Pkp_PcntDiff].
I e is secondary rated current of transformer.
K rel is reliability coefficient (generally K rel = 1.3 - 1.5).
K er is the ratio errors of CT (k=0.03X2 for class 10P; k=0.01X2 for clase 5P and TP).
U is the maximum deviation (in percent of rated voltage) due to tap changing within voltage
regulation range.
m is the error caused by the difference between ratios of CT at all side, and 0.05 is
recommended.
Recommended value: 0.2 I e ~ 0.5 I e

NOTE: Settings ([I_Pkp_PcntDiff], [I_InstDiff] and [I_Alm_Diff]) are all based on the
secondary rated current of the transformer (i.e. Ie). If a setting value got from calculation is
together with its unit Ampere, this setting shall be divided by secondary rated current of
this side of transformer, per unit value.
2. [I_InstDiff]
This setting is the unrestraint differential protection. Unrestraint differential protection can clear
serious internal fault quickly and prevent operation delay caused by CT saturation. It’ s setting
value I cdsd (ie. [I_InstDiff])Shall be greater than inrush current of transformer, generally
I cdsd K I e (Equation 3.2-21)
Where:
K is a multiple depending on the capacity of the transformer and impedance of the power
system.
K will be 3.0 - 6.0 for transformer with capacity 40 - 120 MVA and 2.0 - 5.0 for transformer with
capacity above 120 MVA. It is evident that the larger the transformer capacity or the power system
impedance, the smaller the K .
3. [Slope_PcntDiff]
This setting is the percent restraint coefficient of percent differential protection. Setting calculation
method of differential protection is provided here only for reference. For details, please refer to
relevant specification and setting calculation guidance.
Calculation of unbalanced current is different with the different type of transformer. Following
equations are given to calculate the maximum unbalanced current Iunb.max (secondary current)
in differential scheme for two-winding and three-winding transformer:
 For two windings transformer
I unb. max ( K ap K cc K er U m) I k . max (Equation 3.2-22)
Where:
Definition of K er , U and m have been mentioned above.
Kcc is the “same type coefficient”of CT, and 1.0 is recommended.
I k .max is the maximum value of fundamental component of external short circuit (secondary)
current;
K ap is the coefficient of DC component;

K ap = 1.0 if CT at both sides are class TP, or Kap = 1.5 - 2.0 if CT at both sides are class P.
 For three winding transformer
Take external short circuit fault at LV side as example:
I unb. max K ap K cc K er I k . max Uh I k .h . max Um .I k. m.max mI I k .I . max mII I k .II .max
(Equation 3.2-23)
Where:
Definition of K er , K cc and K ap have been mentioned above.
U h and U m are the maximum deviations (in percent of rated voltage) on HV and MV sides
due to tap changing within voltage regulation range.
I k.max is the maximum value of fundamental component of the short-circuit secondary current
flowing through CT at the fault side during an external fault at LV side.
I k.h. max and I k.m.max are the fundamental components of the secondary currents flowing through
CT at voltage regulating sides during this external fault.
I k.I . max and I k.II . max are the fundamental components of the secondary currents flowing through CT
at other sides during this fault.
m I and m II are the errors caused by difference between ratios of CT (auxiliary CT included) at
relevant sides.
The pickup current (secondary current) of differential relay is:
I op. max K rel I unb . max (Equation 3.2-24)
Where
Krel is the reliability coefficient (generally K rel = 1.3 - 1.5).
Thus the maximum restraint coefficient is:
K res .max I op. max / I res .max (Equation 3.2-25)
Where:
Ires .max is the maximum restraint current (secondary current), which is set according to diff erent
restraint currents during a short-circuit fault at each side.
According to the pickup current of differential relay I cdqd , the first keen point current Ires .01 , the

maximum restraint current Ires .max and the maximum restraint coefficient Kres .max , the slope of
configurable line of operation characteristic curve of percent differential relay, K bl , will be
calculated as following:
K I / I
K bl  res cdqd res (Equation 3.2-26)
1 I res.01 / I res
when I res .max I k. max , we have:
I I cdqd
K bl  op. max (Equation 3.2-27)
I k. max I res.01
Therefore, for percent differential relay, when I res .01 0.5 I e , we have:
I I cdqd
K bl  op .max (Equation 3.2-28)
I k . max 0.5I e
Recommended value: 0.5.
4. [ k_2ndHarm_PcntDiff]
This setting is the restraint coefficient of second harmonics. This parameter is the blocking
threshold of the second harmonics in differential current when the transformer is energized.
Generally, it is set in the range of 10%~20%.
Recommended value: 15%.
5. [k_3rdHarm_PcntDiff]
This setting is the restraint coefficient of the third harmonic. The criterion of distinguishing the 3rd
harmonic is added to block differential protection based on the facts that inrush involves 3rd
harmonics. Generally, it is set in the range of 10%~25%.
Recommended value: 20%.
6. [I_Alm_Diff]
This setting is the alarm setting of differential current abnormality, and it shall be greater than
maximum differential current when the tap of on-load tap-changing transformer is not located in its
middle position, or the maximum differential current caused by other conditions.
NOTE: The setting [I_Alm_Diff] should be set less than the pickup setting [I_Pkp_PcntDiff],
and normally between the value of maximum differential current caused by the tap of
on-load tap-changing transformer not located in its middle position and the value of
minimum pickup setting.
Recommended value:0.8* I cdqd ( I cdqd is the setting [I_Pkp_PcntDiff]).

7. [En_InstDiff]
The logic setting is used to enable or disable the unrestrained instant differential protection which
should be enabled in an actual project.
“0”disable the protection; 1”enable the protection.
8. [En_PcntDiff]
The logic setting is used to enable or disable the conventional percent differential protection which
should be enabled in an actual project.
9. [En_DPFC_Diff]
The logic setting is used to enable or disable the conventional percent differential protection.
Recommended value: 1.
NOTE: The DPFC current differential protection settings have been fixed in program and
user does not need to set but only needs to select whether the protection is enabled or
not.
NOTE: When the secondary rated current of HV side multipled by the corresponding
correction coefficient is less than 0.4In (In is secondary ratec current of CT), DPFC
current differential protection must not be enabled. Otherwise, a corresponding alarm
message is issued with protective equipment being blocked.
10. [Opt_Inrush_Ident]
This logic setting is to select method of identifing inrush current to block differential protection.
“0”waveform distortion criteria is selected.
“1”harmonic restraint principle is selected.
11. [En_3rdHarm_Blk_Diff]
This is the logic setting of enable or diisable the third harmonic blocking function.
“0”the function is disabled.
“1”the function is enabled.
12. [En_CTS_Blk_Diff]
This is logic setting of enabling differential protection blocked by CT circuit failure.
“0”: percent differential protection and restricted earth fault protection is not blocked by CT circuit

failure.
“1”: sensitive percent differential protection element and restricted earth fault protection is blocked
by CT circuit failure.
NOTE: When protection settings are configured and the maximum value of ratio of
calculated rated current of each side to secondary current of CT on that side is less than
0.4, this will be considered abnormal and wrong setting alarm will be sent.
13. [TrpLogic_Diff]
The tripping logic setting is used to specify which breakers will be tripped when current differential
protection operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting of the equipment
is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutp10
TrpOutp9
TrpOutp8
TrpOutp7
TrpOutp6
TrpOutp5
TrpOutp4
TrpOutp3
TrpOutp2
TrpOutp1
Function
N/A
N/A
N/A
N/A
N/A
N/A
NOTE: “TrpOutput1”just means to drive 1st group of tripping output contacts to pickup
and please refer to chapter “Hardware Description”for details. .
The bit corresponding to the breaker to be tripped shall be set as“1”and other bits shall be “0”.
For example, if differential protection operates to make “TrpOutp1”, “TrpOutpu2”, “TrpOutp3”
contacts pickup, the bit “1”and bit “2”and bit “3”positions shall be filled with “1”and other bit
positions shall be filled with “0”. Then a hexadecimal number 0007H is formed as the tripping
output logic setting.
Please note that tripping output logic settings of the equipment have to be set on basis of
application-specific drawings.
NOTE： The logic setting [TrpLog_Diff] is shared by the unrestrained instant differential
protection, conventional percent differential protection and DPFC current differential

protection.
14. [VEBI_Diff]
This setting is the VEBI setting of enabling current differential protection.

Each virtual enabling binary input (VEBI) setting is one of the conditions that decide whether the
relevant protection is in service, when this relay is energized. Each VEBI is an “AND”condition of
enabling the relevant protective element with the corresponding binary input and logic setting.
Through SAS or RTU, the virtual enabling binary input can be set as “1”or “0”; and it means that

the relevant protection can be in service or out of service through remote command. It provides
convenience for operation management.
NOTE: When current differential protection is enabled, if the maximum CT ratio to the
minimum CT ratio related to the protection is greater than 16, this will be considered
abnormal and wrong setting alarm will be sent.
3.2.6 Input and Output
Input signals for current differential protection are list in the following table.
Table 3.2-3 Input signals
No. Input Signal Description

1 EBI_Diff Binary input of enabling differential protection
No.1item is binary input of enabling protective element.
Output signals of current differential protections are list in following two tables.
Table 3.2-4 Output signals: report
No. Output Signal Description

1 Op_InstDiff Unrestrained instant differential protection operates.
2 Op_PcntDiff Conventional percent differential protection operates.
3 Op_DPFC_Diff DPFC percent differential protection operates.
No.1~No.3 items are tripping reports of protection element.
4 FD_PcntDiff Fault detector of percent differential protection picks up.
Fault detector of unrestrained instantaneous differential protection
5 FD_InstDiff
picks up.
6 FD_DPFC_Diff Fault detector of DPFC percent differential protection picks up.
No.4~No.6 items are virtual binary inputs to shows state of fault detector on fault detector DSP
module.
Differential current of current differential protection is in excess of
7 Alm_Diff
normally endurable level.
8 Alm_CTS CT secondary circuit of differential protection fails.
9 Alm_CTS_XXX CT secondary circuit at XXX side fails.
No.7~No.19 items are alarm reports of equipment operation.
NOTE: Symbol ”XXX”represents some side of transformer defined by user through
PCS-PC software, which may be “HVS”, “MVS”, “HVS1”,”HVS2”, etc.
Table 3.2-5 Output signal: sampled value and oscillograph
No. Output Signal Description Unit

No. Output Signal Description Unit

Ia_Corr_Brn
Corrected values of three phase currents of branch n (n=1,
1 Ib_Corr_Brn Ie
2, 3, 4, 5, 6) used for differential protection.
Ic_Corr_Brn
Secondary rated current of branch n (n=1, 2, 3, 4, 5, 6) of
2 I2b_ Diff_Brn A
transformer used for differential protection.
Corrected coefficient of branch n (n=1, 2, 3, 4, 5, 6) used
3 k_Diff_Brn
for differential protection.
4 Ang(Ia)_Br1-Brn
Three phase angles between corrected current of branch 1
5 Ang(Ib)_Br1-Brn deg
and corrected current of branch n (n= 2, 3).
6 Ang(Ic)_Br1-Brn
7 Ida, Idb, Idc Three-phase differential current value. Ie
Ida_2ndH
Secondary harmonic value of three-phase differential
8 Idb_2ndH Ie
current.
Idc_2ndH
9 Ira, Irb, Irc Three-phase restraint current value. Ie
Three-phase threshold current for current differential
10 Itha, Ithb, Ithc Ie
protection.
Ida_2ndH_Pct
11 Idb_2ndH_Pct Secondary harmonic percent of total differential current. %
Idc_2ndH_Pct
Ida_3rdH_Pct
12 Ida_3rdH_Pct Third harmonic percent of total differential current. %
Ida_3rdH_Pct
Ida_5thH_Pct
13 Idb_5thH_Pct Fifth harmonic percent of total differential current. %
Idc_5thH_Pct
No.1 to No. 13items are measured values and phase angles for LCD display
14 Ida, Idb, Idc Waveform of three phase differential currents Ie
No.14tem is used for oscillograph
3.3 Restricted Earth Fault Protection (REF)
The equipment provides three elements of restricted earth fault protection, which are applied for
autotransformer, two-winding and three-winding transformers.
The criterion of fault detector of restricted earth fault protection is as follows. The pickup of this
fault detector will enable restricted earth fault protection of the corresponding side.

I 0 d >[I_Pkp_PcntREF] (Equation 3.3-1)
Where:
I 0 d is the zero-sequence differential current of some side.
[I_Pkp_PcntREF] is the setting threshold of REF protection of the corresponding side .
The difference between current differential protection and restricted earth fault protection is that
the first one is based on ampere-turn balance and the later is based on ampere balance of
calculated zero-sequence current and zero-sequence current from neutral point zero-sequence
CT.
Three phase currents and neutral point current are the inputs to the restricted earth fault protection
of a three-phase winding. Polarity of three-phase CT is at busbar side, and that of neutral point
zero-sequence CT is at transformer side as shown in the Figure 3.3-1.
DANGER: Before REF protection of some side is put into operation on site, polarity of
zero-sequence CT at neutral point of the side must have been checked right by an
energizing test of the side or a test of simulating an external fault of the side in primary
system. Otherwise a maloperation may occur during an external earth fault.
*
Figure 3.3-1 Restricted earth fault protection for a wye winding
Where：
3I0_Cal is secondary values of three times calculated zero-sequence current of HV side.
3I0_NP is secondary values of current from zero-sequence CT at neutral point of HV side.
3.3.2.1 Current Compensation
The equation of calculating zero-sequence differential current is as follows.
0d 
I Klph1I 01 / I 2n_ CT1 Klph2I 02 / I 2n_ CT2 Klph3I 03 / I 2n _CT3 Klph4 I04 / I2n _CT4 KlphNPI NP / I 2n _CTNP
    
1 2 3 4 4 5

(Equation 3.3-2)
I 0 d I 
01 I 
02 I 03
I04
 I 
NP (Equation 3.3-3)
Where:
I 0 d is the zero-sequence differential current.
I 01, I 02, I 03, I04 are secondary values of calculated zero-sequence currents of each branch.
I NP is secondary current of zero-sequence CT at neutral point.
I
01, I  03, I
02 , I 04 are secondary corrected zero-sequence currents of each branch.
I
NP is the secondary corrected current from zero-sequence CT at neutral point.
Klph1 , Klph2 , Klph3 , Klph4 are corrected coefficients of each branch of magnitude compensation
respectively.
K lphNP is corrected coefficient of zero-sequence CT from neutral each branch of magnitude
compensation respectively.
I2 n _ CT 1, I2 n _ CT 2 , I 2n _ CT 3 , I 2n _ CT 4 are secondary rated values of CTs of each branch.
I2 n _ CTNP is the secondary rated values of zero-sequence CT at neutral point.
NOTE: Because the polarity of zero-sequence CT is at transformer side, current from
zero-sequence CT is subtracted in the differential current calculation.
The equation of calculating zero-sequence restraint current is:
, I 
I 0 r max{ I01 , I
02, I03 04 , I 
0 NP } (Equation 3.3-4)
Where:
I 0r is the zero-sequence restraint current.
If CTs used for REF have different primary rated values, then the current compensation is carried
out in the program automatically. Following gives the criteria of calculating correction coefficient.

I I1n _ max
K lph  1n K lb and K lb min( , 2. 95) (Equation 3.3-5)
I 1n _ max I 1n _ min
Where:
Klph is the correction coefficient of the calculated side.
I1 n is the primary value of CT at calculated side.
I1n _ min is the minimum value among primary values of all CTs for REF protection.
I1n _ max is the maximum value among primary values of all CTs for REF protection.
This calculation method is to take the minimum CT ration of all calculated sides as the base ration
and the CT ration at other sides are considered as multiples of the base ratio. If the multiple of the
maximum CT ratio to the minimum CT ratio is greater than 2.95, then the multiple shall be taken as
2.95 and other sides shall be calculated proportionally. Otherwise, the multiple shall be taken as
1, and the currents on other sides will be calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient ( K lph ).
3.3.2.2 Operation Equation
The operation criteria of REF protection are as follows:
I 0d I 0cdqd I 0r 0 .5 I n
I K 0b1 
I 0r 0. 5 I n I 0 cdqd
 0d

I 0r max{ I 01 , I 02 , I 03 , I 04 , I 0 NP } (Equation 3.3-6)
     
I 0d  I 01 I 02 I 03 I 04 I 0 NP


Where:
I n is a unit of current, i.e. the rated secondary current of CT.
I 0d is the zero-sequence differential current of some side.
I 0r is the zero-sequence restraint current of the corresponding side.
I 01 、 I 02 、 I03 、 I 04 are the calculated zero-sequence currents each branch of the corresponding

side.
I 0 NP is the current from zero-sequence CT on neural point.
I 0cdqd is the pick up value of zero-sequence percent differential protection (i.e. the setting
[I_Pkp_PcntREF]).
K 0 bl is the percent restraint coefficient of zero-sequence percent differential protection (i.e. the
setting [Slope_PcntREF]), and 0.5 is recommended.
I n is the rated secondary current of CT.
If the pick up value of REF protection is greater than 0.5 In (i.e. I 0cdqd 0. 5I n ), its keen point
current will be set at In automatically, the operating equation is as follows:
I 0 d I 0 cdqd I 0 r I n

I 0 d K 0 b1 I 0 r I n 
I 0cdqd

I 0 r max{ I 01 , I 02 , I 03 , I 04 , I 0 NP } (Equation 3.3-7)
     
I 0 d I 01 I 02 I 03 I 04 I 0 NP


Operation characteristic of restricted earth fault protection ( I 0cdqd 0.5I n ) is showed in the
following figure.

I0d
K0bl
[I_Pkp_PcntREF] I0r
restraint current
0.5 In
Figure 3.3-2 Operating characteristic curve of REF protection
Where:
The value of m is defined by the branch number for REF protection calculation.
3.3.2.4 Detection of CT Transient Characteristic Difference
Unbalanced three phases of CT can cause zero-sequence. Besides, larger zero-sequence may be
produced because three-phase CT characteristics can not be identical completely during an
external phase-to-phase fault or three-phase symmetrical fault current, which may lead
maloperation of restricted earth fault protection. Therefore, protection equipment shall solve such
problems.
Difference of transient characteristic and saturation of various CT will result in erroneous

zero-sequence differential current during an external three-phase short circuit fault or transformer
energization. In order to eliminate the effect of it, positive sequence current restraint blocking
criterion is used. When the zero-sequence current of each side REF protection is greater than 0
times positive sequence current, it is decided that zero-sequence current is caused by a fault and
release REF protection. Positive sequence current restraint blocking criterion is showed below.
I 0 0 I1 (Equation 3.3-8)
Where:
I 0 is the zero-sequence current at a side.
I 1 is its corresponding positive sequence current.

0 is a proportional constant.
The CT saturation detection principle of REF protection is same to the CT saturation detection
principle of current differential protection, and please refers to section 3.2.3.8 for details.
3.3.2.6 CT Supervision for REF Protection
The CT supervision for REF protection is divided into two kinds: zero-sequence differential CT
circuit abnormality without the pickup of the fault detector of REF protection and differential CT
circuit failure with the pickup of the fault detector pickup.
3.3.2.6.1 CT Circuit Abnormality of REF Protection
If the following operation formula is met and the state is keeping over 10s, CT circuit abnormality
alarm of REF protection will be issued without blocking the protection.
The operation formula is as follows:
I 0 d Max( 0.2 I 0 cdqd ,0 .1I n ) (Equation 3.3-9)
Where:
I 0d is the zero-sequence differential current.
I 0 cdqd is the pickup setting of restricted earth fault protection [I_Pkp_PcntREF].
3.3.2.6.2 CT Circuit Failure
 Criteria
If none of following four conditions is satisfied after the fault detector of differ ential current or
zero-sequence differential current picks up, it will be judged as CT circuit failure and CT circuit
failure alarm will be issued.
1) Negative-sequence voltage at any side is greater than 6V.
2) Any phase current of any side increases than that before the fault detector picks up.
3) The maximum phase current is greater than 1.1 Ie (Ie is secondary calculated rated current of
4) DPFC element of any phase-to-phase voltage of any side picks up.

By configuring different logic settings, user can gent following blocking functions to restricted earth
fault protection after CT circuit failure alarm is issued. Once the alarm signal of differential CT
circuit failure is issued, it can be reset only when the failure is removed and equipment is reset (i.e.
the binary input [BI_RstTarg] is energized).
Restricted earth fault protection of each side can be blocked when CT circuit failure is detected by
configuring the logic setting [En_CTS_Blk_REF].
 If this logic setting is set as “0”, the protection is not blocked by with the alarm signal
being issued.
 If this logic setting is set as “1”, the protection is blocked by with the alarm signal being
issued.
NOTE: The operation time of REF protection with CT circuit failure being distinguished is a
littler greater than that of REF protection without CT circuit failure.
3.3.3 Logic Scheme
Figure 3.3-3 Logic diagram of REF protection of HV side
Where:
Flg_Op_REF_HVS is the internal flag indicating that operation criterion of REF protection of HV
side is satisfied.
[EBI_REF_HVS] is the binary input of enabling REF protection of HV side.
[VEBI_REF_HVS] is the VEBI setting of enabling REF protection of HV side.
HVS: [En_REF] is the logic setting of enabling REF protection of HV side.

Flg_I1_Restraint is the internal flag indicating that difference of CT transient characteristic is

detected.
Flg_CT_Sta is the internal flag indicating that CT saturation is distinguished.
Flg_CTS is the internal flag indicating that instant CT circuit failure is distinguished by the criterion.
Flg_FD_REF_HVS is the internal flag indicating that the fault detector of REF protection of HV
side picks up.
[Op_REF_HVS] is the operation fl ag of REF protection of HV side.
3.3.4 Setting
Table 3.3-1 Settings of REF protection of each side

Pickup setting of REF
1 I_Pkp_PcntREF 0.05~5In 0.01In
protection
Percent restraint coefficient of
2 Slope_PcntREF 0.2~0.75 0.01
REF protection
Logic setting of
0: disable enabling/disabling blocking
3 En_CTS_Blk_REF 0, 1
1: enable REF protection during CT
circuit failure
Logic setting of
0: disable
4 En_REF 0, 1 enabling/disabling REF
1: enable
protection
Tripping logic setting of REF
5 TrpLog_REF 0000~FFFF
protection
VEBI setting of
0: disable enabling/disabling REF
6 VEBI_REF_XXX 0, 1
1: enable protection of XXX side (i.e.,
MVS or LVS)
Three REF protections are equipped for each side of transformer, and they have the same setting
principles.
1. [ I_Pkp_PcntREF]
The pickup current of REF protection shall be greater than the maximum unbalance current while
transformer operates on normal rated load, i.e.
I 0 cdqd K rel (K er m )I n (Equation 3.3-10)
Where:

I0 cdqd is the setting [I_Pkp_PcntREF].
Ie is rated secondary current of the corresponding side of transformer.
K rel is reliability coefficient (generally K rel = 1.3~1.5).
K er is the ratio errors of CT (for type 10P, K er = 0.03×2; for type 5P and TP, K er =0.01X2).
m is the error caused by the difference between ratios of CTs, and 0.05 is recommended.
Note that the pickup setting of the REF protection takes the secondary rated current of CT (i.e. In,
1A or 5A) as its unit, whose setting value is calculated with the reference to the side having the
minimum ratio among all CTs for the REF protection. If it is the actual current value to the
reference side in actual setting calculation, then this actual value will be divided by the secondary
rated current of CT (i.e. In , 1A or 5A) to derive the setting value.
In actual projects, the measured unbalance current of the zero-sequence differential circuit under
the maximum load current can be referred to.
The setting should not be less than 0.1In and the recommended value is 0.2In~0.5In.
NOTE: The unit (i.e. In) of the setting calculation ([I_Pkp_PcntREF]) is the secondary
rated current of CT, and the minimum corrected coefficient of the side is taken as the
reference side. If a setting value got from calculation is together with its unit Ampere, this
setting value shall be divided by the secondary rated current of CT to get per unit value
which is the configuration value input to protection equipment.
2. [Slope_PcntREF]
The setting is percent restraint coefficient of winding differential protection, which shall be greater
than unbalance current caused by zero-sequence current flowing through the transformer during
an external fault.
The setting calculation equation is given below.
K 0 bl Krel ( K ap kcc K er m) (Equation 3.3-11)
Where:
K 0bl is the setting [Slope_REF].
m is the error caused by the difference between ratios of CTs.
K rel is reliability coefficient.
K er is the ratio errors of CT.
K ap = 1.0 if CT at both sides are class TP, or Kap = 1.5~ 2.0 if CT at both sides are class P.

Generally, in practical setting calculation for projects, K 0bl can be taken as 0.3
0.7
Recommended value: 0.5
3. [En_CTS_Blk_REF]
This is logic setting of enabling REF protection blocked by CT circuit failure.
“0”: REF is not blocked by CT circuit failure.
“1”: REF protection is blocked by CT circuit failure.
NOTE: When REF protection is enabled, if the maximum CT ratio to the minimum CT ratio
related to the protection is greater than 16, this will be considered abnormal and wrong
setting alarm will be sent.
4. [En_REF]
The logic setting is used to enable or disable the REF protection of the corresponding side.
5. [TrpLog_REF]
The tripping logic setting is used to specify which breakers will be tripped when REF protection
operates. Please refer to the description of the setting [TrpLog_Diff] in section 3.2.5 for details.
6. [VEBI_REF]
This setting is the VEBI setting of enabling REF protection. Please refer to the setting [VEBI_Diff]
in section 3.2.5 for details.
NOTE: When restricted earth fault protection is enabled, if the maximum CT ratio to the
Input signals of restricted earth fault protection are list in the following table.
Table 3.3-2 Input signal

1 EBI_REF_HVS Binary input of enabling restricted earth fault protection of HV side.
2 EBI_REF_MVS Binary input of enabling restricted earth fault protection of MV side.
3 EBI_REF_LVS Binary input of enabling restricted earth fault protection of LV side.
No.1~No.3 items are binary inputs of enabling protective function
Output signals of restricted earth fault protection are list in following two tables.

Table 3.3-3 Output signal: report

1 Op_REF_HVS Restricted earth fault protection of HV side operates.
2 Op_REF_MVS Restricted earth fault protection of MV side operates.
3 Op_REF_LVS Restricted earth fault protection of LV side operates.
No.1~No3 items are tripping reports of protection element.
Fault detector of restricted earth fault protection of HV side picks
4 FD_REF_HVS
up.
Fault detector of restricted earth fault protection of MV side picks
5 FD_REF_MVS
up.
6 FD_REF_LVS Fault detector of restricted earth fault protection of LV side picks up.
module.
CT secondary circuit for restricted earth fault protection of HV side
7 Alm_REF_HVS
is abnormal.
CT secondary circuit for restricted earth fault protection of MV side
8 Alm_REF_MVS
is abnormal.
CT secondary circuit for restricted earth fault protection of LV side
9 Alm_REF_LVS
is abnormal.
CT secondary circuit for restricted earth fault protection of HV side
10 Alm_CTS_REF_HVS
fails.
CT secondary circuit for restricted earth fault protection of MV side
11 Alm_CTS_REF_MVS
fails.
CT secondary circuit for restricted earth fault protection of LV side
12 Alm_CTS_REF_LVS
fails.
Table 3.3-4 Output signal: sample values and oscillograph

Corrected coefficient of calculated zero-sequence current for
1 k_ REF_HBrn
REF protection of HV side branch n (n=1, 2, 3, 4).
Corrected coefficient of zero-sequence current from neutral
2 k_ REF_HNP
point CT for REF protection of HV side.


3 k_ REF_MBrn
REF protection of MV side branch n (n=1, 2, 3, 4,).
4 k_ REF_MNP
point CT for REF protection of MV side.
5 k_ REF_LBrn
REF protection of LV side branch n (n=1, 2, 3, 4,).
6 k_ REF_LNP
point CT for REF protection of LV side.
Corrected value of calculated zero-sequence current of HV
7 I0_Corr_ REF_HBrn
side branch n (n=1, 2, 3, 4,).
Corrected value of zero-sequence current from neural point
8 I0_Corr_REF_HNP
zero-sequence CT of HV side.
Corrected value of calculated zero-sequence current of MV
9 I0_Corr_REF_MBrn
10 I0_Corr_REF_MNP
zero-sequence CT of MV side.
Corrected value of calculated zero-sequence current of LV
11 I0_Corr_REF_LBrn
12 I0_Corr_REF_LNP
zero-sequence CT of LV side.
Angle between calculated zero-sequence current of HV side
13 Ang(3I0)_HBr1-HBr2 branch 1 and calculated zero-sequence current of HV side
branch 2.
Angle between calculated zero-sequence current of HV side
14 Ang(3I0)_HBr1-HNP branch 1 and zero-sequence current from neutral point CT of
HV side.
Angle between calculated zero-sequence current of MV side
15 Ang(3I0)_MBr1-MBr2 branch 1 and calculated zero-sequence current of MV side
branch 2.
Angle between calculated zero-sequence current of MV side
16 Ang(3I0)_MBr1-MNP branch 1 and zero-sequence current from neutral point CT of
MV side.
Angle between calculated zero-sequence current of LV side
17 Ang(3I0)_LBr1-LBr2 branch 1 and calculated zero-sequence current of LV side
branch 2.
Angle between calculated zero-sequence current of LV side
18 Ang(3I0)_LBr1-LNP branch 1 and zero-sequence current from neutral point CT of
LV side.


Zero-sequence differential current for REF protection of HV
19 I0d_REF_HVS
side
20 I0r_REF_HVS Zero-sequence restraint current for REF protection of HV side
21 I0th_REF_HVS Zero-sequence threshold current for REF protection of HV side
22 I0d_REF_MVS
side
23 I0r_REF_MVS Zero-sequence restraint current for REF protection of HV side
24 I0th_REF_MVS Zero-sequence threshold current for REF protection of HV side
25 I0d_REF_LVS
side
26 I0r_REF_LVS Zero-sequence restraint current for REF protection of HV side
27 I0th_REF_LVS Zero-sequence threshold current for REF protection of HV side
No.1 to No. 27 items are measured values and phase angles for LCD display
28 I0d_H Waveform of zero-sequence differential current of HV side.
29 I0d_M Waveform of zero-sequence differential current of MV side.
30 I0d_L Waveform of zero-sequence differential current of LV side.
No.28~No.30 items are used for oscillograph.
3.4 Winding Differential Protection

The criterion of fault detector of winding differential protection is as follows. The pickup of this fault
detector will enable winding differential protection of the corresponding side.
I wd  [I_Pkp_PcntWdgDiff] (Equation 3.4-1)
Where:
I wd is winding differential current.

[I_Pkp_PcntWdgDiff] is the pickup setting of winding differential protection.

Winding differential protection is based on Kirchhoff's first law (i.e. KCL) and calculates differential
currents of pure electrical connection circuits including phase A , phase B phase C and zero
sequence differential currents.
DANGER: When winding differential protection is used as stub differential protection, the
polarity of CT must be checked. If polarities of the circuit breaker CT and the bush CT of
some side of a transformer are both at busbar side, either of them must be reversed by

PCS-PC software
3.4.2.1 Current Compensation
The equation of calculating winding differential current is as follows.

I wdA  I A1  I A2  I A3 
       
I wdB 
 I I I
K wph1B1 / I 2 n _ CT1 K wph2 B2 / I 2n _ CT 2 K wph3 B3 / I 2 n _ CT 3 

I wdC  
I C1  IC2  IC3 
       

I 0
 I  I  I 
wd
   
01    
02   
03 
1 2 3 4
I A4  I A5 
I  I B5 
K wph4  B4 
/ I K wph 5 / I
I C 4  2 n _ CT 4 I C 5  2n _ CT5
   

I 04  
I  
  05
5 6
(Equation 3.4-2)
I dA I A1 I 
A2 I 
A3 I 
A 4 I A5
     
 dB
I  I B1 I B2 I B3 I B4 I B5
I
dC  I 
C1 I 
C2 I 
C3 I 
C4  I 5
C
I d 0 I 01
I 02 I 03
 I 04
 I 05

Where:
I wdA I wdB I wdC I wd 0 are respectively three phase and zero-sequence winding differential currents.
I An , I Bn , I Cn , I n 0 are respectively secondary values of three phase currents and calculated
zero-sequence current of branch n (n=1, 2, 3, 4 ,5).
I
An , I  , I 
Bn , I Cn n 0 are respectively secondary values of corrected three phase currents and calculated
zero-sequence current of branch n (n=1, 2, 3, 4 ,5）

Kwph1 , Kwph 2 , K wph3 , Kwph 4 , K wph 5 are corrected coefficients of each side for magnitude compensation
respectively.
I2 n _ CT 1, I2 n _ CT 2 , I 2n _ CT 3 , I 2 n _ CT 4 , I2 n _ CT 5 are respectively secondary rated values of CTs of each
branch.
The equation of calculating restraint current is:

 1

I rA 2 I A1 I 
A 2 I 
A 3 I 
A4 I A5 


1

I rB  I  B1 I 
B 2 I 
B 3 I 
B 4 I 
B5 
2
1

I rC  I  C1 I C
2 I C3 I C4 I C5 
 2

 
1
I wr0  I 01 I 02
 I 03
 I 04
 I 05 
 2
Where:
I rA , I rB , I rC , I wr0 are secondary values of three phase restraint currents and zero-sequence
restraint current respectively.
If CTs used for winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically. Following gives the criteria of calculating
correction coefficient.
I I 1n _ max
K wph  1n K b and K wb min( , 2. 95) (Equation 3.4-5)
I 1n _ max I1n _ min
Where:
K wph is the correction coefficient of the calculated side.
I1 n is the primary value of CT at calculated side.
I1n _ min is the minimum value among primary values of all CTs for winding differential protection.
I1n _ max is the maximum value among primary values of all CTs for winding differential protection.
This calculation method is to take the minimum CT ration of all calculated sides as the base ration
and the CT ration at other sides are considered as multiples of the base ratio. If the multiple of the
maximum CT ratio to the minimum CT ratio is greater than 2.95, then the multiple shall be taken as
2.95 and other sides shall be calculated proportionally. Otherwise, the multiple shall be taken as
1, and the currents on other sides will be calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient ( K wph ).
3.4.2.2 Operation Equation
The operation criteria of winding differential protection are as follows, and maximum 5 branches

are supported for the calculation.
I wd I wcdqd I wr 0.5I n
I K wb1  I wr 0.5I n 
I wcdqd


wd
wr
I max{ I w1 , I w 2 , I w 3 , I w 4 , I w 5 } (Equation 3.4-6)
     
I wd I w 1 I w 2 I w 3 I w 4 I w 5


Where:
I w1 … I w5 are currents of five branches of some side respectively.
Iwcdqd is the pickup setting of winding differential protection of the corresponding side, of i.e.
[I_Pkp_PcngWdgDiff]
Iwd is winding differential current.
Iwr is winding restraint current.
K w b l is the percent restraint coefficient, i.e. [Slope_PcntWdiffDiff].
NOTE: For protecting an autotransformer, a winding differential protection is composed of
three-phase currents of HV side, LV side and common winding.
If the pick up value of winding differential protection is greater than 0.5 In (i.e. I 0cdqd 0. 5I n ), its
keen point current will be set at I n automatically, the operating equation is as follows:
I wd I wcdqd I 0 r I n
I K wb1  I wr I n 
I wcdqd


wd
wr
I max{ I w1 , I w 2 , I w 3 , I w 4 , I w 5 } (Equation 3.4-7)
     
I wd I w 1 I w 2 I w 3 I w 4 I w 5


Operation characteristic of restricted earth fault protection ( I wcdqd 0.5 I n ) is showed in the
following figure.

differential current
K= m
Figure 3.4-1 Operating characteristic curve of winding differential protection
Where:
The value of m is defined by the branch number for winding differential protection calculation.

The CT saturation detection principle of REF protection is same to the CT saturation detection
principle of current differential protection, and please refers to section 3.2.3.8 for details.
3.4.2.5 CT Supervision for Winding Differential Protection

3.4.2.5.1 CT Circuit Abnormality of Winding Differential Protection
If the following operation formula is met and the state is keeping over 10s, CT circuit abnormality
alarm of REF protection will be issued without blocking the protection.
The operation formula is as follows:
I wd Max (0. 2 I wcdqd ,0.1I n ) (Equation 3.4-8)
Where:
I wd is the winding differential current.
I wcdqd is the pickup setting of winding differential protection [I_Pkp_PcntWdgDiff].
3.4.2.5.2 CT Circuit Abnormality of Winding Differential Protection
 Criteria

If none of following four conditions is satisfied after the fault detector of differential current or
zero-sequence differential current picks up, it will be judged as CT circuit failure and CT circuit
failure alarm will be issued.
1) Negative-sequence voltage at any side is greater than 6V.
2) Any phase current of any side increases than that before the fault detector picks up.
3) The maximum phase current is greater than 1.1 Ie (Ie is secondary calculated rated current of
4) DPFC element of any phase-to-phase voltage of any side picks up.
By configuring different logic settings, user can gent following blocking functions to winding
differential protections after CT circuit failure alarm is issued. Once the alarm signal of differential
CT circuit failure is issued, it can be reset only when the failure is removed and equipment is reset
(i.e. the binary input [BI_RstTarg] is energized).
Winding differential protection of each side can be blocked when CT circuit failure is detected by
configuring the logic setting [En_CTS_Blk_WdgDiff].
 If this logic setting is set as “0”, the protection is not blocked by with the alarm signal
being issued.
 If this logic setting is set as “1”, the protection is blocked by with the alarm signal being
issued.

3.4.3 Logic Scheme
Figure 3.4-2 Logic diagram of winding differential protection of HV side
Where:
Flg_Op_WdgDiff_HVS is the internal flag indicating that operation criterion of winding differential
protection of HV side is satisfied.
[EBI_WdgDiff_HVS] is the binary input of enabling winding differential protection of HV side.
[VEBI_WdgDiff_HVS] is the VEBI setting of enabling winding differential protection of HV side.
HVS: [En_WdgDiff] is the logic setting of enabling winding differential protection of HV side.
Flg_CT_Sta is the internal flag indicating that CT saturation is distinguished.
Flg_CTS is the internal flag indicating that instant CT circuit failure is distinguished by the criterion.
Flg_FD_WdgDiff_HVS is the internal flag indicating that the fault detector of winding differential
protection of HV side picks up.
[Op_WdgDiff_HVS] is the operation flag of winding differential protection of HV side.
3.4.4 Setting
Table 3.4-1 Settings of winding differential protection of each side

Pickup setting of winding differential
1 I_Pkp_PcntWdgDiff 0.05~5In 0.01In
protection
Percent restraint coefficient of winding
2 Slope_PcntWdgDiff 0.2~0.75 0.01
differential protection
0: disable
3 En_CTS_Blk_WdgDiff 0, 1 blocking winding differential protection
1: enable
during CT circuit failure
0: disable Logic setting of enabling/disabling
4 En_WdgDiff 0, 1
1: enable winding differential protection
Tripping logic setting of winding
5 TrpLog_WdgDiff 0000~FFFF
differential protection


VEBI setting of enabling/disabling
0: disable
6 VEBI_WdgDiff_XXX 0, 1 winding differential protection of XXX
1: enable
side (i.e., MVS or LVS)
Three winding differential protections are equipped for each side of transformer, and they have the
same setting principles.
7. [ I_Pkp_PcntREF]
The pickup current of winding differential protection shall be greater than the maximum unbalance
current while transformer operates on normal rated load, i.e.
I wcdqd K rel (K er m) I n (Equation 3.4-9)
Where:
I wcdqd is the setting [I_Pkp_PcntWdgDiff].
Ie is rated secondary current of the corresponding side of transformer.
K rel is reliability coefficient (generally K rel = 1.3~1.5).
K er is the ratio errors of CT (for type 10P, K er = 0.03×2; for type 5P and TP, K er =0.01X2).
m is the error caused by the difference between ratios of CTs, and 0.05 is recommended.
Note that the pickup setting of the winding differential protection takes the secondary rated current
of CT (i.e. In, 1A or 5A) as its unit, whose setting value is calculated with the reference to the side
having the minimum ratio among all CTs for the winding differential protection. If it is the actual
current value to the reference side in actual setting calculation, then this actual value will be
divided by the secondary rated current of CT (i.e. In , 1A or 5A) to derive the setting value.
In actual projects, the measured unbalance current of the winding differential circuit under the
maximum load current can be referred to.
The setting should not be less than 0.1In and the recommended value is 0.2In~0.5In.
NOTE: The unit (i.e. In) of the setting calculation ([I_Pkp_PcntWdgDiff]) is the secondary
rated current of CT, and the minimum corrected coefficient of the side is taken as the
reference side. If a setting value got from calculation is together with its unit Ampere, this
setting value shall be divided by the secondary rated current of CT to get per unit value
which is the configuration value input to protection equipment.
8. [Slope_PcntWdgDif]
The setting is percent restraint coefficient of winding differential protection, which calculation

equation is given below.
Kwbl Krel ( Kap kcc Ker m) (Equation 3.4-10)
Where:
K wbl is the setting [Slope_PcntWdgDiff].
m is the error caused by the difference between ratios of CTs.
K rel is reliability coefficient.
K er is the ratio errors of CT.
K ap = 1.0 if CT at both sides are class TP, or Kap = 1.5~ 2.0 if CT at both sides are class P.
Generally, in practical setting calculation for projects, K wbl can be taken as 0.30.7
Recommended value: 0.5
9. [En_CTS_Blk_WdgDiff]
This is logic setting of enabling winding differential protection blocked by CT circuit failure.
“0”: Winding differential protection is not blocked by CT circuit failure.
“1”: Winding differential protection is blocked by CT circuit failure.
NOTE: When winding differential protection is enabled, if the maximum CT ratio to the
10. [En_WdgDiff]
The logic setting is used to enable or disable the winding differential protection of the
corresponding side.
11. [TrpLog_WdgDiff]
The tripping logic setting is used to specify which breakers will be tripped when winding differential
protection operates. Please refer to the description of the setting [TrpLog_Diff] in section 3.2.5 for
details.
12. [VEBI_WdgDiff]
This setting is the VEBI setting of enabling winding differential protection. Please refer to the
setting [VEBI_Diff] in section 3.2.5 for details.

NOTE: When winding differential protection is enabled, if the maximum CT ratio to the
Input signals of restricted earth fault protection are list in the following table.

1 EBI_WdgDiff_HVS Binary input of enabling winding differential protection of HV side.
2 EBI_WdgDiff _MVS Binary input of enabling winding differential protection of MV side.
3 EBI_WdgDiff _LVS Binary input of enabling winding differential protection of LV side.
No.1~No.3 items are binary inputs of enabling protective function
Output signals of restricted earth fault protection are list in following two tables.

1 Op_PhWdgDiff_HVS Phase winding differential protection of HV side operates.
2 Op_PhWdgDiff_MVS Phase winding differential protection of MV side operates.
3 Op_PhWdgDiff_LVS Phase winding differential protection of LV side operates.
4 Op_RWdgDiff_HVS Zero-sequence differential protection of HV side operates.
5 Op_RWdgDiff_MVS Zero-sequence differential protection of MV side operates.
6 Op_ZRWdgDiff_LVS Zero-sequence differential protection of LV side operates.
Fault detector of phase winding differential protection of HV side
7 FD_PhWdgDiff_HVS
picks up.
Fault detector of phase winding differential protection of MV side
8 FD_PhWdgDiff_MVS
picks up.
Fault detector of phase winding differential protection of LV
9 FD_PhWdgDiff_LVS
side picks up.
Fault detector of zero-sequence differential protection of HV
10 FD_RWdgDiff_HVS
side operates.
Fault detector of Zero-sequence differential protection of MV
11 FD_RWdgDiff_MVS
side operates.
12 FD_RWdgDiff_LVS Zero-sequence differential protection of LV side operates.
module.


CT secondary circuit for winding differential protection of HV
13 Alm_WdgDiff_HVS
side is abnormal.
CT secondary circuit for winding differential protection of MV
14 Alm_WdgDiff_MVS
side is abnormal.
CT secondary circuit for winding differential protection of LV side
15 Alm_WdgDiff_LVS
is abnormal.
CT secondary circuit for winding differential protection of HV
16 Alm_CTS_WdgDiff_HVS
side fails.
CT secondary circuit for winding differential protection of MV
17 Alm_CTS_WdgDiff_MVS
side fails.
CT secondary circuit for winding differential protection of LV side
18 Alm_CTS_WdgDiff _LVS
fails.

Ia_Corr_WdgDiff_HBrn
Three phase corrected currents of winding differential protection
1 Ib_Corr_WdgDiff_HBrn
of HV side branch n (n=1, 2, 3, 4, 5).
Ic_Corr_WdgDiff_HBrn
Zero-sequence corrected current of winding differential
2 I0_Corr_WdgDiff_HBrn
protection of HV side branch n (n=1, 2, 3, 4, 5).
Ia_Corr_WdgDiff_MBrn
Ib_Corr_WdgDiff_MBrn
of MV side branch n (n=1, 2, 3, 4, 5).
3
Ic_Corr_WdgDiff_MBrn

I0_Corr_WdgDiff_MBrn
protection of MV side branch n (n=1, 2, 3, 4, 5).
Ia_Corr_WdgDiff_LBrn
Ib_Corr_WdgDiff_LBrn
of LV side branch n (n=1, 2, 3, 4, 5).
4 Ic_Corr_WdgDiff_LBrn
I0_Corr_WdgDiff_HBrn
protection of LV side branch n (n=1, 2, 3, 4, 5).

Corrected coefficient of HV side branch n (n=1, 2, 3, 4, 5) for

k_WdgDiff_HBrn
winding differential protection.
Corrected coefficient of MV side branch n (n=1, 2, 3, 4, 5) for
5 k_WdgDiff_MBrn
Corrected coefficient of LV side branch n (n=1, 2, 3, 4, 5) for
k_WdgDiff_LBrn
Phase A differential current of winding differential protection of
6 Ida_WdgDiff_HVS
HV side.
Phase B differential current of winding differential protection of
7 Idb_WdgDiff_HVS
HV side.
Phase C differential current of winding differential protection of
8 Idc_WdgDiff_HVS
HV side.
Zero-sequence differential current of winding differential
9 I0d_WdgDiff_HVS
protection of HV side.
Phase A restraint current of winding differential protection of HV
10 Ira_WdgDiff_HVS
side.
Phase B restraint current of winding differential protection of HV
11 Irb_WdgDiff_HVS
side.
Phase C restraint current of winding differential protection of HV
12 Irc_WdgDiff_HVS
side.
Zero-sequence restraint current of winding differential protection
13 Ir0_WdgDiff_HVS
of HV side.
Phase A threshold current of winding differential protection of HV
14 Itha_WdgDiff_HVS
side.
Phase B threshold current of winding differential protection of HV
15 Ithb_WdgDiff_HVS
side.
Phase C threshold current of winding differential protection of HV
16 Ithc_WdgDiff_HVS
side.
Zero-sequence threshold current of winding differential
17 Ith0_WdgDiff_HVS
Phase A differential current of winding differential protection of
18 Ida_WdgDiff_MVS
MV side.
19 Idb_WdgDiff_MVS
MV side.
20 Idc_WdgDiff_MVS
MV side.
21 I0d_WdgDiff_MVS
protection of MV side.
22 Ira_WdgDiff_MVS Phase A restraint current of winding differential protection of MV

side.
Phase B restraint current of winding differential protection of MV
23 Irb_WdgDiff_MVS
side.
Phase C restraint current of winding differential protection of MV
24 Irc_WdgDiff_MVS
side.
25 Ir0_WdgDiff_MVS
of MV side.
Phase A threshold current of winding differential protection of MV
26 Itha_WdgDiff_MVS
side.
Phase B threshold current of winding differential protection of MV
27 Ithb_WdgDiff_MVS
side.
Phase C threshold current of winding differential protection of MV
28 Ithc_WdgDiff_MVS
side.
29 Ith0_WdgDiff_MVS
Phase A differential current of winding differential protection of LV
30 Ida_WdgDiff_LVS
side.
31 Idb_WdgDiff_LVS
LV side.
32 Idc_WdgDiff_LVS
LV side.
33 I0d_WdgDiff_LVS
protection of LV side.
Phase A restraint current of winding differential protection of LV
34 Ira_WdgDiff_LVS
side.
Phase B restraint current of winding differential protection of LV
35 Irb_WdgDiff_LVS
side.
Phase C restraint current of winding differential protection of LV
36 Irc_WdgDiff_LVS
side.
37 Ir0_WdgDiff_LVS
of LV side.
Phase A threshold current of winding differential protection of LV
38 Itha_WdgDiff_LVS
side.
Phase B threshold current of winding differential protection of LV
39 Ithb_WdgDiff_LVS
side.
Phase C threshold current of winding differential protection of LV
40 Ithc_WdgDiff_LVS
side.
41 Ith0_WdgDiff_LVS

42 Ang(Ia)_HBr1-HBrn
Three phase angles between the current of HV side branch 1
43 Ang(Ib)_HVS1-HVSn
and the current of HV side branch n (n=2, 3, 4, 5).
44 Ang(Ic)_HBr1-HBrn
Angle between zero-sequence current of HV side branch 1 and
45 Ang(3I0)_HBr1-HBrn
zero-sequence current of HV side branch n (n=2, 3, 4, 5).
46 Ang(Ia)_MBr1-MBrn
Three phase angles between the current of MV side branch 1
47 Ang(Ib)_MBr1-MBrn
and the current of MV side branch n (n=2, 3, 4, 5).
48 Ang(Ic)_MBr1-MBrn
Angle between zero-sequence current of MV side branch 1 and
49 Ang(3I0)_MBr1-MBrn
zero-sequence current of MV side branch n (n=2, 3, 4, 5).
50 Ang(Ia)_LBr1-LBrn
Three phase angles between the current of LV side 1 and the
51 Ang(Ib)_LBr1-LBrn
current of LV side n (n=2, 3, 4, 5).
52 Ang(Ic)_LBr1-LBrn
Angle between zero-sequence current of LV side branch 1 and
53 Ang(3I0)_LBr1-LBrn
zero-sequence current of LV side branch n (n=2, 3, 4, 5).
3.5 Overexcitation Protection
Overexcitation protection is used to prevent transformer damage due to overvoltage and low
frequency. Two definite-time stages and one inverse-time stage for tripping and one definite-time
stage for alarm are equipped with overexcitation protection.
The side overexcitation protection being equipped can be selected by user through PCS-PC
software.
 Definite time overexcitation fault detector
The fault detector picks up after the corresponding time delay, when measured U * / f* is greater
than the definite protection setting.
 Inverse time overexcitation fault detector
The fault detector picks up when overexcitation U * / f * accumulated value is greater than
inverse time protection setting and the corresponding time delay is expired.

 Definite-time overexcitation protection
Two-stage definite overexcitation and one-stage overexciation alarm element are equipped.

Degree of overexcitation can be evaluated by following overexcitation multiple:
n U* / f * (Equation 3.5-1)
Where:
U * and f * are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is secondary rated voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
 Inverse-time overexcitation protection
Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, obtaining multiple of overexcitation by calculation, and
getting the corresponding operation delay by sectional linear insertion. It reflects the heat
accumulation and radiation.
Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of different transformers.
Figure 3.5-1 shows inverse-time characteristic of overexcitation protection. As harm of

overexcitation to transformer is mainly part overheat, so accumulation method is adopted to
calculate overexcitation multiple.
U* / f*
Figure 3.5-1 Inverse-time characteristic of overexcitation protection
Overexcitation calculation factor comprises overexcitation information at current instant and also
overexcitation information integrated over various time intervals since its beginning.
Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation between various settings of n and t are:
n0≥n1 ≥ n2 ≥ n3 ≥ n4 ≥ n5 ≥ n6 ≥ n7 ≥ n8 ≥ n9
t0 ≤t1 ≤ t2 ≤ t3 ≤ t4 ≤ t5 ≤ t6 ≤ t7≤ t8 ≤ t9

Where
n0 is the upper-limit multiple setting of inverse-time overexcitation protection, i.e. [k0_InvOvExc].
t0 is the time delay corresponding to the upper-limit multiple setting, i.e. [t0_InvOvExc].
n9 is the lower-limit multiple setting of inverse-time overexcitation protection, i.e. [k9_InvOvExc].
t9 is the time delay corresponding to the lower-limit multiple setting , i.e. [t9_InvOvExc].
ni (i=1,… 8) is the setting of the corresponding point of overexcitation, i.e. [ki_InvOvExc] (i=1,… ,8).
ti (i=1,… 8) is the setting of the corresponding point of overexcitation, i.e. [ki_InvOvExc] (i=1,… ,8).
Because voltage is used for the calculation of overexciation protection, the protection shall be
disabled when voltage transformer of the side where the protection is equipped is out of service.
Inverse-time overexcitation alarm and trip elements both equipped. If only alarm element is
enabled, an alarm signal will be issued after calculated time delay is expired, but if only trip
element is enabled, an alarm signal message will be issued after 0.7 times calculated time delay is
expired and a trip signal will be issued after calculated time delay is expired.

3.5.3 Logic Scheme
[EBI_In_VT_XXX]
[En _In_VT_XXX] & [t_Alm_DefOvExc]
& [Alm_DefOvExc]
[En_Alm_DefOvExc]
U / f > [k_Alm_DefOvExc]
[EBI_In_VT_XXX]
&
[En_In_VT_XXX]
[EBI_OvExc]
&
[VEBI_OvExc] & [t_DefOvExcn] [Op _DefOvExc]
[En_Trp_DefOvExc]
&
U / f > [k_DefOvExcn]
Flg_FD_DefOvExc
[EBI_In_VT_XXX]
&
[En_In_VT_XXX]
[En _Alm_InvOvExc]
& & Alm_InvOvExcn]
U / f > [k9_InvOvExc]
[En_Trp_InvExc]
&
[EBI_In_VT_XXX]
&
[En_In_VT_XXX]
[EBI_OvExc]
&
[VEBI_OvExc] & [Op_InvOvExcn]
[En_Trp_InvExc]
&
Flg_FD_InvOvExc
Figure 3.5-2 Logic diagram of overexcitation protection
Where:
U / f  is the multiple of overexcitation of a transformer.
[EBI_In_VT_XXX] is the binary input of enabling VT of XXX (XXX= HVS, MVS or LVS) side into
service.
[En_In_VT_XXX] is the logic setting of enabling VT of XXX (XXX= HVS, MVS or LVS) side into
service.
[EBI_OvExc] is the binary input of enabling overexciation protection.

[VEBI_OvExc] is the VEBI setting of enabling overexcitation protection.
[En_Alm_DefOvExc] is the logic setting of enabling definite-time overexcitation alarm element.
[En_Alm_InvOvExc] is the logic setting of enabling inverse-time overexciation alarm element.
[En_Trp_DefOvExc] is the logic setting of enabling definite-time overexcitation tripping element.
[En_Trp_InvOvExc] is the logic setting of enabling definite-time overexcitation tripping element.
[k_Alm_DefOvExc] is the setting of definite-time overexcitation alarm element.
[k_DefOvExcn] is the setting of stage n (n=1, 2) of definite-time overexciation tripping element.
[k9_InvOvExc] is the pickup setting of inverse-time overexcitation tripping element.
[t_Alm_DefOvExc] is the delay of definite-time overexcitation alarm element.
[t_DefOvExn] is time delay of stage n (n=1, 2) of definite-time overexcitation tripping element.
Flg_FD_DefOvExc is the internal flag indicating that the fault detector of definite-time
overexcitation protection picks up.
Flg_FD_InvOvExc is the internal flag indicating that the fault detector of inverse-time overexciation
protection picks up.
[Alm_OvExc] is the operation flag of definite-time overexcitation alarm element.
[Alm_InvOvExc] is the operation flag of inverse-time overexcitation alarm element.
[Op_OvExc] is the operation flag of definite-time overexcitation tripping element.
[Op_InvOvExc] is the operation flag of inverse-time overexciation tripping element.
3.5.4 Setting
Table 3.5-1 Settings of overexcitation protection

Setting of stage 1 of definite-time
1 k_DefOvExc1 1.0~1.7 0.001
Delay of stage 1 of definite-time
2 t_DefOvExc1 0~9999.0s 0.1s
overexcitation protection.
Setting of stage 2 of definite-time
3 k_DefOvExc2 1.0~1.7 0.001
Delay of stage 2 of definite-time
4 t_DefOvExc2 0~9999.0s 0.1s
overexcitation protection.
Setting of definite-time overexcitation
5 k_Alm_DefOvExc 1.0~1.7 0.001
alarm element
Delay of definite-time overexcitation
6 t_Alm_DefOvExc 0~9999.0s 0.1s
alarm element


Upper-limit multiple setting of
7 k0_InvOvExc 1.0~1.7 0.001
Inverse-time overexcitation element: n0
Delay corresponding to upper limit
8 t0_InvOvExc 0~9999.0s 0.1s
setting: t0
Multiple setting 1 of inverse-time
9 k1_InvOvExc 1.0~1.7 0.001
overexcitation protection: n1
Delay corresponding to multiple setting
10 t1_InvOvExc 0~9999.0s 0.1s
1: t1
11 k2_InvOvExc 1.0~1.7 0.001
12 t2_InvOvExc 0~9999.0s 0.1s
2: t2
13 k3_InvOvExc 1.0~1.7 0.001
14 t3_InvOvExc 0~9999.0s 0.1s
3: t3
15 k4_InvOvExc 1.0~1.7 0.001
16 t4_InvOvExc 0~9999.0s 0.1s
4: t4
17 k5_InvOvExc 1.0~1.7 0.001
18 t5_InvOvExc 0~9999.0s 0.1s
5: t5
19 k6_InvOvExc 1.0~1.7 0.001
20 t6_InvOvExc 0~9999.0s 0.1s
6: t6
21 k7_InvOvExc 1.0~1.7 0.001
22 t7_InvOvExc 0~9999.0s 0.1s
7: t7
23 k8_InvOvExc 1.0~1.7 0.001
24 t8_InvOvExc 0~9999.0s 0.1s
8: t8
Lower-limit multiple setting of
25 k9_InvOvExc 1.0~1.7 0.001
inverse-time overexcitation: n9.


Delay corresponding to lower-limit
26 t9_InvOvExc 0~9999.0s 0.1s
multiple setting: n9.
0:disable
29 En_Trp_DefOvExc 0, 1 definite-time overexcitation tripping
1:enable
element.
0:disable Logic setting of enabling definite-time
30 En_Alm_DefOvExc 0, 1
1:enable overexcitation alarm element.
0:disable
31 En_Trp_InvOvExc 0, 1 inverse-time overexcitation tripping
1:enable
element.
0:disable Logic setting of enabling inverse-time
32 En_Alm_InvOvExc 0, 1
1:enable overexcitation alarm element.
Tripping logic setting of overexcitation
33 TrpLog_OvExc 0000~FFFF
protection
0:disable VEBI setting of enabling overexcitation
34 VEBI_OvExc 0, 1
1:enable protection
NOTE: The conversion relation in case that the rated voltage of the transformer is not
consistent with that of VT is automatically and internally considered by the protection

equipment. Settings calculation is on the base of per unit value.
NOTE: User can set the location of the overexciation protection being equipped only
through PCS-PC software.
 Setting explanation for definite-time overexcitation protection
1. [k_DefOvExc1], [k_DefOvExc2]
These are settings of stage 1 and stage 2 of definite-time overexcitation protection respectively,
which are set as required.
2. [t_DefOvExc1], [t_DefOvExc2]
These are time delays of stage 1 and stage 2 of definite-time overexcitation protection respectively,
which are set as required
3. [k_Alm_DefOvExc]
This is setting of definite-time overexcitation alarm element, which is set as required.
4. [t_Alm_DefOvExc]
This is time delay of definite-time overexcitation alarm element, which is set as required.
5. [En_DefOvExc ]

This logic setting is used to enable or disable definite-time overexciation protection.
0”disable the protection; 1”enable the protection.
 Setting Explanation for inverse-time overexcitation protection
Inverse-time overexcitation protection is set with reference to the curve given by the transformer
manufactory.
The relation between all settings of inverse-time overexciation protection is:
[k_Alm_InvOvExc]<[k0_InvOvExc]<[k0_InvOvExc]<… <[k9_InvOvExc]
[t_Alm_InvOvExc]>[t0_InvOvExc]>[t1_InvOvExc]>… >[t9_InvOvExc]
1. [ki_InvOvExc] (i=0,1, … , 9)
These are settings of each section of inverse-time overexciation characteristeic curve
2. [ti_ InvOvExc] (i=0,1, … , 9)
These are time delays of each section of inverse-time overexciation characteristeic curve
3. [k_Alm_InvOvExc]
This is setting of inverse-time overexcitation alarm element.
4. [t_Alm_InvOvExc]
This is time delay of inverse-time overexcitation alarm element.
5. [En_Alm_InvOvExc ]
This logic setting is used to enable or disable definite-time overexciation for alarming.
0”disable the alarm element; 1”enable the alarm element.
6. [En_Trp_InvOvExc ]
This logic setting is used to enable or disable definite-time overexciation protection for tripping.
 Settings explanation for common settings of overexciation protection
1. [TrpLog_OvExc]
The tripping logic setting is used to specify which breakers will be tripped when overexcitation
details.
2. [VEBI_OvExc]
This setting is the VEBI setting of enabling overexcitation protection. Please refer to the setting
[VEBI_Diff] in section 3.2.5 for details.

Input signals of overexcitation protection are list in the following table.

1 EBI_OvExc Binary input of enabling overexcitation protection
No.1 item is binary inputs of enabling protective function
2 EBI_In_VT_HVS Binary input of enabling HV side VT in service.
3 EBI_In_VT_MVS Binary input of enabling MV side VT in service.
4 EBI_In_VT_LVS Binary input of enabling LV side VT in service.
No.4~No.6 items are binary inputs of enabling VT in service.
Output signals of overexcitation protection are list in following two tables.

1 Op_DefOvExc Definite-time overexcitation tripping element perates
2 Op_InvOvExc Inverse-time overexcitation tripping element operates
3 Alm_DefOvExc Definite-time overexcitation alarm element operates.
4 Alm_InvOvExc Inverse-time overexcitation alarm element operates.
Fault detector of definite-time overexcitation protection picks
5 FD_DefOvExc
up.
Fault detector of inverse-time overexcitation protection picks
6 FD_InvOvExc
up.
module.

1 U/f_DefOvExc Definite-time overexcitation ratio U/F.
2 U/f_InvOvExc Inverse-time overexcitation ratio U/F.
No.1 ~No.2 items are measured values for LCD display

3.6 Frequency Protection
 Fault detector of underfrequency protection
The pickup of this fault detector will enable underfrequency protection, which operation criterion is
as follows.
f <0.99 x Max([f_UF1], [f_UF2], [f_UF3], [f_UF4]) (Equation 3.6-1)
Where:
f is the measured system frequency.
[f_UF1], [f_UF2], [f_UF3] and [f_UF4] are the frequency settings of stage 1, stage 2, stage 3 and
stage 4 of underfrequency protection respectively.
 Fault detector of overfrequency protection
The pickup of this fault detector will enable overfrequency protection which operation criterion is as
follows.
f >1.01x Min([f_OF1], [f_OF2]) (Equation 3.6-2)
Where:
f is the measured system frequency.
[f_OF1] and [f_OF2] are the setting of stage 1 and stage 2 o frequency settings of overfrequency
protection respectively.
Operation criteria of underfrequency protection and overfrequency protection are shown in the
following two equations respectively, and the corresponding protection operates when one
operation criterion is met. Undervoltage blocking element is equipped to block overfrequency and
underfrequency protections when positive-sequence voltage is less than 30V.
 Operation criterion of underfrequency protection
f <[ f_UFn] (Equation 3.6-3)
Where:
f is system frequency.
[f_UFn] is the frequency settings of stage n (n=1, 2, 3 or 4) of underfrequency protection.
The equation of df/dt blocking function is as follows.
df / dt  [df/dt_UFn] (Equation 3.6-4)
Where:

df / dt is the frequency slip speed and the time step (i.e. dt ) for the calucation is equal to 5
cycle.
[df/dt_UF] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[En_df/dt_UFn] (n=1, 2, 3 or 4) is set as “1”, when (Equation 3.6-3) and (Equation 3.6-4) are met, it
is decided that a fault occurred and the corresponding stage underfrequency protection is blocked
at the same time for the purpose of waiting for operation of other related protection. The blocking
signal will not reset until the system frequency recovers, i.e. the system frequency is greater than
the setting [f_Recov]. If the logic setting is set as “0”, when (Equation 3.6-3) and (Equation 3.6-4)
are met, the stage underfrequency protection will be released to operate.
 Operation criterion of overfrequency protection
f >[ f_OFn] (Equation 3.6-5)
Where:
[f_OFn] is the frequency setting of stage n (n=1, or 2) of overfrequency protection.

3.6.3 Logic Scheme
[EBI_In_VT_XXX]
&
[En_In_VT_XXX]
[EBI_FreqProt]
[VEBI_FreqProt] &
& [t_OFn]
[En_UFn] [Op_OFn]
f > [f_OFn]
Flg_UnderVolt
Flg_FD_OF
[EBI_In_VT_XXX]
&
[En_In_VT_XXX]
[EBI_FreqProt]
[VEBI_FreqProt] &
[En_UFn] [t_UFn]
& [Op_UFn]
f < [f_UFn]
Flg_UnderVolt
Flg_FD_UF
-df/dt≥[df/dt_UF]
&
[En_df/dt_UFn]
Figure 3.6-1 Logic diagram of frequency protection
Where:
[EBI_In_VT_XXX] is the binary input of enabling VT of XXX (XXX= HVS, MVS or LVS) side into
service.
[En_In_VT_XXX] is the logic setting of enabling VT of XXX (XXX= HVS, MVS or LVS) side into
service.
[EBI_FreqProt] is the binary input of enabling frequency protection.
[VEBI_FreqProt] is the VEBI setting of enabling frequency protection.
[En_UFn] is the logic setting of enabling stage n (n=1, or 2) underfrequency protection.
[En_OF] is the logic setting ofenabling overfrequency protection.
[f_UFn] is the frequency setting of stage n (n=1, 2, 3 or 4) of underfrequency protection.
[f_OFn] is the frequency setting of stage n (n=1 or 2) overfrequency protection.

[t_UFn] is the delay of stage n (n=1, 2, 3 or 4) of underfrequency protection.
[t_OFn] is the time delay n (n=1 or 2) of overfrequency protection.
[Op_UFn] is the operation flag of stage n (n=1, 2, 3 or 4) of underfrequency protection.
[Op_OFn] is the operation flag of stage n (n=1 or 2) overfrequency protection.
Flg_UnderVolt is the internal flag indicating that undervoltage blocking element pickus up, which
means that the positive-sequence voltage is less than 30V.
df/dt is the frequency slip speed.
[df/dt_UF] is the setting of df/dt blocking underfrequency protection..
[En_df/dt_UFn] is the logic setting of enabling stage n (n=1, 2, 3 or 4) of underfrequency

protection being controlled by slip.
Flg_FD_UF is the internal flag indicating that the fault detector of underfrequency protection picks
up.
Flg_FD_OF is the internal flag indicating that the fault detector of overfrequency protection picks
up.
3.6.4 Setting
Table 3.6-1 Settings of frequency protection

Lowest frequency threshold of fault
1 f_Recov 40~70Hz 0.01Hz
recovery.
2 df/dt_UF 0.05~20Hz/s 0.01Hz/s Setting of df/dt blocking UF protection.
3 f_UF1 40~70Hz 0.01Hz Frequency setting of UF stage 1.
4 t_UF1 0.1~6000s 0.001s Time delay of UF stage 1.
0:disable Logic setting of enabling/disabling UF
5 En_UF1 0, 1
1:enable stage 1.
0:disable Logic setting of enabling/disabling df/dt
6 En_df/dt_UF1 0,1
1:enable blocking function for UF stage 1.
7 TrpLog_UF1 0000~FFFF Tripping logic setting of UF stage 1.
10 En_UF2 0, 1
1:enable stage 2.
11 En_df/dt_UF2 0,1


15 En_UF3 0, 1
1:enable stage 3.
16 En_df/dt_UF3 0,1
20 En_UF4 0, 1
1:enable stage 4.
21 En_df/dt_UF4 0,1
Frequency setting of stage 1 of OF
23 f_OF1 40~70Hz 0.01Hz
protection.
24 t_OF1 0.1~6000s 0.001s Time delay of stage 1 of OF stage 1.
0:disable Logic setting of stage 1 of
25 En_OF1 0, 1
1:enable enabling/disabling OF protection.
26 TrpLog_OF1 0000~FFFF Tripping logic setting of OF stage 1.
27 f_OF2 40~70Hz 0.01Hz Frequency setting of OF stage 2.
28 t_OF2 0.1~6000s 0.001s Time delay of OF stage 2.
0:disable Logic setting of enabling/disabling OF
29 En_OF2 0, 1
1:enable stage 2.
30 TrpLog_OF2 0000~FFFF Tripping logic setting of OF stage 2.
0:disable VEBI setting of enabling/disabling
31 VEBI_FreqProt 0, 1
1:enable frequency protection.
1. [f_Recov]
The setting is the lowest frequency threshold of fault recovery, i.e. the recognized normal level of
frequency after a fault is eliminated.
After some stage of underfrequency protection is blocked by df/dt, the stage underfrequency
protection will not be released to operate unless that system frequency increases to be greater than
the setting [f_Recov].
Recommended value: 0.95~0.99* f n ( f n is the system rated frequency)
2. [ df/dt_UF]

The setting of df/dt blocking underfrequency protection is set to avoid the underfrequency
protection operating during a short-circuit fault. When the variation of system frequency is greater
than the setting, some stage of underfrequency protection can be blocked if the corresponding
logic setting of the stage protection is enabled.
Recommended value: 5~6Hz/s
3. [f_UFX] (X=1, 2, 3, 4)
This is the frequency setting of stage X (X=1, 2, 3, 4) of underfrequency protection, which should
be set according to system frequency and stability control strategy.
4. [t_UFX] (X=1, 2, 3, 4)
This is the time delay of stage X (X=1, 2, 3, 4) of underfrequency protection, which should be set
according to system frequency and stability control strategy.
5. [En_UFX] (X=1, 2, 3, 4)
This is the logic setting of enabling stage X (X=1, 2, 3, 4) of underfrequency protection, which
should be set according to the actual number of load shedding stage.
6. [En_df/dt_UFX] (X=1, 2, 3, 4)
This is the logic setting of enabling stage X (X=1, 2, 3, 4) of underfrequency protection being
blocking by df/dt, which should be set according to requirements.
7. [TrpLog_UFX] (X=1, 2, 3, 4)
The tripping logic setting is used to specify which breakers will be tripped when stage X (X=1, 2, 3,
4) of underfrequency protection of some side operates. Please refer to the description of the
setting [TrpLog_Diff] in section 3.2.5 for details.
8. [f_OFX] (X=1, 2)
This is the frequency setting of stage X (X=1, 2) of overfrequency protection, which should be set
9. [t_OFX] (t=1, 2)
This is the time delay of stage X (X=1, 2) of overfrequency protection, which should be set
10. [En_OFX] (X=1, 2)

This is the logic setting of enabling stage X (X=1, 2) of overfrequency protection, which should be
set according to the actual number of generator rejection stage.
11. [TrpLog_OFX] (X=1, 2)
The tripping logic setting is used to specify which breakers will be tripped when stage X (X=1, 2) of
overfrequency protection of some side operates. Please refer to the description of the setting
[TrpLog_Diff] in section 3.2.5 for details.
12. [VEBI_FreqProt]
This setting is the VEBI setting of enabling frequency protection. Please refer to the setting

Input signals of frequency protection are list in the following table.

1 EBI_FreqProt Binary input of enabling frequency protection
No.1 item is binary input of enabling protective function
Output signals of frequency protection are list in following two tables.

1 Op_UF1 Stage 1 of underfrequency protection operates.
5 Op_OF1 Stage 1 of overfrequency protection operates.
6 Op_OF2 Stage 1 of overfrequency protection operates.
7 FD_UF Fault detector of underfrequency protection picks up.
8 FD_OF Fault detector of overfrequency protection picks up.
module.

1 f System frequency
No.1 is measured value for LCD display
3.7 Mechanical Protection

Mechanical protection without fault detector will operates after a delay if a mechanical signal
reaches the relay.

3.7.2 Logic Scheme
Figure 3.7-1 Logic diagram of mechanical protection
Where:
[EBI_MR] is the binary input of enabling mechanical protection.
[VEBI_MR] is the VEBI setting of enabling mechanical relay.
[BI_MRn] is the binary input of mechancia signal n (n=1, 2, 3, or 4).
[Op_MRn] is the operation flag of MRn (n=1, 2, 3 or 4) mechanical protection.
3.7.3 Setting
Table 3.7-1 Settings of mechanical protection

1 t_MR1 0~6000s 0.001s Time delay of MR1 mechanical protection.
0:disable Logic setting of enabling/disabling MR1
2 En_MR1 0, 1
1:enable mechanical protection.
Tripping logic setting of MR1 mechanical
3 TrpLog_MR1 0000~FFFF
protection.
5 En_MR2 0, 1
protection.
8 En_MR3 0, 1
protection.
10 t_MR4 0~6000s 0.001s Time delay of MR4 mechanical protection
11 En_MR4 0, 1
protection.
13 VEBI_MR 0, 1 0:disable VEBI setting of enabling mechanical


1:enable protection.
NOTE: Before mechanical protection is put into service, input signals for the logic module
of mechanical protection should be configured through PCS-PC software. In order to

ensure the reliability of the mechanical protection, high-power repeater relay modules
should be equipped to avoid the maloperation of the protection due to all kinds of
interference. Input signals for the logic module of mechanical protection are recommended
to be adopted from high-power repeater relay module, and if those input signals are from
normal binary inputs module, the denouncing time of binary input must be set great
enough and generally greater than one and a half cycle.
1. [t_MRX] (X=1, 2, 3, 4)
This is the time delay of MRX (X=1, 2, 3, 4) mechanical protection for tripping. If the function of
tripping with time delay is not needed the setting can be set as “0”.
2. [En_MRX] (X=1, 2, 3, 4)
This is the tripping logic setting of enabling MRX mechanical protection to trip.
3. [TrpLog_MRX] (X=1, 2, 3, 4)
The tripping logic setting is used to specify which breakers will be tripped when stage X (X=1, 2, 3,
4) of mechanical protection operates. Please refer to the description of the setting [TrpLog_Diff] in
section 3.2.5 for details.
4. [VEBI_MR]
This setting is the VEBI setting of enabling mechanical protection. Please refer to the setting
[VEBI_Diff] in section 3.2.5 for details
Input signals of mechanical protection are list in the following table.

1 EBI_MR Binary input of enabling mechanical protection
No.1 item is binary input of enabling protective function
2 BI_MR1 Binary input of MR1 mechanical signal.
No.2~No.5 items are binary inputs of mechanical signals.
Output signals of mechanical protection are list in following two tables.


1 Op_MR1 MR1 mechanical protection operates.
5 FD_MR1 Fault detector of MR1 mechanical protection picks up.
module.
3.8 Impedance Protection
Three impedance protection elements of HV, MV, and LV sides are provided with totally same
configuration.
Fault detector of impedance protection includes the fault detector of DPFC phase-to-phase current
and the fault detector of negative-sequence current. Impendence protection will be enabled for
500 ms if any fault detector picks up to enable impedance protection and will keep be enabled if
phase-to-phase or phase-to-earth impedance relay operates.
3.8.1.1 Fault Detector of DPFC Phase-to-phase Current
I 1.25I t I th (Equation 3.8-1)
Where:
It is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold voltage is
slightly greater than the unbalance voltage, multiple 1.25 of the deviation component is
reasonable.
I is the half-wave calculated of phase-to-phase current.
I th is the fixed threshold of 0.2 In and does not need to be set on site.

3.8.1.2 Fault Detector of Negative-sequence Current
I 2 0.2In (Equation 3.8-2)
Where:
I 2 is the negative-sequence current of some side.
In is the secondary rated current of CT.

Impedance protection consists of phase-to-phase impedance protection and phase-to-earth
protection. CT polarity of each side is at busbar side, and directions of settings are based on this
polarity.
3.8.2.1 Phase-to-Phase Impedance Protection
Following figure shows operating characteristic of phase-to-phase impedance relay with reach
angle 78º. In this figure, Zn is the reverse impedance setting (pointing to system direction) and
Zp is the forward impedance setting (pointing to transformer direction).
jx
Zp
m
R
Zn
Figure 3.8-1 Operating characteristic of phase-to-phase impedance relay
Operation criterion of phase-to-phase impedance relay is as follows.

 
(U I Z P )
90 Arg

 
270 (Equation 3.8-3)
(U I Zn )
3.8.2.2 Phase-to-Earth Impedance Protection
Following figure shows operating characteristic of phase-to-earth impedance relay with reach
angle 78º. In this figure, Zn is the reverse impedance setting (pointing to system direction) and
Zp is the forward impedance setting (pointing to transformer direction).

jx
Zp
m
R
Zn
Figure 3.8-2 Operating characteristic of phase-to-earth impedance relay
Operation criterion of phase-to-phase impedance relay is as follows.
 
U ( I k * 3I 0 ) ZP
90Arg  
270  (Equation 3.8-4)
U( I k * 3I 0 )Z n
Where:
z z
k  0 1 is the zero-sequence compensation coefficient (i.e. setting [K0_ZPE_HVS ]) and
3z1
recommended value is 0~2. “k”is generally 0.6 if protection direction points to local busbar, and “k”
is 0~0.1, if protection direction points to transformer.
3.8.2.3 Power Swing Blocking Releasing (PSBR)
PCS-978 adopts releasing power swing blocking to avoid maloperation of distance protection
resulting from power swing. In another word,in order to avoid unwanted operation of impedance
relay during system oscillation, the protection is blocked all along under the normal condititon and
power swing. Only if fault (internal fault or power swing with internal fault) is detected, power swing
blocking for distance protection is released by PSBR element.
There is a logic setting [En_PSBR_Ctrl_Z] to enable or disable PSBR function. If it is set as “1”
then, the PSBR function is enabled. Otherwise, i t is disabled.
Power swing blocking for distance element will be released if any of the following PSBR elements
operate.
 Fault detector PSBR element (FD PSBR)
 Unsymmetrical fault PSBR element (UF PSBR)
 Symmetrical fault PSBR element (SF PSBR)
1. Fault detector PSBR element
If any of the following condition is matched, FD PSBR will operate for 160ms.

1) Positive sequence overcurrent element with setting higher than maximum load current does
not operate before one of the fault detectors of backup protection operates.
2) Positive sequence overcurrent element with setting higher than maximum load current not
operates before one of the fault detectors of backup protection operates, but the duration is less
than 10ms.
2. Unsymmetrical fault PSBR element
The operation criterion:
I 0  I 2 m  I1 (Equation 3.8-5)
The “m”is a internal fixed coefficient which can ensure UF PSBR operate during power swing with
internal unsymmetrical fault, while not operate during power swing or power swing with external
fault
3. Symmetrical fault PSBR element
If a three-phase fault occurs and FD PSBR is invalid (160ms after GFD operates), neither FD
PSBR nor UF PSBR will be able to operate to release the distance protection. Thus, SF PSBR is
provided for this case specially. This detection is based on measuring the voltage at power swing
center:
UOS U1 cos  (Equation 3.8-6)
Where:
: the angle between positive sequence voltage and positive sequence current
U1 : the positive sequence voltage
The criterion of SF PSBR element comprises the following two parts:
1) when 0.03U N U OS 0.08U N , the SF PSBR element will operate after 150ms.
2) when 0.1U N U OS 0.25U N , the SF PSBR element will operate after 500ms.
NOTE: If time delay of impedance protection is more than 1.5 s, PSBR function is not
needed for the impendence protection.
3.8.2.4 Influence of VT Circuit Failure and VT Out of Service on Impedance Protection
When VT circuit failure is detected, the impedance protection will be disabled automatically.
When VT of one side is maintained or bypass circuit breaker is closed with its relevant VT having
not been switched on, in order to avoid unwanted operation of impedance protection of this side,

the binary input [EBI_In_VT_XXX] (XXX represents HVS, MVS or LVS) shall be de-energized and
impedance protection is disabled automatically.
3.8.3 Logic Scheme
Logic scheme of phase-to-earth impedance protection is same to that of phase-to phase

impedance protection, and stage 1 of phase-to-phase impendance protection at HV side is taken
as an example to show below.
Figure 3.8-3 Logic diagram of stage 1 of phase-to-phase impedance protection
Where:
Flg_Pkp_PSB is the internal flag indicating that power swing blocking releasing element picks up.
Flg_Op_ZPP1_HVS is the internal flag indicating that stage 1 of phase -to-phase impendence
protection of HV side satisfies the operation criterion.
Flg_VTS_HVS is internal flag indicating that VT supervision program detects VT circuit failure
HVS:[En_PSBR_ZPP1] is the logic setting of enabling power swing blocking releasing element to
control stage 1 of phase-to-phase impendence protection of HV side.
[EBI_Z_HVS] is the binary input of enabling impeddance protection of HV side.
[VEBI_Z_HVS] is the VEBI setting of enabling impeddance protection of HV side.
HVS:[En_ZPP1] is the logic setting of enabling stage 1 of phase-to-phase impendence protection

of HV side.
[EBI_In_VT_HVS] is the binary input of enabling VT of HV side into service.
[En_In_VT_HVS] is the logic setting of enabling VT of HV side into service.
[En_Bak_HVS] is the logic setting of enabling all the backup protections of HV side.
Flg_FD_Z_HVS is the operation of the fault detector of DPFC phase-to-phase current or that of
negative-sequence current of HV side, which are used to enable impendence protection.
HVS:[t_ZPP1] is the time delay of stage 1 of phase-to-phase impendence protection of HV side.
[Op_ZPP1_HVS] is the operation of stage 1 of phase-to-phase impendence protection of HV side

3.8.4 Setting
Table 3.8-1 Settings of impedance protection (HVS, MVS, LVS)

Forward impedance setting of stage 1 of
1 ZPP1_Fwd 0~200Ω 0.01Ω
phase-to-phase impedance protection
Reverse impedance setting of stage 1 of
2 ZPP1_Rev 0~200Ω 0.01Ω
Time delay of stage 1 of phase-to-phase
3 t_ZPP1 0~20s 0.001s
impedance protection
Logic setting of enabling/disabling stage 1
0: disable
4 En_ZPP1 0, 1 of phase-to-phase impedance
1: enable
protection
0000~ Tripping logic setting of stage 1 of
5 TrpLog_ZPP1
FFFF phase-to-phase impedance protection
6 ZPP2_Fwd 0~200Ω 0.01Ω
7 ZPP2_Rev 0~200Ω 0.01Ω
Time delay of stage 2 of phase-to-phase
8 t_ZPP2 0~20s 0.001s
0: disable
9 En_ZPP2 0, 1 of phase-to-phase impedance
1: enable
protection
10 TrpLog_ZPP2
FFFF phase-to-phase impedance protection
11 ZPE1_Fwd 0~200Ω 0.01Ω
phase-to-earht impedance protection
12 ZPE1_Rev 0~200Ω 0.01Ω
phase-to-earth impedance protection
Time delay of stage 1 of phase-to-earth
13 t_ZPE1 0~20s 0.001s
0: disable Logic setting of enabling/disabling stage 1
14 En_ZPE1 0, 1
1: enable of phase-to-earth impedance protection
15 TrpLog_ZPE1
FFFF phase-to-earth impedance protection
16 ZPE2_Fwd 0~200Ω 0.01Ω
phase-to-earht impedance protection
17 ZPE2_Rev 0~200Ω 0.01Ω
phase-to-earth impedance protection


Time delay of stage 2 of phase-to-earth
18 t_ZPE2 0~20s 0.001s
0: disable Logic setting of enabling/disabling stage 2
19 En_ZPE2 0, 1
1: enable of phase-to-earth impedance protection
20 TrpLog_ZPE2
FFFF phase-to-earth impedance protection
21 K0_ZPE 0~2 0.01 zero-sequence compensation coefficient
Logic setting of enabling power swing
0: disable
22 En_PSBR_Ctrl_Z 0, 1 blocking releasing function to control
1: enable
VEBI_Z_XXX
VEBI setting of enabling impedance
23 (XXX=HVS, MVS, 0, 1
protection of the corresponding side
LVS）
NOTE: When current protection fails to satisfy the sensitivity requirement or follow the
coordination requirement between power girds, impedance protection can be used as the
backup protection of transformer. The impedance protection provided by PCS-978 is plain
impedance relay and its positive and reverse impedance values can be set independently.
1. [ZPPn_Fwd], [ZPEn_Fwd] (n=1, 2)
The two settings are positive impedance settings of the stage n of phase-to-phase and
phase-to-earth impedance protections respectively, and the protection direction of the positive
impedance setting points to a transformer.
If impedance protection is used for protecting transformer, the following conditions as below can
be included:
Based on that there is the enough sensitivity for the fault at the opposite side busbar, the following
formula can be get：
Zop K sen Zt
Where:
Ksen is sensitivity coefficient, and it is 1.3 generally.
Zt is the secondary impedance value of the transformer.
Based on coordination with the outgoing line of opposite side, the following formula can be get:
Zop 0.7Zt 0.8Kinf Z
Where:
Zt is the secondary impedance value of the transformer.
Kinf is the infeed coefficient and shall be the minimum value under various operation modes.

Z is the setting value of coordination stage of line protection.

If impedance protection is used for protecting system, it is suggested to be set as 5%-10% reverse
impedance.
2. [ZPPn_Rev]，[ZPEn_Rev] (n=1,2)
The two settings are reverse impedance settings of the stage n of phase-to-phase and
phase-to-earth impedance protections respectively, and the protection direction of the positive
impedance setting points to the system.
If impedance protection is used for protecting transformer, it is suggested to be set as 5%-10%
positive impedance. The setting value shall be smaller than the operation value at stage 1 of
impedance protection of the shortest outgoing line from the busbar on the local side.
If impedance protection is used for protecting system, it shall be set according to the zone to be
protected and it also can be in coordination with the adjacent line.
Z op K rel K inf Z
Wherein, Krel is the reliability coefficient and can be 0.8.

Kinf is infeed coefficient and shall be the minimum value under various operation modes.
Z is the setting value of coordination stage of line protection.
3. [t_ZPPn]，[t_ZPEn] (n=1,2)
The two settings are time delays of the stage n of phase-to-phase and phase-to-earth impedance
protections respectively.
tmax + t
t=
Where:
t max is the maximum operation time of line protection.
t is time differential and can be 0.3s~0.5s.

If such coordination is not required, t=0.5s~1s is proper.
If multi-stage impedance protection is used, the time differential between stages can be
t =0.3s~0.5s.
If the power swing blocking releasing function equipped on this device is not used, then the time
delay shall be set greater than the period of power swing and more than 1.5s generally.
4. [En_ZPPn], [En_ZPEn] (n=1, 2)
The two settings are is logic setting of enabling stage n of phase-to-phase and phase-to-earth
impedance protection respectively, which shall be set as required.
“0”: disable the stage protection. “1”: enable the stage protection.
5. [K0_ZPE]]
This is the zero-sequence compensation coefficient used by phase-to-ground impedance.

If impedance protection is used for protecting transformer, the recommended value is 0. If
impedance protection is used for protecting system, it shall be set according to the actual
compensation coefficient and the recommended setting value is 0.6.
6. [En_PSBR_Ctrl_Z]

This is the logic setting of enabling power swing blocking releasing function.
“0”: disable the function; “1”: enable the function.
When the time delay of impedance protection can not be set greater than the period of power
swing, it is suggested that power swing blocking releasing function shall be enabled. , and the
recommended value is 1.
7. [TrpLog_ZPPn], [TrpLog_ZPEn] (n=1, 2)
These tripping logic settings are used to specify which breakers will be tripped when stage n of
phase-to-phase or phase-to-earth impedance protection operates. Please refer to the description
of the setting [TrpLog_Diff] in section 3.2.5 for details.
8. [VEBI_Z_XXX] (XXX=HVS, MVS, LVS)
This setting is the VEBI setting of enabling impedance protection. Please refer to the setting
Input signals of impedance protection are list in the following table.

1 EBI_Z_HVS Binary input of enabling impedance protection of HV side.
2 EBI_Z_MVS Binary input of enabling impedance protection of MV side.
3 EBI_Z_LVS Binary input of enabling impedance protection of LV side.
No.4~No.6 items are binary inputs of enabling protective function.
Output signals of impedance protections of HV, MV and LV sides are list in the following table.

Stage 1 of phase-to-phase impedance protection of HV side
1 Op_ZPP1_HVS
operates.
Stage 2 of phase-to-phase impedance protection of HV side
2 Op_ZPP2_HVS
operates.
Stage 1 of phase-to-earth impedance protection of HV side
3 Op_ZPE1_HVS
operates.
Stage 2 of phase-to-earth impedance protection of HV side
4 Op_ZPE2_HVS
operates.
5 Op_ZPP1_MVS Stage 1 of phase-to-phase impedance protection of MV side


operates.
Stage 2 of phase-to-phase impedance protection of MV side
6 Op_ZPP2_MVS
operates.
Stage 1 of phase-to-earth impedance protection of MV side
7 Op_ZPE1_MVS
operates.
Stage 2 of phase-to-earth impedance protection of MV side
8 Op_ZPE2_MVS
operates.
Stage 1 of phase-to-phase impedance protection of LV side
9 Op_ZPP1_LVS
operates.
Stage 2 of phase-to-phase impedance protection of LV side
10 Op_ZPP2_LVS
operates.
Stage 1 of phase-to-earth impedance protection of LV side
11 Op_ZPE1_LVS
operates.
Stage 2 of phase-to-earth impedance protection of LV side
12 Op_ZPE2_LVS
operates.
13 FD_Z_HVS Fault detector of impedance protection of HV side picks up.
14 FD_Z_MVS Fault detector of impedance protection of MV side picks up.
15 FD_Z_LVS Fault detector of impedance protection of LV side picks up.
module.
3.9 Phase Overcurrent Protection (OC)
The function of phase overcurrent protection for transformer is to avoid some physical damages to
the transformer when an external fault occurs with a long-term through fault current. The
directional element is to select protection direction to protect transformer or system. The voltage
control element can improve the sensitivity of overcurrent protection without considering some
special conditions like the motor self-starting process, so the operating threshold setting of
overcurrent protection could be lower properly.
Four phase overcurrent protection elements of HV, MV, and LV sides and common winding (CW)
are provided with totally same configuration, which can be controlled by directional element and
voltage control element and be blocked by harmonic blocking element by configuring
corresponding logic settings.
 Fault detector for definite-time overcurrent protection
Criteria:

I _ max >0.95x Min([I_OC1], [I_OC2],[I_OC3], [I_OC4]) (Equation 3.9-1)
Where:
I _ max is the maximum value of three-phase current of one side.
[I_OC1], [I_OC2], [I_OC3] and [I_OC4] are respectively the current settings of stage 1, stage 2,
stage 3 and stage 4 of definite-time overcurrent protection of the corresponding side.
The pickup of this fault detector will enable definite-time overcurrent protection of corresponding
side.
 Fault detector for inverse-time overcurrent protection
When phase current of one side is greater than base current setting [I_OCn] （n=1, 2, 3 or 4）, the
fault detector picks up to enable stage n (n=1, 3, 4 or 4) of inverse-time overcurrent protection at
relevant side.
There are four stages of overcurrent protection are equipped for each side of transformer, which
can be definite-time or inverse-time overcurrent protection by configuring the logic setting XXX:
[Opt_Characteristic_OCn] (XXX represents HVS, MVS, LVS, CW; n=1, 2, 3, 4) “0”for definite-time
overcurrent protection , and “1”for inverse-time overcurrent protection.
3.9.2.1 Definite-Time Overcurrent Protection
Operation criterion of definite-time overcurrent protection is as follows.
I _ max > [I_OCn] (Equation 3.9-2)
Where:
I _ max is the maximum value of three phase-current of some side.
[I_OCn] is the setting of stage n (n=1, 2, 3, or 4) of overcurrent protection of the corresponding

side.
3.9.2.2 Inverse-Time Overcurrent Protection
Inverse delay characteristics (IDMT) defined in IEC60255-3 are adopted, which formula is shown
as follows.
Kt
t (I )  Tp
I  (Equation 3.9-3)
( ) 1
Ip
Where :

I p is base current (also called current limit), i.e. setting [I_OCn] (n=1, 2, 3 or 4).
Tp is base time, i.e. setting [k_BaseTime_InvOCn] (n=1, 2, 3 or 4).
Kt is time multiplier, i.e. setting [k_TimeMult_InvOCn] (n=1, 2, 3 or 4).
 is exponent, i.e. setting [k_Exponent_InvOCn] (n=1,2, 3 or 4)

I is actual value of measured phase current.
User can get different inverse delay characteristic curves by configuring above settings, and four
common inverse delay characteristics with parameters are list in the following table.
Table 3.9-1 Inverse delay characteristic parameters
Inverse Delay Curve  Kt
Standard Inverse 0.02 0.14

Very Inverse 1 13.5
Extremely Inverse 2 80
Long Time Inverse 1 120
3.9.2.3 Voltage Control Element (VCE)
 Operation criterion of VCE
The voltage control element will pickup if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is greater than its setting.
Criteria:
U  < [Vpp_UV_VCE] or U 2  [V_NegOV_VCE] (Equation 3.2-3)
Where:
U  is the phase-to-phase voltage of some side.
U 2 is the negative-sequence voltage of some side.
[Vpp_UV_VCE] is the setting of undervoltage element.
[V_NegOV_VCE] is the setting of negative-sequence overvoltage element.
Voltage of other side can be used as the input of voltage control element, and there are logic
settings used to select which side voltage control element to control OC protection of some side.
 OC being controlled by VCE of local side
The logic setting [En_VCE_Ctrl_OCn] (n=1, 2, 3, 4) is used to select which stage overcurrent

protection is controlled by local voltage control element. For example, if setting HVS:
[En_VCE_Ctrl_OC1] is set as “1”, stage 1 overcurrent protection of HV side will be controlled by
the voltage control element of HV side. Otherwise it will not.
3.9.2.4 Directional Element (DE)
Positive sequence voltage with memory is used in directional element. There is no dead zone for
directional element during close-in three-phase short circuit fault due to its memory function. The
directional relay is connected in the naught degree mode. The polarity of CT connected to
protection equipment is shown in the application scheme figure, and the positive polarity of CTs of
each side shall be at the side near busbar.
Protection direction of each stage of overcurrent protection can be set respectively by the logic
setting [Opt_Dir_Ctrl_OCn] (n=1, 2, 3, 4). If the setting is set as “1”, its direction is to protect
transformer and reach angle is 45º, and if the setting is set as “2”, its direction is to protect power
system and reach angle is 225º. If this setting is set as “0”, the corresponding stage of the
protection is not controlled by directional element. The operating characteristic is shown in the
following figure in which the shadow zone is the operation zone of the directional element.
Operation criteria of directional element are as follows, when protection direction is to protect
transformer.
Phase A: -45°<arg(U1)-arg(Ia)<135°
Phase B: -165°<arg(U1)-arg(Ib)<15° (Equation 3.9-4)
Phase C: 75°<arg(U1)-arg(Ic)<-255°
Operation criteria of directional element are as follows, when protection direction is to protect
power system.
Phase A: 135°<arg(U1)-arg(Ia)<315°
Phase B: 15°<arg(U1)-arg(Ib)<195° (Equation 3.9-5)
Phase C: -105°<arg(U1)-arg(Ic)<75°
Where:
U1 is positive sequence voltage of calculated side.
Ia, Ib, Ic are three phase currents of calculated side.

Ul Ul
φlm=45°
φlm =225°
a) Direct to transformer b) Direct to power system
Figure 3.9-1 Operating characteristic of phase-to-phase directional relay
NOTE: The protection direction mentioned above is based on that the positive polarity of
CT is at the side of busbar. Otherwise actual protection direction is not consistent to that
mentioned above.
3.9.2.5 Influence of VT Circuit Failure and VT Out of Service on VCE and DE
Voltage control element and directional element both picks up to release overcurrent protection
when VT circuit failure is distinguished, which means voltage controlled directional overcurrent
protection becomes overcurrent protection without any control element.
not been switched on, in order to ensure correct operation of voltage controlled directional
overcurrent protection, the binary input [EBI_In_VT_XXX] (XXX represent HVS, MVS or LVS)
should be de-energized. Then voltage control element and directional element both pick up to
release overcurrent protection which becomes overcurrent protection without any control element.
3.9.2.6 Harmonic Blocking Element
The equipment has harmonic blocking functions. When the following operation equation is
satisfied, harmonic blocking element picks up to block overcurrent protection.
I 2 nd K 2 xb * max( I1st , 0.3In) (Equation 3.9-6)
Where:
I2 nd is secondary harmonic of phase current.
I1 st is fundamental component of phase current.
K2 xb is harmonic blocking coefficient, i.e. the setting [k_Harm_Blk_OC].
3.9.3 Logic Scheme
Logic schemes of overcurrent protection of each side are same, and that of HV side is taken as an

example to show the logic diagram.
3.9.3.1 Logic Scheme of Voltage Control Element
Logic schemes of voltage control element of each side are same, and that of HV side is taken as
an example to show the logic diagram.
U _ min
U2
Figure 3.9-2 Logic diagram of voltage control element
Where:
U _ min is the minimum value of phase-to-phase voltages of HV side.
U 2 is negative-sequence voltage of HV side.
[EBI_In_VT_HVS] is the binary input of enabling HV side VT in service.
[En_In_VT_HVS] is the logic setting of enabling HV side VT in service.
HVS:[Vpp_UV_VCE] is the setting of undervoltage element for controlling HV side OC.
HVS:[V_NegOV_VCE] is the setting of negative-sequence overvoltage element for controlling HV

side OC.
Flg_VTS_HVS is the internal flag indicating that VT circuit failure of HV side is distinguished.
Flg_Pkp_VCE_HVS is the internal flag indicating that the local VCE for controlling OC of HV side
picks up.
3.9.3.2 Logic Scheme of Directional Element
Figure 3.9-3 Logic diagram of directional element
Where:
Flg_Direction_OC_HVS is the internal flag indicating that DE decides the fault is in the protection
direction of overcurrent protection of HV side.

Flg_Pkp_DE_HVS is the internal flag indicating that DE of HV side picks up.
Please refer to the above section for other symbols.
3.9.3.3 Logic Scheme of Definite-Time Overcurrent Protection
I  _ max
Figure 3.9-4 Logic diagram of definite-time overcurrent protection
Where:
Flg_Pkp_VCE_HVS is the internal flag indicating that the local VCE for controlling HV side OC
protection picks up.
HVS:[En_VCE_Ctrl_OCn] is the logic setting of enabling VCE to control stage n (n=1, 2, 3 or 4) of

OC protection of HV side.
Flg_Pkp_DE_HVS is the internal flag indicating that directional element of HV side picks up.
HVS:[Opt_Dir_Ctrl_OCn] is the logic setting of selecting control mode of directional element to

stage n (n=1, 2, 3 or 4) of OC protection of HV side, “0”for not control OC, “1”for protecting
transformer, and “2”for protecting system.
HVS:[Opt_Characteristic_OC n] is the logic setting of selecting characteristic of stage n (n=1, 2, 3

or 4) of OC protection, “0” for definite-time overcurrent protection and “1” for inverse-time
overcurrent protection.
I _ max is the maximum value of three-phase current of HV side.
HVS:[I_OCn] is the setting of stage n (n=1, 2, 3 or 4) of definite-time overcurrent protection of HV

side.
[EBI_OC_HVS] is the binary input of enabling OC protection of HV side.
[VEBI_OC_HVS] is the VEBI setting of enabling OC protection of HV side.
HVS:[En_OCn] is the logic setting of enabling stage n (n=1, 2, 3 or 4) of OC protection of HV side.
Flg_FD_DefOC_HVS is the operation of the fault detector of definite-time OC protection of HV

side.
HVS:[t_DefOCn] is the time delay of stage n (n=1, 2, 3 or 4) of definite-time OC protection of HV

side.
[Op_OCn_HVS] is the operation flag of stage n (n=1, 2, 3 or 4) of OC protection of HV side.
3.9.3.4 Logic Scheme of Inverse-Time Overcurrent Protection
HVS:[En_Harm_Blk_OCn]
≥1
Flg_Pkp_Harm_HVS
HVS:[En_VCE_Ctrl_OCn]
≥1
Flg_Pkp_VCE_HVS
HVS:[Opt_Dir_Ctrl_OCn]=0
≥1 & [ Op_OCn_HVS]
Flg_Pkp_DE_HVS
I  _ max >HVS:[I_OCn]
[EBI_OC_HVS]
&
[VEBI_OC_HVS]
HVS:[En_OCn]
HVS:[Opt_Characteristic_OCn]=1
Flg_FD_InvOC_HVS
Figure 3.9-5 Logic diagram of inverse-time overcurrent protection
Where:
HVS:[I_OCn] is the base current setting of stage n (n=1, 2, 3 or 4) of inverse-time overcurrent

Flg_FD_InvOC_HVS is the operation of the fault detector of inverse-time OC protection of HV

side.
Please refer to above sections for detailed descriptions of each symbol.
3.9.4 Setting
3.9.4.1 Setting List
Table 3.9-2 Settings of overcurrent protection (HVS, MVS, LVS, CW)

Setting of undervoltage control
1 Vpp_UV_VCE 2~110V 0.01V
element for OC protection
Setting of negative-sequence
2 V_NegOV_VCE 2~110V 0.01V voltage control element for OC
protection.
Harmonic blocking coefficient of OC
3 k_Harm_Blk_OC 0.05~0.35 0.01
protection.
4 I_OC1 0.05~150A 0.01A Current setting of OC protection


stage 1.
Time delay of definite-time OC
5 t_DefOC1 0~20s 0.001s
protection stage 1.
Base time ( T p ) of inverse-time OC

6 k_BaseTime_InvOC1 0~20s 0.001s
protection stage 1.
Minimum delay of inverse-time OC
7 t_MinDly_InvOC1 0~20s 0.001s
protection stage 1.
Time multiplier ( Kt ) of inverse-time

8 k_TimeMult_InvOC1 0.01~200 0.01
OC protection stage 1.
Exponent () of inverse-time OC
9 k_Exponent_InvOC1 0.01~10 0.01
protection stage 1.
10 En_OC1 0, 1
1: enable OC protection stage 1.
0: disable
11 En_VCE_Ctrl_OC1 0, 1 VCE to control OC protection stage
1: enable
1.
0: disable
12 En_Harm_Blk_OC1 0, 1 function of harmonic blocking OC
1: enable
stage 1.
Logic setting of selecting control
13 Opt_Dir_Ctrl_OC1 0~2 1 mode of directional element to stage
Tripping logic setting of OC
14 TrpLog_OC1 0000~FFFF
protection stage 1
Logic setting of selecting
15 Opt_Characteristic_OC1 0, 1 characteristic of OC protection stage
1.
Current setting of OC protection
16 I_OC2 0.05~150A 0.01A
stage 2.
17 t_DefOC2 0~20s 0.001s
protection stage 2.

protection stage 2.
protection stage 2.


protection stage 2.
22 En_OC2 0, 1
0: disable
1: enable
2.
stage 2.
protection stage 2.
27 Opt_Characteristic_OC2 0, 1 characteristic of OC protection stage
2.
28 I_OC3 0.05~150A 0.01A
stage 3.
29 t_DefOC3 0~20s 0.001s
protection stage 3.

protection stage 3.
Minimum delay of IDMT protection
stage 3.

protection stage 3.
34 En_OC3 0, 1
35 En_VCE_Ctrl_OC3 0, 1
1: enable VCE to control OC protection stage


3.
0: disable
1: enable
stage 3.
protection stage 3
39 Opt_Characteristic_OC3 0, 1 1 characteristic of OC protection stage
3.
40 I_OC4 0.05~150A 0.01A
stage 4.
41 t_DefOC4 0~20s 0.001s
protection stage 4.

protection stage 4.
protection stage 4.

protection stage 4.
46 En_OC4 0, 1
0: disable
1: enable
4.
0: disable
1: enable
stage 4.
protection stage 4.


51 Opt_Characteristic_OC4 0, 1 1 characteristic of OC protection stage
4.
VEBI_OC_XXX
0: disable VEBI setting of enabling OC
52 (XXX=HVS, MVS, LVS, 0, 1
1: enable protection of the corresponding side.
CW)
3.9.4.2 Setting Explanation
 Rated Current Calculation
The setting of backup protection is usually related to the rated current of various sides of the
transformer. The calculation method is the same for the rated currents on various sides. The
following shows an example for the HV side.
Sn
The rated current of HV side is: I1 n 
3U 1n
Where:
U1 is the rated voltage of HV side of the transformer.
Sn is the rate capacity of the transformer.
I 1n
The secondary rated current of HV side is: I 2n  .
n CT
Where:
I1n is rated primary current at the calculated side of transformer;
nCT is the ratio of CT at the calculated side of transformer.
 Overcurrent Elements
The method for configuring overcurrent settings varies with the need and wiring mode.
1. [I_OCn], [Opt_Characteristic_OCn] (n=1, 2, 3, 4)
[I_OCn] is current setting of stage n of definite-time overcurrent protection or base current setting
( I p ) of stage n of inverse-time overcurrent protection depending on the characteristic of stage n of
OC protection.
[Opt_Characteristic_OCn] is logic setting of selecting characteristic of stage n of OC protection.
“0”: definite-time OC protection.
“1”: inverse-time OC protection.
Therefore, when [Opt_Characteristic_OCn] is set as “0”, [I_OCn] is current setting of stage n of

definite-time OC protection, and when [Opt_Characteristic_OCn] is set as “1”, [I_OCn] is base

current setting of stage n of inverse-time OC protection.
The setting [Opt_Characteristic_OCn] is set according requirements. Inverse-time OC protection

of the relay is recommended to be used with inverse-time OC protection of line, and if there are no
line parameters, definite-time OC is recommended to be used and the setting is to be set as “0”.
For the setting [I_OCn] is used in definite-time overcurrent protection, there are following three
ways to set the setting.
1) The setting is set according to rated current of transformer. The operating current of the
current relay should be greater than the rated current of the transformer, whose calculation
formula is as follows:
K
I op  rel I n (Equation 3.9-7)
Kr
Where:
K rel is reliability coefficient, which can be taken as 1.2.
K r is drop-off coefficient, which can be taken as 0.95.
I n is the rated current of the transformer (secondary value).
2) The setting is set in coordination with other overcurrent protection.
Iop KP * Kbr Idz (Equation 3.9-8)
Where:
K p is the coordination coefficient, which can be taken as 1.15-1.25;
Kbr is branch coefficient of current, which is equal to the ratio of the current passing through
this protection equipment to the current passing through the faulty line during an earth fault at
the end of protection section of the coordinated stage of overcurrent protection of the power
line.
Idz is the overcurrent setting to be coordinated.
3) The setting is set to ensure enough sensitivity of the protection during a fault at the local side
busbar.
I op I min / K sen (Equation 3.9-9)
Where:
Ksen is the sensitivity coefficient, which can be set as 1.5.

Imin is the minimum current value during a short-circuit fault at the local side bus.
Recommended value: when coordination is not considered, following formula can be taken for the
stage with the lowest setting.
K
I op  rel I n (Equation 3.9-10)
Kr
Where:
K rel =1.2 and K r =0.95.
If there is more than one stage, settings of other stages can be amplified in sequence.
For the setting [I_OCn] is used in inverse-time overcurrent protection, the setting should be
configured as follows.
1) The setting is set according the rated current of transformer, which can be set equal to the
minimum value of current settings of definite-time overcurrent protection.
2) The setting is set to coordinate with other overcurrent protection.
Iop KP * Idz (Equation 3.9-11)
Where:
K P is coordinating coefficient, which can be taken as 1.15~1.25.
I dz is the overcurrent setting to be coordinated
2. [t_DefOCn] (n=1, 2, 3, 4)
1) In coordination with the main protection of the transformer, the following formula is
recommended.
t =0.5s
Where:
t is the time delay.
2) In coordination with the phase-to-phase overcurrent protection of the line, the following
formula is recommended.
t = t max + t
Where:

tmax is the maximum time delay for line protection.
t is the time difference which can be taken as 0.3~0.5.

3) For different time delays of the same stage, the following formula is recommended.
t n1 t n t
Where:
t n , t n 1 are respectively delay n and delay n+1 of the same stage.

4) If stage n OC protection is used as instant OC, the setting can be set as “0”.
Recommended value: when no coordination is required, the minimum operating time can be set as
2s, with other time delays amplified in sequence.
3. [En_OCn] (n=1, 2, 3, 4)
This logic setting is used to enable or disable some stage of overcurrent protection.
4. [k_BaseTime_InvOCn] (n=1, 2, 3, 4)
This is the base time ( T p ) of inverse-time OC protection stage 1.
If stage n of inverse-time OC protection coordinates with a line, the setting should be set equal to
the base time of inverse-time OC protection of the line.
If stage n of inverse-time OC protection is used independently, recommended value is 0.05s~3.2s
5. [t_MinDly_InvOCn] (n=1, 2, 3, 4)
This is the minimum delay of stage n of inverse-time OC protection.
Recommended value: 0.1s.

6. [k_TimeMult_InvOCn], [k_Exponent_InvOCn] (n=1, 2, 3, 4)
[k_TimeMulti_InvOCn] and [k_Exponent_InvOCn] are respectively the time multiplier ( Kt ) and the
exponent ( ) of stage n of inverse-time OC protection, which are set according to the model of
inverse-time OC protection. Parameters of different models of inverse-time OC protection
supported by the relay are shown in the table below.
Very Inverse 1 13.5

7. [TrpLog_OCn] (n=1, 2, 3, 4)
The tripping logic setting is used to specify which breakers will be tripped when stage n (n=1, 2, 3,
4) of overcurrent protection operates. Please refer to the description of the setting [TrpLog_Diff] in
8. [VEBI_OC_XXX] (XXX=HVS, MVS, LVS, CW)
This setting is the VEBI setting of enabling overcurrent protection of some side. Please refer to the
setting [VEBI_Diff] in section 3.2.5 for details
 Control element and blocking element
1. [Vpp_UV_VCE]
The voltage setting of undervoltage relay should be greater the lowest voltage during starting
process of largest motor started.
1) When voltage for undervoltage relay is taken from LV side VT, t he calculation formula is as
follows:
U
U op  min (Equation 3.9-12)
K rel 
Kr
Where:
U op is the setting .
Krel is reliability coefficient, which can be taken as 1.11.2.
Kr is drop-off coefficient, which can be taken as 1.05.
U min is the minimum possible phase-to-phase voltage during normal operation of the
transformer which can be normally taken as 0.9Un (Un is secondary value of the rated line
voltage.
2) When voltage for undervoltage relay is taken from HV side VT, the calculation formula is as
follows:
Uop 0.7Un (Equation 3.9-13)

Where:
U n is the secondary value of the rated phase-to-phase voltage.
3) For a step-up transformer in a power plant, when voltage for undervoltage relay is taken from
VT of generator, the setting should be greater than the possible lowest voltage during
generator operation in loss of excitation condition. The calculation formula is as follows:
U op (0.5 0.6)U n (Equation 3.9-14)
Where:
U n is the secondary value of the rated phase-to-phase voltage.
Recommended value: 0 .7U n .
2. [V_NegOV_VCE]
The setting should be greater than the unbalance voltage during transform er normal operation,
which can be derived through actual measurement.
Uop .2 (0.06 0.08)U n (Equation 3.9-15)
Where:
U op 2 is the setting.
U n is secondary rated phase voltage.
3. [k_Harm_Blk_OC]
This is the harmonic blocking coefficient of OC protection.
4. [En_VCE_Ctrl_OCn] (n=1, 2, 3, 4)
This logic setting is used to enable or disable the function that certain stage of overcurrent
protection of some side is controlled by voltage control element (VCE).
“0”: the function is disabled; “1”: the function is enabled.
If multi-stage protection is enabled, it is recommended that the first stage be controlled by voltage
control element. If only one stage of OC protection is enabled, it is recommend that this stage not
be controlled by VCE.
5. [Opt_Dir_Ctrl_OCn] (n=1, 2, 3, 4)

This is the logic setting of selecting control mode of directional element to stage n of OC
protection.
“0”: control function disabled.
“1”: protect transformer.
“2”: protect power system.
If only one stage of OC protection is enabled, it is recommend that this stage not be controlled by
directional element.
6. [En_Harm_Blk_OCn] (n=1, 2, 3, 4)
This is the logic setting of enabling some stage of OC protection to be blocked by harmonics.
If there is no special requirement, it is recommend to be set as “0”.
“0”: the blocking function is disabled; “1”: the blocking function is enabled.
Input signals of overcurrent protection are list in the following table.

1 EBI_OC_HVS Binary input of enabling overcurrent protection of HV side.
2 EBI_OC_MVS Binary input of enabling overcurrent protection of MV side.
3 EBI_OC_LVS Binary input of enabling overcurrent protection of LV side.
4 EBI_OC_CW Binary input of enabling overcurrent protection of common winding
Output signals of impedance protection are list in the following table.

1 Op_OC1_HVS Overcurrent protection stage 1 of HV side operates.
5 Op_OC1_MVS Overcurrent protection stage 1 of MV side operates.


9 Op_OC1_LVS Overcurrent protection stage 1 of LV side operates.
13 Op_OC1_CW Overcurrent protection stage 1 of common winding operates.
17 FD_OC_HVS Fault detector of Overcurrent protection of HV side picks up.
18 FD_OC_MVS Fault detector of Overcurrent protection of MV side picks up.
19 FD_OC_LVS Fault detector of Overcurrent protection of LV side picks up.
Fault detector of Overcurrent protection of common winding picks
20 FD_OC_CW
up.
module.
3.10 Zero-Sequence Overcurrent protection (ROC)
Zero-sequence overcurrent relay is mainly used as the backup protection of earth fault for
transformer with neutral point earthed solidly.
Four zero-sequence overcurrent protection elements of HV, MV, and LV sides and common
winding (CW) are provided with totally same configuration, which can be controlled by directional
element and be blocked by harmonic blocking element.
The current from zero-sequence CT at neutral point is used for the protection calculation.
 Fault detector for definite-time zero-sequence overcurrent protection
Operation criteria:
3I0> 0.95xMin([I_ROC1], [I_ROC2], [I_ROC3], [I_ROC4]) (Equation 3.10-1)
Where:
3I0 is the current from the zero-sequence CT or calculated three times of zero-sequence current of
one side.
[I_ROC1], [I_ROC2], [I_ROC3] and [I_ROC4] are respectively the current settings of stage1, stage

2 stage 3 and stage 4 of zero-sequence overcurrent protection of the corresponding side.
The pickup of the fault detector will enable definite-time zero-sequence overcurrent protection at
the relevant side.
 Fault detector for inverse-time zero-sequence overcurrent protection
When zero-sequence current from zero-sequence CT of one side is greater than base current
setting [I_ROCn] （n=1, 2, 3 or 4）, the fault detector picks up to enable stage n (n=1, 3, 4 or 4) of
inverse-time zero-sequence overcurrent protection at relevant side.
There are four stages of zero-sequence overcurrent protection are equipped for each side of
transformer, which can be definite-time or inverse-time zero-sequence overcurrent protection by
configuring the logic setting XXX: [Opt_Characteristic_ROCn] (XXX represents HVS, MVS, LVS,
CW; n=1, 2, 3, 4), “0”for definite time characteristic, and “1”for inverse time characteristic.
NOTE: One stage of zero-sequence overcurrent protection can be configured as
inverse-time characteristic by user freely, but if user wants to configure more stages as
inverse-time characteristics please inform the manufacturer when placing an order.
NOTE: Zero-sequence current for ROC protection, RDE element and harmonic
calculation are from the same source. If the setting [En_3I0_Calc_ROC] is set as “0”,
then the current from zero-sequence CT is used, and otherwise the calculated
zero-sequence current is used.
3.10.2.1 Definite-Time Zero-sequence Overcurrent Protection
Operation criterion of definite-time zero-sequence overcurrent protection is as follows.
3I0> [I_ROCn] (Equation 3.10-2)
Where:
one side.
[I_ROCn] is the current setting of stage n (n=1, 2, 3, 4) of zero-sequence overcurrent protection of

the corresponding side.
3.10.2.2 Inverse-Time Zero-Sequence Overcurrent Protection
Inverse delay characteristics defined in IEC60255-3 are adopted, which formula is shown as
follows.

Kt
t (I 0 )  Tp
I0  (Equation 3.10-3)
( ) 1
Ip
Where:
I p is base current (also called current limit), i.e. setting [I_ROCn] (n=1, 2, 3 or 4).
Tp is base time, i.e. setting [k_BaseTime_InvROCn] (n=1, 2, 3 or 4).
Kt is time multiplier, i.e. setting [k_TimeMult_InvROCn] (n=1, 2, 3 or 4).
 is exponent, i.e. setting [k_Exponent_InvROCn] (n=1,2, 3 or 4)

I is actual value of measured current from the zero-sequence CT or calculated three times of
zero-sequence current.

Very Inverse 1 13.5
3.10.2.3 Zero-sequence Direction Element (RDE)
Protection direction of each stage of zero-sequence overcurrent protection can be set respectively
by the logic setting [Opt_Dir.RD_Ctrl_ROCn] (n=1, 2, 3, 4). If the setting is set as “1”, its direction
is to protect power system and reach angle is 255º, and if the setting is set as “2”, its direction is to
protect transformer and reach angle is 75º. If this setting is set as “0”, the corresponding stage of
the protection is not controlled by zero-sequence directional element. The operating characteristic
is shown in the following figure in which the shadow zone is the operation zone of the residual
directional element.
Operation criteria of directional element are as follows, when protection direction is to power
system.
-15°<arg(U0)-arg(I0)<165° (Equation 3.10-4)
Operation criteria of directional element are as follows, when protection direction is to transformer.

165°<arg(U0)-arg(I0)<345° (Equation 3.10-5)
Where:
I0 is the current from the zero-sequence CT or calculated three times of zero-sequence current of
one side.
U0 is the calculated zero-sequence voltage.
a) Direct to power system b) Direct to transformer
Figure 3.10-1 Operating characteristic of zero-sequence directional protection
NOTE: The direction mentioned above is based on positive polarities of three-phase CT
and zero-sequence CT being set as the function figures in Chapter 1 shows. Otherwise
actual protection direction is not consistent to that mentioned above.
3.10.2.4 Influence of VT Circuit Failure and VT Out of Service on RED
Directional element pick up to release zero-sequence overcurrent protection when VT circuit

failure is distinguished, which means directional zero-sequence overcurrent protection becomes
zero-sequence overcurrent protection without any control element.
not been switched on, in order to ensure correct operation of controlled directional
zeros-sequence overcurrent protection, the binary input [EBI_In_VT_XXX] (XXX represent HVS,
MVS or LVS) should be de-energized. Then zero-sequence directional element picks up to release
zero-sequence overcurrent protection which becomes zero-sequence overcurrent protection
without any control element.
3.10.2.5 Harmonic Blocking Element
In order to prevent effects of sympathetic inrush current on zero-sequence overcurrent relay,

harmonics blocking function can be set for every stage of this relay by configuring logic setting
[En_Harm_Blk_ROCn] (n=1, 2, 3, 4). When the logic setting is set as “1”, then stage n of
zero-sequence overcurrent protection is blocked if harmonics reaches its setting value. When the
logic setting is set as “0”, stage n of zero-sequence overcurrent protection does not be blocking by
harmonic.

Operation criterion:
I 2 nd K 2 xb * max( I1st , 0.3In) (Equation 3.10-6)
Where:
I2nd is secondary harmonic of zero-sequence current.
I2nd is fundamental component of zero-sequence current.
K2 xb is harmonic blocking coefficient, i.e. the setting [k_Harm_Blk_ROC].
3.10.3 Logic Scheme

Logic schemes of zero-sequence overcurrent protection of each side are same, and that of HV
side is taken as an example to show the logic diagram.
3.10.3.1 Logic Scheme of Zero-sequence Directional Element
Figure 3.10-2 Logic diagram of directional element
Where:
Flg_Direction_ROC_HVS is the internal flag indicating that DE decides the fault is in the protection
direction of overcurrent protection of HV side.
Flg_Pkp_RDE_HVS is the internal flag indicating that zero-sequence directional element of HV

side picks up.

3.10.3.2 Logic Scheme of Definite-Time Zero-sequence Overcurrent Protection
Figure 3.10-3 Logic diagram of definite-time zero-sequence overcurrent protection
Where:
HVS:[Opt_Dir.RD_Ctrl_ROCn] is the logic setting of selecting control mode of directional element

to stage n (n=1, 2, 3 or 4) of ROC protection of HV side, 0 for not control ROC, “1”for protecting
system and “2”for protecting transformer,.
HVS:[Opt_Characteristic_ROCn] is the logic setting of selecting characteristic of stage n (n=1, 2,

3 or 4) of ROC protection, “0”for definite-time zero-sequence overcurrent protection and “1”for
inverse-time zero-sequence overcurrent protection.
HV side.
HVS:[I_ROCn] is the setting of stage n (n=1, 2, 3 or 4) of definite-time ROC protection of HV side.
[EBI_ROC_HVS] is the binary input of enabling ROC protection of HV side.
[VEBI_ROC_HVS] is the VEBI setting of enabling ROC protection of HV side.
HVS:[En_ROCn] is the logic setting of enabling stage n (n=1, 2, 3 or 4) of ROC protection of HV

side.
Flg_FD_DefROC_HVS is the operation of the fault detector of definite-time ROC protection of HV

side.
HVS:[t_DefROCn] is the time delay of stage n (n=1, 2, 3 or 4) of definite-time ROC protection of

HV side.
[Op_OCn_HVS] is the operation flag of stage n (n=1, 2, 3 or 4) of ROC protection of HV side.

3.10.3.3 Logic Scheme of Inverse-Time Zero-sequence Overcurrent Protection
Figure 3.10-4 Logic diagram of inverse-time zero-sequence overcurrent protection
Where:
HVS:[I_ROCn] is the base current setting of stage n (n=1, 2, 3 or 4) of inverse-time ROC

Flg_FD_InvROC_HVS is the operation of the fault detector of inverse-time ROC protection of HV

side.
Please refer to above sections for detailed descriptions of each symbol.
3.10.4 Setting
3.10.4.1 Setting List
Table 3.10-2 Settings of zero-sequence overcurrent protection (HVS, MVS, LVS, CW)

Harmonic blocking coefficient of
1 k_Harm_Blk_ROC 0.05~0.35 0.01
ROC protection
zero-sequence current source.
0: disable 0: neutral point zero-sequence
2 En_3I0_Calc_ROC 0, 1
1: enable current
1: calculated zero-sequence
current
Current setting of ROC protection
3 I_ROC1 0.05~150A 0.01A
stage 1.
Time delay of definite-time ROC
4 t_DefROC1 0~20s 0.001s
protection stage 1.
Base time ( T p ) of inverse-time

5 k_BaseTime_InvROC1 0~20s 0.001s
ROC protection stage 1.


Minimum delay of inverse-time
6 t_MinDly_InROC1 0~20s 0.001s
Time multiplier ( Kt ) of
7 k_TimeMult_InvROC1 0.01~200 0.01
inverse-time ROC protection
stage 1.
Exponent () of inverse-time
8 k_Exponent_InvROC1 0.01~10 0.01
9 En_ROC1 0, 1
1: enable ROC protection stage 1.
0: disable
10 En_Harm_Blk_ROC1 0, 1 function of harmonic blocking
1: enable
ROC stage 1.
mode of zero-sequence
11 Opt_Dir.RD_Ctrl_ROC1 0~2 1
directional element to stage OC
protection stage 1.
Tripping logic setting of ROC
12 TrpLog_ROC1 0000~FFFF
protection stage 1
13 Opt_Characteristic_ROC1 0, 1 1 characteristic of ROC protection
stage 1.
14 I_ROC2 0.05~150A 0.01A
stage 2.
15 t_DefROC2 0~20s 0.001s
protection stage 2.

stage 2.
20 En_ROC2 0, 1


0: disable
1: enable
ROC stage 2.
protection stage 2.
protection stage 2.
stage 2.
25 I_ROC3 0.05~150A 0.01A
stage 3.
26 t_DefROC3 0~20s 0.001s
protection stage 3.

stage 3.
31 En_ROC3 0, 1
0: disable
1: enable
ROC stage 3.
protection stage 3.
protection stage 3
35 Opt_Characteristic_ROC3 0, 1 1
characteristic of ROC protection


stage 3.
36 I_ROC4 0.05~150A 0.01A
stage 4.
37 t_DefROC4 0~20s 0.001s
protection stage 4.

stage 4.
42 En_ROC4 0, 1
0: disable
1: enable
ROC stage 4.
protection stage 4.
protection stage 4.
stage 4.
VEBI_ROC_XXX Logic setting of enabling ROC
0: disable
47 (XXX=HVS, MVS, LVS, 0, 1 protection of the corresponding
1: enable
CW) side.
3.10.4.2 Setting explanation
The method for configuring overcurrent settings varies with the need and wiring mode.
 Zero-sequence protection element
1. [I_ROCn], [Opt_Characteristic_ROCn] (n=1, 2, 3, 4)
[I_ROCn] is current setting of stage n of definite-time zero-sequence protection or base current

setting ( I p ) of stage n of inverse-time zero-sequence protection depending on the characteristic
of stage n of ROC protection.
[Opt_Characteristic_ROCn] is logic setting of selecting characteristic of stage n of ROC

protection.
“0”: definite-time ROC protection.
“1”: inverse-time ROC protection.
Therefore, when [Opt_Characteristic_ROC n] is set as “0”, [I_ROCn] is current setting of stage n of

definite-time ROC protection, and when [Opt_Characteristic_ROCn] is set as “1”, [I_ROCn] is
base current setting of stage n of inverse-time ROC protection.
The setting [Opt_Characteristic_ROCn] is set according requirements. Inverse-time ROC

protection of the relay is recommended to be used with inverse-time ROC protection of line, and if
there are no line parameters, definite-time ROC is recommended to be used and the setting is to
be set as “0”.
If the setting [I_ROCn] is used as current setting of definite-time zero-sequence overcurrent

protection, there are following three ways to set the setting.
1) Zero-sequence overcurrent protection of transformer normally coordinates with the

zero-sequence overcurrent protection of the line.
I op K rel K br I op. o (Equation 3.10-7)
Where:
I op is the setting value (secondary value).
K br is the branching coefficient of the zero sequence current, which is equal to ratio of zero
sequence current passing through this protection equipment to passing through the faulty line
during an earth fault at the end of protected section of stage 1 of residual overcurrent
protection of the power line. Maximum value among various operation conditions being taken.
K rel is the reliability factor, which is taken as 1.1.
I op.o is the setting (secondary value) of the related stage of coordinating zero-sequence
overcurrent protection of line.
2) The setting is set to ensure enough sensitivity of the protection during a fault at the local side
busbar.

I op I min / K sen (Equation 3.10-8)
Where:
Ksen is the sensitivity coefficient, which can be set as 1.5.
Imin is the minimum zero-sequence current value during a short-circuit fault at the local side
bus.
If the setting [I_ROCn] is used in inverse-time ROC protection, the setting should be configured as
follows.
Inverse-time ROC protection coordinates with inverse-time ROC protection of a power line, so the
setting is set according the following formular.
Iop KP * Idz (Equation 3.10-9)
Where:
K P is coordinating coefficient, which can be taken as 1.15~1.25.
I dz is the current setting of inverse-time ROC to be coordinated
9. [t_Def ROCn] (n=1, 2, 3, 4)
1) The time delay of zero-sequence overcurrent protection coordinates with the corresponding
line zero-sequence protection. Following equation is recommended:
t = t max + t
Where:
tmax is the maximum operating time delay of coordinated stage of the line zero-sequence
overcurrent protection.

2) For different time delays of the same stage, the following formula is recommended.
t n1 t n t
Where:
t n , t n 1 are respectively delay n and delay n+1 of the same stage.

3) If stage n OC protection is used as instant OC, the setting can be set as “0”.
Recommended value: when no coordination is required, the minimum operating time can be set as
2s, with other time delays amplified in sequence.
10. [En_ROCn] (n=1, 2, 3, 4)
This logic setting is used to enable or disable some stage of zero-sequence overcurrent
protection.
11. [k_BaseTime_InvROCn] (n=1, 2, 3, 4)
This is the base time ( T p ) of inverse-time ROC protection stage 1.
If stage n of inverse-time ROC protection coordinates with a line, the setting should be set equal to
the base time of inverse-time ROC protection of the line.
If stage n of inverse-time ROC protection is used independently, recommended value: 0.05s~3.2s
12. [t_MinDly_InvROCn] (n=1, 2, 3, 4)
This is the minimum delay of stage n of inverse-time ROC protection.

13. [k_TimeMult_InvROCn], [k_Exponent_InvROCn] (n=1, 2, 3, 4)
[k_TimeMulti_InvROCn] and [k_Exponent_InvROCn] are respectively the time multiplier ( Kt ) and
the exponent ( ) of stage n of inverse-time ROC protection, which are set according to the model
of inverse-time ROC protection. Parameters of different models of inverse-time ROC protection
Very Inverse 1 13.5
14. [TrpLog_ROCn] (n=1, 2, 3, 4)

The tripping logic setting is used to specify which breakers will be tripped when stage n (n=1, 2, 3,
4) of zero-sequence overcurrent protection operates. Please refer to the description of the setting
15. [VEBI_ROC_XXX] (XXX=HVS, MVS, LVS, CW)
This setting is the VEBI setting of enabling zero-sequence overcurrent protection of some side.
Please refer to the setting [VEBI_Diff] in section 3.2.5 for details
 Control element and blocking element

1. [k_Harm_Blk_ROC]
This is the harmonic blocking coefficient of OC protection.
[Opt_Dir_Ctrl_ROCn] (n=1, 2, 3, 4)
This is the logic setting of selecting control mode of directional element to stage n of ROC
protection.
“0”: control function disabled.
“1”: protect transformer.
“2”: protect power system.
If only one stage of ROC protection is enabled, it is recommend that this stage not be controlled by
zero-sequence directional element.
2. [En_Harm_Blk_ROCn] (n=1, 2, 3, 4)
This is the logic setting of enabling some stage of ROC protection to be blocked by harmonics.
If there is no special requirement, it is recommend to be set as “0”.
“0”: the blocking function is disabled; “1”: the blocking function is enabled.
3.10.5 Input and output

Input signals of zeros-sequence overcurrent protection are list in the following table.

Binary input of enabling zero-sequence overcurrent protection of
1 EBI_ROC_HVS
HV side.
2 EBI_ROC_MVS
MV side.
3 EBI_ROC_LVS
LV side.
4 EBI_ROC_CW
common winding.
Output signals of zero-sequence overcurrent protection are list in the following table.


Zero-sequence overcurrent protection stage 1 of HV side
1 Op_ROC1_HVS
operates.
2 Op_ROC2_HVS
operates.
3 Op_ROC3_HVS
operates.
4 Op_ROC4_HVS
operates.
Zero-sequence overcurrent protection stage 1 of MV side
5 Op_ROC1_MVS
operates.
6 Op_ROC2_MVS
operates.
7 Op_ROC3_MVS
operates.
8 Op_ROC4_MVS
operates.
9 Op_ROC1_LVS Zero-sequence overcurrent protection stage 1 of LV side operates.
Zero-sequence overcurrent protection stage 1 of common winding
13 Op_ROC1_LVS
operates.
14 Op_ROC2_LVS
operates.
15 Op_ROC3_LVS
operates.
16 Op_ROC4_LVS
operates.
Fault detector of Zero-sequence overcurrent protection of HV side
17 FD_ROC_HVS
picks up.
Fault detector of Zero-sequence overcurrent protection of MV side
18 FD_ROC_MVS
picks up.
Fault detector of Zero-sequence overcurrent protection of LV side
19 FD_ROC_LVS
picks up.
20 FD_ROC_CW Fault detector of Zero-sequence overcurrent protection of


common winding picks up.
module.
3.11 Phase Overvoltage Protection (OV)
Three overvoltage protection elements of HV, MV, and LV sides are provided with totally same
configuration.

 Fault detector for definite-time overvoltage protection
Criteria:
U _ max >0.95x Min([V_OV1], [V_OV2] (Equation 3.11-1)
Where:
U _ max is the maximum value of three-phase voltage of one side.
[V_OV1] and [V_OV2] are respectively the voltage settings of stage 1 and stage 2 of definite-time
overvoltage protection of corresponding side.
The pickup of this fault detector will enable definite-time overvoltage protection of corresponding
side.
 Fault detector for inverse-time overvoltage protection
When phase voltage of one side is greater than base voltage setting [I_OVn] （n=1 or 2）, the fault
detector picks up to enable stage n (n=1 or 2) of inverse-time overvoltage protection at relevant
side.
There are two stages of overvoltage protection are equipped for each side of transformer, which
can be definite-time or inverse-time overvoltage protection by configuring logic setting
[Opt_Characteristic_OVn].
Overvoltage protection has two modes for selection according to the logic setting [Opt_Mode_OV].
 If [Opt_Mode_OV] is set as “0”, when the maximum phase voltage satisfies operation
equation of overvoltage protection, the protection operates after its time delay.
 If [Opt_Mode_OV] is set as “1”, when three phase voltage all satisfy operation equation of
overvoltage protection, the protection operates after its time delay.
Overvoltage protection is disabled, when VT circuit failure is distinguished or VT is out of service.

3.11.2.1 Definite-Time Overvoltage Protection
Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected depending on the logic setting [Opt_Mode_OV].
U _ max [V _ OVn] (Equation 3.11-2)

U a [V _ OVn]

U b [V _ OVn]

U c [V _ OVn]

Where:
U _ max is the maximum value of three phase-voltage of some side.
U a ,U b ,U c are three phase voltages of some side.
[V_OVn]is the setting of stage n (n=1 or 2) of overvoltage protection of the corresponding side.
When [Opt_Mode_OV] is set as “0”(Equation 3.11-2) is selected as operation equation, and when
[Opt_Mode_OV] is set as “1”, (Equation 3.11-3) is selected.
3.11.2.2 Inverse-Time Overvoltage Protection
as follows.
Kt
t(U )  Tp
U 
( ) 1 (Equation 3.11-4)
Up
Where :
U p is base voltage (also called voltage limit), i.e. setting [V_OCn] (n=1 or 2).
Tp is base time, i.e. setting [k_BaseTime_InvOCn] (n=1 or 2).
Kt is time multiplier, i.e. setting [k_TimeMult_InvOCn] (n=1 or 2).
 is exponent, i.e. setting [k_Exponent_InvOCn] (n=1 or 2).

U is actual value of measured phase voltage, which is maximum phase voltage or three phase
voltages depending on the logic setting [Opt_Mode_OV].

Inverse Delay Curve Tp  Kt
Standard Inverse 0.02 0.14 0.05~1.1

Very Inverse 1 13.5 0.05~1.1
Extremely Inverse 2 80 0.05~1.1
Long Time Inverse 1 120 0.05~1.1
3.11.3 Logic Scheme
Logic schemes of overvoltage protection of each side are same, and that of HV side is taken as an
example to show the logic diagram.
3.11.3.1 Logic Scheme of Definite-Time Overvoltage Protection
U _ max
U a ,U b ,Uc
Figure 3.11-1 Logic diagram of definite-time overvoltage protection
Where:
U _ max is the maximum value of three-phase voltage of HV side.
U a ,U b ,U c are three phase voltages of some side.
HVS:[I_OVn] is the setting of stage n (n=1 or 2) of definite-time overvoltage protection of HV side.

HVS :[Opt_Mode_OV] is the logic setting of selecting operation criterion of overvoltage protection.
[EBI_OV_HVS] is the binary input of enabling OV protection of HV side.
[VEBI_OV_HVS] is the VEBI setting of enabling OV protection of HV side.
HVS:[En_OVn] is the logic setting of enabling stage n (n=1 or 2) of OV protection of HV side.
Flg_FD_DefOV_HVS is the operation of the fault detector of definite-time OV protection of HV

side.
HVS:[t_DefOVn] is the time delay of stage n (n=1 or 2) of definite-time OV protection of HV side.
[Op_OVn_HVS] is the operation flag of stage n (n=1 or 2) of OV protection of HV side.
HVS:[Opt_Characteristic_OVn] is the logic setting of selecting characteristic of stage n (n=1 or 2)

of OV protection, “0”for definite-time OV protection and “1”for inverse-time OV protection.
3.11.3.2 Logic Scheme of Inverse-Time Overvoltage Protection
U _ max
U a ,Ub ,U c
Figure 3.11-2 Logic diagram of inverse-time overvoltage overcurrent protection
Where:
HVS:[I_OVn] is the base voltage dryyinh of stage n (n=1 or 2) of inverse-time OV protection of HV

side.
Flg_FD_InvOV_HVS is the operation of the fault detector of inverse-time OV protection of HV side.
Please refer to above sections for detailed descriptions of other symbols.
3.11.4 Setting
Table 3.11-2 Settings of overvoltage protection (HVS, MVS, LVS)

1 V_OV1 0.05~150V 0.01V Voltage setting of OV protection stage 1.


Time delay of definite-time OV
2 t_DefOV1 0~20s 0.001s
protection stage 1.
Base time ( T p ) of inverse-time OV

3 k_BaseTime_InvOV1 0~20s 0.001s
protection stage 1.
Minimum delay of inverse-time OV
4 t_MinDly_InvOV1 0~20s 0.001s
protection stage 1.
Time multiplier ( K t ) of inverse-time OV

5 k_TimeMult_InvOV1 0.01~200 0.01
protection stage 1.
Exponent (  ) of inverse-time OV
6 k_Exponent_InvOV1 0.01~10 0.01
protection stage 1.
0:
disable Logic setting of enabling/disabling OV
7 En_OV1 0, 1
1: protection stage 1.
enable
Logic setting of selecting characteristic
8 Opt_Characteristic_OV1 0, 1 1
of OV protection stage 1.
Tripping logic setting of OV protection
9 TrpLog_OV1 0000~FFFF
stage 1
10 I_OV2 0.05~150V 0.01V Voltage setting of OV protection stage 2.
11 t_DefOV2 0~20s 0.001s
protection stage 2.
Base time ( T p ) of inverse-time OV

12 k_BaseTime_InvOV2 0~20s 0.001s
protection stage 2.
Minimum delay of inverse-time OV
13 t_MinDly_InvOV2 0~20s 0.001s
protection stage 2.
Time multiplier ( K t ) of inverse-time OV

14 k_TimeMult_InvOV2 0.01~200 0.01
protection stage 2.
Exponent (  ) of inverse-time OV
15 k_Exponent_InvOV2 0.01~10 0.01
protection stage 2.
0:
disable Logic setting of enabling/disabling OV
16 En_OV2 0, 1
1: protection stage 2.
enable
Logic setting of selecting characteristic
17 Opt_Characteristic_OV2 0, 1 1
of OV protection stage 2.


Tripping logic setting of OV protection
18 TrpLog_OV2 0000~FFFF
stage 2.
Logic setting of selecting operation
19 Opt_Mode_OV 0, 1 1
criteria of OV protection.
0:
VEBI_OV_XXX disable VEBI setting of enabling/disabling OV
20 0, 1
(XXX=HVS, MVS, LVS) 1: protection of the corresponding side.
enable
1. [V_OVn], [Opt_Characteristic_OVn] (n=1, 2)
[V_OVn] is the voltage setting of stage n of definite-time overvoltage protection or base voltage
setting ( U p ) of stage n of inverse-time overvoltage protection depending on the characteristic of
stage n of overvoltage protection.
[Opt_Characteristic_OVn] is logic setting of selecting characteristic of stage n of OV protection.
“0”: definite-time OV protection.
“1”: inverse-time OV protection.
Therefore, when [Opt_Characteristic_OVn] is set as “0”, [I_OVn] is voltage setting of stage n of

definite-time OV protection, and when [Opt_Characteristic_OVn] is set as “1”, [V_OVn] is base
voltage setting of stage n of inverse-time OV protection.
The setting [Opt_Characteristic_OVn] is set according requirements. Inverse -time OV protection

of the relay is recommended to be used with inverse-time OV protection of line, and if there are no
line parameters, definite-time OV is recommended to be used and the setting is to be set as “0”.
If the setting [V_OVn] is used as current setting of definite-time OV protection, it shall be set
according to the equipment affordability, generally:
U op (1.3 ~ 1.5)U n
Where:
U n is the secondary rated phase voltage value. In case of multi stages to be used, the
U n U n
recommended maximum value is 1.3 and the value differential is 0.2 .
If the setting [I_OVn] is used in inverse-time OV protection, the setting should be configured as
follows.
U op K P *U max

Where:
KP is the reliability coefficient of and can be 1.05~1.1.
U max is the minimum voltage under which the equipment can operate for a long term.
2. [t_DefOVn] (n=1, 2)
The time delay of stage 1 of definite-time overvoltage protection shall be set according to the
equipment affordability, and the recommended value is 0.3s~1s. In case of multi stages to be used,
the recommended maximum value is 0.3s and the time differential is 0.5s.
3. [k_BaseTime_InvOVn] (n=1, 2)
This is the base time ( T p ) of inverse-time OV protection, and it shall be set according to the
equipment affordability, and the recommended setting value is 0.05s~3.2s.
4. [t_MinDly_InvOVn] (n=1, 2)
This is the minimum delay of stage n of inverse-time OV protection.
5. [k_TimeMult_InvOVn], [k_Exponent_InvOVn] (n=1, 2)
[k_TimeMulti_InvOVn] and [k_Exponent_InvOVn] are respectively the time multiplier ( Kt ) and the
exponent ( ) of stage n of inverse-time OV protection, which are set according to the model of
inverse-time ROC protection. Parameters of different models of inverse-time OV protection
Very Inverse 1 13.5
6. [En_OVn] (n=1, 2)
This logic setting is used to enable or disable some stage of phase overvoltage protection.

7. [Opt_Mode_OVn] (n=1, 2)
This is the logic setting of selecting operation criteria of overvoltage protection, which shared by

overvoltage protection stage 1 and stage 2.
“0": when the maximum phase voltage satisfies operation equation of overvoltage protection, the
protection operates after its time delay.
“1”: when three phase voltage all satisfy operation equation of overvoltage protection, the
protection operates after its time delay.
8. [TrpLog_OVn] (n=1, 2)
The tripping logic setting is used to specify which breakers will be tripped when stage n of phase
overvoltage protection operates. Please refer to the description of the setting [TrpLog_Diff] in
9. [VEBI_OV_XXX] (XXX=HVS, MVS, LVS)
This setting is the VEBI setting of enabling phase overvoltage protection of some side. Please
refer to the setting [VEBI_Diff] in section 3.2.5 for details
Input signals of overvoltage protection are list in the following table.

1 EBI_OV_HVS Binary input of enabling overvoltage protection of HV side.
2 EBI_OV_MVS Binary input of enabling overvoltage protection of MV side.
3 EBI_OV_LVS Binary input of enabling overvoltage protection of LV side.
Output signals of overvoltage protection are list in the following table.

1 Op_OV1_HVS Overvoltage protection stage 1 of HV side operates.
2 Op_OV2_HVS Overvoltage protection stage 2 of HV side operates.
3 Op_OV1_MVS Overvoltage protection stage 1 of MV side operates.
4 Op_OV2_MVS Overvoltage protection stage 2 of MV side operates.
5 Op_OV1_LVS Overvoltage protection stage 1 of LV side operates.
6 Op_OV2_LVS Overvoltage protection stage 2 of LV side operates.


7 FD_OV_HVS Fault detector of overvoltage protection of HV side picks up.
8 FD_OV_MVS Fault detector of overvoltage protection of MV side picks up.
9 FD_OV_LVS Fault detector of overvoltage protection of LV side picks up.
module.
3.12 Zero-Sequence Overvoltage Protection (ROV)
Three zero-sequence overvoltage protection elements of HV, MV, and LV sides are provided with
totally same configuration.

 Fault detector for definite-time zero-sequence overvlotage protection
Operation criteria:
3U0>0.95x Min([V_ROV1], [V_ROV2]) (Equation 3.12-1)
Where:
3U0 is the zero-sequence voltage from the broken-delta VT of one side.
[V_ROV1] and [V_ROV2] are respectively the voltage settings of stage 1 and stage 2 of
zero-sequence overvoltage protection of the corresponding side.
The pickup of the fault detector will enable definite-time zero-sequence overvoltage protection at
the relevant side.
 Fault detector for inverse-time zero-sequence overvoltage protection
When zero-sequence voltage of one side is greater than base voltage setting [I_ROVn] （n=1 or
2）, the fault detector picks up to enable stage n (n=1 or 2) of inverse-time zero-sequence
overvoltage protection at relevant side.
There are two stages of zero-sequence overvoltage protection are equipped for each side of
transformer, which can be definite-time or inverse-time zero-sequence overvoltage protection by
configuring logic setting [Opt_Characteristic_ROVn].
Zero-sequence overvoltage protection is disabled, when VT is out of service.
3.12.2.1 Definite-Time Zero-Sequence Overvoltage Protection
Operation criterion of definite-time zero-sequence overvoltage protection is as follows.

3I0> [I_ROVn] (Equation 3.12-2)
Where:
3U0 is the zero-sequence voltage from the broken-delta VT of one side.
[V_ROVn] is the voltage setting of stage n (n=1, 2) of zero-sequence overvoltage protection of the
corresponding side.
When VT circuit failure is distinguished, zeros-sequence overvoltage protection is disabled.
3.12.2.2 Inverse-Time Zero-Sequence Overvoltage Protection
as follows.
Kt
t(U )  Tp
U  (Equation 3.12-3)
( ) 1
Up
Where :
U p is base voltage (also called voltage limit), i.e. setting [V_ROVn] (n=1 or 2).
Tp is base time, i.e. setting [k_BaseTime_InvROVn] (n=1 or 2).
Kt is time multiplier, i.e. setting [k_TimeMult_InvOVn] (n=1 or 2).
 is exponent, i.e. setting [k_Exponent_InvOVn] (n=1 or 2).
U is actual value of measured zeros-sequence voltage.

Very Inverse 1 13.5
3.12.3 Logic Scheme

Logic schemes of zero-sequence overvoltage protection of each side are same, and that of HV
side is taken as an example to show the logic diagram.

3.12.3.1 Logic Scheme of Definite-Time Zero-Sequence Overvoltage Protection
Figure 3.12-1 Logic diagram of definite-time zero-sequence overvoltage protection
Where:
3U0 is t3U0 is the zero-sequence voltage from the broken-delta VT of one side.
HVS:[I_ROVn] is the setting of stage n (n=1 or 2) of definite-time zero-sequence overvoltage

[EBI_ROV_HVS] is the binary input of enabling ROV protection of HV side.
[VEBI_ROV_HVS] is the VEBI setting of enabling ROV protection of HV side.
HVS:[En_ROVn] is the logic setting of enabling stage n (n=1 or 2) of ROV protection of HV side.
Flg_FD_DefOV_HVS is the operation of the fault detector of definite-time ROV protection of HV

side.
HVS:[t_DefROVn] is the time delay of stage n (n=1 or 2) of definite-time ROV protection of HV

side.
[Op_ROCVn_HVS] is the operation flag of stage n (n=1 or 2) of ROV protection of HV side.
HVS:[Opt_Characteristic_ROVn] is the logic setting of selecting characteristic of stage n (n=1 or 2

of ROV protection, “0”for definite-time ROV protection and “1”for inverse-time ROV protection.
3.12.3.2 Logic Scheme of Inverse-Time Zero-Sequence Overvoltage Protection
Figure 3.12-2 Logic diagram of inverse-time overvoltage overcurrent protection Where:
HVS:[I_OVn] is the base voltage of stage n (n=1 or 2) of inverse-time ROV protection of HV side.
Flg_FD_InvROV_HVS is the operation of the fault detector of inverse-time ROV protection of HV

side.

Please refer to above sections for detailed descriptions of other symbols.
3.12.4 Setting
Table 3.12-2 Settings of zero-sequence overvoltage protection (HVS, MVS, LVS)

Voltage setting of ROV protection
1 I_ROV1 0.05~300V 0.01V
stage 1.
2 t_DefROV1 0~20s 0.001s
protection stage 1.

3 k_BaseTime_InvROV1 0~20s 0.001s
ROV protection stage 1.
4 t_MinDly_InvROV1 0~20s 0.001s

5 k_TimeMult_InvROV1 0.01~300 0.01
Exponent ( ) of inverse-time ROV
6 k_Exponent_InvROV1 0.01~10 0.01
protection stage 1.
7 En_ROV1 0, 1
1: enable ROV protection stage 1.
8 Opt_Characteristic_ROV1 0, 1 characteristic of ROV protection
stage 1.
Tripping logic setting of ROV
9 TrpLog_ROV1 0000~FFFF
protection stage 1
Voltage setting of ROV protection
10 I_ROV2 0.05~300V 0.01V
stage 2.
Time delay of definite-time ROV
11 t_DefROV2 0~20s 0.001s
protection stage 2.

12 k_BaseTime_InvROV2 0~20s 0.001s
13 t_MinDly_InvROV2 0~20s 0.001s

14 k_TimeMult_InvROV2 0.01~300 0.01
Exponent ( ) of inverse-time ROV
15 k_Exponent_InvROV2 0.01~10 0.01
protection stage 2.


16 En_ROV2 0, 1
1: enable ROV protection stage 2.
17 Opt_Characteristic_ROV2 0, 1 characteristic of ROV protection
stage 2.
Tripping logic setting of ROV
18 TrpLog_ROV2 0000~FFFF
protection stage 2.
VEBI setting of enabling/disabling
VEBI_ROV_XXX 0: disable
19 0, 1 ROV protection of the
(XXX=HVS, MVS, LVS) 1: enable
corresponding side.
1. [V_ROVn], [Opt_Characteristic_ROVn] (n=1, 2)

[V_ROVn] is the voltage setting of stage n of definite-time zero-sequence overvoltage protection
or base voltage setting ( U p ) of stage n of inverse-time zero-sequence overvoltage protection
depending on the characteristic of stage n of zero-sequence overvoltage protection.
[Opt_Characteristic_ROVn] is logic setting of selecting characteristic of stage n of ROV protection.
“0”: definite-time ROV protection.
“1”: inverse-time ROV protection.
Therefore, when [Opt_Characteristic_ROVn] is set as “0”, [I_ROVn] is voltage setting of stage n of
definite-time ROV protection, and when [Opt_Characteristic_ROVn] is set as “1”, [V_ROVn] is
base voltage setting of stage n of inverse-time ROV protection.
For grounded system, definite-time ROV protection can be used as air-gap protection. When
directly grounded transformers in the system are all tripped due to a fault, the protection can
ensure the enough sensitivity to zero-sequence overvoltage caused in the situation. Besides, the
protection should not maloperation during pole disagreement of transformer.
Recommended value: 150~180V. In case of multi stages to be used, the recommended minimum
value is 150V, and the differential value is 30V.
For ungrounded system, definite-time ROV protection can be used as definite-time overvoltage
protection against single phase faults.
Recommend value: 15~40V, and the differential value is 15V.
If the setting [I_ROVn] is used in inverse-time ROV protection, the recommended value is 150V for
grounded system and 30V for ungrounded system.
2. [t_DefROVn] (n=1, 2)
This is the time delay of some stage of definite-time ROV protection, and it shall be set to keep the
stage protection away from the influence of transient characteristic and the recommended value is
0.3s~0.5s. In case of multi stages to be used, the minimum value will be considered to be 0.3s,
and the voltage differential shall be 0.5s.
10. [k_BaseTime_InvROVn] (n=1, 2)
This is the base time ( T p ) of inverse-time ROV protection, and it shall be set according to the

equipment affordability, and the recommended setting value is 0.05s~3.2s.
11. [t_MinDly_InvROVn] (n=1, 2)

This is the minimum delay of stage n of inverse-time ROV protection.
12. [k_TimeMult_InvROVn], [k_Exponent_InvROVn] (n=1, 2)
[k_TimeMulti_InvROVn] and [k_Exponent_InvROVn] are respectively the time multiplier ( Kt ) and
the exponent ( ) of stage n of inverse-time ROV protection, which are set according to the model
of inverse-time ROV protection. Parameters of different models of inverse-time ROV protection
Very Inverse 1 13.5
13. [TrpLog_ROVn] (n=1, 2)
The tripping logic setting is used to specify which breakers will be tripped when stage n of
zero-sequence overvoltage protection operates. Please refer to the description of the setting
14. [VEBI_ROV_XXX] (XXX=HVS, MVS, LVS)
This setting is the VEBI setting of enabling zero-sequence overvoltage protection of some side.
Please refer to the setting [VEBI_Diff] in section 3.2.5 for details
Input signals of zero-sequence overvoltage protection are list in the following table.

Binary input of enabling zero-sequence overvoltage protection of
1 EBI_ROV_HVS
HV side.
Binary input of enabling zero-sequenceovervoltage protection of
2 EBI_ROV_MVS
MV side.


Binary input of enabling zero-sequenceovervoltage protection of LV
3 EBI_ROV_LVS
side.
Output signals of overvoltage protection are list in the following table.

1 Op_ROV1_HVS Zero-sequence overvoltage protection stage 1 of HV side operates.
2 Op_ROV2_HVS Zero-sequence overvoltage protection stage 2 of HV side operates.
3 Op_ROV1_MVS Zero-sequence overvoltage protection stage 1 of MV side operates.
4 Op_ROV2_MVS Zero-sequence overvoltage protection stage 2 of MV side operates.
5 Op_ROV1_LVS Zero-sequence overvoltage protection stage 1 of LV side operates.
6 Op_ROV2_LVS Zero-sequence overvoltage protection stage 2 of LV side operates.
Fault detector of zero-sequence overvoltage protection of HV side
7 FD_ROV_HVS
picks up.
Fault detector of zero-sequence overvoltage protection of MV side
8 FD_ROV_MVS
picks up.
Fault detector of zero-sequence overvoltage protection of LV side
9 FD_ROV_LVS
picks up.
module.
3.13 Undervoltage Protection (UV)
Three undervoltage protection elements of HV, MV, and LV sides are provided with totally same
configuration.
The pickup of this fault detector will enable definite-time undervoltage protection of corresponding
side, which operation criterion is as follows.
U1 <1.05x Min([V_UV1], [V_UV2]) (Equation 3.13-1)
Where:
U1 is the positive-sequence voltage of one side.

[V_UV1] and [V_UV2] are the voltage settings of stage 1 and stage 2 of definite-time overvoltage
protection of corresponding side respectively.
The calculation of the fault detector of undervoltage protection will not be carried out when any of
the following three conditions is met.
1) The positive-sequence voltage is greater than 30V or negative-sequence voltage is less than
8V.
2) VT is out of service.
3) The following du/dt blocking equation is met.
Two stages of zero-sequence overvoltage protection are equipped for each side of transformer,
and the operation equation is as follows.
U 1 <[V_UVn] (Equation 3.13-2)
Where:
U1 is the positive-sequence voltage of one side.
[V_UVn] is the voltage setting of stage n (n=1, 2) of definite-time undervoltage protection of

corresponding side.
The equation of du/dt blocking function is as follows.
du / dt  [du/dt_UV] (Equation 3.13-3)
Where:
du / dt is the voltage slip speed and dt is equal to 5 cycle.
[du/dt_UV] is the setting of du/dt blocking undervoltage protection.
Undervoltage protection can be blocked by the voltage slip speed (du/dt). If the logic setting
[En_du/dt_UVn] (n=1 or 2) is set as “1”, when (Equation 3.13-2) and (Equation 3.13-3) are met, it
is decided that a fault occurred and the corresponding stage of undervoltage protection is blocked
at the same time for the purpose of to wait for other related protections operating. If the logic
setting is set as “0”, when (Equation 3.13-2) and (Equation 3.13-3) are met, the stage of
undervoltage protection is released to operate. The blocking signal will not reset until the system
voltage recovers i.e. the system voltage is greater than the setting [V_Recov].
3.13.3 Logic Scheme
Logic schemes of undervoltage protection of each side are same, and that of HV side is taken as

Figure 3.13-1 Logic diagram of zero-sequence overvoltage protection
Where:
U2 is negative-sequence voltage of HV side.
U1 is positive-sequence voltage of HV side.
HVS:[I_UVn] is the setting of stage n (n=1 or 2) of definite-time undervoltage protection of HV

side.
[EBI_UV_HVS] is the binary input of enabling UV protection of HV side.
[VEBI_UV_HVS] is the VEBI setting of enabling UV protection of HV side.
HVS:[En_UVn] is the logic setting of enabling stage n (n=1 or 2) of U protection of HV side.
du/dt is the voltage slip speed.
[du/dt_UV] is the setting of du/dt blocking undervoltage protection.
[En_du/dt_UVn] is the logic setting of enabling du/dt blocking stage n (n=1, or 2) of undervoltage
protection.
Flg_FD_UV_HVS is the internal flag indicating that operation criterion of UV protection is satisfied.
HVS:[t_UVn] is the time delay of stage n (n=1 or 2) of definite-time UV protection of HV side.
[Op_UVn_HVS] is the operation flag of stage n (n=1 or 2) of UV protection of HV side.

3.13.4 Setting
Table 3.13-1 Settings of undervoltage protection (HVS, MVS, LVS)

Lowest voltage threshold of fault
1 V_Recov 0.05~150V 0.01V
recovery.
Setting of du/dt blocking undervoltage
2 du/dt_UV 0.05~150V 0.01V/s
protection.
3 V_UV1 30~150V 0.01V Voltage setting of UV stage 1
4 t_UV1 0.05~20s 0.001s Time delay of UV stage 1
0: disable Logic setting of enabling/disabling UV
5 En_UV1 0, 1
1: enable stage 1
0: disable Logic setting of enabling/disabling du/dt
6 En_du/dt_UV1 0, 1
1: enable blocking function for UV stage 1.
7 TrpLog_UV1 0000~FFFF Tripping logic setting of UV stage 1.
8 V_UV2 30~150V 0.01V Voltage setting of UV stage 2.
9 t_UV2 0.05~20s 0.001s Time delay of UV stage 2.
0: disable Logic setting of enabling/disabling UV
10 En_UV2 0, 1
1: enable stage 2.
0: disable Logic setting of enabling/disabling du/dt
11 En_du/dt_UV2 0, 1
1: enable blocking function for UV stage 2.
12 TrpLog_UV2 0000~FFFF Tripping logic setting of UV stage 2.
VEBI_UV_XXX
0: disable VEBI setting of enabling/disabling UV
13 (XXX=HVS, MVS, 0, 1
1: enable protection of corresponding side.
LVS)
1. [V_Recov]
The setting is the lowest voltage threshold of fault recovery, i.e. the recognized normal level of voltage
after a fault is eliminated.
After some stage of undervoltage protection is blocked by du/dt, the stage undervoltage protection will
not be released to operate unless that system voltage increases to be greater than the setting
[V_Recov].
Recommended value: 0.7~0.9* U n ( U n is the secondary rated voltage of the corresponding
side)
2. [ du/dt_UV]
The setting of du/dt blocking undervoltage protection is set to avoid the undervoltage protection
operating during a short-circuit fault. When the variation of system voltage is greater than the

setting, some stage of undervoltage protection can be blocked if the corresponding logic setting of
the stage protection is enabled.
Recommended value: 1.2 U n / s.
13. [V_UVn] (n=1, 2)
This is the voltage setting of stage n (n=1, 2) of undervoltage protection, which should be set
according to voltage control strategy.
14. [t_UVn] (n=1, 2)
This is the time delay of stage n (n=1, 2) of undervoltage protection, which should be set according
to voltage control strategy.
15. [En_UVn] (n=1, 2)
This is the logic setting of enabling stage n (n=1, 2) of undervoltage protection, which should be
set according to he actual number of load shedding stage.
16. [En_du/dt_UV4n] (n=1, 2)
This is the logic setting of enabling stage n (n=1, 2) of undervoltage protection being blocking by
du/dt, which should be set according to requirements.
17. [TrpLog_UVn] (n=1, 2)

The tripping logic setting is used to specify which breakers will be tripped when stage n of
overvoltage protection operates. Please refer to the description of the setting [TrpLog_Diff] in
18. [VEBI_UV_XXX] (XXX=HVS, MVS, LVS)
This setting is the VEBI setting of enabling undervoltage protection of some side. Please refer to
the setting [VEBI_Diff] in section 3.2.5 for details.
Input signals of undervoltage protection are list in the following table.

1 EBI_UV_HVS Binary input of enabling undervoltage protection of HV side.
2 EBI_UV_MVS Binary input of enabling undervoltage protection of MV side.
3 EBI_UV_LVS Binary input of enabling undervoltage protection of LV side.


Output signals of undervoltage protection are list in the following table.

1 Op_ROV1_HVS Undervoltage protection stage 1 of HV side operates.
2 Op_ROV2_HVS Undervoltage protection stage 2 of HV side operates.
3 Op_ROV1_MVS Undervoltage protection stage 1 of MV side operates.
4 Op_ROV2_MVS Undervoltage protection stage 2 of MV side operates.
5 Op_ROV1_LVS Undervoltage protection stage 1 of LV side operates.
6 Op_ROV2_LVS Undervoltage protection stage 2 of LV side operates.
7 FD_ROV_HVS Fault detector of undervoltage protection of HV side picks up.
8 FD_ROV_MVS Fault detector of undervoltage protection of MV side picks up.
9 FD_ROV_LVS Fault detector of undervoltage protection of LV side picks up.
module.
3.14 Thermal Overload Protection
Four thermal overload protection elements of HV, MV, and LV sides and common winding are
provided with totally same configuration.
When phase current of one side is greater than base current setting [Ib_ThOvLd], the fault
detector picks up to enable thermal overload protection at relevant side.

The heat generated within an item of plant, such as a cable or a transformer, is the resistive loss
(Ι2R x t). Thus, heating is directly proportional to current squared. The thermal time characteristic
used in the relay is therefore based on current squared, integrated over time. The relay
automatically uses the largest phase current for input to the thermal model.
Equipment is designed to operate continuously at a temperature corresponding to its full load

rating, where heat generated is balanced with heat dissipated by radiation etc. Over-temperature
conditions therefore occur when currents in excess of rating are allowed to flow for a period of
time.
Three thermal overload protection elements with the same characteristic and independent settings
are provided for each side of transformer, and their thermal time characteristic defined in IEC

60255-8 follows the equation:
I 2 I 2p
t 
ln (Equation 3.14-1)
I ( k 
2
IB ) 2
Where:
t is time to trip, following application of the overload current.

 is thermal time constant of the protected plant, i.e. the setting [ThTime_ThOvLd]
I is maximum phase current of a side.
I p is steady-state pre-loading current before application of the overload.
I B is base current , i.e. the setting [Ib_ThOvLd].
k is thermal overload coefficient, i.e. [k_ThOvLd], and k 

I B is the minimum steady state trip
current with infinite operating time, and also called full load rating.
Thermal overload protection provides tripping function, sending alarm signal function and sending
blocking signal for closing breaker, and the protection can be enabled or disabled by the logic
setting [En_ThOvLd]. When the heat accumulation of winding is greater than setting
[k_Trp_ThOvLd] or [k_Alm_ThOvLd], the protection operates to trip circuit breaker or to send
alarm signal. After thermal overload protection operates to trip, heat accumulation can not
dissipate in short time, so two contacts “BO_ThOvLd_Blk_ClsCB”are provided to block closing
circuit breaker. When heat accumulation value is less than 0.7x[k_Trp_ThOvLd], the contacts drop
off.
NOTE: When binary input [EBI_ThemOvLd_XXX] （ XXX represents HVS, MVS, LVS etc.）
is de-energized, the heat accumulation is cleared and set as “0”automatically.
3.14.3 Logic Scheme
Logic schemes of thermal overload protection of each side are same, and that of HV side is taken
as an example to show the logic diagram.

Figure 3.14-1 Logic diagram of thermal overload protection
Where:
Accu_ThOvLd is the heat accumulation value of thermal overload protection of HV side.
HVS:[k_Trp_ThOvLd] is the thermal overload coefficient for tripping of HV side.
HVS:[k_Alm_ThOvLd] is the thermal overload coefficient for alarming of HV side.
[EBI_ThOvLd_HVS] is the binary input of enabling thermal overload protection of HV side.
[VEBI_BakProt_HVS] is the VEBI setting of enabling thermal overload protection of HV side.
HVS:[En_ThOvLd] is the logic setting of enabling thermal overload protections of HV side.
Flg_FD_ThOvLd_HVS is the internal flag indicating that the fault detector of thermal overload
[Op_ThOvLd_HVS] is the operation flag of thermal overload tripping element of HV side.
[Alm_ThOvLd_HVS] is the operation flag of thermal overload alarm element.
[Alm_ThOvLd_Blk_ClsCB_HVS] is the operation flag of thermal overload for blocking closing

circuit breaker of HV side.
3.14.4 Setting
Table 3.14-1 Settings of thermal overload protection (HVS, MVS, LVS, CW)
Base current ( I B ) of thermal

1 Ib_ThOvLd 0.05~150A 0.01A
overload protection of HV side.
Transformer thermal time constant
2 ThTime_ThOvLd 0~200min 0.01min
( ) of HV side.
3 k_Trp_ThOvLd 0.01~200 0.01 Thermal overload coefficient ( k ) for


tripping.
Thermal overload coefficient ( k ) for

4 k_Alm_ThOvLd 0.01~200 0.01
alarming.
5 En_ThOvLd 0, 1
1: enable thermal overload protection
Tripping logic setting of thermal
6 TrpLog_ThOvLd 0000~FFFF
overload protection
VEBI_ThOvLd_XXX VEBI setting of enabling/disabling
0: disable
7 (XXX=HVS, MVS, LVS, 0, 1 thermal overload protection of the
1: enable
CW) corresponding side
1. [Ib_ThOvLd]
This is the base current ( I B ) of thermal overload protection, which is generally recommended to
be set equal to rated current of the transformer.
2. [ThTime_ThOvLd]
This the thermal time constant ( )decided by the thermal characteristic of the transformer
winding.
3. [k_Trp_ThOvLd]
This is the hermal overload coefficient ( k ) for tripping shall be set according actual requirements,
and generally be set as 1.2~1.5.
4. [k_Alm_ThOvLd]
This is the thermal overload coefficient ( k ) for alarming shall be set according to actual
requirements, and generally be set as 1.1~1.3.
5. [En_ThOvLd]
The logic setting is used to enable or disable thermal overload protection.
“0”disable the protection; “1”: enable the protection.
6. [TrpLog_ThOvLd]
The tripping logic setting is used to specify which breakers will be tripped when thermal overload
details.

7. [VEBI_ThOvLd_XXX] (XXX=HVS, MVS, LVS, CW)
This setting is the VEBI setting of enabling thermal overload protection of some side. Please refer
to the setting [VEBI_Diff] in section 3.2.5 for details.
Input signals of undervoltage protection are list in the following table.

1 EBI_ThOvLd_HVS Binary input of enabling thermal overload protection of HV side.
2 EBI_ThOvLd _MVS Binary input of enabling thermal overload protection of MV side.
3 EBI_ThOvLd _LVS Binary input of enabling thermal overload protection of LV side.
Binary input of enabling thermal overload protection of common
4 EBI_ThOvLd _CW
winding.
Output signals of thermal overload protection are list in the following table.

1 Op_ThOvLd_HVS Thermal overload protection of HV side operates to trip.
2 Op_ThOvLd_MVS Thermal overload protection of MV side operates to trip.
3 Op_ThOvLd_LVS Thermal overload protection of LV side operates to trip.
4 Op_ThOvLd_CW Thermal overload protection of common winding operates to trip.
5 FD_ThOvLd_HVS Fault detector of thermal overload protection of HV side operates.
6 FD_ROV_MVS Fault detector of thermal overload protection of MV side operates.
7 FD_ROV_LVS Fault detector of thermal overload protection of LV side operates.
Fault detector of thermal overload protection of common winding
8 FD_ROV_LVS
operates.
module.
9 Alm_ThOvLd_HVS Thermal overload alarm element of HV side operates.
10 Alm_ThOvLd_MVS Thermal overload alarm element of MV side operates.
11 Alm_ThOvLd_LVS Thermal overload alarm element of LV side operates.
12 Alm_ThOvLd_CW Thermal overload alarm element of common winding operates.
Alm_ThOvLd_Blk_ Thermal overload element of HV side for blocking close circuit
13
ClsCB_HVS breaker operates.


Alm_ThOvLd_Blk_ Thermal overload element of MV side for blocking close circuit
14
ClsCB_MVS breaker operates.
Alm_ThOvLd_Blk_ Thermal overload element of LV side for blocking close circuit
15
ClsCB_LVS breaker e operates.
Alm_ThOvLd_Blk_ Thermal overload element of common winding for blocking close
16
ClsCB_CW circuit breaker operates.
3.15 Breaker Failure Protection (BFP)
Three breaker failure protections of HV, MV, and LV sides are provided with totally same
configuration. When trip signal from those protection relay is received, the protection operate to
trip each side breaker of transformer.
When operation criteria (refer to the following section) are satisfied, the corresponding fault
detector picks up.
3.15.2 Protection Theory
When the binary input of external tripping is energized and current element picks up, a trip
command will be issued after a delay to trip circuit breakers at each side of transformer.
Current criteria include phase current criterion, zero-sequence current criterion,

negative-sequence current criterion and DPFC current criterion. If any current criterion is satisfied
and current flowing through the protective equipment is detected, current element of breaker
failure protection picks up.
1) Phase current criterion：
I _ max [I_OC_BFP] (Equation 3.15-1)
Where:
I _ max is the maximum value of three phase-current of some side.

[I_OC_BFP] is the current setting of breaker failure protection of the corresponding side.
2) Zero-sequence current criterion：
3I0 >[I_ROC_BFP] (Equation 3.15-2)
Where:
3I0 is three times calculated zero-sequence current of some side.

[I_ROC_BFP] is zero-sequence current of breaker failure protection of the corresponding side.
3) Negative-sequence current criterion：
I2> [I_NegOC_BFP] (Equation 3.15-3)
Where:
I2 is negative-sequence current of some side.
[I_NegOC_BFP] is negative-sequence current of breaker failure protection of the corresponding

side.
4) DPFC current criteria：
There is no setting for user to configure in the criteria.
I 1.25 * I t I th (Equation 3.15-4)
Where:
It is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold voltage is
slightly greater than the unbalance voltage, multiple 1.25 of the deviation component is
reasonable.
I is the half-wave calculated of phase-to-phase current.
I th is the fixed threshold of 0.1 In and does not need to be set on site.
When the binary input [BI_ExtTrp_BFP] is keeping being energized for 10s, the alarm signal
[Alm_BI_ExtTrp_BFP] is issued with blocking breaker failure protection.
3.15.3 Logic Scheme
Logic schemes of breaker failure protection of each side are same, and that of HV side is taken as

I _ max
I _ max
I 1 . 25* I t I th
Figure 3.15-1 Logic diagram of thermal overload tripping element
Where:
In is rated secondary current of CT.
I _ max is the maximum value of three phase-current of HV side.

3I0 is three times calculated zero-sequence current of HV side.
I2 is negative-sequence current of HV side.
HVS: [I_OC_BFP] is the current setting of breaker failure protection of the corresponding side.
HVS: [I_ROC_BFP] is zero-sequence current of breaker failure protection of the corresponding

side.
HVS: [I_NegOC_BFP] is negative-sequence current of breaker failure protection of the

corresponding side.
[EBI_BFP_HVS] is the binary input of enabling breaker failure protection of HV side.
[VEBI_BFP_HVS] is the VEBI setting of enabling breaker failure protection of HV side.
HVS:[En_BFP] is the logic setting of enabling breaker failure protection of HV side.
[BI_ExtTrp_BFP_HVS] is the binary input of external tripping signal to initiate breaker failure
Flg_FD_BFP_HVS is the internal flag indicating that fault detector of breaker failure protection of
HV side picks up.
HVS:[t_BFP] is the time delay of breaker failure protection.
[Op_BFI_HVS] is the operation flag of breaker failure protection.

Please refer to above section for descriptions of other symbols.
3.15.4 Setting
Table 3.15-1 Settings of breaker failure protection (HVS, MVS, LVS)

Current setting of phase current
1 I_OC_BFP 0.05~150A 0.01A
criterion.
Current setting of zero-sequence
2 I_ROC_BFP 0.05~150A 0.01A
current criterion.
Current setting of negative-sequence
3 I_NegOC_BFP 0.05~150A 0.01A
current criterion.
Time delay of breaker failure
4 t_BFP 0 ~20s 0.001s
protection.
5 En_OC_Ctrl_BFP 0/ 1
1: enable phase current criterion to control BFP
0: disable
6 En_NegOC_Ctrl_BFP 0/ 1 zero-sequence current criterion to
1: enable
control BFP element
0: disable
7 En_ROC_Ctrl_BFP 0/ 1 negative-sequence current criterion to
1: enable
control BFP element
En_DPFC_Curr_Ctrl_ 0: disable
8 0/ 1 DPFC current criterion to control BFP
BFP 1: enable
element
0: disable Logic setting of enabling/disabling BFP
9 En_BFP 0/ 1
1: enable element
10 TrpLog_BFP 0000~FFFF Tripping logic setting of BFP element
VEBI_BFP_XXX
0: disable VEBI setting of enabling/disabling BFP
11 (XXX=HVS, MVS, 0/ 1
1: enable element of the corresponding side
LVS)
1. [I_OC_BFP]
This is phase current setting of breaker failure protection, and it shall be set greater than the
normal load current.
I op Ie
Recommended value: = 1.1×
Ie is the rated current (secondary value) of the transformer.

2. [I_ROC_BFP]
This is the zero-sequence current setting of breaker failure protection.
I op0 In
I n is the secondary rated current of the mutual inductor.
3. [I_NegOC_BFP]
This is the negative-sequence current setting of breaker failure protection.
I op2 In
I n is the secondary rated current of the mutual inductor.
4. [t_BFP]
This is the time delay of breaker failure protection..
If other protection operation contacts are connected to PCS-978 to initiate breaker failure
protection, the time delay shall be greater than the maximum time of circuit beaker being tripped.
Recommended value: 2s~2.5s.
If breaker failure protection contacts from other protection are connected to PCS-978, the contact
can be used to intertrip circuit breakers of each side of transformer and the setting can be set as
0.05s.
5. [En_OC_Ctrl_BFP]
This is the logic setting of enabling phase current element to control breaker failure protection.
“0”: disabling the control element; “1”: enabling the control element.
6. [En_NegOC_Ctrl_BFP]
This is the logic setting of enabling negative-sequence current element to control breaker failure
protection.
7. [En_ROC_Ctrl_BFP]
This is the logic setting of enabling zero-sequence current element to control breaker failure
protection.
8. [En_DPFC_Curr_Ctrl_BFP]
This is the logic setting of enabling DPFC current element to control breaker failure protection.

9. [En_BFP]:
This is the logic setting of enabling breaker failure protection, which not only can be used for
independent breaker failure protection, but also can be used to intertrip circuit breakers of each
side of main transformer. If this protection is used as breaker failure protection, it only can be used
at one side with single circuit breaker. If there are two or more circuit breakers at one side, then
this protection can not be used as independent breaker failure protection. It has no restriction
when being used as intertripping function.
8. [TrpLog_BFP]
The tripping logic setting is used to specify which breakers will be tripped when breaker failure
details.
9. [VEBI_BFP_XXX] (XXX=HVS, MVS, LVS)
This setting is the VEBI setting of enabling breaker failure protection of some side. Please refer to
the setting [VEBI_Diff] in section 3.2.5 for details.

Input signals of breaker failure protection are list in the following table.

1 EBI_BFP_HVS Binary input of enabling breaker failure protection of HV side.
2 EBI_BFP_MVS Binary input of enabling breaker failure protection of MV side.
3 EBI_BFP_LVS Binary input of enabling breaker failure protection of LV side.
Binary input of external tripping signal to initiate BFP element of HV
4 BI_ExtTrp_BFP_HVS
side.
5 BI_ExtTrp_BFP_MVS
side.
6 BI_ExtTrp_BFP_LVS
side.
No.4~No.6 items are binary inputs of external tripping.
Output signals of breaker failure protection are list in the following table.

Breaker failure protection of HV side operates to trip each side of
1 Op_BFP_HVS
transformer.


Breaker failure protection of MV side operates to trip each side of
2 Op_BFP_MVS
transformer.
Breaker failure protection of LV side operates to trip each side of
3 Op_BFP_LVS
transformer.
4 FD_BFP _HVS Fault detector of breaker failure protection of HV side picks up.
5 FD_BFP_MVS Fault detector of breaker failure protection of HV side picks up.
6 FD_BFP_LVS Fault detector of breaker failure protection of HV side picks up.
module.
Alm_BI_ExtTrp_BFP
7 Binary input of external tripping signal of HV side is abnormal.
_HVS
Alm_BI_ExtTrp_BFP
8 Binary input of external tripping signal of MV side is abnormal.
_MVS
Alm_BI_ExtTrp_BFP
9 Binary input of external tripping signal of LV side is abnormal.
_LVS
No.7~No9 items are alarm reports of equipment operation.
3.16 Overload Alarm Element
Four overload alarm elements of HV, MV, and LV sides and common winding (CW) are provided
with totally same configuration.
3.16.1 Principle
When following criterion is satisfied, overload alarm element operates to send its alarm
message after the corresponding delay and output contacts pick up at the same.
I _ max >[I_Alm_OvLdn] (Equation 3.16-1)
Where:
[I_Alm_OvLdn] is the current setting of stage n (n=1, or 2) overload alarm element.
3.16.2 Logic Scheme
Logic schemes of overload alarm element of each side are same, and that of HV side is taken as

I _ max
Figure 3.16-1 Logic diagram of overload alarm element
Where:
I _ max
is the maximum value of three-phase current of HV side.
HVS:[En_Alm_OvLdn] is the setting of stage n (n=1 or 2) of overload alarm element of HV side.
HVS:[t_Alm_OvLdn] is the delay of stage n (n=1 or 2) of overload alarm element of HV side.
[Alm_OvLdn_HVS] is the operation flag of stage n (n=1 or 2) of overload alarm element of HV

side.
3.16.3 Setting
Table 3.16-1 Settings of overload alarm element (HVS, MVS, LVS, CW)

Current setting of stage 1 of
1 I_Alm_OvLd1 0.05~150A 0.01A
overload alarm element.
Time delay of stage 1 of
2 t_Alm_OvLd1 0~20s 0.001s
Logic setting of
3 En_Alm_OvLd1 0, 1 enabling/disabling stage 1 of
Current setting of stage 2 of
4 I_Alm_OvLd2 0.05~150A 0.01A
Time delay of stage 2 of
5 t_Alm_OvLd2 0~20s 0.001s
Logic setting of
6 En_Alm_OvLd2 0, 1 enabling/disabling stage 2 of
1. [I_Alm_OvLdn] (n=1, 2)
The current setting of overload alarm element of some side shall be greater than the normally
operating load current of the transformer.
Iop K * Ie
,
Where

K refers to reliability coefficient and generally 1.1~1.2 is taken
Ie is secondary rated transformer voltage of the corresponding side.
2. [t_Alm_OvLdn] (n=1, 2)
This is the time delay of some stage of overload alarm element of some side.
The setting is set according to actual requiems and recommended value 6s~10s.
3. [En_Alm_OvLdn] (n=1, 2)
The logic setting is used to enable or disable some stage of overload alarm element of some side.
“0”disable the alarm element; “1”enable the alarm element.
Stage 1 of overload alarm element is recommended to be enabled.

Output signals of overload alarm element are list in the following table.

1 Alm_OvLd1_HVS Stage 1 of overload alarm element of HV side operates.
3 Alm_OvLd1_MVS Stage 1 of overload alarm element of MV side operates.
5 Alm_OvLd1_LVS Stage 1 of overload alarm element of LV side operates.
Stage 1 of overload alarm element of common winding
7 Alm_OvLd1_CW
operates.
8 Alm_OvLd2_CW
operates.
No.1~No.8 items are alarm reports equipment operation.
3.17 Initiating Cooler Element
Four overload for initiating cooler elements of HV, MV, and LV sides and common winding (CW)
are provided with totally same configuration.
3.17.1 Principle
When following criterion is satisfied, overload for initiating cooler element operates to send its
alarm message after the corresponding delay and output contacts pick up at the same.

I _ max >[I_InitCooln_OvLd] (Equation 3.17-1)
Where:
[I_InitCooln_OvLd] is the current setting of stage n (n=1, or 2) of overload for initiating cooler.
3.17.2 Logic Scheme
Logic schemes of overload for initiating cooler element of each side are same, and that of HV side
is taken as an example to show the logic diagram.
I _ max
Figure 3.17-1 Logic diagram of overload for initiating cooler element
Where:
I _ max
HVS:[En_InitCooln_OvLd] is the setting of stage n (n=1 or 2) of overload for initiating cooler

element of HV side.
HVS:[t_InitCooln_OvLd] is the delay of stage n (n=1 or 2) of overload for initiating cooler element
of HV side.
[Alm_InitCooln_OvLd_HVS] is the operation flag of stage n (n=1 or 2) of overload for initiating

cooler element of HV side.
3.17.3 Setting
Table 3.17-1 Settings of overload for initiating cooler element (HVS, MVS, LVS, CW )

Current setting of stage 1 of overload for
1 I_InitCool1_OvLd 0.05~150A 0.01A
initiating cooler element.
Time delay of stage 1 of overload for
2 t_InitCool1_OvLd 0~20s 0.001s
3 En_InitCool1_OvLd 0, 1
of overload for initiating cooler element.
4 I_InitCool2_OvLd 0.05~150A 0.01A
5 t_InitCool2_OvLd 0~20s 0.001s


6 En_InitCool2_OvLd 0, 1
of overload for initiating cooler element.
1. [I_InitCool_OvLdn] (n=1, 2)
This is the current setting of some stage of overload for initiating cooler element of some side,
which is set as followings:
Iop K * Ie
,
Where
2. [t_InitCool_OvLdn] (n=1, 2)
This is the time delay of some stage of overload for initiating cooler element of some side.
Recommended value: 1s~5s.
3. [En_InitCool_OvLdn] (n=1, 2)
The logic setting is used to enable or disable of some stage of overload for initiating cooler
element of some side.
“0”disable the initiating cooler element; “1”: enable the initiating cooler element.
The setting shall be set according to the actual cooling equipment and if an air cooler is equipped,
the overload for initiating cooler element is recommended to be enabled.
Output signals of overload for initiating element are list in the following table.

Stage 1 of overload for initiating cooler element of HV side
1 Alm_InitCool1_OvLd_HVS
operates.
Stage 2 of overload for initiating cooler element of HV side
2 Alm_InitCool2_OvLd_HVS
operates.
Stage 1 of overload for initiating cooler element of MV side
3 Alm_InitCool1_OvLd_MVS
operates.
Stage 2 of overload for initiating cooler element of MV side
4 Alm_InitCool2_OvLd_MVS
operates.


Stage 1 of overload for initiating cooler element of LV side
5 Alm_InitCool1_OvLd_LVS
operates.
Stage 2of overload for initiating cooler element of LV side
6 Alm_InitCool2_OvLd_LVS
operates.
Stage 1 of overload for initiating cooler element of common
7 Alm_InitCool1_OvLd_CW
winding operates.
Stage 2 of overload for initiating cooler element of common
8 Alm_InitCool2_OvLd_CW
winding operates.
3.18 Blocking On-load Tap Change Element
Four overload for blocking on-load tap change (OLTC) elements of HV, MV, and LV sides and
common winding are provided with totally same configuration.
3.18.1 Principle
When following criterion is satisfied, overload for blocking on-load tap change element operates to
send its alarm message after the corresponding delay and output contacts pick up at the same.
I _ max >[I_BlkOLTC_OvLd] (Equation 3.18-1)
Where:
[I_BlkOLTC_OvLd] is the current setting of overload for blocking OLTC.
3.18.2 Logic Scheme
Logic schemes of overload for blocking OLTC element of each side are same, and that of HV side
is taken as an example to show the logic diagram.
I _ max
Figure 3.18-1 Logic diagram of overload for blocking OLTC element
Where:
I _ max
HVS:[En_BlkOLTC_OvLd] is the setting of overload for blocking OLTC element of HV side.

HVS:[t_BlkOLTC_OvLd] is the delay of overload for blocking OTLC element of HV side.
[Alm_BlkOLTC_OvLd_HVS] is the operation flag of overload for blocking OTLC element of HV

side.
3.18.3 Setting
Table 3.18-1 Settings of overload for blocking OLTC element (HVS, MVS, LVS, CW)

1 I_ BlkOLTC _OvLd 0.05~150A 0.01A
blocking OLTC element.
2 t_BlkOLTC_OvLd 0~20s 0.001s
blocking OLTC element.
3 En_BlkOLTC_OvLd 0, 1
of overload for blocking OLTC element.
1. [I_BlkOTLC_OvLd]
This is the current setting of overload for blocking OLTC of some side, which is set as followings:
Iop K * Ie
,
Where
2. [t_BlkOLTC_OvLd]
This is the time delay of overload for blocking OLTC element of some side.
Recommended value: 0s~5s.
3. [En_BlkOLTC_OvLd]
The logic setting is used to enable or disable of overload for blocking OLTC element of some side.
“0”disable the initiating cooler element; “1”: enable the initiating cooler element.
The setting shall be set according to the actual requirements.
Output signals of overload for blocking OLTC are list in the following table.


1 Alm_BlkOLTC_OvLd_HVS Overload for blocking OLTC element of HV side operates.
2 Alm_BlkOLTC_OvLd_MVS Overload for blocking OLTC element of MV side operates.
3 Alm_BlkOLTC_OvLd_LVS Overload for blocking OLTC element of LV side operates.
Overload for blocking OLTC element of common winding
4 Alm_BlkOLTC_OvLd_CW
operates.
No.1~No4 items are alarm reports equipment operation.
3.19 Zero-sequence Overvoltage Alarm Element
Four zero-sequence overvoltage alarm elements of HV, MV, and LV sides and common winding
3.19.1 Principle
When following criterion is satisfied, zero-sequence overvoltage alarm element operates to
send its alarm message after the corresponding delay and output contacts pick up at the
same.
3U0>[I_Alm_ROV] (Equation 3.19-1)
Where:
3U0 is the zero-sequence voltage from broken-delta VT of one side.
[I_Alm_ROV] is the voltage setting of zero-sequence overvoltage alarm element.
3.19.2 Logic Scheme
Logic schemes of zero-sequence overvoltage alarm element of each side are same, and that of
HV side is taken as an example to show the logic diagram.
Figure 3.19-1 Logic diagram of zero-sequence overvoltage alarm element
Where:
3U0 is the zero-sequence voltage from broken-delta VT of one side.
HVS:[En_Alm_ROV] is the setting of zero-sequence overvoltage element of HV side.
HVS:[t_Alm_ROV] is the delay of zero-sequence overvoltage alarm element of HV side.
[Alm_ROV_HVS] is the operation flag of zero-sequence overvoltage alarm element of HV side.

3.19.3 Setting
Table 3.19-1 Settings of zero-sequence overvoltage alarm element (HVS, MVS, LVS, CW)

Voltage setting of zero-sequence
1 I_Alm_ROV 0.05~300V 0.01V
overvoltage alarm element.
Time delay of zero-sequence overvoltage
2 t_Alm_ROV 0~20s 0.001s
alarm element.
0:disable Logic setting of enabling/disabling
3 En_Alm_ROV 0, 1
1:enable zero-sequence overvoltage alarm element.
1. [V_Alm_ROV]
This is voltage setting of zero-sequence overvoltage alarm element of some side, when LV side is
connected to an ungrounded system.
Recommended value: 15V~40V.
2. [t_Alm_ROV]
This is the time delay of zero-sequence overvoltage alarm element of some side, which is set as
0.2~5s.
3. [En_Alm_ROV]
The logic setting is used to enable or disable zero-sequence overvoltage alarm element of some
side.
“0”disable the alarm element;
“1”enable the alarm element
When the side is connected to ungrounded system, it is recommended to enable the element.
Output signals of zero-sequence overvoltage alarm element are list in the following table.

1 Alm_ROV_HVS Zero-sequence overvoltage alarm element of HV side operates.
2 Alm_ROV_HVS Zero-sequence overvoltage alarm element of MV side operates.
3 Alm_ROV_HVS Zero-sequence overvoltage alarm element of LV side operates.
Zero-sequence overvoltage alarm element of common winding
4 Alm_ROV_CW
operates.

3.20 Zero-sequence Overcurrent Alarm Element
Four zero-sequence overcurrent alarm elements of HV, MV, and LV sides and common winding
3.20.1 Principle
When following criterion is satisfied, zero-sequence overcurrent alarm element operates to

send its alarm message after the corresponding delay and output contacts pick up at the
same.
3I0>[I_Alm_ROC] (Equation 3.20-1)
Where:
3I0 is the zero-sequence current from zero-sequence CT of one side.
[I_Alm_ROV] is the voltage setting of zero-sequence overcurrent alarm element.
3.20.2 Logic Scheme
Logic schemes of zero-sequence overcurrent alarm element of each side are same, and that of
HV side is taken as an example to show the logic diagram.
Figure 3.20-1 Logic diagram of zero-sequence overcurrent alarm element
Where:
3I0 is the zero-sequence current from zero-sequence CT of HV side.
HVS:[En_Alm_ROC] is the setting of zero-sequence overcurrent element of HV side.
HVS:[t_Alm_ROC] is the delay of zero-sequence overcurrent alarm element of HV side.
[Alm_ROC_HVS] is the operation flag of zero-sequence overcurrent alarm element of HV side.
3.20.3 Setting
Table 3.20-1 Settings of zero-sequence overcurrent alarm element (HVS, MVS, LVS, CW)

Current setting of zero-sequence
1 I_Alm_ROC 0.05~150A 0.01A
overcurrent alarm element.
Time delay of zero-sequence overcurrent
2 t_Alm_ROC 0~20s 0.001s
alarm element.
0:disable Logic setting of enabling/disabling
3 En_Alm_ROC 0, 1
1:enable zero-sequence overcurrent alarm element.

1. [V_Alm_ROC]
This is current setting of zero-sequence overcurrent alarm element of some side, which shall be
set according to system zero-sequence network structure and the actual measured maximum
zero-sequence current during normal operation.
The recommended value for the setting is 0.5 times minimum current setting of zero-sequence
overcurrent protection of the corresponding side and shall be greater than 0.1 I n ( In is the
secondary rated current of CT) at the same time
Recommended value: 15V~40V.
2. [t_Alm_ROC]
This is the time delay of zero-sequence overcurrent alarm element of some side, which is set as
10s.
3. [En_Alm_ROC]
The logic setting is used to enable or disable zero-sequence overcurrent alarm element of some
side.
“0”disable the alarm element;
“1”enable the alarm element
The zero-sequence overcurrent alarm element is not recommended to be enabled for the system
the load of which is long-time imbalance.

Output signals of zero-sequence overcurrent alarm element are list in the following table.

1 Alm_ROC_HVS Zero-sequence overcurrent alarm element of HV side operates.
2 Alm_ROC_MVS Zero-sequence overcurrent alarm element of MV side operates.
3 Alm_ROC_LVS Zero-sequence overcurrent alarm element of LV side operates.
Zero-sequence overcurrent alarm element of common winding
4 Alm_ROC_CW
operates.

3.21 Voltage Element
3.21.1 Principle
A voltage element is equipped to collect three-phase voltage and zero-sequence voltage of each
side and to carry out calculation, and then send the calculation result to other protective elements
which need that information. Voltage element includes single-phase and three-phase voltage
inputs.
Users can configure voltage input terminals of each side of transformer.
If one of following two criteria is met and there is no any one fault detector picked up, VT circuit
abnormality alarm will be issued after 10s. The abnormality alarm will be reset after 10s if
equipment returns to normal condition.
When the secondary phase-to-phase voltage of VT is equal to 100V:
1) Positive sequence voltage is less than 30 V and any phase current is greater than 0.04 In.
2) Positive sequence voltage is less than 30 V and the breaker is in closed position;
3) The negative-sequence voltage is greater than 8 V and zero-sequence voltage is grater than
6V.
4) The negative-sequence voltage is greater than 8 V and negative-sequence voltage is grater

than positive-sequence voltage.
In the duration of abnormality, action of each element related to voltage is decided by the relevant
logic settings as mentioned in above sections.
NOTE: When VT of some side is out of service, criteria of VT circuit failure on that side
will be disabled automatically.
NOTE: For the secondary phase-to-phase voltage of VT is equal to 110V, the threshold
values for the voltage element will be changed correspondingly.
Input signals of current element are list in the following table. The name of each group current
input can be defined by user through PCS-PC software, and the related alarm message and
sampled value change correspondingly.

1 Ua_1
2 Ub_1 Input of the 1st group of three-phase voltage input
3 Uc_1


Input of the 1st group of zero-sequence voltage (i.e. broken-delta
4 3U0_1
voltage) input
5 Ua_2
6 Ub_2 Input of the 2nd group of three-phase voltage input
7 Uc_2
Input of the 2nd group of zero-sequence voltage (i.e. broken-delta
8 3U0_2
voltage) input
9 Ua_3
10 Ub_3 Input of the 3rd group of three-phase voltage input
11 Uc_3
Input of the 3rd group of zero-sequence voltage (i.e. broken-delta
12 3U0_3
voltage) input
No. 1~No. 12 items are voltage channel inputs.
Output signals of current element are list in the following two tables.

1 Alm_VTS_HVS Voltage transformer circuit of HV side is abnormal.
2 Alm_VTS_MVS Voltage transformer circuit of HV side is abnormal.
3 Alm_VTS_LVS Voltage transformer circuit of HV side is abnormal.
No. 1~No. 3 items are alarm reportes of equipment operation.

1 Ua_HVS
2 Ub_HVS Three-phase voltage of HV side.
3 Uc_HVS
4 3U0_Calc_HVS Three times calculated zero-sequence voltage of HV side.
Zero-sequence voltage from broken-delta winding of VT of HV
5 3U0_Delt_HVS
side.
6 U1_HVS Positive-sequence voltage of HV side
7 U2_HVS Negative-sequence voltage of HV side.
8 Ia_HVSn
9 Ib_HVSn Three-phase current of HV side n (n=1, 2).
10 Ic_HVSn
11 3I0_Calc_HVSn Three times calculated zero-sequence current of HV side n


(n=1, 2).
Zero-sequence current from zero-sequence CT at neutral point
12 3I0_NP_HVS
of HV side.
13 Ua_MVS
14 Ub_MVS Three-phase voltage of MV side.
15 Uc_MVS
16 3U0_Calc_MVS Three times calculated zero-sequence voltage of MV side.
Zero-sequence voltage from broken-delta winding of VT of MV
17 3U0_Delt_MVS
side.
18 U1_MVS Positive-sequence voltage of MV side
19 U2_MVS Negative-sequence voltage of MV side.
20 Ia_MVSn
21 Ib_MVSn Three-phase current of MV side n (n=1, 2).
22 Ic_MVSn
Three times calculated zero-sequence current of MV side n
23 3I0_Calc_MVSn
(n=1, 2).
24 3I0_NP_MVS
of MV side.
25 Ua_LVS
26 Ub_LVS Three-phase voltage of LV side.
27 Uc_LVS
28 3U0_Calc_LVS Three times calculated zero-sequence voltage of LV side.
Zero-sequence voltage from broken-delta winding of VT of LV
29 3U0_Delt_LVS
side.
30 U1_LVS Positive-sequence voltage of LV side
31 U2_LVS Negative-sequence voltage of LV side.
32 Ia_LVSn
33 Ib_LVSn Three-phase current of LV side n (n=1, 2).
34 Ic_LVSn
Three times calculated zero-sequence current of LV side n
35 3I0_Calc_LVSn
(n=1, 2).
36 3I0_NP_LVS
of LV side.
Angle between phase A and phase B currents of HV side n
37 Ang(Ia-Ib)_HVSn
(n=1, 2).
38 Ang(Ia-Ic)_HVSn Angle between phase B and phase C currents of HV side n


(n=1, 2).
Angle between phase A and phase B currents of MV side n
39 Ang(Ia-Ib)_MVSn
(n=1, 2).
Angle between phase B and phase C currents of MV side n
40 Ang(Ia-Ic)_MVSn
(n=1, 2).
Angle between phase A and phase B currents of LV side n (n=1,
41 Ang(Ia-Ib)_LVSn
2).
Angle between phase B and phase C currents of LV side n
42 Ang(Ia-Ic)_LVSn
(n=1, 2).
43 Ang(Ua-Ub)_HVS Angle between phase A and phase B voltages of HV side.
44 Ang(Ua-Uc)_HVS Angle between phase B and phase C voltages of HV side.
45 Ang(Ua-Ub)_MVS Angle between phase A and phase B voltages of MV side.
46 Ang(Ua-Uc)_MVS Angle between phase B and phase C voltages of MV side.
47 Ang(Ua-Ub)_LVS Angle between phase A and phase B voltages of LV side.
48 Ang(Ua-Uc)_LVS Angle between phase B and phase C voltages of LV side.
49 Ang(Ua-Ia)_HVS Angle between phase A voltage and current of HV side
50 Ang(Ub-Ib)_HVS Angle between phase B voltage and current of HV side
51 Ang(Uc-Ic)_HVS Angle between phase C voltage and current of HV side
52 Ang(Ua-Ia)_MVS Angle between phase A voltage and current of MV side
53 Ang(Ub-Ib)_MVS Angle between phase B voltage and current of MV side
54 Ang(Uc-Ic)_MVS Angle between phase C voltage and current of MV side
55 Ang(Ua-Ia)_LVS Angle between phase A voltage and current of LV side
56 Ang(Ub-Ib)_LVS Angle between phase B voltage and current of LV side
3.22 Current Element
3.22.1 Principle
A current element is equipped to collect three-phase voltage and zero-sequence voltage of each
side and to carry out calculation, and then send the calculation result to other protective elements
which need that information. Current element includes single-phase and three-phase voltage
inputs.
Users can configure voltage input terminals of each side of transformer.
When the negative-sequence current of some side is greater than 0.06In, CT circuit abnormality
alarm will be issued after 10s, and be reset after 10s if equipment returns to normal condition.

Input signals of current element are list in the following table. The name of each group current
input can be defined by user through PCS-PC software, and the related alarm message and
sampled value change correspondingly.

1 Ia_1
2 Ib_1 Values of the 1st group of three-phase current input.
3 Ic_1
4 3I0_1 Values of the 1st group of zero-sequence current input.
5 Ia_2
6 Ib_2 Values of the 2nd group of three-phase current input.
7 Ic_2
8 3I0_2 Values of the 2nd group of zero-sequence current input.
9 Ia_3
10 Ib_3 Values of the 3rd group of three-phase current input.
11 Ic_3
12 3I0_3 Values of the 3rd group of zero-sequence current input.
13 Ia_4
14 Ib_4 Values of the 4th group of three-phase current input.
15 Ic_4
16 3I0_4 Values of the 4th group of zero-sequence current input.
17 Ia_5
19 Ic_5
21 Ia_6
23 Ic_6
25 Ia_7
27 Ic_7
29 Ia_8 Values of the 8th group of three-phase current input.


30 Ib_8
31 Ic_8
33 Ia_9
35 Ic_9
37 Ia_10
39 Ic_10
No. 1~No. 40 items are current channel inputs.
Output signals of current element are list in the following table.

1 Alm_SensCTS_HVSn Current transformer circuit of HV side n (n=1, 2) is abnormal.
2 Alm_SensCTS_MVSn Current transformer circuit of MV side n (n=1, 2) is abnormal.
3 Alm_SensCTS_LVSn Current transformer circuit of LV side n (n=1, 2) is abnormal.
No. 1~No. 3 items are alarm reportes of equipment operation.
3.23 Tripping Output Element
3.23.1 General Description
Tripping output element consists of tripping matrix of protection element and programmable
tripping output element. Each protection element has its corresponding tripping logic setting used
to configure tripping output contacts of each element, and 10 programmable tripping output
elements are equipped for visualization programming of user level.
Tripping pulse of protection equipment shall be broadened and held to ensure circuit breakers are
tripped reliably after a tripping command is issued, which is realized by by tripping output element.
After any protection element operates, 120ms tripping pulse is issued at first. Then equipment
detects whether operation element drops off or not, if the protection element dropps off, tripping
pulse will be gone after 120ms, and if not, tripping pulse will be broadened and held until the
element drops off.

3.23.2 Tripping Matrix of Protection Element
Each protection element has its corresponding tripping logic setting used to configure tripping
output contacts of each element, and total 10 groups of tripping output contacts can be controlled
by tripping logic settings. Therefore, user can configure the tripping output contacts of each
protection element individually though the corresponding tripping logic setting, and following figure
shows the tripping matrix map of protection element.
10 Groups of Tripping Output Contacts

Tripping Logic Settings of Protection Element
1 2 3 4 5 6 7 8 9 10
[TrpLog_Diff]
HVS:[TrpLog_REF]
MVS:[TrpLog_REF]
LVS:[TrpLog_REF]
[TrpLog_OvExc]
[TrpLog_MR1]
HVS:[TrpLog_OC1]
HVS: [TrpLog_ROC1]
Figure 3.23-1 Tripping matrix map of protection element
 Tripping output contacts
10 groups of independent tripping output contacts can be defined to trip HV side, MV side, and
LVS side etc. Each group of tripping contacts can correspond to certaint amount of contacts on
binary output plug-in modules.
 Tripping logic settings
Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting of the equipment
is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutp10
TrpOutp9
TrpOutp8
TrpOutp7
TrpOutp6
TrpOutp5
TrpOutp4
TrpOutp3
TrpOutp2
TrpOutp1
Function
N/A
N/A
N/A
N/A
N/A
N/A
NOTE: “TrpOutput1”just means to drive 1st group of tripping output contacts to pickup
and please refer to chapter “Hardware Description”for details. .
The bit corresponding to the breaker to be tripped shall be set as“1”and other bits shall be “0”.
For example, if differential protection operates to make “TrpOutp1”, “TrpOutpu2”, “TrpOutp3”
contacts pickup, the bit “1”and bit “2”and bit “3”positions shall be filled with “1”and other bit
positions shall be filled with “0”. Then a hexadecimal number 0007H is formed as the tripping
output logic setting, i.e. [TrpLog_Diff] shall be set as “0007H”.
Please note that tripping output logic settings of the equipment have to be set on basis of
application-specific drawings.
3.23.3 Programmable Tripping Output Element
10 programmable tripping output elements with inputs, outputs and settings are provided for
visualization programming of user level.
Users can program output of existing elements by visualization programming software if existing
tripping output matrixes of protection element provided by protective equipment can not meet
application requirements completely.
For example, if user need stage 1 of overcurrent protection of HV side operate to issue trip
command after its operation criterion is satisfied “AND”receiving a binary input which can be a
blocking signal from other protection equipment, users can complete the function configuration as
following steps.
1) Set tripping logic setting of stage 1 of overcurrent protection of HV side as “0”, i.e.
[TrpLog_Diff]=0000H.
2) Finish required logic programming by visualization programming tool.
3) Connect final logic programming output to input of programming tripping output elment.
4) Set corresponding programmable tripping logic setting to complete the function configuration.
Please refer to logic chapter for detailed operation steps.
3.23.4 Setting
Table 3.23-1 Settings of programmable tripping output element
No. Setting Item Range Step

1 TrpLog_ProgTrp1 0000~FFFF Setting of programmable tripping output element 1.
2 TrpLog_ProgTrp2 0000~FFFF Setting of programmable tripping output element 2

No. Setting Item Range Step

1. [TrpLog_ProgTrpn] （X=1, 2, … , 10）
This is tripping logic setting of programmable tripping output element. If the programmable tripping
output element is used, please set the setting by referring to the setting [TrpLog_Diff] in section
3.2.5 for details, and if not, the setting is recommended to be set as 0000.

Input signals of programmable tripping output element are list in the following table.

1 Input_ProgTrp1 Input signal of programmable tripping output element 1.
No. 1 ~ No. 10 items are input signals of programmable tripping output element.
Output signals of programmable tripping output element are list in the following table.

1 Output_ProgTrp1 Output signal of programmable tripping output element 1.


No.1~No.10 items are output signals of programmable tripping output elements, which are
recorded as tripping reports.
3.24 Intermediate Variable Element
3.24.1 Principle
In order to better support logic programming function, 20 intermediate variables are provided.
The user can distribute the middle results of logic programming to intermediate variables, and
use the intermediate variables to carry out other logic programming. Not only intermediate
variable display is supported by the equipment, but also its state change report is recorded by the
equipment.

1 Input_IntVar1 Input signal of intermediate variable 1 for logic programming.


No. 1 ~ No. 20 items are input signals of programmable logic.
Table 3.24-2 Output signal

1 Output_IntVar1 Output signal of intermediate variable 1 for logic programming.
No. 1 ~ No. 20 items are output signals of programmable logic.

3.25 GOOSE Function
3.25.1 General Description
The relay also provides some auxiliary functions, such as on-line data metering, binary input
status, event and disturbance recording, etc. All these make the relay meet the demands of the
modern power grid requirements.
Besides traditional binary inputs and outputs can be connected to PCS equipments, GOOSE
binary inputs and outputs are supported by PCS equipments. In a digital substation supporting
GOOSE, GOOSE interfaces are connected to switches in the process level. A GOOSE.txt file
recording the related information of GOOSE input and output is exported at the same time when a
CID file is exported from a SCD file through a software tool. After the equipment parses the
GOOSE.txt, it sends out signals desired by other equipment on the network and receives its
desired signals (binary inputs). Because only an optical fiber is needed for the connection between
one equipment and other equipments, cables used in substation construction are reduced greatly.
During the normal operation of equipment, heart beat messages are sent out constantly for the
receiver detection, which improves the reliability of transmitting GOOSE si gnals. After PCS
equipment parses the GOOSE.txt file, it detects the desired heart beat messages according to
GOOSE control blocks. When those messages are not received during 2xTATL (TATL: Time Allow
to Live), the equipment will issue the alarm of link disconnection of the corresponding GOOSE
control block. Besides, the equipment checks the number of received data from a GOOSE control
block, and if the number is not consistence with the GOOSE.txt, an alarm message will be issued
at once.
Each output data is equipped with a sending VEBI setting. PCS protection equipment is equipped
with an output GOOSE control block associated with a GOOSE data set, which can meet the
requirement of most substations and also can be customized according to user needs. PCS
equipment supports maximum 64 GOSSE control blocks.
3.25.2 Setting
Table 3.25-1 GOOSE Settings
No. Setting Item Range Description

DefaultValue_GBI_XXX Default valve of GOOSE binary input
1 0/1
(XXX=1, 2, 3, … , 64) XXX (1, 2, 3, … , 64)
Setting used to define the name of
NameDef_GBI_Recv_XXX Maximum 10
2 GOOSE receiving binary input XXX
(XXX=1, 2, 3, … , 64), characters
(XXX=1, 2, 3, … , 64).
GOOSE VEBI setting of
GVEBI_TrpOut_XXX
3 0/1 enabling/disabling tripping output XXX
(XXX=1, 2, … , 16)
(XXX=1, 2, … , 16)


GVEBI_Sent_SpareXXX
4 0/1 enabling/disabling sending signal XXX
(XXX=1, 2,… 64)
(XXX=1, 2,… 20)
GVEBI_Recv_XXX
5 0/1 enabling/disabling receiving signal XXX
(XXX=1, 2, 3, … , 64)
(XXX=1, 2, 3, 4)
GOOSE VEBI setting of enabling
6 GVEBI_RemoteCfg 0/1 /disabling to configure GOOSE settings
remotely.
1. [DefaultValue_GBI_XXX] (XXX=1, 2, 3, … , 64)
These settings are displayed in the menu ”SETTINGS”-> “EQUIP SETTINGS”. When there is
an abnormality network communication, the binary input [GBI_XX] (XX=1, 2, 3, 4) is set as the
corresponding default value.
2. [NameDef_GBI_Recv_XXX] (XXX=1, 2, 3, … , 64)
These settings are displayed in the menu “SETTINGS” -> “EQUIP DESCRON”. When a
receiving GOOSE binary input is defined with a specific name, its corresponding alarm signal will
be changed simultaneously, but the corresponding default setting and GOOSE binary input are
not changed.
For example, if [NameDif_GBI_Recv_1] is defined as “TrpHVS”, then the corresponding alarm

messages [GAlm_Disc_NetA_1], [GAlm_Disc_NetB_1], [GAlm_CfgUnmatch_1] are changed
to the following three alarm messages:
[GAlm_Disc_NetA_TrpHVS], [GAlm_Disc_NetB_TrpHVS], [GAlm_CfgUnmatch_TrpHVS]
3. [GVEBI_TrpOut_XXX] (XXX=1, 2, … , 16), [GVEBI_Sent_SpareXXX] (XXX=1, 2, 3, … , 64)
These settings are called GOOSE functional VEBI settings and recorded as binary input
change report, which can be located in the menu "SETTINGS” -> “GOOSE VEBI
SETTINGS”.
4. [GVEBI_Recv_XXX] XXX=1, 2, 3, … , 64), [GVEBI_RemoteCfg]
These settings are called GOOSE VEBI settings and recorded as binary input change
reports, which can be located in the menu "SETTINGS”-> “GOOSE VEBI SETTINGS”.
Input signals for GOOSE function module are list in the following table.
Table 3.25-2 Input signals

1 OGBI_SpareXXX Original valve of GOOSE binary input signal XXX(XXX=1, 2,


(XXX=1, 2, 3, … , 64) 3, … , 64)
GBI_SpareXXX Valve of GOOSE binary input signal XXX (XXX=1, 2, 3, … , 64)
2
(XXX=1, 2, 3, … , 64) for protection calculations after checking.
No.1~No.2 items are two types of GOOSE binary inputs.
Output signals of GOOSE function module are list in following two tables.
Table 3.25-3 Output signals: report

GBO_SpareXXX GOOSE binary output signal XXX (XXX=1, 2, 3, … , 64)
1
(XXX=1, 2, 3, … , 64) for protection calculations after checking.
No.1 item is GOOSE binary output.
GOOSE alarm signal indicating that there is a network
2 GAlm_NetStorm_NetA
storm occurring on the network A.
GOOSE alarm signal indicating that there is a network
3 GAlm_NetStorm_NetB
storm occurring on the network B.
GOOSE alarm signal indicating that there is an error in
4 GAlm_ConfigFile
the GOOSE configuration file (i.e. GOOSE.txt).
GOOSE alarm signal indicating that network A for
GAlm_Disc_NetA_NameXXX
5 NameXXX is disconnected. (NameXXX is the name
(XXX=1, 2, 3, … , 64)
defined by the setting [NameDef_GBI_Recv_01XXX].)
GOOSE alarm signal indicating that network B for
GAlm_Disc_NetB_NameXXX
6 NameXXX is disconnected. (NameXXX is the name
(XXX=1, 2, 3, … , 64)
defined by the setting [NameDef_GBI_Recv_XXX].)
The GOOSE control blocks received on network and the
GAlm_CfgUnmatch_NameXXX GOOSE control blocks in GOOSE.txt file for NameXXX
7
(XXX=1, 2, 3, … , 64) are unmatched for NameXXX. (NameXXX is the name
defined by the setting [NameDef_GBI_Recv_XXX]).
No.2~No.7 items are GOOSE alarm reports. When any alarm message is issued, the LED “ALARM”
is lit without equipment being blocked. After the abnormality is removed, the equipment will return to
normal with the LED “ALARM”being distinguished automatically.
Handling suggestion:
1. Please check the related switches. (No1, No.2)
2. Please check the GOOSE configuration file (i.e. GOOSE.txt). (No.3)
3. Please check the network. (No.4, No.5)
4. Please check the GOOSE configuration file and the network. (No.6)
Table 3.25-4 Output signal: statistic data


Count the number of frames received through
1 N_RecvdFrame_GOOSE
GOOSE
Count the number of frames sent through
2 N_SentFrame_GOOSE
GOOSE.
Count the number of DMA (Direct Memory
3 N_Err_RecvdDMA_GOOSE
Access) error for receiving data through GOOSE.
Count the number of DMA errors for transmitting
4 N_Err_SentDMA_GOOSE
data through GOOSE.
Count the number of miscellaneous errors of
5 N_Err_Recvd_Misc_GOOSE
receiving data through GOOSE.
Count the number of miscellaneous errors for
6 N_Err_Sent_Misc_GOOSE
transmitting data through GOOSE.
Count the number of network storms occurred
7 N_NetStorm_GOOSE
through GOOSE.
Counter the number of memory errors of
8 N_Err_RecvdMemData_GOOSE
receiving data through GOOSE
Count the number of being failed to transmit data
9 N_Fail_Sent_GOOSE
through GOOSE.
Count the number of decoding errors through
10 N_Err_Decode_GOOSE
GOOSE.


Chapter 4 Automatic Supervision
Though the protection system is in non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail. When
equipment is in energizing process before the LED “HEALTHY”is on, the equipment needs to be
checked to ensure no errors. Therefore, the automatic supervision function, which checks the
health of the protection system when startup and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a fatal fault is detected during automatic supervision, the equipment will be blocked out. It
means that relay is out of service. Before you must re-energize the relays or reset CPU module
and MON module to make relay back into service, please find out the cause and inform the
factory.
When a failure is detected by the automatic supervision, it is followed with an LCD message, LED
indication and alarm contact outputs. At the same time event recording will record the failure alarm
which can be viewed in event recording report and be printed.
4.2 Relay Self-supervision
4.2.1 Relay Hardware Supervision
All chips on each module are monitored to ensure whether they are damaged or have errors. If
any one of them is detected damaged or having error, the corresponding alarm signal
[Alm_DSP_ProtBrd] or [Alm_DSP_FDBrd] is issued with equipment being blocked.
AC current and voltage samplings of protection DSP module and fault detector DSP module are
monitored and if the samples are detected to be wrong or inconsistent, an alarm [Alm_Sample] will
be issued and the relay will be blocked.
4.2.2 Output Tripping Circuit Supervision
State of binary outputs on each BO modules is continually monitored. If any abnormality is

detected, the alarm signal [Alm_TrpOut] will be issued with equipment being blocked.
4.2.3 Setting Checking
This relay has 10 setting groups, while only one is active at the same time. The settings of active
setting group are checked to ensure they are reasonable. If settings are checked to be
unreasonable or out of setting scopes, a corresponding alarm signal will be issued, and the
protective device is also blocked.

4.2.4 Opto-coupler Power Supervision
Positive power supply of opto-coupler is continually monitored, and if a failure or damage is

detected, then the alarm signal [Alm_Pwr_Opto] will be issued.
4.2.5 Fault Detector Element Supervision

If any fault detector on fault detector DSP module picks up, the corresponding binary input
changing report will be recorded in “BI CHG REPORT”menu with tripping report [Op_FD] being
issued.
If a fault detector on protection or fault detector DSP module keeps picking up for 10s, the
corresponding alarm signal [Alm_PersistFD_ProtBrd] or [Alm_PersistFD_FDBrd] will be issued
without equipment being blocked.
If the operating fault detector on fault detector DSP module is not inconsistent with the tripping
element on protection module, the alarm signal [Alm_InconsistFD] is issued without equipment
being blocked.
4.2.6 Voltage and Current Drift Monitoring and Auto Adjustment
Zero point of voltage and current may drift influenced by variation of temperature or other
environment factors. The equipment continually automatically traces the drift and adjusts it to
normal value.
4.2.7 Test Mode Supervision

When protection equipment is set in test mode by configuring the corresponding logic setting, the
alarm signal [Alm_BO_Test] is issued without blocking equipment.
4.2.8 Hardware Configuration Supervision
Module configuration is checked automatically during equipment initialization, if plug -in module
configuration is not consistent to the design drawing of an applied -specific, the alarm signal
[Alm_BoardConfig] is issued with the equipment being blocked.
4.3 Secondary Circuit Supervision
All the alarm signals issued during secondary circuit supervision have being introduced in chapter
“Description of Operation Theory”, so please refer to sections “Current Element”and “Voltage
Element”of the chapter “Description of Operation Theory”for details.
4.3.1 Voltage Transformer Supervision (VTS)
The VTS logic in the relay is designed to detect the VT secondary circuit to ensure that voltage
measurement is the actual value of power system. When VT failure is detected, equipment can
automatically adjust the configuration of protective elements whose stability would be affected by
voltage element to avoiding maloperation.

4.3.2 Current Transformer Supervision (CTS)
The CTS function will be always processed all the time, which includes following two aspects
The CTS logic in the relay is designed to detect the CT secondary circuit to ensure that current
measurement is the actual value of power system. The main purpose of the CTS function is to
detect faults in the secondary circuits of CT and avoid influence on the operation of corresponding
protection functions.
4.4 Failure and Abnormality Alarms
NOTE ： Following alarm messages and corresponding LED indicators are fixed in
equipment software. Besides, there are other programmable LED indicators configured
according to user requirement.
4.4.1 Hardware Self-supervision Alarms
Equipment hardware circuits and software working conditions are always monitored by the relay. If
any abnormality occurs, the corresponding alarm message will be issued on the LCD of the
equipment.
When some light failures are detected, part of protection functions probably be disabled and
others can still work. Some server failures of hardware or software will result in the equipment
being blocked and the contacts of equipment failure will operate at same time. During that
condition, the protection relay has to be out of service for maintenance.
NOTE：If alarm signal is issued with equipment being blocked, please try to make a fault
diagnosis by referring the issued alarm messages but not to simply reboot or re-power the
relay. If user cannot find the failure reason on site, please inform manufacturer for
maintenance.
Table 4.4-1 Equipment self-check alarm list
No. Alarm Message Meaning Description

1 Alm_BO_Test The relay is in test mode.
Mismatch between operating fault detector on fault
2 Alm_InconsistFD detector DSP module and the tripping element on
protection module
Duration of pickup of any fault detector on protection
3 Alm_PersistFD_ProtBrd
module is in excess of 10s.
Duration of pickup of any fault detector on fault detector
4 Alm_PersistFD_FDBrd
module is in excess of 10s.
Loss of power supply of the opto-couplers for binary
5 Alm_Pwr_Opto
inputs.


When No.1~No.5 messages are issued on the LCD of the relay, the LED “HEALTHY”is
steady green and the protection equipment is not blocked with the LED “ALARM”being lit.
6 Alm_Setting_Out-of-Scope Setting value is out of setting scope.
The equipment is in the process of modifying setting
7 Alm_ModifyingSetting
parameters
Mismatch between the configuration of plug-in boards
8 Alm_BrdConfig and the designing drawing of an applied-specific
project
Settings of protection DSP module are set to be
9 Alm_Setting_ProtBrd
unreasonable.
Settings of fault detector DSP module are set to be
10 Alm_Setting_FDBrd
unreasonable.
Error is found during checking sample values on the
11 Alm_Sample
two DSP modules.
12 Alm_TrpOut Driving transistors of binary outputs are damaged.
13 Alm_DSP_ProtBrd DSP chip on protection module is damaged.
14 Alm_DSP_FDBrd DSP chip on fault detector module is damaged.
When No.6~No.14 messages are issued on the LCD, the LED “HEALTHY”is extinguished
and the protection equipment is blocked。
Handling suggestion:
5. No special treatment is needed, and only wait for the completion of testing.（No.1）
6. Please inform the manufacturer or agent for maintenance. After the abnormality is eliminated,
“ALARM”LED will go off automatically and equipment returns to normal operation. (No.2)
7. Please check secondary circuits and protection settings. After the abnormality is eliminated,
“ALARM” LED will go off automatically and equipment returns to normal operation.
(No.3~No.4)
8. Please check if the power supply circuit of BI module is connected correctly. After the
abnormality is eliminated, “ALARM”LED will go off automatically and equipment returns to
normal operation. (No.5)
9. Please checking setting value scope and re-set the corresponding settings. After the
abnormality is eliminated, the equipment can returns to normal operation by re-energizing it.
(No.6)
10. No special treatment is needed. The equipment will return to normal operation after the
completion of setting modification. (No.7)
11. Please check whether the configuration of plug-in module is consistent to the designing
drawing of an applied-specific project, or inform the manufacturer or agent for maintenance.
After the abnormality is eliminated, the equipment can returns t o normal operation by

re-energizing it. (No.8)
12. Please inform the manufacturer or agent for maintenance. After the abnormality is eliminated,
the equipment can returns to normal operation by re-energizing it. (No.9~No.14)
4.4.2 Equipment Operation Alarms
During the equipment normal operation, VT and CT circuit and some binary input circuits are
always monitored by the relay. If any abnormality of them occurs or any alarm element operates,
the corresponding alarm message will be issued on the LCD of the equipment without blocking
equipment.
When this kind of alarm messages are issued, user need to find the abnormality reason, and then
take corresponding measures to eliminate the alarm message to make the equipment return to the
normal operation.
Table 4.4-2 Equipment operation alarm list

Secondary circuit failure of CT used in all differential
1 Alm_CTS
protections.
When No.1~No.2 messages are issued on LCD, conventional differential protection can be
blocked by configuring the corresponding logic setting.
CT secondary circuit for restricted earth fault protection
3 Alm_CTS_REF_HVS
of HV side fails.
4 Alm_CTS_REF_MVS
of MV side fails.
5 Alm_CTS_REF_LVS
of LV side fails.
When No.5~No.7 messages are issued on LCD, restricted earth fault protection of the
corresponding side can be blocked by configuring the corresponding logic setting.
CT secondary circuit for winding differential protection of
6 Alm_CTS_WdgDiff_HVS
HV side fails.
7 Alm_CTS_WdgDiff_MVS
MV side fails.
8 Alm_CTS_WdgDiff_LVS
LV side fails.
When No.8~No.10 messages are issued on LCD, winding differential protection of the
corresponding side can be blocked by configuring the corresponding logic setting.
Differential current of current differential protection is in
9 Alm_Diff
excess of normally endurable level.
CT secondary circuit for restricted earth fault protection of
10 Alm_REF_HVS
HV side is abnormal.


11 Alm_REF_MVS
MV side is abnormal.
12 Alm_REF_LVS
LV side is abnormal.
13 Alm_WdgDiff_HVS
HV side is abnormal.
14 Alm_WdgDiff _MVS
MV side is abnormal.
15 Alm_WdgDiff _LVS
LV side is abnormal.
16 Alm_VTS_XXX VT secondary circuit at XXX side is abnormal.
17 Alm_SensCTS_XXX CT secondary circuit at XXX side is abnormal.
Thermal overload element operates to block closing circuit
18 Alm_ThOvLd_Blk_ClsCB_HVS breaker of HV side with corresponding contacts being
closed.
19 Alm_ThOvLd_Blk_ClsCB_MVS breaker of MV side with corresponding contacts being
closed.
20 Alm_ThOvLd_Blk_ClsCB_LVS breaker of LV side with corresponding contacts being
closed.
21 Alm_ThOvLd_Blk_ClsCB_CW breaker of common winding with corresponding contacts
being closed.
22 Alm_DefOvExc Definite-time overexciation alarm element operates.
23 Alm_InvOvExc Inverse-time overexciation alarm element operates.
24 Alm_ThOvLd_HVS breaker of HV side with corresponding contacts being
closed.
25 Alm_ThOvLd_MVS breaker of MV side with corresponding contacts being
closed.
26 Alm_ThOvLd_LVS breaker of LV side with corresponding contacts being
closed.
27 Alm_ThOvLd_CW breaker of common winding with corresponding contacts
being closed.


34 Alm_OvLd1_CW
operates.
35 Alm_OvLd2_CW
operates.
Stage 1 of overload element of MV side for initiating
36 Alm_IntiCool1_OvLd_MVS
cooling system side operates.
Stage 2 of overload element of MV side for initiating
37 Alm_IntiCool2_OvLd_MVS
cooling system side operates.
Stage 1 of overload element of LV side for initiating cooling
38 Alm_IntiCool1_OvLd_LVS
system side operates.
Stage 2 of overload element of LV side for initiating cooling
39 Alm_IntiCool2_OvLd_LVS
system side operates.
Stage 1 of overload element of common winding for
40 Alm_IntiCool1_OvLd_CW
initiating cooling system side operates.
Stage 2 of overload element of common winding for
41 Alm_IntiCool2_OvLd_CW
initiating cooling system side operates.
Overload element of HV side for blocking on-load tap
42 Alm_BlkOLTC_OvLd_HVS
changing function operates.
Overload element of MV side for blocking on-load tap
43 Alm_BlkOLTC_OvLd_MVS
Overload element of LV side for blocking on-load tap
44 Alm_BlkOLTC_OvLd_LVS
Overload element of common winding for blocking on-load
45 Alm_BlkOLTC_OvLd_CW
tap changing function operates.
Alm_ROV_MVS Zero-sequence overvoltage alarm element of MV side
46
operates.
Alm_ROV_LVS Zero-sequence overvotlage alarm element of LV side
47
operates.
Zero-sequence overvcurrent alarm element of HV side
48 Alm_ROC_HVS
operates.
Zero-sequence overcurrent alarm element of MV side
49 Alm_ROC_MVS
operates.
50 Alm_ROC_LVS Zero-sequence overcurrent alarm element of LV side


operates.
Zero-sequence overcurrent alarm element of common
51 Alm_ROC_CW
winding operates.
Binary input of external tripping signal of HV side is
52 Alm_BI_ExtTrp_BFP_HVS
abnormal.
Binary input of external tripping signal of MV side is
53 Alm_BI_ExtTrp_BFP_MVS
abnormal.
Binary input of external tripping signal of LV side is
54 Alm_BI_ExtTrp_BFP_LVS
abnormal.
Handing suggestion:
1. Please check the corresponding CT secondary circuit. After the abnormality is eliminated,
“ALARM”LED will go off automatically and equipment returns to normal operation. (No.1,
No.9~No.15)
2. Please check the corresponding CT secondary circuit. After the abnormality is eliminated,
equipment can return to normal operation by energizing the binary i nput [BI_RstTarg].
(No.1~No.8）
3. Please check the corresponding sampling values and VT/ CT secondary circuit to find out the
reason resulting in the abnormality. If sample values of the equipment are not correct, please
inform the manufacturer or agent for maintenance, and if it is caused by the failure of the
VT/CT secondary circuit or primary system, please finish troubleshooting according to the
operating code of protection relay. (No.16~No.17)
4. No treatment is needed. (No.18~No.21)
5. Please treat according to the specific application requirements. (No.22~No.51)
6. Please check the secondary circuit of the corresponding binary input. (No.52~No.54)

Chapter 5 Metering and Recording
The relay also provides some auxiliary functions, such as on-line data metering, binary input
status, event and disturbance recording, etc. All these make the relay meet the demands of the
modern power grid requirements.
5.2 Metering
The equipment performs continuous measurement of the analogue input quantities. The
measurement data shown below is displayed on the LCD of the relay front panel or on the local or
remote PC.
Equipment samples 24 points per cycle. Calculate the RMS value in each interval and LCD will be
updated every 0.5 second.
By navigating the path “SETTINGS”— >“SLD SETTINGS”, primary or secondary sampled values
can be selected to be displayed by configuring the setting [Opt_ DisplayValue]. User can view
these data on LCD by navigating the menu “VALUES”, or by PCS-PC software or SAS software.
1. RMS Value
Directly measured value
 Phase currents and phase voltages of each side
 Broken-delta voltages of each side
 Zero-sequence currents and gap zero-sequence currents of each side
Calculated value
 Calculated zero-sequence voltages and negative-sequence voltages of each side.
 Calculated zero-sequence currents of each side
 Corrected currents of each side
 Differential current and restraint threshold for conventional current differential protection
 Zero-sequence currents and zero-sequence restraint thresholds for each REF protection
 Winding differential current and restraint threshold for winding differential protection
 Secondary rated currents of each side
 Corrected coefficients for REF protection and winding differential protection.
 the percents of secondary and third harmonics to differential current respectably

2. Phase angle
 Angle between currents of each side
 Angle between voltages of each side
 Angle between voltage and current of each side
 Angle between corrected currents of each side for conventional current differential protection
 Angle between corrected currents of each REF protection
 Angle between corrected currents of each winding differential proteciton
Please refer to each protection element in the chapter “Description of Operation Theory”for
detailed sample value and phase angle,
5.3 Event & fault Records
5.3.1 Introduction
The protection equipment provides the following recording functions:
 Event recording
 Fault and disturbance recording
 Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform must be printed or be extracted using PCS-PC software and a waveform software.
5.3.2 Event Recording
The equipment can store the latest the latest 1024 abnormality alarm reports, the latest 1024
binary input stage changing reports respectively. All the records are stored in non-volatile memory,
and when the available space is exhausted, the oldest report is automatically overwritten by the
latest one
 Abnormality alarm reports
An abnormality alarm being detected during relay self-check supervision or an alarm of secondary
circuit abnormality or protection alarm element will also be logged as individual events.
 Binary input status changing reports
When binary input status changes, the change information will be displayed on LCD and logged as
binary input change report at the same time.
5.3.3 Disturbance and Fault Recording
5.3.3.1 Application
Use the disturbance recorder to achieve a better understanding of the behavior of the power

network and related primary and secondary equipment during and after a disturbance. An analysis
of the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
5.3.3.2 Design
Disturbance recorder is consisted of tripping report and fault waveform. Disturbance recorder is
triggered by fault detector. The equipment can store 64 pieces of trip reports and waveforms in
non-volatile memory.
When protection operates, the operating information will be displayed on LCD and logged as trip
record at same time, which can be viewed in trip report. Here fault recording includes two kinds of
cases:
1) Only the fault detector element operates.
2) The fault detector element operates associated with the operation of protective elements.
1. Trip record capacity and information
The equipment can store 64 pieces of trip reports in non-volatile memory. If a new fault occurs
when 64 faults have been stored, the oldest will be overwritten by the latest one..
The following items are recorded for one fault:
1) Sequence number
Each operation will be recorded with a sequence number in the report and displayed on LCD
screen.
2) Date and time of fault occurrence
The time resolution is 1 ms using the relay internal clock. Initiating date and time is when a fault
detector picks up. Relative time is the time when protection element operates to send tripping
signal after fault detector picks up.
3) Faulty phase
The faulty phase detected by the operating element is showed in the record report.
4) Trip mode
This shows the protection element that issues the tripping command. If no protection operates to
trip but only equipment fault detector picks up, fault report will record the title of fault detector.
2. Fault waveform record capacity and information
MON module of the relay can store 64 pieces of fault waveform oscillogram in non-volatile memory.
If a new fault occurs when 64 fault waveform recorders have been stored, the oldest will be
overwritten by the latest one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.

Each time recording includes 2-cycle waveform before a fault detector pickup, and most 250
cycles can be recorded.
5.3.4 Present Recording
Present recording is used to record a piece of waveform of present operation equipment which
can be trigger manually on LCD of equipment or remotely through PCS-PC software. Recording
content of present recording is same to that of disturbance recording.
Each time recording includes 2-cycle waveform before triggering, and most 250 cycles can be
recorded.

Chapter 6 Hardware Description
The PCS-978 adopts 64-bit microchip processor CPU produced by FREESCALE as control core
for logic calculation and management function, meanwhile, adopts high-speed digital signal
processor DSP to be in charge of all the protection calculation. 24 points are sampled in every
cycle and parallel processing of sampled data can be realized in each sampling interval to ensure
ultrahigh reliability and safety of protection equipment.
The working process of the equipment is as follows: firstly, the current and voltage is converted
into small voltage signal and sent to protection calculation module (also called DSP module 1) and
fault detector calculation module (also called DSP module 2) respectively, and accesses into DSP
after being filtered and converted by AD. When MON module completes all the protection
calculation, the result will be sent to 64-bit CPU on MON module to be recorded. DSP module 1
carries out protection logic calculation, tripping output, and MON module completes SOE
(sequence of event) record, waveform recording, printing, communication between protection and
SAS and communication between HMI and CPU. The work process of fault detector calculation
module is similar to that of protection calculation module, and the only difference is, when fault
detector calculation module decides a fault detector picks up, only positive power supply of output
relay is switched on.
The PCS-978 is comprised of intelligent modules, except that few particular modules’position
cannot be changed in the whole device, the others like AI (analog input) module such as AC
current, AC voltage, DC current, and etc., and IO (input and output) module such as binary input,
tripping output, signal output, and etc can be flexibly configured according to the remained slot
positions.
Table 6.1-1 PCS-978 module configuration
No. Module description

1 Management module (MON module)
2 Protection calculation module (DSP module 1)
3 Fault detector calculation module (DSP module 2)
4 Analog input module ( AI module )
5 DC analog input module (DC AI module)
6 Binary input module (BI module)
7 Tripping output module (BO trip module )
8 Signal output module (BO signal module )
9 Power supply module (PWR module)
10 Human machine interface module (HMI module)
11 GOOSE module (optional)

 MON module provides functions like management function, completed event record, setting
management, and etc.
 DSP modules are totally the same, to carry out filtering, sampling and protection calculation
and fault detector calculation respectively.
 AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.
 BI module provides binary input, and the binary is inputted via 24V/36V/110V/125V/
220V/250V opto-coupler (configurable).
 BO trip module provides all tripping outputs.
 BO signal module provides all kinds of signal output contact, including annunciation signal,
remote signal, fault and disturbance signal, operation abnormal signal and etc.
 PWR module converts DC 250/220/125/110V into different DC voltage levels needed by

various modules of the equipment
 HMI module is comprised of LCD, keypad, LED indicator and test serial ports, and it is
convenient for user to perform human-machine interaction with equipment.
 GOOSE Module (optional) is applied for realization of GOOSE level interlocking, and for
connection to ECVT with supporting IEC61850-9-1and IEC61850-9-2 protocols.
Following figures show 4U and 8U front views of PCS-978 respectively.

RP
G C
ES
Figure 6.1-1 Front view of 4U equipment

PCS -978
HEALTHY
ALARM TRANSFORMER PROTECTION
TRIP
ENT
Figure 6.1-2 Front view of 8U equipment
Following figures show of 4U and 8U typical rear views of PCS-978 respectively.

Figure 6.1-3 Rear view of 4U equipment
NR1102D NR1156A NR1156A NR1504 NR1504 NR1521A NR1521A NR1521B NR1523B NR1301A
1 2 3 1 2 3 5V BJ
4 5 6 4 5 6 BJJ BSJ
1 COM1
2 BSJ1
3 BJJ 1
4 COM2
5 BSJ2
6 BJJ2
7 24 V
8 24VGND
9
10 DC+
11 DC-
12 FGND
NR1401 NR1401 NR1401 NR1401 NR1301A

5V BJ
BJJ BSJ
DANGER DANGER DANGER DANGER

1 COM1
2 BSJ1
3 BJJ1
4 COM2
5 BSJ2
6 BJJ2
7 24 V
8 24VGND
9
10 DC+
11 DC -
12 FGND
optional
Figure 6.1-4 Rear view of 8U equipment
6.2 Plug-in Module Configuration
6.2.1 Configuration Principle

The PCS-978 includes two types of chassis, 4U and 8U, and the interior 8U comprises two 4U
chassises.
6.2.1.1 Module Configuration of 4U PCS-978
4U chassis has 16 slots, and the irremovable modules are power supply module, MON module
and DSP module.

DSP module 1
DSP module 2
MON module
PWR module
Figure 6.2-1 Rear view of fixed module position of 4U equipment
Besides the fixed four modules are shown in above figure, there are twelve slots can be flexibly
configured.
 AI module, BI module and BO module can be configured at position between slot B04 to slot
07.
 The AC AI module can be configured up to 4 pieces, and each AC AI module occupying 2

slots can provide 12 analog inputs.
 A DC current input module (also called DC AI module) can be configured at any slot between
slot B04 and slot B11, which can provide 6 DC current inputs.
 If the slots from slot B04 to slot B11 are not used up, the BI module and BO module can be
configured at the rest slots.
 BI module and BO module can be configured at any slot between slot B12 and slot B15.
6.2.1.2 Module configuration of 8U PCS-978
8U chassis consists of two 4U chassises, and the upper layer is the first layer (layer 1) and the
lower layer is the second layer (layer 2). The irremovable modules are power supply module, MON
module and DSP module in the first layer, and second layer is mainly used to configure AC
modules.

DSP module 1
DSP module 2
MON module
PWR module
Figure 6.2-2 Rear view of fixed module position of 8U equipment
Besides the fixed four modules are shown in above figure, there are twenty nine slots can be
flexibly configured.
 8U chassis support duplicate power modules and one power module is fixed configured at slot
B16 and the other one must be configured at slot B31.
 BI module or BO module can be configured between slot B04 to slot B15.
 Layer 2 is applied for configuration of analog input modules. Maximum 7 AC AI modules with
84 analog input channels can be configured between slot B17 and slot B29.
 Each AC AI module occupies two slots where two DC AI modules can be configured.
 Slot B30 and slot B31 are blank, i.e. module can not be equipped at those slots.
 After finishing AI module configuration, BI module and BO module can be configured at the
rest slots of layer 2 except slot B30, slot B31 and slot B32.
6.2.2 Typical Configuration

PCS-978 typical configurations of plug-in module are as follows:

BO module for signal

BO module 1 for trip
AC AI module 1
AC AI module 2
DSP module 1
DSP module 2
MON module
PWR module
BI module
Figure 6.2-3 Typical configurations 1
BO module for signal

DSP module 1
DSP mod ule 2
MON module
PWR module
BI module 1
BI module 2
AC AI module 2
AC AI module 3
AC AI module 4
AC AI module 1
Figure 6.2-4 Typical configuration 2
6.3 Plug-in Module Terminal Definition
Equipment consists of power supply module, MON module, DSP module, Analog input module,
opto-coupler input module, tripping output module, and signal output module. The definition and
application of each module and its terminal is introduced as follows.
6.3.1 PWR Module (NR1301)
The power supply module is a DC/DC or AC/DC converter with electrical insulation between input
and output. The power supply module has an input voltage range as described in chapter 2
“Technical Data”. The standardized output voltages are +3.3V, +5V, ±12V and +24V DC. The
tolerances of the output voltages are continuously monitored.
The +3.3V DC output provides power supply for the microchip processors, and the +5V DC output
provides power supply for all the electrical elements that need +5V DC power supply in this device.
The ±12V DC output provides power supply for A/D conversion circuits in this device, and the

+24V DC output provides power supply for the static relays of this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on the front of the power supply module. The pin definition of the
connector is described as below.
NR1301A
COM 1 01 01
BO_Fail_1
BSJ1 02 02
BO_Alm_Abnor_1
BJJ1 03 03
COM 2 04
04
BSJ2 05 BO_Fail_1
05
BJJ2 06 BO_Alm_Abnor_1
06
24V+ 07
24V- 08
09
DC + 10
DC - 11
FGND 12
Grounding S crew
Grounding Bus
Figure 6.3-1 Pin definition of DC power supply module NR1301A
Pin No. Symbol Description

01 COM1 Common terminal 1.
01, 02 BO_Fail_1 Binary output 1 of equipment failure.
01, 03 BO_Alm_Abnor_1 Binary output 1 of equipment abnormality alarm.
04 COM2 Common terminal 2.
01, 05 BO_Fail_2 Binary output 2 of equipment failure.
01, 06 BO_Alm_Abnor_2 Binary output 2 of equipment abnormality alarm.
07 24V+ Pins 07 and 08 are 24V power supply output for the
binary input module. Pin 07 is 24V+ and Pin 08 is 24V-,
08 24V-
the rated current of this power supply is 200mA.
09 Not used
10 DC+ Positive input of power supply for the equipment


11 DC- Negative input of power supply for the equipment
12 FGND Grounded connection of this equipment
NOTE: The rated voltage of DC power supply module is self-adaptive to 220Vdc and
110Vdc, but the power supply in other DC voltage level or power supply of AC voltage
need to be specially ordered, and check if the rated voltage of power supply module is
the same as the voltage of external control power supply before equipment being put into
service.
NOTE: The DC power supply module provides pin 12 and earth connector for grounding
of equipment. The pin 12 shall be connected to earth connector and the connected to the
earth copper bar of panel via dedicated grounding wire.
NOTE: Efficient grounding is the most important measure for equipment to prevent EMI,
so efficient grounding must be ensured before the device is put into operation.
6.3.2 MON Module (NR 1102)
The terminals of MON modules and its wiring method are shown in the following figure.
The MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM,
Ethernet controller and other peripherals. Its functions include management of the complete
device, human machine interface, communication and waveform recording etc.
The MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module is provided with 100BaseT
Ethernet interfaces, RS-485 communication interfaces, PPS/IRIG-B differential time
synchronization interface and RS-232 printing interface.

ET HERNET
ETHERNET
ET HERNET
ETHERNET
GPS
GPS
GPS
PRINT
PRINT
PRINT
ETHERNET
ETHERNET
ETHERNET
ET HERNET
GPS
GPS
G PS
PRINT
PRINT
PRINT
Figure 6.3-2 Rear view of MON modules
Module ID Memory Interface Physical Layer

NR1102A 64M DDR 2 RJ45 Ethernet Twisted pair wire
NR1102B 64M DDR 4 RJ45 Ethernet Twisted pair wire
NR1102C 128M DDR 2 RJ45 Ethernet Twisted pair wire
NR1102D 128M DDR 4 RJ45 Ethernet Twisted pair wire
2 RJ45 Ethernet Twisted pair wire
NR1102H 128M DDR
2 FO Ethernet Optical fibre SC
2 RJ45 Ethernet Twisted pair wire
NR1102I 128M DDR
2 FO Ethernet Optical fibre TC

Figure 6.3-3 Wiring of communication interface
The correct method of connection is shown in Figure 6.3-3. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to
connect the “+”and “–”terminals of difference signal; the other pair of twisted pairs are used to
connect the signal ground of the interface, i.e. connect the signal groundings of all the devices
connected with the bus to the twisted pair. The module reserves a free terminal for all the
communication ports; the free terminal has no connection with any signal of the device; it is used
to connect the external shields of the two cables when connecting multiple devices in series. The
external shield of cable shall be grounded at one of the ends.
6.3.3 DSP Module 1 (Protection Calculation)

The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, sample data exchanging with the opposite side,
calculation of protection logic and tripping output etc.
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the
real-time synchronous sample data from merging unit through the multi-mode optical-fibre
interface.
The module can provide 2,048 kbit/s or 64 kbit/s single-mode optical-fibre to exchange data and
signal with the opposite-side protection device
6.3.4 DSP Module 2 (Fault Detector Calculation)
The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, calculation of fault detector elements and providing
positive power supply to output relay.
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the

real-time synchronous sample data from merging unit through the multi-mode optical-fibre
interface.
DSP module 1 and DSP module 2 have same hardware configuration. The following figure shows
rear views and terminal definitions for different type of DSP modules; the corresponding module
shall be adopted in accordance with concrete situation.
Figure 6.3-4 Rear view of DSP modules
Module ID Description
NR1156A 48 analog sampling channels, applied for conventional CT/VT.
4 transmitting channels and 4 receiving channels, applied for ECVT to
NR1151A
receive signal directly.
No analog sampling channel, applied for ECVT to receive signal from
NR1151D
motherboard bus
It is used to ECVT, 8 receiving channels, applied for ECVT to receive signal
NR1152A
directly.
6.3.5 Binary Input Module (NR1504)
The NR1504 module is a standard binary input module, which can provide 25 binary inputs, the
inputted voltage can be selected to be 24V, 48V, 110V, 220V, 125V and 250V and the module has
opto-coupler power monitor circuit. Pins ~14 and ~15 are power supply inputs for opto-coupler.
[BI_n](n=1,2,… ,16 can be configured as a specified binary input by PCS-PC software。
A 22-pin connector is fixed on the front of the binary input module. The pin definition of the
connector is described as below.

Figure 6.3-5 Pin definition of binary input module NR1504

01 Opto+ Positive pole of power supply of the module
02 BI_Pulse_GPS Binary input of time synchronization pulse
03 BI_Print Binary input of triggering printing
Binary input of blocking communication between equipment
04 BI_BlkComm and substation automatic system (SAS) or remote terminal unit
(RTU).
05 BI_RstTarg Binary input of resetting signal of protective equipment.
06 BI_1 Configurable binary input 1.
Common terminal 1 of negative pole of power supply of the
08 COM1-
module


15 COM2-
module
22 COM3-
module
NOTE: The rated voltage of binary input is optional: 24V, 46V, 110V , 220V, 125V or 250V,
which must be definitely declared in the technical scheme and the contract. It is
necessary to check whether the rated voltage of BI module meets the demand of the
engineering before putting the relay into operation.
The application of the binary input [BI_BlkComm] for digital substation communication adopting
IEC61850 protocol is given as follows.
A. Processing mechanism for MMS (Manufacturing Message Specification) message
1) The protection device should send the state of this binary input to client.
2) When this binary input is energized, the bit “Test”of quality (Q) in the message sent
should be set as “1”.
3) When this binary input is energized, the client cannot remote control the isolator link
and circuit breaker, modify settings and switch setting group.
4) According to the value of the bit “Test”of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it
correspondingly. If the message is the maintenance message, the content of the
message will be not displayed real-time message window, not issue audio alarm, but
should refresh the picture so as to ensure that the state of the picture is in step with the
actual state. The maintenance message should be stored, and can be inquired by
independent window.
B. Processing mechanism for GOOSE message
1) When this binary input is energized, the bit “Test”in the GOOSE message sent by the
protection device should be set as “1”.
2) For the receiving end of GOOSE message, it will compare the value of the bit “Test”in
the GOOSE message received by it with the state of its own binary input (i..e
[BI_BlkComm]), the message will be thought as invalid unless they are conformable.

C. Processing mechanism for SV (Sampling Value) message
1) When this binary input of merging unit is energized, the bit “Test”of quality (Q) of
sampling data in the SV message sent should be set as “1”.
2) For the receiving end of SV message, if the value of bit “Test”of quality (Q) of sampling
data in the SV message received by it is “1”, the relevant protection functions will be
disabled, but under maintenance state, the protection device should calculate and
display the magnitude of sampling data.
3) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices
and dual merging units should be fully independent each other, and one of them is in
maintenance state will not affect the normal operation of the other.
6.3.6 Binary Output Module
6.3.6.1 Tripping Output Module (NR1521)
NR1521A and NR 1521B modules are two standard binary output modules. NR1521A can provide
11 tripping output contacts, and each output contact can be controlled separately by positive
power supply of fault detector. NR1521B can provide 9 tripping output contacts, and two signal
output contacts, and each output contact can be controlled separately by positive power supply of
fault detector. The contacts provide by NR1521A and NR1521B are all normally open (NO)
contacts.
[BO_Trp_n] (n=1,2,… ,11) and [BO_Signal_n] (n=1, 2) can be configured as a specified tripping
output contact and a signal output contact respectively by PCS-PC software according to user
requirement.
A 22-pin connector is fixed on the front of this module. The pin definition of the connector is
described as below.

NR1521A NR1521B
BO_Trp_1+ 01 01 BO_Trp_1+ 01 01
BO_Trp_1 BO_Trp_1
BO_Trp_1- 02 02 BO_Trp_1- 02 02
BO_Trp_2+ 03 03 BO_Trp_2+ 03 03
BO_Trp_2 BO_Trp_2
BO_Trp_2- 04 04 BO_Trp_2- 04 04
BO_Trp_3+ 05 05 BO_Trp_3+ 05 05
BO_Trp_3 BO_Trp_3
BO_Trp_3- 06 06 BO_Trp_3- 06 06
BO_Trp_4+ 07 07 BO_Trp_4+ 07 07
BO_Trp_4 BO_Trp_4
BO_Trp_4- 08 08 BO_Trp_4- 08 08
BO_Trp_5+ 09 09 BO_Trp_5+ 09 09
BO_Trp_5 BO_Trp_5
BO_Trp_5- 10 10 BO_Trp_5- 10 10
BO_Trp_6+ 11 11 BO_Trp_6+ 11 11
BO_Trp_6 BO_Trp_6
BO_Trp_6- 12 12 BO_Trp_6- 12 12
BO_Trp_7+ 13 13 BO_Trp_7+ 13 13
BO_Trp_7 BO_Trp_7- BO_Trp_7
BO_Trp_7- 14 14 14 14
BO_Trp_8+ 15 15 BO_Trp_8+ 15 15
BO_Trp_8 BO_Trp_8
BO_Trp_8- 16 16 BO_Trp_8- 16 16
BO_Trp_9+ 17 17 BO_Trp_9+ 17 17
BO_Trp_9 BO_Trp_9
BO_Trp_9- 18 18 BO_Trp_9- 18 18
BO_Trp_10+ 19 19 BO_Signal_1+ 19 19
BO_Trp_10- 20 BO_Trp_10 BO_Signal_1- 20 BO _Signal_1
20 20
BO_Trp_11+ 21 21 BO_Signal_2+ 21 21
BO_Trp_11- 22 BO_Trp_11 BO_Signal_2- 22 BO _Signal_2
22 22
Figure 6.3-6 Pin definition of tripping output module
6.3.6.2 Signal Output Module (NR1523B)
The NR1523B module is a standard binary output module for signal, which can provide 11 signal
output contacts. Among those contacts, contacts [BO_Signal_n] (n=1,2,… ,7, 10,11) are normally
open (NO) contacts and [BO_Signal_8] and [BO_Siganl_9] are normally closed (NC) contacts. All
contacts can be configured as specified signal output contacts of some protection by PCS-PC
software according to user requirement. Besides the contact [BO_signal_11] is a magnetic latched
NO contact defined as protection tripping signal fixedly.
described as below.

NR1523B
BO_Signal_1+ 01 01
BO_Signal_1
BO_Signal_1- 02 02
BO_Signal_2+ 03 03
BO_Signal_2
BO_Signal_2- 04 04
BO_Signal_3+ 05 05
BO_Signal_3
BO_Signal_3- 06 06
BO_Signal_4+ 07 07
BO_Signal_4
BO_Signal_4- 08 08
BO_Signal_5+ 09 09
BO_Signal_5
BO_Signal_5- 10 10
BO_Signal_6+ 11 11
BO_Signal_6- 12 BO_Signal_6
12
BO_Signal_7+ 13 13
14
BO_Signal_8+ 15 15
BO_Signal _8
BO_Signal_8- 16 16
BO_Signal_9+ 17 17
18
BO_Signal _10+ 19 19
20
BO_Signal _11+ 21 21
22
Figure 6.3-7 Pin definition of signal output module
NOTE: If user needs more magnetic latched contacts or normally closed (NC) contacts,
please declare in the technical scheme and the contract.
6.3.7 Analog Input Module
6.3.7.1 AC Analog Input Module (NR1401)
The analog input module can transform these high AC input values to relevant low AC output
value for the DSP module. The transformers are used both to step-down the currents and voltages
to levels appropriate to the electronic circuitry of this device and to provide effective isolation
between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analog AC input signal.
NOTE: The rated value of the input current transformer is optional: 1A or 5A. The rated
value of the CT must be definitely declared in the technical scheme and the contract.
NOTE: Because the rated value of the input current transformer is optional, it is
necessary to check whether the rated values of the current transformer inputs are
accordant to the demand of the engineering before putting the device into operation.
The NR1401 can provide 12-channel analog signal inputs, and each channel can be configured as

a specified current or voltage input channel by PCS-PC software according to user requirement.
There are three kinds of typical application module as follwing shows.
Type A: 6 voltage channels and 6 current channels.
Type B: 3 voltage and 9 current channels.
Type C: 12 current channels.
described as below.
Figure 6.3-8 Pin definition of AC analog output module
NOTE: In above figure, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12 and U1, U2, U3, U4, U5,
U6 are polarity terminals of corresponding relevant voltage and current inputs

respectively.
NOTE: If user needs other analog input configuration, please declare in the technical
scheme and the contract.
6.3.7.2 DC Analog Input Module (NR1410B)
Transducer input module NR1410B can receive six input signals which can be 4~20mA current or
0~5V voltage from external dcmA output transducer. Hardware and software are provided to
receive these signals from the external transducers and convert these signals into a digital for use
as required. There are four pins 13, 16, 19 and 22 on the module are ground terminals of the
equipment.

described as below.
Figure 6.3-9 Pin definition of DC analog output module
Typical connection of output transducers is shown in the figure below, and there is a jumper
between pin S1 and pin S6 on module NR1401B to control the input signal type of the module.
Output Transducer
To_Transducer_24V
Transducer_24V_Return
4-20mA
dcmA_In_+
NR1410B
S1
Jumper
S6
dcmA_In_- R
Figure 2: Typical connection of output transducer
4-20mA shunt disabled and return paths interconnected and 0~5V measure
S1~S6 (OFF)
provided.
S1~S6 (ON) Input resistance with 4-20mA shunt enabled and 4~20mA measure provided.

6.3.8 GOOSE Module (Optional)
This module consists of high-performance digital signal processor, two 100M optical-fibre Ethernet,
two 100M RJ-45 Ethernet and other peripherals. The module supports GOOSE function and IEC
61850-9-1 and IEC 61850-9-2 Protocols. Its functions include that the protective device receives
data from the merging unit and sending GOOSE command to the intelligent control device etc.
This module is not required when the GOOSE function is not applied.
The sending and receiving functions of GOOSE should be completed through configuring the
sending module and receiving module.
Optional types of GOOSE module are listed in the following.
NR1126B NR1126D
SC Interface ST Interface
100M FX 100M FX
SC Interface ST Interface
100M FX 100M FX
RX1
ST Interface RX 1
ST Interface
IRIGB IRIGB
Module ID Interface Physical Layer Description

NR1126A 2 Ethernet SC multi-mode optical fibre
2 Ethernet SC multi-mode optical fibre
NR1126B Support IEC61850, GOOSE and
IRIGB ST
IEC61850-9-1, IEC61850-9-2,
NR1126C 2 Ethernet ST multi-mode optical fibre
receiving and sending data
2 Ethernet ST multi-mode optical fibre
NR1126D
IRIGB ST
6.4 Tripping Matrix
The PCS-978 provides output contacts which are controlled by tripping logic settings (or called
tripping matrix setting). The tripping logic setting of each protection element can be set so that the
flexible tripping mode of each protection can be realized as user required.
The tripping logic setting in form of [TrpLog_xxx] is comprised of 10-bit binary number, but that
displayed on the LCD is 3-bit hexadecimal number. Each binary bit controls a set of tripping output
contacts. When the protection element operates, if the corresponding bit is set as “1”, the relevant

output contacts will pick up; if the bit is set as “0”, the relevant output relays will not pick up.
For typical configuration 1 of PCS-978 in 4U, two NR1521A modules are equipped with being
installed adjacently in slot S28 and slot S29, and then tripping output contacts controlled by logic
setting are list in the following table.
Table 6.4-1 Tripping matrix output contact list of typical configuration A
Contact
Bit Tripping output group Controlled contacts
amount
2801-2802, 2803-2804,
0 TrpOutp1: the 1st group of tripping output contacts 3
2805-2806
1 TrpOutp2: the 2nd group of tripping output contacts 2807-2808, 2809-2810 2
2 TrpOutp3: the 3rd group of tripping output contacts 2811-2812, 2813 -28 14 2
3 TrpOutp4: the 4th group of tripping output contacts 2815-2816, 2817-2818 2
4 TrpOutp5: the 5th group of tripping output contacts 2819-2820, 2821-2822 2
2901-2902, 2903-2904
5 TrpOutp6: the 6th group of tripping output contacts 3
2905-2906,
6 TrpOutp7: the 7th group of tripping output contacts 2907-2908 2909-2910, 2
7 TrpOutp8: the 8th group of tripping output contacts 2911-2912, 2913 -29 14 2
8 TrpOutp9: the 9th group of tripping output contacts 2915-2916 2917-2918 2
2919-2920
9 TrpOutp10: the 10th group of tripping output contacts 2
2921-2922
10 No definition
11 No definition
12 No definition
13 No definition
14 No definition
15 No definition
NOTE: Controlled contacts are represents with its slot position and pin number. For
example, contact 2801-2802 means terminal 01-02 of the module at the slot B28, i.e. 28
represents the slot position of module, 01(02) represents the pin number on the module.
6.5 Output Contact
There are two types of output contact tripping output contact and signal output contact.
6.5.1 Tripping Output Contact
The protection equipment provides tripping contacts for tripping breaker generally. These contacts

are fixed on the tripping output modules. The number of tripping contacts can be flexibly
configured according to user requirement.
6.5.2 Signal Output Contact
The signal output contacts are classified into two types based on the sources: tripping signal
output contact and abnormal signal output contact. The tripping signal output contact picks up
when protective equipment operates and the abnormal signal output contact picks up when
protective equipment is in abnormal operation. Signals are divided into three types based on their
applications: annunciation signal, remote signal and fault&disturbance record (FDR) signal. The
annunciation signal is sent to local control panel the remote signal is sent to substation automation
system, the FDR signal is provided to independent fault recorder device. The annunciation output
contact is generally magnetic latched, so it needs manual reset and then the output contact can
drop off.
The number of signal output contacts can be flexibly configured according t user requirement.
 Tripping Signal output Contact
When the protection element operates, the equipment sends tripping command to drive the
tripping output contact and signal contact simultaneously. For example, when differential
protection operates, in addition to the pickup of tripping output contact controlled by the tripping
logic setting, the signal contacts are closed simultaneously, producing annunciation signal, remote
signal and FDR signal respectively. These contacts are assigned to contacts on signal output
module by PCS-PC software as user requirement.
 Abnormal Signal Output Contact
When some abnormal operation conditions are detected by protection equipment, the equipment
will send abnormal message to be displayed on the LCD and generate abnormal alarm signal.
These signals, such as equipment failure signal, CT circuit failure and so on, are used to produce
annunciation signal, remote signal and FDR signal. Please refer to power supply module for
detailed abnormal signal output contact.
 Abnormal Operation Contact
The abnormal operation contacts include initiating cooler, blocking on-load tap changing (OLTC)
function and etc. These contacts are assigned to contacts on signal output module by PCS-PC
software as user requirement.

Chapter 7 Common Settings

Settings are classified to two kinds, protection settings and common settings. Each protection
element has its independent setting menu to configure which are given detailed description in
“Description of Operation Theory”. Common settings consist of equipment settings, description
settings, SLD settings, VEBI settings and etc.
The equipment has 10 setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, common settings are shared by all
protection setting groups, and settings of protection element are set according to secondary
values.
NOTE: All current settings in this chapter are secondary current converted from primary
current by CT ratio. Zero sequence current or voltage setting is configured acc ording to
3I0 or 3U0 and negative sequence current setting according to I2 or U2.
7.1 Equipment Settings
 Setting list
Table 7.1-1 Equipment settings

24V, 48V, 110V,
1 Un_BinaryInput Voltage level of binary input
220V
DefaultValue_GBI_XXX Default valve of GOOSE binary input XXX
2 0/1
(XXX=1, 2, 3, … , 64) (1, 2, 3, … , 64)
Setting used to define the name of
NameDef_GBI_Recv_XXX Maximum 10
3 GOOSE receiving binary input XXX
(XXX=1, 2, 3, … , 64) characters
(XXX=1, 2, 3, … , 64).
1. Un_BinaryInput
The setting is used to set the voltage level of binary input module. If low-voltage BI module is
equipped, 24V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V or 220V can be set according to the actual requirement.
2. [DefaultValue_GBI_XXX], [NameDef_GBI_Recv_XXX] (XXX=1, 2, … , 64)
These settings are special for GOOSE function module, and if GOOSE function module is not
equipped and these settings will not displayed at this submenu.
 Setting path

Access path in menu is:
Main Menu -> SETTINGS -> EQUIP SETTINGS
7.2 Communication Settings
 Setting list
Table 7.2-1 Equipment settings

1 Equip_ID Max 10 characters Identity of the protection equipment
2 IP_Addr_NetA IP address of Ethernet port A
3 Subnet_Mask_A Subnet mask of Ethernet port A
4 En_NetA 0,1 Put Ethernet port A into service
5 IP_Addr_NetB IP address of Ethernet port B
6 Subnet_Mask_NetB Subnet mask of Ethernet port B
7 En_NetB 0,1 Put Ethernet port B into service
8 IP_Addr_NetC IP address of Ethernet port C
9 Subnet_Mask_C Subnet mask of Ethernet port C
10 En_NetC 0,1 Put Ethernet port C into service
11 IP_Addr_NetD IP address of Ethernet port D
12 Subnet_Mask_D Subnet mask of Ethernet port D
13 En_NetD 0,1 Put Ethernet port D into service
Communication address between the
14 Comm_Addr 0～255 protective device with the SCADA or RTU
via RS-485
4800,9600,19200, Baud rate of rear RS-485 communication
15 COM_Baud
38400,57600,115200 port
Communication protocol of rear RS-485
16 COM1_Protocol 0～2
serial port 1
Communication protocol of rear RS-485
17 COM2_Protocol 0～2
serial port 2
Logic setting of enabling/disabling blocking
18 En_BlkComm 0/1
direction of communication
4800,9600,
19 Printer_Baud Baud rate of printer port
19200,38400
20 En_Auto_Print 0/1
automatic printing function
21 En_HiSpeed_Print 0/1 Logic setting of enabling/disabling


high-speed printing function
0: PPS(RS-485)
Logic setting of selecting time
22 Opt_TimeSync 1: IRIG-B(RS-485)
synchronization mode
2: PPM(DIN)
Logic setting of enabling/disabling the
23 En_DuralNet_GOOSE 0/1 GOOSE module to work in dual Ethernet
mode.
3. [IP_Addr_NetX], [Subnet_Mask_NetX], [En_NetX] (X=A, B, C, D)
These are used for Ethernet communication based on the 103 protocol. When the IEC 61850
protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.
4. [COMX_Protocol] (X=1, 2)
Communication protocol of rear RS-485 serial port X (X=1, 2).
0: IEC 60870-5-103 protocol
2: Modbus Protocol
5. [En_BlkComm]
It is set as “1”when the equipment is in maintenance. During such period, the fault report due to
test will not be sent upstream through communication ports, while local display and printing will not
be affected.
It is set as “0”when the equipment is in service. The relation between this setting and binary input
[BI_BlkComm] is “OR”, i.e. as long as one of them is set as “1”, such information as fault report
and waveform will not be sent upstream.
6. [En_Auto_Prin]t
If automatic print is required for fault report after protection operating, it is set as “1”. Otherwise, it
should be set to “0”.
7. [En_HiSpeed_Print]
It is set as “0”for common printing with high definition, while it is set as “1”for high -speed printing.
8. [Opt_TimeSync]
It is set as "0", “1”or “2”for different external clock source.
0: PPS (pulse per second) differential
1: IRIG-B differential
2: PPM (pulse per minute) via external contact

9. [En_DuralNet_GOOSE]
It is the logic setting of enabling the GOOSE module to work in dual Ethernet mode.
“1”: The GOOSE module is able to work in dual Ethernet mode.
“0”: Disable the NET B link of the GOOSE module, and then the GOOSE module can only work in
single Ethernet mode.
 Setting path
Main Menu -> SETTINGS -> COMM SETTINGS
7.3 System Settings
 Setting list
Table 7.3-1 System settings

1 Active_Grp 1~4 1 Current setting group
Max 10
2 Equip_ID Identity of the protection equipment
characters
Secondary phase-to-phase voltage
3 U2n_PP_VT 100~130 0.01
of VT
Secondary broken-delta voltage of
4 U2n_DeltVT_XXX 100~130 0.01
XXX side of VT.
0.01~10000
5 Sn 0.01MVA Transformer capacity
MVA
Connection type of HV side winding.
6 WdgConn _HVS 0~1 1
“0”: Y connection; “1”: Δ connection
Relative o’
clock of MV side winding
7 Clk_MVS_WRT_HVS 1~12 1
with respect to HV side winding.
Relative o’
clock of LV side winding
8 Clk_LVS_WRT_HVS 1~12 1
with respect to HV side winding.
Primary rated voltage of HV side
9 U1n_HVS 0~9999 kV 0.01kV
stated on nameplate.
Primary rated voltage of MV side
10 U1n_MVS 0~9999 kV 0.01kV
Primary rated voltage of LV side
11 U1n_LVS 0~9999 kV 0.01kV
12 U1n_VT_XXX 1~2000 kV 0.01kV Primary voltage of VT of XXX side.


I1n_BakCT_HVS Primary current of CT of HV side for
13 0~60000A 1A
backup protections.
Secondary current of CT of HV side
14 I2n_BakCT_HVS 1A or 5A
for backup protections.
Primary current of CT of MV side for
15 I1n_BakCT_MVS 0~60000A 1A
backup protections.
Secondary current of CT of MV side
16 I2n_BakCT_MVS 1A or 5A
Primary current of CT of LV side for
17 I1n_BakCT_LVS 0~60000A 1A
backup protections.
Secondary current of CT of LV side
18 I2n_BakCT_LVS 1A or 5A
Primary current of CT of common
19 I1n_BakCT_CW 0~60000A 1A
winding for backup protections.
Secondary current of CT of common
20 I2n_BakCT_CW 1A or 5A
winding for backup protections.
21 I1n_CT_XXX 0~60000A 1A Primary current of CT of XXX side.
Secondary current of CT of XXX
22 I2n_CT_XXX 1A or 5A
side.
Primary current of zero-sequence CT
23 I1n_CT_NP_XXX 0~60000A 1A
of XXX side.
Secondary current of zero-sequence
24 I2_CT_NP_XXX 1A or 5A
CT of XXX side.
25 En_In_VT_XXX 0/ 1
VT of XXX side into service.
PCS-PC software, which may be “HVS”, “MVS”, “HVS1”,”HVS2”and etc.
1. [ Active_Grp]
Number of protection setting group. Four group settings are provided, but the system settings
are common for each group.
2. [Equip_Name]
This setting is used to set the name of the equipment being protected by the relay. Maximum
six characters of ASCII code, for report printing only.
3. [Sn], [U1n_HVS], [U1n_MVS], [U1n_LVS], [I1n_CT_XXX], [I2n_CT_XXX]

During the calculation of current differential protection, in order to get current correction ratio
of each side of the transformer automatically, these basic parameters are needed, such as
transformer capacity, phase-to-phase primary voltages of each side and CT ratios of each
side.
4. [WdgConn_HVS], [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]
[WdgConn_HVS] is the setting of selecting the winding connection mode of side 1. “0”is for Y
winding and “1”is for delta winding.
[Clk_MVS_WRT_HVS] and [Clk_LVS_WRT_HVS] are repectively settings to set the actual

o’clock of MVS winding and LVS winding. If anyone is not used, the corresponding setting is
recommended to be set as 0.
These logic settings are used to set connection group of transformer for the calculation of
differential protection in the equipment.
5. [U1n_XXX]
Setting principle of rated voltages of each side is to take the primary rated voltage marked on
the nameplate of transformer as the primary rated voltage of corresponding side. For an
on-load tap changing transformer, the voltage of transformer with tap in middle position can
be taken as the value of this setting. As to other kind of transformers, actual operation voltage
(i.e. phase-to-phase voltage) shall be taken as this setting value, otherwise the calculation of
correction coefficient may be wrong
For example, if the voltage at 220kV side is 230kV for an on-load tap changing transformer
with tap in its middle position, and then the setting is set as 230kV.
NOTE: For one side not used in the relay, please set the primary rated voltage value (i.e.
[U1n_XXX]) of the corresponding side as “0”.
6. [U1n_VT_XXX], [U2n_VT_XXX]
These settings are primary voltage and secondary voltage values of the three-phase VT of
three side of a transformer respectively, which are phase-to-phase voltage values.
For example, if the voltage ratio is 220kV/100V at HV side of a transformer, [U1n_VT_HVS]

shall be set as “220kV”and [U2n_VT_HVS] should be set as “100V”.
7. [I1n_CT_XXX], [I2n_CT_XXX]
Set the settings [I1n_CT_XXX] and [I2n_CT_XXX] respectively according to the actual
primary value and secondary value of the corresponding side CT.
NOTE: For some CT not used, the secondary rated current value of the corresponding CT
must be set as “1A”or “5A”.
8. [I1n_BakCT_HVS], [I2n_CT_HVS], [I1n_BakCT_MVS], [I2n_BakCT_MVS] ,

[I1n_BakCT_LVS], [I2n_BakCT_LVS]

Set the settings [I1n_BakCT_HVS(MVS,LVS)] and [I2n_BakCT_HVS(MVS,LVS)] respectively

according to the actual primary value and secondary value of the corresponding side CT for
backup protection.
NOTE: If the summation value of currents of multi CTs at one side is used as for backup
protection calculation, ratios of each CT must be same.
NOTE: For some CT not used, the secondary rated current value of the corresponding CT
must be set as “1A”or “5A”.
5. [En_In_VT_XXX]
This is the logic setting of enabling or disabling VT of XXX side into service.
“0”: disable VT into service; “1”: enable VT into service
If VT of some side is not installed or the protection equipment is in service, the setting should
be set as “0”.
 Setting path
Main Menu -> SETTINGS -> SYSTEM SETTINGS
7.4 Equipment Description Settings
 Setting list
Table 7.4-1 Equipment description settings
No. Setting Item Range

1 NameDef_CB_XXX Setting used to define the name of circuit breaker of XXX side.
Setting used to define the name of tripping output group n
2 NameDef_TrpOutn
(n=1,2,… , 10).
PCS-PC software, which may be “HVS”, “MVS”, “HVS1”,”HVS2”and etc.
1. [NameDef_CB_XXX]
This setting is used for user to define the name of circuit breaker of XXX side only for SLD display
according to user habit. For example HV side circuit breaker is named as 5001.
2. [NameDef_CB_XXX]

This setting is used to define the name of tripping output group n (n=1,2,… , 10). For example,
“TrpOutp1”is named as “TrpHVS”(i.e. Trip HV side breaker).
 Setting path
Main Menu -> SETTINGS -> EQUIP DESCRON SETTINGS
7.5 SLD Settings
SLD settings are dedicated for configuring single line diagram (SLD) on LCD display of the
protected transformer. User can set the branches of each side of transformer for the SLD on LCD
by the following settings which are stored in non-volatile memory, so the LCD can always display
the latest configured SLD.
The winding connection mode of SLD is controlled by the logic settings [WdgConn_HVS],
[Clk_MVS_WRT_HVS] and [Clk_LVS_WRT_HVS] in “SYSTEM SETTINGS”menu.,
 Setting list
Table 7.5-1 SLD settings

1 4 SLD_Branch_HVS 0~3 1 Display branches of HV side
2 5 SLD_Branch_MVS 0~3 1 Display branches of MV side
3 6 SLD_Branch_LVS 0~3 1 Display branches of LV side
Primary value/ Select display primary value or
4 7 Opt_SLD_ValueDispl
Second value secondary value on SLD.
1. [SLD_Branch_HVS], [SLD_Branch_MVS], [SLD_Branch_LVS]
These settings are to configure branch amount of each side of transformer for SLD displaying on
local LCD. If the setting of one side is set as “0”,
“0”: no branch, the corresponding side will not be displayed on SLD.
“1”: one branch.
“2”two braches
“3”: three branches.
 Setting path
Main Menu -> SETTINGS -> SLD SETTINGS

7.6 Equipment VEBI Settings
Each virtual enabling binary input (VEBI) setting is one of the conditions that decide whether the
relevant protection is in service, when this relay is energized. Each VEBI is an “AND”condition
of enabling the relevant protective element with the corresponding binary input and logic
setting. Through SAS or RTU, the virtual enabling binary input can be set as “1”or “0”; and it
means that the relevant protection can be in service or out of service through remote command. It
provides convenience for operation management.
 Setting List
Table 7.6-1 Equipment VEBI settings
No. Symbol Range Explanation

VEBI setting of enabling/disabling current differential
1 VEBI_Diff 0/ 1
protection and DPFC current differential protection.
VEBI setting of enabling/disabling restricted earth fault
2 VEBI_REF_HVS 0/ 1
protection element of HV side.
3 VEBI_REF_MVS 0/ 1
protection element of MV side.
4 VEBI_REF_LVS 0/ 1
protection element of LV side.
VEBI setting of enabling/disabling winding differential
5 VEBI_WdgDiff_HVS 0/ 1
6 VEBI_WdgDiff_MVS 0/ 1
7 VEBI_WdgDiff_LVS 0/ 1
VEBI setting of enabling/disabling overexcitation
8 VEBI_OvExc 0/ 1
protection.
9 VEBI_FreqProt 0/ 1 VEBI setting of enabling/disabling frequency protection.
10 VEBI_MR 0/ 1 VEBI setting of enabling/disabling mechanical protection.
VEBI setting of enabling/disabling impedance protection
11 VEBI_Z_HVS 0/ 1
element of HV side.
12 VEBI_Z_MVS 0/ 1
element of MV side.
13 VEBI_Z_LVS 0/ 1
element of LV side.
VEBI setting of enabling/disabling overcurrent protection
14 VEBI_OC_HVS 0/ 1
element of HV side.
15 VEBI_OC_MVS 0/ 1
element of MV side.


16 VEBI_OC_LVS 0/ 1
element of LV side.
VEBI setting of enabling/disabling zero-sequence
17 VEBI_ROC_HVS 0/ 1
overcurrent protection element of HV side.
18 VEBI_ROC_MVS 0/ 1
overcurrent protection element of MV side.
19 VEBI_ROC_LVS 0/ 1
overcurrent protection element of LV side.
VEBI setting of enabling/disabling overvoltage protection
20 VEBI_OV_HVS 0/ 1
element of HV side.
21 VEBI_OV_MVS 0/ 1
element of MV side.
22 VEBI_OV_LVS 0/ 1
element of LV side.
23 VEBI_ROV_HVS 0/ 1
overvoltage protection element of HV side.
24 VEBI_ROV_MVS 0/ 1
overvoltage protection element of MV side.
25 VEBI_ROV_LVS 0/ 1
overvoltage protection element of LV side.
VEBI setting of enabling/disabling undervoltage protection
26 VEBI_UV_HVS 0/ 1
element of HV side.
27 VEBI_UV_MVS 0/ 1
element of MV side.
28 VEBI_UV_LVS 0/ 1
element of LV side.
VEBI setting of enabling/disabling thermal overload
29 VEBI_ThOvLd_HVS 0/ 1
protection element of HV side.
30 VEBI_ThOvLd_MVS 0/ 1
protection element of MV side.
31 VEBI_ThOvLd_LVS 0/ 1
protection element of LV side.
VEBI setting of enabling/disabling breaker failure
32 VEBI_BFP_HVS 0/ 1
33 VEBI_BFP_MVS 0/ 1
34 VEBI_BFP_LVS 0/ 1


VEBI setting of enable/disable protection settings being
35 VEBI_Remote_Cfg 0/1
modified remotely.
 Setting path
Main Menu -> SETTINGS -> EQUIP VEBI SETTINGS


Chapter 8 Configurable Function
By adoption of PCS-PC software, it is able to make system configuration, function configuration,

binary input and binary output configuration, LED indicator configuration and programming logic
for PCS-978 protection device.
8.2 Introduction on PCS-PC software
PCS-PC software, assorted with UAPC platform device, is developed in order to meet customer’ s
demand on functions of device such as device configuration and programmable design. It selects
substation as the core of data management and the device as fundamental unit, supporting one
substation joint to govern many ones of the devices. The software provides on-line and off-line
functions: on-line mode: Ethernet connected with the device to support IEC 60870-5-103 protocol
and downloading of binary files through Ethernet net; off -line mode: off-line setting configuration.
In addition, it also supports programmable logic to meet customer’ s corresponding demand. For
any detail, please refer to Instruction Manual of PCS-PC Auxiliary Software.
Overall functions:
 Protective equipment Configuration (off-line function)
 Programmable logic (off-line function)
 Setting configuration (off-line & on-line function)
 Real-time display of analogue and digital quantity of device (on-line function)
 Display of sequence of report (SOE) (on-line function)
 Analysis of waveform (on-line function)
 Remote control (on-line function)
 File downloading/uploading (on-line function)
8.3 Protective Equipment Configuration
8.3.1 System Configuration
Warning: The system configuration shall only be operated by professionals who are
familiar with protection object and protection device. Or else, any incorrect configuration
may cause serious damage to the device during its operation. In general, these
configuration works have been completed before equipment leaving factory.

Warning: If the system configuration is really need, user must select “Run the whole
script”item in the right click menu before other configuration operations.
8.3.1.1 Configuration of 3-phase Current Input
1. Select number of 3-phase current branch supported by the equipment (no more than 10).
2. Define name of each group of 3-phase current input (I1~I10), e.g. HV side I branch, MV side,
etc. There will be corresponding changes in displaying CT alarm message and sampling
value item relevant to current.
3. Define AC input number of phase A, B, C of 3-phase current corresponding to analog input

module. For example, AC module NR1401 provides 12 groups of current/voltage input which
shall be numbered from top to bottom. Seeing from the rear of device, AI module on the left
side is numbered from 1 as shown in the diagram below.
Presently, PCS-978 provides two types of AC module for selection: full current module (12
current input) and 6 current inputs and 6 voltage inputs module (the last 3 voltage inputs shall
vary according to phase voltage or zero sequence voltage input.).
Schematic diagram of current input numbering of AC slots (rear view)
4. Configuration steps
(1) Firstly click “Three_phase_current configuration”in configuration tree and unfold it:

After unfolding:
(2) Confirm number of 3-phase current of protected transformer that leads to protection
equipment and input it to configuration software; meanwhile, name selected 3-phase
current inputs.
(3) Continually unfold selected 3-phase current input and configurate AC input number of
phase A, B and C corresponding to AI module. When the AC input number is “0”, it
means that there is no effective input defined.

8.3.1.2 Configuration of Zero-Sequence Current
1. Select number of zero-sequence current branches supported by the equipment (no more than
10).
2. Define name of each group of 3-phase zero-sequence current input（I1g~I10g）, e.g. HV side
zero-sequence, MV side zero-sequence, etc. There will be corresponding changes in
displaying CT alarm message and sampling value item relevant to zero-sequence current.
3. Define AC input number of each zero-sequence current corresponding to AI module.
8.3.1.3 Voltage Configuration
1. Select voltage branch (including 3-phase voltage and zero sequence voltage) number
supported by the equipment (no more than 3).
2. Define name of each group of voltage input, e.g. HV side, MV side, etc. There will be
corresponding changes in displaying VT alarm message and sampling value item relevant to
voltage.
3. Define AC input number of phase A, B and C voltages and zero-sequence voltage

corresponding to AI module.
4. Small VTs of the equipment for collecting zero-sequence voltage and phase voltage are
different. Please pay attention during voltage configuration.
8.3.1.4 Configuration of Current Differential Protection
1. Select “Enable” for the next operation or “Disable” for hiding the protective function in
protective equipment.

2. Make configuration of current engaged in current differential protection. Firstly select

corresponding 3-phase current input of each differential branch. Protective equipment is able
to provide differential protection with 6 branches at most. Names of branch current are
“Branch_1_Current_Configuration”~”Branch_6_current_configuration”and that of 3-phase
current inputs are “I1”~“I10”.
3. Protective equipment needs to know which side each curren t branch engaged in current
differential protection belongs to and make configuration for current branch at each side.
Effective and ineffective current branch configurations are set as “1”and “0”respectively. For
example, there are two branches at HV side defined as “Branch_1_current_configuration”and
“Branch_2_current_configuration”respectively; therefore, “1”shall be set at corresponding
position and “0”is for others. PCS-PC software has the function of automatic mutual exclusion.
Once one current is confined to be at HV side, it will not be configured to other sides.
8.3.1.5 Configuration of Restricted Earth Fault Protection
1. Select “Enable” for the next operation or “disable” for hiding the protective function in
2. Make configuration of restricted earth fault (REF) protection of each side and select current
engaged in REF protection calculation. REF protection of some side is able to be configured

with three groups of 3-phase current and one group of zero-sequence current at most. If there
is one branch no used, select “NONE”. For example, I1 and I2 are two branches at HV side
and I1g is zero-sequence current at HV side; these three groups of current form REF
protection at HV side. It is able to set “Three_phase_current_1_configuration” as “I1”,
“Three_phase_current_2_configuration” as “I2”, “Three_phase_current_3_configuration” as
“NONE”and “Zero_sequence_current_configuration”as “I1g”.
8.3.1.6 Winding Differential Protection
2. Make configuration of winding differential protection of each side and select current engaged
in the protection calculation. Winding differential protection of some side is able to be
configured with maximum five groups of 3-phase current. If there is one branch no used, select
“NONE”.
3. Make configuration of current direction. Configure the current direction according to the actual
CT polarity in order to ensure that winding differential current is equal to zero during the
normal operation. For example, if I1 and I2 two branches are engaged for winding differential
protection and the differential current calculation equation is I1-I2 according to the actual CT
polarity, then “Three_phase_current_2_direction_reverse”is set as “Enabled”.

8.3.1.7 Configuration of Backup Protection
2. Configure current with the range of None, I1 , I2, … ,and I10 for backup protection at one side,
and “1”for used, “0”for not used. Current for protection calculation is summation of currents of
all branches at this side.
3. Select zero-sequence current with the range of I1g, I2g, … , and I10g for backup protection.
4. Select voltage with the range of U1, U2 and U3 for backup protection.
5. For example, if current value for backup protection at HV side is summation of I1 and I2,
corresponding value of I1 and I2 shall be set as “1”and others set as 1. Zero-sequence current
is I1g, so pull down the menu to select I1g in configuration for zero-sequence current input. If
voltage is selected to be U1, pull down the menu to select U1 in voltage configuration.

8.3.1.8 Configuration of Voltage for Overexcitation and Frequency Protections
Overexcitation protection and frequency protection share the same voltage, and user can select
the voltage to do relevant calculation by configuration software with a range U1~U3.
8.3.1.9 Configuration of System Frequency
1. System frequency can be selected to be 50Hz or 60Hz.
There is a logic setting [En_FreqTrack] in “INTERNAL SETTINGS”menu to enable the

frequency tracking function which is the sampling interval of the equipment is auto-adjusted
according to actual frequency. This setting can be set only by PCS -PC software. Frequency
tracking scope is 45Hz to 51Hz for system of 50Hz and is 55Hz to 62Hz for system of 60Hz.
The equipment will switch over to non-tracking mode automatically if positive-sequence
voltage is less than 8V.
2. Select whether frequency tracking function shall be enabled. (The logic setting is in the
submenu of system settings.)
3. Select time delay mode of backup protection in frequency tracking. This configuration can not
work until the device has enabled frequency tracking function. There are two parameters –
time and cycle– available for selection. In time mode, operation time of backup protection is
time delay setting; in cycle mode, operation time of backup protection is the cycles calculated
from time delay setting and rated system frequency.
For example: when rated system frequency is 50Hz, the value of time delay setting is 1s. In

actual operation, system frequency is 49Hz when protection operates and the equipment is in
frequency tracking state, so the actual time delay amounts 50 cycles or 1.02s
( 1/49*50=1.02s). Selection of time delay mode shall coincide with time delay mode of
protection equipment. For instance, if PCS-978 equipment works with other microcomputer
protection equipment, it is recommended to select cycle mode (Microcomputer protection
usually adopts sampling cycle as interval.); while if it works with IC (integrated circuit) time
relay, time mode can be selected.
8.3.1.10 Configuration of LCD Single Line Diagram
1. Configure voltages to be displayed at each side, with a range of None, I1, I2 and I3.
2. Configure currents to be displayed at each side, with a range from I1g toI10g.
3. Configure the display of the sum of currents of some side.
4. Configure zero-sequence currents to be displayed at each side, with a range from I01 toI010
5. For example, if there are two branches I1 and I2 at HV side, “HV_side_current_configuration”

shall be 2; and “Branch_1_current_configuration”and “Branch_2_current_configuration”shall
be I1 and I2 respectively.
8.3.1.11 Configuration of Menu Display
1. Select voltage displayed at each side with a range none, U1, U2 and U3.
2. Configure current displayed at each side with a range I1~I10.
3. Configure zero-sequence current displayed at each side with a range I1~I10.

4. For example, if there are two branches I1 and I2 at HV side; and zero-sequence current is I1g
and voltage is U1, voltage shall be selected to be “1”and that at position corresponding to
current and others shall be “1”and “0”respectively.
8.3.2 Function Configuration

Whether some protection is enabled or disabled shall be configured. In case of “Disable”is
selected, the protective function in protective equipment is hidden.
8.3.3 Configuration of LED Indicators
1. This equipment provides 20 LED indicators, among which the first three are “HEALTHY”LED,
“ALARM“LED and “TRIP”LED and the rest 17 LEDs can be configured by users as required.
2. The right tree structure in the software provides elements for lighting up, including protection
elements, alarm elements and binary input elements.
3. Use “KeepLight”to choose whether hold LED or not. In case of “Yes”selected, resetting must
be performed by the resetting button once it is lit. In case of “No”selected, the signals will reset
automatically once the input signal returns.

4. If users hope the user-defined LED 1 (the fourth one) is lit and held when differential protection
operates; the user-defined LED 2 (the fifth one) is lit and not held when restricted earth fault
protection of HV side operates , configure it as per the following picture.
8.3.4 Configuration of Binary Input
1. Pin number of user-defined binary input on module is provided on the left of the interface.
2. The next step is to set debounce time (unit: ms) of the corresponding binary inputs. Debounce
mode can be from 0 to 1 or from 1 to 0, which can be set separately.
3. The “BinaryIn BinaryOut List”at the right is the corresponding function of the binary input,
which needs the user to configure. User can draw it from the right list.
4. The available variables are: binary inputs of enabling protective function, binary input of
mechanical signal, output of programmable logic.
In case of binary inputs of enabling protective function, the binary input is enabled when it is “1”.
If some binary input of enabling protective function has no corresponding connection, it is fixed
enabled.
If mechanical signal input is connected, the corresponding module must be mechanical module
NR1533. On condition that “Destination”is connected, no any operation is executed within the
program, and only directly transform input into output used as input of programmable logic.

8.3.5 Configuration of Binary Output

1. The function is applied for configuration of binary output terminals of NR1123 signal module of
equipment
2. There are total 7 groups of binary output, and each group includes one contact or two
contacts.
3. Users can draw the elements from the right list, serving as input for contact outputting.
4. The optional signals include: protection elements, alarm elements, binary inputs and fault
detector signal of protection element.
5. In the event that user want to use the first group output contacts (i.e. contacts (pin1,pin2), (pin3,
pin4) on board 15) as alarm output contacts of thermal overload of HV side, find the
corresponding alarm element in the right tree structure and draw it to the corresponding
position of the “Board15_Pin1_2_Pint3_4”.

8.3.6 Setting configuration

After function configuration is finished, disabled protective function is hidden in equipment and in
setting configuration list of PCS-PC software.
1. Users can configure the communication parameters, system settings, SLD settings and etc.
2. Each stage of protection can be configured. For example, the maximum configuration of
overcurrent protection of HV side is four stages, and characteristic of each stage can be
configured as definite time, standard inverse time, very inverse time, extremely inverse time,
long-time inverse time, user-defined inverse time, or out of service.
3. Users can select to show or hide some setting, and modify typical setting values.


Chapter 9 HMI Operation Instruction
9.1 Human Machine Interface Overview
The human-machine interface consists of a human-machine interface (HMI) module which

allows a communication as simple as possible for the user. The HMI module includes:
 A 320×240 backlight LCD visible in dim lighting conditions for monitoring status, fault
diagnostics and setting, etc.
 LED indicators on the front panel for denoting the status of this protection operation.
 A 9-key keypad on the front panel of the device for full access to the device.
PCS-978 has two types of chassis 4U and 8U shown in the following two figures.
G RP
C
ES
Figure 9.1-1 Front panel of 4U chassis

5
PCS-978
HEALTHY
ALARM TRANSFORMER PROTECTION
TRIP
RP
G
ENT
C
ES
1 3
4
2
Figure 9.1-2 Front panel of 8U chassis
Indication No. Description

1 A 320×240 dots liquid crystal display (LCD)
2 20 LED indicators
3 A 9-key keypad
A DB9 RS-232 port for communication with a PC for local
4
communication
5 LOG, device type and name
9.1.1 Functionality
 The HMI module helps to draw your attention to something that has occurred which may
activate a LED or a report display on the LCD.
 You as the operator may have own interest to view a certain data.
 Use menus navigate through menu commands and to locate the data of interest.
9.1.2 Keypad and Keys
The keypad and keys on the front panel of the equipment provide convenience to the operator to
view a certain data or change the device’
s setting.
The keypad contains nine keys, and each key has different function to the other one. Figure 9.1-3

shows the keypad and keys.
P
GR
E SC
Figure 9.1-3 Keypad mounted on the front panel
No. Symbol Description

, , and , arrow
1 Move between selectable branches of the menu tree.
buttons
2 “+”, “-“ Change parameters or setting values.
3 ENT Provide Enter/Execute function.
4 GRP Setting Group selection.
5 ESC Exit the present level in the menu tree.
NOTE:
 Any setting change shall be confirmed by simply pressing “+”, “”, “”, “-“, “ENT”in
sequence.
 Any report delete operation shall be executed by pressing “+”, “-“, “+”, “-“, “ENT”in
sequence.
9.1.3 LED Indications
Figure 9.1-4 the figure shows the LED indications
A brief explanation has been made as bellow.
LED Display Description

When the equipment is out of service or any hardware
HEALTHY Off
error is defected during self-check.

LED Display Description

Lit when the equipment is in service and ready for
Steady Green
operation.
Off When equipment in normal operating condition.
ALARM Lit when VT circuit failure, CT circuit failure or other
Steady Yellow
abnormal alarm is issued.
Off when the equipment is in normal operating condition
TRIP
Steady Red Lit when any protection element trips.
NOTE:
 The “HEALTHY”LED can only be turned on by energizing the equipment again to restart
the relay.
 “ALARM” LED is turned on when abnormalities of equipment occurs like above

mentioned and can be turned off after abnormalities are removed except alarm report
[Alm_CTS] which can only be reset only when the failure is removed and the equipment
is rebooted or re-energized.
 The “TRIP”LED is turned on once any protection element operates and remains lit even
after the trip command goes off. The “TRIP” LED can be turned off by pressing the
signal RESET button on the front panel.
 Other LED indicators with no labels are programmable and user can configure them to be
lit by signals of operation element, alarm element and binary output contact according to
requirement through PCS-PC software.
9.1.4 Communication Port
Figure 9.1-5 Communication ports
It is used to access the hardware of the protection device via HyperTerminal. This port is only used
to monitor the communication state by engineering debugging personnel and debug the program
by developers.
9.1.5 Communication
The MON module is comprised by embedded processor of high performance, FLASH, SRAM,
SDRAM, Ethernet controller and other peripheral equipments. It can realize the management,
human machine interface, communication and waveform recording of the whole device. The MON
module uses the data of other modules in the receiver device of internal bus, and communicates
with LCD panel via RS-485 bus.

Figure 9.1-6 Rear view and terminal definition of NR1102C
Take NR1102A as an example, its rear view and the definition of terminals are shown as Figure
9.1-6. This module is equipped with two 100BaseT Ethernet interface, PPS/IRIG -B differential
synchronization interface and RS-232 printer interface.
The Ethernet interface can be used to communication with PC via auxiliary software (PCS-PC) by
connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-PC). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “SETTINGS→ EQUIP_SETTINS”, it should be ensured that the protection
device and PC are in the same network segment. For example, setting the IP address and subnet
mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
The IP address and subnet mask of protection device should be [IP_Addr_NetA]= 198.87.96.XXX,
[Subnet_Mask_A]=255.255.255.0, [En_NetA]=1. (XXX can be any value from 0 to 255 except
102)
9.2 Understand the HMI Menu Tree
9.2.1 Overview
Press “▲ ”of any running interface and enter the main menu. Select different submenu by “▲ ”and
“▼ ”. Enter the selected submenu by pressing “ENT”or “► ”. Press “◄ ”and return to the previous
menu. Press “ESC”and exit the main menu directly. For sake of executing the command menu

again, one command menu will be recorded in the quick menu after its first execution. Five latest
menu commands can be recorded in the quick menu. When the five menu commands are
recorded, the latest menu command will cover the earliest one, adopting the “first in first out”
principle. It is arranged from top to bottom and in accordance with the execution order of command
menus. Press “▲ ”to enter the main menu with the interface as shown in the following diagram:
For the first powered protective device, there is no recorded shortcut menu. Press “▲ ”to enter the
main menu with the interface as shown in the following diagram:
INTERFACE
TEST_MODE
VERSION
CLOCK
LOCAL_CTRL
SETTINGS
PRINT
REPORT
VALUES

Figure 9.2-1 Tree diagram of total command menu
Under the main interface, press “▲ ”to enter the main menu, and select submenu by pressing “▲ ”,
“▼ ”and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all the submenus under menu tree of the protection device.
9.2.2 VALUES
This menu is mainly used to display the real time sampling value of current and voltage and the
input state of the protection device, which fully reflects the running environment of the protection
device. As long as the displayed values of the equipment consist with the actual running situation,
basically, the protection device can work normally. This menu is set to greatly facilitate the
debugging and maintenance of people on site.

The submenu “VALUES”has following submenus.
No. Item Description

Display sampled and calculated values on protection
1 PROT_MEASUREMENT
DSP module.
Display sampled and calculated values on fault detector
2 FD_MEASUREMENT
DSP module.
3 BI_STATE Display the input signal state.
4 ALM_STATE Display the alarm signal state.
5 COMM STATE Display the communication state
9.2.2.1 PROT_MEASUREMENT
The submenu “PROT_ MEASUREMENT”has following submenus.

Display measured values of HV side on protection
1 PROT_HVS_METERING
DSP module.
Display measured values of MV side on protection
2 PROT_MVS_METERING
DSP module.
Display measured values of LV side on protection DSP
3 PROT_LVS_METERING
module.
Display corrected currents for current differential
4 PROT_DIFF_CORR_CURR
protection on protection DSP module.
Display corrected currents for REF protection on
5 PROT_REF_CORR_CURR
protection DSP module.
Display corrected currents for winding differential
6 PROT_WDG_CORR_CURR
Display differential and restraint currents, restraint
7 PROT_CALC_DIFF_CURR thresholds, and harmonics for current differential
8 PROT_CALC_REF_CURR thresholds, and harmonics for REF protection on
9 PROT_CALC_WDG_CURR thresholds, and harmonics for winding differential
PROT_OVEXC_PROT_ Display frequency related values for overexcitation
10
METERING protection on protection DSP module.
11 PROT_PHASE_ANGLE Display phase angles on protection DSP module.
Display calculated settings for current differential
12 PROT_DIFF_CALC_SETTINGS
Display calculated settings for REF protection on
13 PROT_REF_CALC_SETTING
Display calculated settings for wingding differential
14 PROT_WDG_CALC_SETTING

The submenu “PROT_PHASE_ANGLE”has following submenus.

Display phase angles between currents of each side
1 PROT_CURR_ANG_BET_SIDES
on protection DSP module.
2 PROT_VOLT_ANG_BET_SIDES Display phase angles between voltages of each side
Display phase angles between voltage and current of
3 PROT_ANG_BET_CURR&_VOLT
each side on protection DSP module.
Display phase angles between corrected currents for
4 PROT_DIFF_CORR_CURR_ANG current differential protection on protection DSP
module.
5 PROT_REF_CORR_CURR_ANG
REF protection on protection DSP module.
6 PROT_WDG_CORR_CURR_ANG winding differential protection on protection DSP
module.
9.2.2.2 FD_MEASUREMENT
The submenu “FD_MEASUREMENT”has following lower submenus.

Display measured values of HV side on fault detector
1 FD_HVS_METERING
DSP module.
Display measured values of MV side on fault detector
2 FD_MVS_METERING
DSP module.
Display measured values of LV side on fault detector
3 FD_LVS_METERING
DSP module.
4 FD_PHASE_ANGLE Display phase angles on fault detector DSP module.
The submenu “PROT_PHASE_ANGLE”has following submenus.

Display phase angles between currents of each side
1 FD_CURR_ANG_BET_SIDES
on protection DSP module.
2 FD_VOLT_ANG_BET_SIDES Display phase angles between voltages of each side
Display phase angles between voltage and current of
3 FD_ANG_BET_CURR&VOLT
each side on protection DSP module.
9.2.2.3 BI_STATE
The submenu “BI_STATE”has following submenus.

Display binary inputs derived from opto-isolated
1 BI_STATE
channels
Display virtual binary values generated by the
2 VIRTUAL_BI_STATE
equipment itself calculation.


3 GOOSE_BIBO_STATE Display GOOSE binary inputs and binary outputs.
9.2.2.4 COMM_STATE
The submenu “COMM_STATE has following submenus.

1 NET_COMM_STATE Display communication state of all Ethernet interfaces.
Display communication stage of all UART serial
2 UART_COMM_STATE
interfaces.
9.2.3 REPORT
This menu is used for displaying the fault report, abnormal record, binary signal and running
reports , so that the operator can load to view and use as the reference of analyzing accidents and
maintaining the device. All the reports are stored in non-volatile memory, it can still record the
reports even if it losses its power.
This menu includes the following command menus.
No. Item Function description

Display running and operation reports of protective
1 CTRL_REPORT
equipment.
2 BI_CHG_REPORT Display status change of binary signal.
Display self-check alarm and equipment operation
3 ALM_REPORT
abnormal alarm reports.
4 TRP_REPORT Display trip reports.
9.2.4 PRINT
This menu is used for printing device description, setting, fault report, abnormal record report,
binary signal, waveform and information related with 103 Protocol.
This menu includes the following command menus and submenus.

Print the description information of protective equipment
1 EQUIP_DESCRON
including software version.
Print settings, including communication parameter,
protection setting, virtual binary input setting, and equipment
2 SETTINGS settings. It can print by different classifications as well as
printing all settings of the device. Besides, it can also print
out the latest modified setting item.
3 TRP_REPORT Print trip reports.
4 BI_CHG_REPORT Print status change of binary signal.
Print self-check alarm and equipment operation abnormal
5 ALM_REPORT
alarm reports.


6 PRESENT_VALUES Print present sampled values, BI state, settings, etc.
7 WAVEFORM Print recorded waveforms.
Print 103 Protocol information, including function type
(FUN), information serial number (INF), general
8 IEC103_PROTOCOL
classification service group number, and channel number
(ACC).
9.2.4.1 SETTINGS
The submenu “SETTINGS”includes the following command menus.

1 SYSTEM_SETTINGS Print the system settings.
2 DIFF_PROT_SETTINGS Print the settings of current differential protection.
3 HVS_REF_SETTINGS Print the settings of REF protection of HV side.
4 MVS_REF_SETTINGS Print the settings of REF protection of MV side.
5 LVS_REF_SETTINGS Print the settings of REF protection of LV side.
Print the settings of winding differential protection of HV
6 HVS_WDG_DIFF_SETTINGS
side.
Print the settings of winding differential protection of MV
7 MVS_WDG_DIFF_SETTINGS
side.
Print the settings of winding differential protection of LV
8 LVS_WDG_DIFF_SETTINGS
side.
9 OVEXC_PROT_SETTINGS Print the settings of overexcitation protection.
10 FREQ_PROT_SETTINGS Print the settings of frequency protection.
11 MR_PROT_SETTINGS Print the settings of mechanical protection.
12 HVS_BAKPROT_SETTINGS Print the settings of backup protection of HV side.
13 MVS_BAKPROT_SETTINGS Print the settings of backup protection of MV side.
14 LVS_BAKPROT_SETTINGS Print the settings of backup protection of LV side.
15 TRP_LOGIC_SETTINGS Print the settings of tripping logic settings.
16 EQUIP_VEBI_SETTINGS Print the equipment VEBI settings of protection element.
17 GOOSE_VEBI_SETTINGS Print the GOOSE VEBI settings of protection element.
Print the equipment settings including GOOSE module
18 EQUIP_SETTINGS
settings..
19 COMM_SETTINGS Print the communication settings.
20 EQUIP_DESCRON_SETTINGS Print the description settings of protective equipment.
Print the settings of configuring SLD display on LCD of
21 SLD_SETTINGS
22 ALL_SETTINGS Print the content of all settings including equipment


parameters, system parameters, protection settings, logic
settings and virtual EBI settings.
23 LASTEST_MODIFIED Print the content of the latest modified setting.
9.2.4.2 WAVEFORM
The submenu “WAVEFORM”has following submenus.

1 DIFF_WAVE To print differential current waveforms.
2 HVS_WAVE To print voltage and current waveforms of HV side.
3 MVS_WAVE To print voltage and current waveforms of MV side.
4 LVS_WAVE To print voltage and current waveforms of LV side.
9.2.5 SETTINGS
This menu is used for checking the setting of device equipment parameter, virtual binary input
setting, protection setting, logic setting and system parameter, as well as modifying any of the
above setting items. Moreover, it can also execute the setting copy between different setting
groups.

1 SYSTEM_SETTINGS To view and modify the system settings
To view and modify the settings of current differential
2 DIFF_PROT_SETTINGS
protection.
To view and modify the settings of REF protection of HV
3 HVS_REF_SETTINGS
side.
To view and modify the settings of REF protection of MV
4 MVS_REF_SETTINGS
side.
To view and modify the settings of REF protection of LV
5 LVS_REF_SETTINGS
side.
To view and modify the settings of winding differential
6 HVS_WDG_DIFF_SETTINGS
7 MVS_WDG_DIFF_SETTINGS
8 LVS_WDG_DIFF_SETTINGS
To view and modify the settings of overexcitation
9 OVEXC_PROT_SETTINGS
protection.
10 FREQ_PROT_SETTINGS To view and modify the settings of frequency protection.
11 MR_PROT_SETTINGS To view and modify the settings of mechanical protection.
To view and modify the settings of backup protection of
12 HVS_BAKPROT_SETTINGS
HV side.


13 MVS_BAKPROT_SETTINGS
MV side.
14 LVS_BAKPROT_SETTINGS
LV side.
15 TRP_LOGIC_SETTINGS To view and modify the settings of tripping logic settings.
16 EQUIP_VEBI_SETTINGS Print the equipment VEBI settings of protection element.
17 GOOSE_VEBI_SETTINGS Print the GOOSE VEBI settings of protection element.
To view and modify the equipment settings including
18 EQUIP_SETTINGS
GOOSE module settings.
19 COMM_SETTINGS To view and modify the communication settings.
To view and modify the description settings of protective
20 EQUIP_DESCRON_SETTINGS
equipment.
To view and modify the settings of configuring SLD
21 SLD_SETTINGS
display on LCD of protective equipment.
22 COPY_SETTINGS To copy settings from one group to another group.
9.2.6 LOCAL_CTRL
This menu is used for resetting the tripping relay with latch, protection device signal lamp, LCD
display, as the same as the resetting function of binary input. Record the currently acquired
waveform data of the protection device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download.

Reset the local signal, the signal indicator lamp and the
1 TARG_RESET
LCD display.
2 TRIG_OSCILLOG Trigger waveform recording.
3 DOWNLOAD Send out the download request.
9.2.7 CLOCK
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
9.2.8 VERSION
In this menu the LCD displays software information of DSP module, MON module and HMI module,
which consists of version, creating time of software, CRC codes and management sequence
number.
9.2.9 TEST MODE
This menu is mainly used for developers to debug the program and for engineers to maintain
device. It can be used to check module information and item fault message, and fulfill the

communication test function. It’

s also used to generate all kinds of report or event to transmit to the
SAS without any external input, so as to debug the communication on site.

1 BOARD_INFO Monitor the current working state of each intelligent module.
Automatically generate all kinds of message to transmit to
the backstage, including tripping, self-check and binary
2 COMM_TEST signal transmission. It can realize the transmission of
messages of different classification, as well as the
transmission of all types of messages.
3 ITEM_TRP_REPORT Check the fault report one by one.
4 GOOSE_COMM_STATE Check the GOOSE communication state.
9.2.10 INTERFACE
This menu is mainly used for set LCD display language. This menu includes the following
command menus.

1 LANGUAGE Set LCD display language
9.3 Understand the LCD Display
9.3.1 Overview
There are five kinds of LCD display, SLD (single line diagram) display, tripping reports, alarm
reports, binary input changing reports and control reports. Tripping reports and alarm reports will
not disappear until these reports are acknowledged by pressing the RESET button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). User can press both “ENT”and
“ESC”at the same time to switch the display among trip reports, alarm reports and the SLD display.
Binary change reports will be displayed for 5s and then it’
ll return to the previous display interface
automatically. Control reports will not pop up and can only be viewed by navigating the
corresponding menu.
9.3.2 Display during Normal Operation
After the protection device is powered and turns into the initiating interface, it takes 30 seconds to
complete the initialization of protection device. During the initialization of protection device, the
“HEALTHY”indicator of the protection device goes out.
Under normal condition, the LCD will display the following interface. The LCD adopts white color
as its backlight that is activated if once there is any keyboard operation, and is extinguished
automatically after 60 seconds of no operation.
When the equipment is powered on, based on actual connection of the transformer, the LCD will

display single line diagram on its connection diagrams. If the transformer has three windings and 2
branches on LV side, the LCD will display by configuring the logic settings.
Figure 9.3-1 LCD display of single line diagram
means breaker is open. means breaker is closed.
The displayed content of the interface contains: the current date and time of the protection device
(with a format of yy-mm-dd hh:mm:ss:), the currently valid setting group number, the three-phase
current and voltage sampling values of each side, differential current, zero-sequence differential
current, frequency etc.
9.3.3 Display When Tripping
This protection device can store 64 times of fault reports and 64 times of fault waveforms. When
there is protection element operating, the LCD will automatically display the latest fault report, and
two kinds of LCD display interfaces will be available depending on whether there is self-check
report at present.
If the device has no self-check report, the display interface will only show the fault report.

Figure 9.3-2 LCD display 1 of trip report
TRP REPORT NO.2 shows the titile and SOE number of the report.
2008-11-28 07:10:00:200 shows the time when fault detector picks up, the format is
year–month-date and hour:minute:second:millisecond.
0ms FD_PcntDiff shows fault detector of protection element and operation time of fault
detector is set as 0ms fixedly.
24ms AB Op_PcntDiff shows the relative operation time and operation element of protection
element
All the protection elements have been list in chapter “Description of Operation Theory”, and please
refer to each protection element for details. Operation reports of fault detector and the reports
related to oscillography function are showed in the following table.
Table 9.3-1 Tripping report messages
No. Message Description

1 Op_FD Fault detector of some protection picks up.
2 Op_ManTrigOscillog Oscillography function is triggered manually.
3 Op_RmtTrigOscillog Oscillography function is triggered remotely.
Oscillography function is triggered by protection DSP
4 Op_ProtBrdFailTrigOscillog
module.
Oscillography function is triggered by fault detector
5 Op_FDBrdFailTrigOscillog
DSP module.
For the situation that the fault report and the self-check alarm report occur simultaneously in the
following figure, the upper half part is fault report, and the lower half part is self-check report. As to
the upper half part, it displays separately the record number of fault report, fault name, generating

time of fault report (with a format of yy-mm-dd hh:mm:ss:), protection element and tripping element.
If there is protection element, there are relative time on the basis of fault detector element and fault
phase. At the same time, if the total lines of protection element and tripping element are more than
3, a scroll bar will appear at the right. The height of the black part of the scroll bar basically
indicates the total lines of protection element and tripping element, and its position suggests the
position of the currently displayed line in the total lines. The scroll bar of protection element and
tripping element will roll up at the speed of one line per time. When it rolls to the last three lines, it’
ll
roll from the earliest protection element and tripping element again. The displayed content of the
lower half part is similar to that of the upper half part.
Figure 9.3-3 LCD display 2 of trip report and alarm report
9.3.4 Display under Abnormal condition

This protection device can store 1024 self-check reports. During the running of protection device,
the self-check report of hardware self-check errors or system running abnormity will be displayed
immediately.

Figure 9.3-4 LCD display of alarm report
ALM REPORT NO.4 shows the SOE number and title of the report
2008-11-28 09:18:47:500 shows the real time of the report: year–month-date and
hour:minute:second:millisecond
Alm_Pwr_Opto 0->1 shows the content of abnormality alarm
All the alarm elements have been listed in chapter “Automatic Supervision”.
9.3.5 Display When Binary Input Changes Status

When any binary or virtual binary input state changes or VEBI setting is modified, a new report on
change of status will be automatically displayed on LCD as follows. This protective equipment can
store 1024 events of binary signals. During the running of the equipment, the binary signals will be
displayed once the input signal state changes.

Figure 9.3-5 Display of binary change report
No.004 BI CHG REPORT shows the number and title of the report
2008-11-28 09:18:47:500 shows date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
EBI_Diff 0->1 shows the state change of binary input, including binary input name,
original state and final state
Binary inputs have been listed in input signal table and virtual binary inputs list in output table and
VEBI settings lit in setting list table in chapter “Description of Operation Theory”and please refer to
each protection element for details.
9.3.6 Display Control Report
This protection device can store 1024 pieces of the control report (i.e. user operating reports).
During the running of the protection device, the running report will be displayed after any operation
of it is conducted.

Figure 9.3-6 Display of control report
CTRL REPORT NO. 4 shows the title and the number of the report
2008-11-28 10:18:47:569 shows date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Reboot shows the state content of the user operation report.
User operating information listed below may be displayed.
Table 9.3-2 User Operating event list
No. Message Description

1 Reboot The protective equipment has been reboot.
2 Reset_Target The protective equipment has been reset.
3 Settings_Chg The settings of protective equipment have been changed.
4 ActiveGrp_Chgd Active setting group has been changed.
All reports have been deleted. （User operating event can not
5 Report_Cleared
be deleted.）
6 Waveform_Cleared All waveforms have been deleted.
7 SubProcess_Exit A Subprocess has exited.
8 Alm_Setting_Out-of-Scope A setting value is out of setting scope.
9.4 Keypad Operation

9.4.1 View Device Status
The operation is as follows:
1. Press the key “▲ ”to enter the main menu.

2. Press the key “▲ ”or “▼ ”to move the cursor to the “VALUES”menu, and then press the
“ENT”or “► ”to enter the menu.
3. Press the key “▲ ”or “▼ ”to move the cursor to any command menu item, and then press
the key “ENT”to enter the submenu.
4. Press the “▲ ”or “▼ ”to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5. Press the key “◄ ”or “► ”to select pervious or next command menu.
6. Press the key “ENT”or “ESC”to exit this menu (returning to the “VALUES”menu).
9.4.2 View Device Report

2. Press the key “▲ ”or “▼ ”to move the cursor to the “REPORT”menu, and then press the
key “ENT”or “► ”to enter the menu.
3. Press the key “▲ ”or “▼ ”to move the cursor to any command menu, and then press the
key “ENT”to enter the submenu.
4. Press the key “▲ ”or “▼ ”to page up/down.
5. Press the key “＋”or “－”to select pervious or next record.
7. Press the key “ENT”or “ESC”to exit this menu (returning to the “REPORT”menu).
For the fault report, view the single item fault report by the command menu
“ITEM_TRP_REPORT”, and the item fault report produces with change of any item of fault report.
The item fault report can save for 1024 events at most.
2. Press the key “▲ ”or “▼ ”to move the cursor to the “TEST MODE”menu, and then press
the key “ENT”or “► ”to enter the menu.
3. Press the key “▲ ” or “▼ ” to move the cursor to the command menu

“ITEM_TRP_REPORT”, and then press the “ENT”to enter the menu.
4. Press the key “＋”or “－”to select pervious or next record.
5. Press the key “ESC”to exit this menu (returning to the “TEST MODE”menu).
9.4.3 View Module Information


3. Press the key “▲ ”or “▼ ”to move the cursor to the command menu “BOARD_INFO”, and
then press the “ENT”to enter the menu.
4. Press the key “▲ ”or “▼ ”to move the scroll bar.
5. Press the key “ENT”or “ESC”to exit this menu (returning to the “TEST MODE”menu).
9.4.4 Print Device Report

2. Press the key “▲ ”or “▼ ”to move the cursor to the “PRINT”menu, and then press the
“ENT”or “► ”to enter the menu.
“ENT”to enter the menu.
 Selecting the “TRP_REPORT”, and then
Press the “＋”or “－”to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing... ”, and then automatically exit this menu
(returning to the menu “PRINT”). If the printer doesn’
t complete its current print task
and re-start it for printing, and the LCD will display “Printer Busy… ”. Press the key
“ESC”to exit this menu (returning to the menu “PRINT”).
 Selecting the command menu “ALM_REPORT”or “BI_CHG_REPORT”, and then

press the key “▲ ”or “▼ ”to move the cursor. Press the “＋”or “－”to select the
starting and ending numbers of printing message. After pressing the key “ENT”, the
LCD will display “Start Printing… ”, and then automatically exit this menu (returning to
the menu “PRINT”). Press the key “ESC”to exit this menu (returning to the menu
“PRINT”).
4. If selecting the command menu “IEC103 PROTOCOL”, “PRESENT_VALUES“ or

“EQUIP_DESCRON”, press the key “ENT”, the LCD will display “Start printing..”, and
then automatically exit this menu (returning to the menu “PRINT”).
5. If selecting the “SETTINGS”, press the key “ENT”or “► ”to enter the next level of menu.
6. After entering the submenu “SETTINGS”, press the key “▲ ”or “▼ ”to move the cursor,
and then press the key “ENT”to print the corresponding default value. If selecting any
item to printing:
Press the key “＋”or “－”to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing… ”, and then automatically exit this menu
(returning to the menu “SETTINGS”). Press the key “ESC”to exit this menu (returning to
the menu “SETTINGS”).

7. After entering the submenu “WAVEFORM”, press the “＋”or “－”to select the waveform
item to be printed and press ”ENT”to enter. If there is no any waveform data, the LCD will
display “No Waveform Data!”(Before executing the command menu “HVS_WAVE”, it is
necessary to execute the command menu “TRIG_OSCILLOG” in the menu
“LOCAL_CTRL”, otherwise the LCD will display “No Waveform Data!”). With waveform
data existing:
Press the key “＋”or “－”to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing… ”, and then automatically exit this menu (returning to
the menu “WAVEFORM”). If the printer does not complete its current print task and
re-start it for printing, and the LCD will display “Printer Busy… ”. Press the key “ESC”to
exit this menu (returning to the menu “WAVEFORM”).
9.4.5 View Device Setting

2. Press the key “▲ ”or “▼ ”to move the cursor to the “SETTINGS”menu, and then press
key “ENT”to enter the menu.
4. Press the key “▲ ”or “▼ ”to move the cursor.
5. Press the key “+”or “-”to page up/down.
7. Press the key “ESC”to exit this menu (returning to the menu “SETTINGS”).
NOTE:
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side of
the LCD to indicate the quantity of all displayed information of the command menu and the
relative location of information where the current cursor points at.
9.4.6 Modify Device Setting

2. Press the key “▲ ”or “▼ ”to move the cursor to the “SETTINGS”menu, and then
press the key “ENT”or “► ”to enter the menu.
3. Press the key “▲ ”or “▼ ”to move the cursor to any command menu, and then press
the key “ENT”to enter the menu.
4. Press the key “▲ ”or “▼ ”to move the cursor.

5. Press the key “+”or “-”to page up/down.
7. Press the key “ESC”to exit this menu (returning to the menu “SETTINGS”).
8. If selecting the command menu “EQUIP_SETTINGS”or “COMM_SETTINGS”, move

the cursor to the setting item to be modified, and then press the key “ENT”.
Press the key “＋”or “－”to modify the value (if the modified value is of multi-bit, press
the key “◄ ”or “► ”to move the cursor to the digit bit, and then press the “＋”or “－”to
modify the value), press the key “ESC ”to cancel the modification and return to the
displayed interface of the command menu “EQUIP_SETTINGS”. Press the key “ENT”
to automatically exit this menu (returning to the displayed interface of the command
menu “EQUIP_SETTINGS”).
Move the cursor to continue modifying other setting items. After all setting values are
modified, press the key “◄ ”, “► ”or “ESC”, and the LCD will display “Save or Not?”.
ESC”or press the key “◄ ”or “► ”to move the cursor. Select the
Directly press the “
“Cancel”, and then press the key “ENT”to automatically exit this menu (returning to the
displayed interface of the command menu “EQUIP_SETTINGS”).
Press the key “◄ ”or “► ”to move the cursor. Select “No”and press the key “ENT”, all
modified setting item will restore to its original value, exit this menu (returning to the
menu “SETTINGS”).
Press the key “◄ ”or “► ”to move the cursor to select “Yes”, and then press the key
“ENT”, the LCD will display password input interface.
Figure 9.4-1 Display of inputting password
Input a 4-bit password (“ ＋ ”, “◄ ”, “▲ ”or “－”). If the password is incorrect, continue

inputting it, and then press the “ESC”to exit the password input interface and return to
the displayed interface of the command menu “EQUIP_SETTINGS”. If the password is

correct, LCD will display “Save Settings… ”, and then exit this menu (returning to the
displayed interface of the command menu “EQUIP_SETTINGS”), with all modified
setting items as modified values.
NOTE:
For different setting items, their displayed interfaces are different but their modification
methods are the same.
NOTE:
After modifying the parameter settings of equipment i.e. settings in menu

“EQUIP_SETTINGS”or “COMM_SETTINGS”, the “HEALTHY”indicator of the protection
device will go out, and the protection device will automatically restart and re-check the
protection setting. If the check doesn’
t pass, the protection device will be blocked.
9. If selecting the command menu of protection element or tripping matrix such as

“DIFF_PROT_SETTINGS”, the LCD will display the following interface:
2. DIFF_PROT_SETTINGS
Group NO select
Current Group NO: 01
Group NO To be Edited 02
Figure 9.4-2 Display 1 of modifying settings
Then move the cursor to the modified value and press “ENT”to enter. If the setting
[I_Pkp_PcntDiff] is selected to modify, then press the “ENT”to enter and the LCD will
＋”or “－”to modify the value and then press
display the following interface. is shown the “
the “ENT”to enter.

Figure 9.4-3 Display 2 of modifying settings
10. If selecting the other menus, move the cursor to the setting to be modified, and then
press the “ENT”.
9.4.7 Copy Device Setting

1. Press the key “▲ ”to enter the main menu;
2. Press the key “▲ ”or “▼ ”to move the cursor to the “SETTINGS”menu, and then press
the key “ENT”or “► ”to enter the menu;
3. Press the key “▲ ”or “▼ ”to move the cursor to the command menu “COPY_SETTINGS”,
and then press the key “ENT”to enter the menu. The following display will be shown on
LCD.

Figure 9.4-4 Display of copy settings
Press the key “＋ ”or “－ ”to modify the value. Press the key “ESC”, and return to the
menu “SETTINGS”. Press the “ENT”, the LCD will display the interface for password
input, if the password is incorrect, continue inputting it, press the key “ESC”to exit the
password input interface and return to the menu “SETTINGS”. If the password is correct,
the LCD will display “Copy Settings Success!”, and exit this menu (returning to the menu
“SETTINGS ”).
9.4.8 Switch Setting Group

The ope ration is as follows:
1. Exit the main menu.
2. Press the “GRP”.

Figure 9.4-5 Display of switching setting group
Press the “＋”or “－ ”to modify the value, and then press the key “ESC”to exit this menu
(returning to the main menu). After pressing the key “ENT”, the LCD will display the password
input interface. If the password is incorrect, continue inputting it, and then press the key “ESC”to
exit the password input interface and return to its original state. If the password is correct, the
“HEALTHY”indicator of the protection device will go out, and the protection device will re-check
the protection setting. If the check doesn’
t pass, the protection device will be blocked. If the check
is successful, the LCD will return to its original state.
9.4.9 Delete Report

1. Exit the main menu.
2. Press the “＋”, “－”, “＋”, “－”and key “ENT”; Press the key “ESC”to exit this menu
(returning to the original state). Press the key “ENT”to carry out the deletion.

Figure 9.4-6 Display of deleting report
NOTE:
The operation of deleting device report will delete all messages saved by the protection
device, including tripping report, alarm report and binary change report except user
operation reports (i.e. control reports). Furthermore, the report is irrecoverable after
deletion, so the function shall be used with great cautious.
9.4.10 Modify Device Clock

2. Press the key “▲ ”or “▼ ”to move the cursor to the “CLOCK”menu, and then press the
key “ENT”to enter clock display.

CLOCK
Year 2008
Month 11
Day 28
Hour 20
Minute 59
Second 14
Figure 9.4-7 Display of modifying clock
3. Press the key “▲ ”or “▼ ”to move the cursor to the date or time to be modified.
4. Press the key ＋”or “－”, to modify value, and then press the key “ENT”to save the
modification and return to the main menu.
5. Press the key “ESC”to cancel the modification and return to the main menu.
9.4.11 Check Software Version

2. Press the key “▲ ”or “▼ ”to move the cursor to the “VERSION”menu, and then press the
key “ENT”to display the software version.
3. Press the key “ESC”to return to the main menu.
9.4.12 Communication Test

3. Press the key “▲ ”or “▼ ”to move the cursor to the command menu “COMM_TEST”, and
then press the key “ENT”to enter the menu, at this moment, the LCD will display
“Entering Communication Test… ”.

Figure 9.4-8 Display of communication test
4. Press the key “▲ ”or “▼ ”to move the cursor to select the corresponding command menu
“All Test”, “Trip Test”, “Alarm Test”and “BI Test”.
5. If selecting the “All Test”, press the “ENT”, and the device will successively carry out the
“Trip Test”, “Alarm Test”and “BI Test”.
6. If selecting the “Trip Test”, “Alarm Test”or “BI Test”, press the key “ENT”.
7. Press the ＋”or “－”to page up/down, and then press the key “▲ ”or “▼ ”to move the
scroll bar. (taking the “Trip Test”as an example):
Move the cursor to select the corresponding protection elements. Press the key “ENT”to
execute the communication test one by one, the SAS will receive the corresponding fault
report, and view the fault report produced by communication test in the command menu
“ITEM_TRP_REPORT”. Press the key “ESC”to return to the diagram of Figure 9.4-8.
NOTE:
If no input operation is carried out within 60s, exit the communication transmission and
return to the “TEST MODE”menu, at this moment, the LCD will display “Communication
Test Timeout and Exiting...”.
If selecting the “Alarm Test”or “BI Test”, not only the SAS can receive the corresponding
self-check report or binary signals, but also the self-check report or binary signals
produced by communication test can be respectively viewed by the two command menus
of “ALM_REPORT”and “BI_CHG_REPORT”in the menu “REPORT”.
8. Press the key “ESC”to exit this menu (returning to the menu “TEST MODE”, at this

moment, the LCD will display “Communication Test Exiting… ”.
9.4.13 Select Language
2. Press the key “▲ ”or “▼ ”to move the cursor to the “INTERFACE”menu, and then press
3. Press the key “▲ ”or “▼ ”to move the cursor to the command menu “LANGUAGE”, and
then press the key “ENT”to enter the menu and the following display will be shown on
LCD.
Figure 9.4-9 Display of selecting language
4. Press the key “▲ ”or “▼ ”to move the cursor to the language user preferred and press
the key “ENT”to execute language switching. After language switching is finished, LCD
will return to the menu “INTERFACE”, and the display language is changed. Otherwise,
press the key “ESC”to cancel language switching and return to the menu “INTERFACE”.
NOTE:
The LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual protection device may be
some different from it, so you shall be subject to the actual protection device.

Chapter 10 Communications

This section outlines the remote communications interfaces of NR equipment. The protective
device supports a choice of three protocols via the rear communication interface (RS -485 or
Ethernet), selected via the model number by setting. The protocol provided by the protective
device is indicated in the submenu in the “EQUIP SETTINGS”column. Using the keypad and LCD,
set the parameter [COM1_Protocol] and [COM2_Protocol], the corresponding protocol will be
selected.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be “daisy chained”together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information

10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. Please refer to the section of
“Communication Interface module”for details of the connection terminals. The rear ports provide
RS-485 serial data communication and are intended for use with a permanently wired connection
to a remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.

Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm2 per core is normally adequate. Total cable length
must not exceed 500m. The screen must be continuous and connected to ground at one end,
normally at the master connection point; it is important to avoid circulating currents, especially
when the cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the product’
s chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.
NOTE:

 It is extremely important that the 120Ω termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
 As the field voltage is much higher than that required, NR cannot assume
responsibility for any damage that may occur to a device connected to the network as
a result of incorrect application of this voltage.
 Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface
This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the submenu “EQUIP
SETTINGS”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
also connected to the exchanger and will play a role of master station, so the every equipment
which has been connected to the exchanger will play a role of slave unit.

Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication
The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings of the protective
device must be configured. To do this use the keypad and LCD user interface. In the submenu
“EQUIP SETTINGS”, set the parameters [COM1_Protocol], [COM2_Protocol] and [COM_Baud].
For using the Ethernet port with IEC60870-5-103 communication, the IP address and submask of
each Ethernet port can be set in the same submenu. Please refer to the corresponding section in
Chapter “Settings”for further details.
10.3 IEC60870-5-103 Interface over Serial Port

The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 2; compatibility level 3 is not supported.
The following IEC60870-5-103 facilities are supported by this interface:
 Initialization (reset)
 Time synchronization
 Event record extraction
 General interrogation
 General functions

 Disturbance records
10.3.1 Physical Connection and Link Layer
Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization
The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.
10.3.4 Spontaneous Events

Events are categorized using the following information:
 Type identification (TYP)
 Function type (FUN)
 Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103

protocol. Operation elements are sent by ASDU2 (time -tagged message with relative time), and
status of binary Input and alarm element are sent by ASDU1 (time-tagged message). The cause of
transmission (COT) of these responses is 1.
1. Operation elements sent by ASDU2

Table 10.3-1 Function and information numbers of operation element
FUN INF Content FUN INF Content

10 001 Op_ManTrigOscillog 10 072 Op_OC2_LVS
10 002 Op_ProtBrdFailTrigOscillog 10 073 Op_OC3_LVS
10 003 Op_FDBrdFailTrigOscillog 10 074 Op_OC4_LVS
10 004 Op_RmtTrigOscillog 10 075 Op_ROC1_LVS
10 005 Op_FD 10 076 Op_ROC2_LVS
10 006 Op_InstDiff 10 077 Op_ROC3_LVS
10 007 Op_PcntDiff 10 078 Op_ROC4_LVS
10 008 Op_DPFC_Diff 10 086 Op_ROV1_LVS
10 009 Op_REF_HVS 10 087 Op_ROV2_LVS
10 010 Op_REF_MVS 10 091 Op_ProgTrp1
10 011 Op_REF_LVS 10 092 Op_ProgTrp2
10 018 Op_DefOvExc1 10 093 Op_ProgTrp3
10 019 Op_DefOvExc2 10 094 Op_ProgTrp4
10 020 Op_InvOvExc 10 095 Op_ProgTrp5
10 031 Op_OC1_HVS 10 096 Op_ProgTrp6
10 035 Op_ROC1_HVS 10 100 Op_ProgTrp10
10 036 Op_ROC2_HVS 10 101 T01
10 037 Op_ROC3_HVS 10 102 T02
10 038 Op_ROC4_HVS 10 103 T03
10 046 Op_ROV1_HVS 10 104 T04
10 047 Op_ROV2_HVS 10 105 T05
10 051 Op_OC1_MVS 10 106 T06
10 052 Op_OC2_MVS 10 107 T07
10 053 Op_OC3_MVS 10 108 T08
10 054 Op_OC4_MVS 10 109 T09
10 055 Op_ROC1_MVS 10 110 T10
10 056 Op_ROC2_MVS 10 111 T11
10 057 Op_ROC3_MVS 10 112 T12
10 058 Op_ROC4_MVS 10 113 T13
10 066 Op_ROV1_MVS 10 114 T14
10 067 Op_ROV2_MVS 10 115 T15
10 071 Op_OC1_LVS 10 116 T16
2. Alarm element sent by ASDU1

Table 10.3-2 Function and information numbers of alarm element

11 001 Alm_BO_Test 11 049 Alm_Pwr_Opto
11 002 Alm_Setting_Out_of_scope 11 050 Alm_TrpOut
11 003 Alm_ModifySetting 11 051 Alm_DSP_ProtBrd
11 004 Alm_BoardConfig 11 052 Alm_DSP_FDBrd
11 005 Alm_Setting_ProtBrd 11 053 Alm_DefOvExc
11 006 Alm_Setting_FDBrd 11 054 Alm_InvOvExc
11 07 Alm_Sample 11 064 Alm_OvLd1_HVS
11 08 Alm_InconsistFD 11 065 Alm_OvLd2_HVS
11 09 Alm_PersistFD_ProtBrd 11 066 Alm_InitCool1_OvLd_HVS
11 010 Alm_PersistFD_FDBrd 11 067 Alm_InitCool2_OvLd_HVS
11 012 Alm_CTS_HVS 11 068 Alm_BlkOLTC_OvLd_HVS
11 013 Alm_CTS_MVS 11 069 Alm_ROV_HVS
11 014 Alm_CTS_LVS 11 070 Alm_ROC_HVS
11 022 Alm_Diff 11 071 Alm_OvLd1_MVS
11 023 Alm_REF_HVS 11 072 Alm_OvLd2_MVS
11 024 Alm_REF_MVS 11 073 Alm_InitCool1_OvLd_MVS
11 025 Alm_REF_LVS 11 074 Alm_InitCool2_OvLd_MVS
11 029 Alm_CTS 11 075 Alm_BlkOLTC_OvLd_MVS
11 030 Alm_CTS_REF_HVS 11 076 Alm_ROV_MVS
11 031 Alm_CTS_REF_MVS 11 077 Alm_ROC_MVS
11 032 Alm_CTS_REF_LVS 11 078 Alm_OvLd1_LVS
11 036 Alm_SensCTS_HVS 11 079 Alm_OvLd2_LVS
11 037 Alm_SensCTS_MVS 11 080 Alm_InitCool1_OvLd_LVS
11 038 Alm_SensCTS_LVS 11 081 Alm_InitCool2_OvLd_LVS
11 046 Alm_VTS_HVS 11 082 Alm_BlkOLTC_OvLd_LVS
11 047 Alm_VTS_MVS 11 083 Alm_ROV_LVS
11 048 Alm_VTS_LVS 11 084 Alm_ROV_MVS
3. Binary input sent by ASDU1
Table 10.3-3 Function and information numbers of binary signal

12 001 BI_Print 12 040 EBI_In_VT_LVS
12 002 BI_BlkComm 12 048 FD_PcntDiff
12 003 BI_RstTarg 12 049 FD_DPFC_Diff
12 004 EBI_Diff 12 050 FD_InstDiff
12 005 EBI_REF_HVS 12 051 FD_REF_HVS
12 006 EBI_REF_MVS 12 052 FD_REF_MVS


12 007 EBI_REF_LVS 12 053 FD_REF_LVS
12 011 EBI_OvExc 12 060 FD_DefOvExc
12 014 EBI_OC_HVS 12 061 FD_InvOvExc
12 015 EBI_ROC_HVS 12 068 FD_OC_HVS
12 017 EBI_ROV_HVS 12 069 FD_ROC_HVS
12 022 EBI_OC_MVS 12 072 FD_ROV_HVS
12 023 EBI_ROC_MVS 12 076 FD_OC_MVS
12 025 EBI_ROV_MVS 12 077 FD_ROC_MVS
12 030 EBI_OC_LVS 12 080 FD_ROV_MVS
12 031 EBI_ROC_LVS 12 084 FD_OC_LVS
12 033 EBI_ROV_LVS 12 085 FD_ROC_LVS
12 038 EBI_In_VT_HVS 12 088 FD_ROV_LVS
12 039 EBI_In_VT_MVS 12 092 TimeSync_Failed
10.3.5 General Interrogation
The GI can be used to read the status of the relay, the function numbers, and information numbers
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Functions
The generic functions can be used to read the setting and protection measurement of the relay,
and modify the setting. Two supported type identifications are ASDU 21 and ASDU 10. For more
details about generic functions, see the IEC60870-5-103 standard.
Table 10.3-4 Generic service group numbers
Group Number Group Caption Description (English)
0001 Equip_Description
0002 Trip_Element
0003 Self-Check_Alarm
0004 Binary_Input
0005 Control
0006 System_Settings
0007 Diff_Prot_Settings
0008 HVS_REF_Settings
0009 MVS_REF_Settings

0010 LVS_REF_Settings
0011 OvExc_Prot_Settings
0012 Freq_Prot_Settings
0013 HVS_BakProt_Settings
0014 MVS_BakProt_Settings
0015 LVS_BakProt_Settings
0016 Trp_Logic_Settings
0017 VEBI_Settings
18 GOOSE_VEBI_Settings
19 Device_Settings
20 Comm_Settings
21 Equip_Descrion_Settings
22 SLD_Settings
23 Setting_Group
24 Prot_HVS_Metering
25 Prot_MVS_Metering
26 Prot_LVS_Metering
27 Diff_Corr_Curr_Metering
28 REF_Corr_Curr_Metering
29 Wdg_Corr_Curr_Metering
30 Calc_Diff_Curr_Metering
31 Calc_REF_Curr_Metering
32 Calc_WDG_Curr_Metering
33 OvExc_Metering
34 Curr_Ang_Bet_Sides_Metering
35 Volt_Ang_Bet_Sides_Metering
36 Ang_Bet_Curr&Volt_Metering
37 Diff_COrr_Curr_Ang_Meteirng
38 REF_COrr_Curr_Ang_Meteirng
39 Wdg_COrr_Curr_Ang_Meteirng
40 Disturb_Info_Analog
41 Disturb_Info_Binary00

44 Fault_Data
45 Control Report
NOTE：If the setting [VEBI_Remote_Cfg] in the submenu “EQUIP VEBI SETTINGS”is
set as “0”, to modify protection settings remotely will not be allowed. Moreover,
equipment parameters are not allowed to be modified remotely whether the item
[VEBI_Remote_Cfg] is “1”or “0”.
NOTE：The above table is only an example and it will change with the differential
protection configurations.
10.3.7 Disturbance Records
This protective device can store up to eight disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
Table 10.3-5 Disturbance ACC numbers
ACC No. Content ACC No. Content

1 Ia_1 21 3I0_Calc_3
2 Ib_1 22 3I0_NP_1
3 Ic_1 23 3I0_NP_2
4 Ia_2 24 3I0_NP_3
5 Ib_2 25 3U0_Calc_1
6 Ic_2 26 3U0_Calc_2
7 Ia_3 27 3U0_Calc_3
8 Ib_3 28 3U0_NP_1
9 Ic_3 29 3U0_NP_2
10 Ua_1 30 3U0_NP_3
11 Ub_1 31 U2_1
12 Uc_1 32 U2_2
13 Ua_2 33 U2_3
14 Ub_2 34 Ida_Diff
15 Uc_2 35 Idb_Diff
16 Ua_3 36 Idc_Diff
17 Ub_3 37 I0d_REF_HVS
18 Uc_3 38 I0d_REF_MVS

ACC No. Content ACC No. Content

19 3I0_Calc_1 39 I0d_REF_LVS
20 3I0_Calc_2
10.4 IEC60870-5-103 Interface over Ethernet
The IEC60870-5-103 interface over Ethernet is a master/slave interface with the relay as the slave
device. It is properly developed by NR too. All the service of this relay is based on generic
functions of the IEC60870-5-103. The following table lists all the group number of this relay. And
this relay will send all the relevant information about group caption to the SAS or RTU after
establishing a successful communication link.
Please refer to Table 10.3-4 for detailed description of generic service group numbers.
10.5 Messages Description for IEC61850 Protocol

10.5.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
 IEC 61850-5: Communications and requirements for functions and device models
 IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs
 IEC 61850-7-1: Basic communication structure for substation and feeder equipment -
Principles and models
 IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)
 IEC 61850-7-3: Basic communication structure for substation and feeder equipment –
Common data classes
 IEC 61850-7-4: Basic communication structure for substation and feeder equipment –
Compatible logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3

 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.5.2 Communication Profiles
The PCS-978 series relay supports IEC 61850 server services over TCP/IP communication
protocol stacks. The TCP/IP profile requires the PCS-978 series to have an IP address to establish
communications.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. Actual MMS protocol services are mapped to IEC 61850 abstract services in
IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3. Peer-to-peer
This is a non-connection-oriented, high speed type of communication usually between substation

equipment, such as protection relays. GOOSE is the method of peer-to-peer communication.
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe the configuration of

substation equipment. Each configured device has an IEC Capability Description (ICD) file and a
Configured IED Description (CID) file. The substation single line information is stored in a System
Specification Description (SSD) file. The entire substation configuration is stored in a Substation
Configuration Description (SCD) file. The SCD file is the combination of the individual ICD files
and the SSD file.
10.5.3 Server Data Organization
IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing

various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one logical
device, and the logical device contains many logical nodes. The logical node LPHD contains
information about the IED physical device. The logical node LLN0 contains information about the
IED logical device.
10.5.3.1 Digital Status Values
The GGIO logical node is available in the PCS-978 series relays to provide access to digital status
points (including general I/O inputs and warnings) and associated timestamps and quality flags.
The data content must be configured before the data can be used. GGIO provides digital status
points for access by clients. It is intended that clients use GGIO in order to access digital status
values from the PCS-978 series relays. Clients can utilize the IEC61850 buffered reporting
features available from GGIO in order to build sequence of events (SOE) logs and HMI display
screens. Buffered reporting should generally be used for SOE logs since the buffering capability
reduces the chances of missing data state changes. All needed status data objects are transmitted
to HMI clients via buffered reporting, and the corresponding buffered reporting control block
(BRCB) is defined in LLN0.
10.5.3.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from a IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:
 MMXU.ST.Hz: frequency
 MMXU.ST.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.ST.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.ST.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.ST.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.ST.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.ST.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.ST.A.phsA: phase A current magnitude and angle
 MMXU.ST.A.phsB: phase B current magnitude and angle
 MMXU.ST.A.phsC: phase C current magnitude and angle

10.5.3.3 Protection Logical Nodes
The following list describes the protection elements for all PCS-978 series relays. The specified
relay will contain a subset of protection elements from this list.
 PDIF: current differential and transfer trip
 PDIS: phase-to-phase distance, phase-to-ground distance and SOTF distance
 PTUC: undercurrent
 PTOC: phase overcurrent, zero sequence overcurrent and overcurrent when CTS
 PTUV: undervoltage
 PTUF: underfrequency
 PTOV: overvoltage and auxiliary overvoltage
 RREC: automatic reclosing
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pic kup)
flags “PTRC.ST.Str.general”. The operate flag for PTOC1 is “PTOC1.ST.Op.general”. For the
PCS-978 series relay protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and it also locates in LLN0.
10.5.3.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings. System settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-978 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:
 LPHD: Physical device information, the logical node to model common issues for physical
device.
 PTRC: Protection trip conditioning, it shall be used to connect the “operate”outputs of one or
more protection functions to a common “trip”to be transmitted to XCBR. In addition or alternatively,
any combination of “operate”outputs of protection functions may be combined to a new “operate”
of PTRC.
 RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System”(IEC

60255-24). All enabled channels are included in the recording, independently of the trigger mode.
10.5.4 Server Features and Configuration
10.5.4.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
 TrgOps: Trigger options. The following bits are supported by the PCS-978 series
relays:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields. The following bits are supported by the PCS-978 series relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
 IntgPd: Integrity period.
 BufTm: Buffer time.
10.5.4.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from
a PCS-978 series relay.
10.5.4.3 Timestamps
The timestamp values associated with all IEC61850 data items represent the time of the last
change of either the value or quality flags of the data item.

10.5.4.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.5.4.5 GOOSE Services
IEC61850 specifies the type of peer-to-peer data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also Devices that transmit GOOSE messages
also function as servers. Each GOOSE publisher contains a “GOOSE control block”to configure
and control the transmission.
The transmission is also controlled via device setting “GOOSE Group ID”in the setting submenu
“EQUIP SETUP”. The “GOOSE Group ID”setting item defines a definite IED group in which the
IED can communicate with each other via GOOSE protocol, and if GOOSE Group ID is configured
to “0”, GOOSE service is blocked in this IED. IEC61850 recommends a default priority value of 4
for GOOSE. Ethernet traffic that does not contain a priority tag has a default priority of 1. More
details are specified in IEC61850 part 8-1. IEC61850 recommends that the Ether-type Application
ID number be configured according to the GOOSE source.
The PCS-978series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-978 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
The general steps required for transmission configuration are:
1. Configure the transmission dataset.
2. Configure the GOOSE service settings.

3. Configure the data.
The general steps required for reception configuration are:
1. Configure the reception dataset.
2. Configure the GOOSE service settings.
3. Configure the data.
10.5.5 ACSI conformance
10.5.5.1 ACSI Basic Conformance Statement
Services Client Server PCS-978

Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC 61850-8-1 used N N Y
B22 SCSM: IEC 61850-9-1 used N N N
B23 SCSM: IEC 61850-9-2 used N N N
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-978 relay
N: Currently not supported by PCS-978 relay
10.5.5.2 ACSI Models Conformance Statement

M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y


M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
M7 Buffered report control O O Y
M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
M7-6 buffer-overflow Y Y Y
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N
M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N
M16 Time M M Y
M17 File transfer O O Y

Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by PCS-978 relay
N: Currently not supported by PCS-978 relay
10.5.5.3 ACSI Services Conformance Statement
Service Server/Publisher PCS-978

Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O
S14 CreateDataSet O
S15 DeleteDataSet O
S16 GetDataSetDirectory M Y
Substitution


S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
S21 ConfirmEditSGValues M/O Y
S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
S24-1 data-change M Y
S24-2 qchg-change M Y
S24-3 data-update M Y
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M Y
S27-3 data-update M Y
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block
S30 GetLCBValues O
S31 SetLCBValues O
Log
S32 QueryLogByTime O
S33 QueryLogAfter O
S34 GetLogStatusValues O
Generic substation event model (GSE)
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O


S37 GetGOOSEElementNumber O Y
S38 GetGoCBValues M Y
S39 SetGoCBValuess M Y
Control
S51 Select O
S52 SelectWithValue M Y
S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O
File transfer
S57 GetFile M/O Y
S58 SetFile O Y
S59 DeleteFile O
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.5.6 Logical Nodes
10.5.6.1 Logical Nodes Table
The PCS-978relays support IEC61850 logical nodes as indicated in the following table. Note that
the actual instantiation of each logical node is determined by the product order code.
Nodes PCS-978
L: System Logical Nodes
LPHD: Physical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential YES
PDIR: Direction comparison －
PDIS: Distance YES
PDOP: Directional overpower －
PDUP: Directional underpower －
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint YES
PHIZ: Ground detector －

Nodes PCS-978
PIOC: Instantaneous overcurrent YES
PMRI: Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault YES
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload YES
PTUC: Undercurrent －
PTUV: Undervoltage YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent YES
PVPH: Volts per Hz YES
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure YES
RDIR: Directional element YES
RFLO: Fault locator －
RPSB: Power swing detection/blocking YES
RREC: Autoreclosing －
RSYN: Synchronism-check or synchronizing －
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －

Nodes PCS-978
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements －
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement －
MMXU: Measurement YES
MSQI: Sequence and imbalance －
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －

Nodes PCS-978
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer YES
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor －
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.6 GOOSE Service

10.6.1 GOOSE Introduction
The general object oriented substation event (GOOSE) defined in IEC61850 standard is based on
the fast Ethernet multi-broadcasting message transmission, taking place of the hard-wired
communication mode between classic intelligent electronic device (IED) and providing a fast,
efficient and reliable method for communication among logic nodes.
The GOOSE service supports the exchange of public data comprised of data sets, it is used to
protect the data transmission which requires high real-time like tripping, breaker position and
interlocked information. The information exchange of GOOSE service is based on the
publish/subscribe mechanism, and any IED device in the same GOOSE network can be
conducted as subscription terminal to receive data and as publication terminal to provide
data to other IED device as well, so that the increasing or modification of communication data
between IED devices can be realized in a much easier way.
10.6.2 GOOSE Function
The PCS-978 series devices use independent high efficient DSP board to realize GOOSE, so it
has super-high real-time property and reliability. Two 100M FDX optical fiber Ethernet interfaces

on the DSP board can be corresponded to differe nt VLAN networks. The GOOSE dual-networks
configuration improves the reliability and stability of system.
(1) GOOSE receiving/sending mechanism
In order to ensure the real-time property and reliability of GOOSE service, GOOSE message
adopts ASN.1 code which relates to basic encoding rule (BER) and transmit data directly in
Ethernet link layer without passing through TCP/IP protocol and also adopts special
receiving/sending mechanism.
Sending of the GOOSE message adopts heartbeat message and position-altering message fast
resending combination mechanism. If the data in GOOSE data sets is not changed, the heartbeat
message whose interval is T0 will be sent, the status number (stnum) in message will not be
changed and the sequence number (sqnum) will be increased progressively. If the data in GOOSE
data set is changed, after sending a frame of position -altering message, the position-altering
message will be fast resent in the interval of T0, T1, T2, and T3. The status number (stnum) in the
message whose data is position-altered will be increased, and the sequence number (sqnum) will
be started from zero.
The GOOSE receiving can detect link interrupt according to the TATL (Time Allow to Live) in the
GOOSE message. The GOOSE data receiving mechanism can be divided into single frame
receiving and dual-frames receiving. The intelligent operation box uses dual-frames receiving
mechanism and update data after receiving two frames of messages with the same GOOSE data.
Other protection and monitoring devices use single frame receiving mechanism and update data
immediately after receiving position-altering message (stnum changed). If the status number
(stnum) in the received message is not changed, dual-frames message confirmation will be used
to update data.
(2) GOOSE Alarm
GOOSE will alarm the abnormal conditions produced during receiving/sending process, the
GOOSE alarms mainly include: GOOSE network A/B network link breaking alarm, GOOSE
configuration inconformity alarm and GOOSE network A/B network-storm alarm.
The GOOSE network A/B link breaking alarm is: this alarm will be produced when correct GOOSE
message is not received in 2 times of the TATL ( Time Allow to Live).
The GOOSE configuration inconformity alarm is: the attribute of GOOSE control block of GOOSE
publisher and subscriber like configuration version number must be identical. Otherwise this
GOOSE configuration inconformity alarm will be produced.
The GOOSE network A/B network-storm alarm is: when network-storm is produced in GOOSE
network, if data flow of network port is beyond normal range and abnormal message is produced,
this GOOSE network A/B network-storm alarm will be produced.
(3) GOOSE Service
When service status of the device is set to 1, the GOOSE message sent by the device has a Test
Flag and receiving terminal can obtain service status of sending terminal by the test flag of
message. When the service status of sending terminal conforms to that of receiving terminal, the

device will carry out normal processing to the received GOOSE data. When the service status of
sending terminal doesn’
t conform to that of receiving terminal, the device will process the received
GOOSE data accordingly to ensure that the serviced device will not influence the normal running
of device, improving the flexibility and reliability of GOOSE service.
Output signal model.
Ref. Name of Ref. Name of

Signal Description LN Remark
Signal Related Strap
Tripping Output 1 PTRC1 Tr. general TrStrp
Cooler Startup GGIO1 SPCSO1. stVal TrStrp
On-load Voltage
GGIO1 SPCSO2. stVal TrStrp
Regulation Lock-out

Chapter 11 Installation and Commissiong
11.1 Introduction
The chapter contains instructions on how to install, commission and maintenance the protection
equipment. It can also be used as a reference if a periodic test is performed. The chapter covers
procedures for mechanical and electrical installation, energizing and checking of external circuitry,
setting and configuration as well as verifying settings and performing a directionality test.
The chapter contains the following information:
1) The “Safety information” presents warning and note signs, which the user should draw
attention to.
2) The “Overview”gives an overview over the major task when installing and commissioning the
protection equipment.
3) The “Unpacking and checking the protection equipment”contains instructions on how to

receive the protection equipment.
4) The “Installing the protection equipment” contains instructions on how to install the
5) The “Checking the external circuitry” contains instructions on how to check that the
protection equipment is properly connected to the protection system.
6) The “Energizing the protection equipment”contains instructions on how to start-up the

7) The “Setting the protection equipment”contains instructions on how to download settings

and configuration to the protection equipment.
8) The “Establishing connection and verifying communication”contains instructions on how

to verify the communication.
9) The “Verifying settings by secondary injection”contains instructions on how to verify that

each included function operates correctly according to the set value.
10) The “Final check”contains instructions on how to do final check to make the equipment
ready for being put into service.
The chapter is addressing the installation, commissioning and maintenance personnel responsible
for taking the protection into normal service and out of service. The installation personnel must
have a basic knowledge in handling electronic equipment. The commissioning and maintenance
personnel must be well experienced in using protection equipment, test equipment, protection
functions and the configured functional logics in the protection.

11.2 Safety Information
This section contains safety information. Warning signs are presented which attend the user to be
careful during certain operations in order to avoid human injuries or damage to equipment.
 Warning signs
WARNING！
 Strictly follow the company and country safety regulations. Working in a high voltage
environment requires serious approach to avoid human injuries and damage to
equipment.
 Do not touch circuitry during operation. Potentially lethal voltages and currents are
present.
 Always avoid touching the circuitry when the cover is removed. The product contains
electronic circuitries which can be damaged if exposed to static electricity (ESD). The
electronic circuitries also contain high voltage which is lethal to humans.
 Always use suitable isolated test pins when measuring signals in open circuitry.
Potentially lethal voltages and currents are present.
 Never connect or disconnect a wire and/or a connector to or from a protection equipment

during normal operation. Hazardous voltages and currents are present that may be lethal.
Operation may be disrupted and protection equipment and measuring circuitry may be
damaged.
 Always connect the protection equipment to protective ground, regardless of the

operating conditions. This also applies to special occasions such as bench testing,
demonstrations and off-site configuration. Operating the protection equipment without
proper grounding may damage both terminal and measuring circuitry, and may cause
injuries in case of an accident.
 Never disconnect a secondary connection of current transformer circuit without

short-circuiting the transformer’
s secondary winding. Operating a current transformer
with the secondary winding open will cause a massive potential build-up that may
damage the transformer and may cause injuries to humans.
 Never unmount the front or back cover from a powered equipment or from a protection
equipment connected to powered circuitry. Potentially lethal voltages and currents are
present.
 Caution signs
CAUTION！
 Always transport modules using certified conductive bags. Always handle modules using

a conductive wrist strap connected to protective ground and on a suitable antistatic

surface. Electrostatic discharge (ESD) may cause damage to the module.
 Do not connect live wires to the protection equipment. Internal circuitry may be damaged.
 Always use a conductive wrist strap connected to protective ground when replacing
modules. Electrostatic discharge (ESD) may damage the module and protection
equipment circuitry.
 Take care to avoid electrical shock if accessing wiring and connection protection
equipment when installing and commissioning.
 Note signs
NOTE！
 Changing the active setting group will inevitably change the protection equipment’
s
operation. Be careful and check regulations before making the change.
 The protection assembly is designed for a maximum continuous current of four times
rated value.
 Activating the other setting group without proper configuration may seriously affect the
protection equipment’
s operation.
11.3 Overview
The settings for each function must be calculated before the commissioning task can start. A
configuration, made in the configuration and programming tool, must also be available if the
protection equipment does not have a factory configuration downloaded.
The protection equipment is unpacked and visually checked. It is preferably mounted in a cubicle.
The connection to the protection system has to be checked in order to verify that the installation
was successful.
The installation and commissioning task starts with configuring the digital communication modules,
if included. The protection equipment can then be configured and set, which means that settings
and a configuration has to be applied if the protection equipment does not have a factory
configuration downloaded. Then the operation of each included function according to applied
settings has to be verified by secondary injection. A complete check of the configuration can then
be made. A conformity test of the secondary system has also to be done. When the primary
system has been energized a directionality check should be made.
11.4 Unpacking and Checking The Protection Equipment

Procedure
1) Remove the transport casing.
2) Visually inspect the protection equipment.

 Carefully examine the protection panel, protection equipment inside and other parts
inside to see that no physical damage has occurred since installation.
 The rating information should be given for the protection equipment.
 The rating information of other auxiliary protections should be checked to ensure it is

correct for the particular installation.
Panel wiring:
Check the conducting wire used in the panel to assure that their cross section meet the
requirement. Carefully examine the wiring to see that they are no connection failure exists.
Label:
Check all the isolator links, terminal blocks, ferrules, indicators, switches and push buttons to
make sure that their labels meet the requirements of this project.
Equipment plug-in modules:
Check each plug-in module of the equipments on the panel to make sure that they are well
installed into the equipment without any screw loosened.
Earthing cable:
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
Switch, keypad, isolator links and push button:
Check whether all the switches, equipment keypad, isolator links and push buttons work normally
and smoothly.
3) Check that all items are included in accordance with the delivery documents.
The user is requested to check that all software functions are included according to the delivery
documents after the terminal has been energized.
4) Check for transport damages.
These product checks cover all aspects of the protection, which should be checked to ensure that
the protection not only has not been physically damaged prior to commissioning but also functions
correctly and all input quantity measurements are within the stated tolerances.
11.5 Installing the Protection Equipment
11.5.1 Overview
The mechanical and electrical environmental conditions at the installation site must be within
permissible range according to the technical data of the protection equipment. Dusty, damp places,
places liable to rapid temperature variations, powerful vibrations and shocks, surge voltages of
high amplitude and fast rise time, strong induced magnetic fields or similar extreme conditions

should be avoided. Please refer to Chapter 2 for details.
Sufficient space must be available in front of and at rear of the protection panel to allow access for
maintenance and future modifications. Flush mounted protection equipment should be mounted
so that equipment modules can be added and replaced without excessive demounting.
11.5.2 Dimensions
The equipment adopts IEC standard chassis and is rack with modular structure. It uses an integral
faceplate and plug terminal block on backboard for external connections. PCS-978is IEC 4U high
or 8U high and 19”wide. Following figures shows dimensions and the panel cut-out of two kinds of
chassis.
101.6
177.0
Figure 11.5-1 Dimensions of 4U equipment

101. 6
179.0
Figure 11.5-2 Panel cut-out dimensions of 4U equipment

Figure 11.5-3 Dimensions of 8U equipment
465 .0
450.0
8-Ф 6.8
Figure 11.5-4 Panel cut-out dimensions of 8U equipment
11.5.3 Grounding Guidelines
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus. On the other hand,
electronic apparatus can transmit interference that can disrupt the operation of other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.

NOTE: All these precautions can only be effective if the station ground is of good quality.
11.5.4 Cubicle Grounding
The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTE: If the above conditions are not fulfilled, there is a possibility of the cubicle or parts
of it forming a resonant circuit at certain frequencies that would amplify the transmission
of interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (refer to Figure 11.5-5).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTE: For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a grounding strip
(braided copper).
Figure 11.5-5 Cubicle grounding system
11.5.5 Ground Connection on the Device
There is a ground terminal on the rear panel (refer to Figure 11.5-6), and the ground braided
copper strip can be connected with it. Take care that the grounding strip is always as short as

possible. The main thing is that the device is only grounded at one point. Grounding loops from
unit to unit are not allowed.
There are some ground terminals on some connectors of the equipments, and the sign is “GND”.
All the ground terminals are connected in the cabinet of this equipment. So, the ground terminal on
the rear panel (refer to Figure 11.5-6) is the only ground terminal of this device.
Figure 11.5-6 Ground terminal
11.5.6 Grounding Strips and Their Installation
High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Data of braided copper strip: threaded M4, 4.0mm2. Proper terminations must be fitted to both
ends (press/pinch fit and tinned) with a hole for bolting them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Figure 11.5-7 Ground strip and termination
11.5.7 Making the Electrical Connections
Always make sure established guidelines for this type of terminal is followed during installation.
When necessary, use screened twisted-pair cables to minimize susceptibility. Otherwise, use any
kind of regular nonscreened tinned RK cable or equivalent.
When using screened cabling always use 360° full screen cable bushing to ensure screen
coupling. Ensure that all signals of the single circuit are in the same single cable. Avoid mixing
current and voltage measuring signals in the same cable. Also use separate cables for control and

measuring circuits.
1) Connecting the VT/CT circuits:
Heavy-duty terminal block, M4 threaded terminal ends. VT circuit must be connected with the
protective device through an MCB.
2) Connecting the auxiliary power:
Auxiliary power cords can be directly screw fixed on the rear panel of power board.
3) Input/output signal connectors:
Welding terminals. Those devices are supplied with sufficient M4 screws for making connections
to the rear mounted terminal blocks using ring terminals, with a recommended maximum of two
ring terminals per terminal.
To meet the insulation requirements of the terminal block, for the sake of safety, an insulating
sleeve should be fitted over the ring terminal after crimping.
The wire used for all connections to the welding terminal blocks and heavy duty terminal blocks,
except the EIA RS-485 port, should have a minimum voltage rating of 300Vrms.
It is recommended that the auxiliary power circuit wiring should be protected by using a 16A high
rupture capacity (HRC) fuse of type NIT or TIA. For safety reasons, current transformer circuits
must never be open.
4) Connecting to protective ground:
Connect the unit to the grounding bar of the cubicle with green/yellow conductor; connected to the
protective Earthing terminal at the back of the PWR board. Attend that the earth wire must be as
short as possible. All cautions have to be taken to ensure the best electrical conductivity,
particularly the contact quality, stainless conductor. The impedance between the equipment
Earthing terminal and the Earth must be less than 20mΩ under 12Volt, 50Hz. What matters is that
the device has to be only grounded at one point. Loop grounding from unit to unit is not allowed.
5) Installing the optic fibres
Connectors are generally color coded; connect blue or dark grey cable connectors to blue or dark
grey (receive) back-side connectors. Connect black or grey cable connectors to black or grey
(transmit) back-side connectors.
Fiber optical cables are sensitive to handling. Do not bend too sharply. The minimum curvature
radius is 15 cm for plastic fibers and 25 cm for glass fibers. If cable straps are used, apply with
loose fit.
NOTE: Always hold the connector, never the cable, when connecting or disconnecting
optical fibres. Do not twist, pull or bend the fibre. Invisible damage may increase fibre
damping thus making communication impossible.
6) Installing the RS-485 serial port communication cables:

When using galvanic connection between the synchronizer equipment and communication
equipment or point-to-point galvanic connection between two equipments it is essential that the
cable installation is carefully done. This is true regardless of type of module used, only the
possible length of the cable differs. The factors that must be taken into account is the susceptibility
for noise disturbance, due to that the levels of the communication signal are very low. For a best
result, a cable with twisted pairs with screen should be used.
RS-485 serial communication interface, a termination 120-ohm resistor has to be connected at

each extremity of the bus. Refer to Chapter 10.
11.6 Check the External Circuitry
The user must check the installation, which includes verifying that the relay is connected to the
other parts of the protection system. This is done with the relay and all connected circuits
de-energized.
1) Checking the VT/CT circuits
Check that the wiring is in strict accordance with the supplied wiring diagram.
Test the circuitry. The following tests are recommended:
 Polarity check
 CT circuit current measurement (primary injection test)
 Grounding check
The polarity check verifies the integrity of the circuits and the phase relationship. The check should
be performed as close as possible to the relay. The primary injection test verifie s the CT ration and
the wiring all the way through from the primary system to the relay. Injection must be performed for
each phase-to-neutral circuit and each phase-to-phase pair. In each case currents in all phases
and the neutral line are measured.
2) Checking the power supply
Check that the value of the auxiliary supply voltage remains with the permissible range under all
operating conditions. Check that the polarity is correct according to the instruction manual on the
rear plate of PWR board.
3) Checking binary input circuits
Preferably, disconnect the binary input connector form the binary input cards. Check all connected
signals so that both input level and polarity are in accordance with the relay’
s specifications.
NOTE: The binary inputs may be energized from an external dc auxiliary supply (e.g. the
station battery) in some installations. Check that this is not the case before connecting
the field voltage otherwise damage to the protection may result. The status of each binary
input can be viewed using either PCS-PC software installed in a portable PC or by

checking the front man-machine interface LCD. When each binary input is energized the
display will change to indicate the new state of the inputs.
4) Checking binary output circuits
Preferably, disconnect the binary output connector form the binary output cards. Check all
connected signals so that both load and polarity are in accordance with the relay’
s specifications.
11.7 Energizing the Protection Equipment
Before the procedures in this section can be carried out the connection to external circuitry must
have been checked which ensures that the installation was made correctly.
The user must energies the power supply to the relay to start it up. This could be done in a
numerous of ways, from energizing a whole cubicle to energizing a single relay. The user should
reconfigure the relay settings. The relay time must be set. The self -supervision function should
also be checked to verify that the relay unit operates properly. The user could also check the
software version, the relay’
s serial number, the installed modules, and their ordering number to
ensure that the relay is according to delivery and ordering specifications.
1) Checking front panel LCD display
Connect the relay to DC power supply correctly and turn the relay on. Check program version and
forming time displayed in command menu to ensure that are corresponding to what ordered.
2) Setting the date and time of the protective device
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “CLOCK”. Refer to the
section “Adjust the Clock”for detailed procedures.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date will
be maintained. Therefore when the auxiliary supply is restored the time and date will be correct
and not need to set again.
To test this, remove the auxiliary supply from the relay for app roximately 30s. After being
re-energized, the time and date should be correct.
3) Checking light emitting diodes (LEDs)
On power up, the green LED “HEALTHY”should have illuminated and stayed on indicating that
the protective device is healthy.
The relay has latched signal relays which remember the state of the trip, auto-reclose when the
relay was last energized from an auxiliary supply. Therefore these indicators may also illuminate
when the auxiliary supply is applied. If any of these LEDs are on then they should be reset before
proceeding with further testing. If the LED successfully reset, the LED goes out. There is no testing
required for that that LED because it is known to be operational.

It is likely that alarms related to voltage transformer supervision will not reset at this stage.
11.8 Setting the Protection Equipment
The customer specific values for each setting parameter have to be available. Each function
included in the relay has several setting parameters which has to be set in order to make the relay
behave as intended. A default value is provided for each parameter from factory.
All settings can be:
 Download from a PC or laptop with PCS-PC software or remotely by SCADA. Front port
communication has to be established before the settings can be downloaded.
 Input manually through the local HMI (refer to section “Input Operation through Keypad”).
To change settings through the local HMI need a password which is “+”, “◄ ”, “▲ ”and “-”keyboard
on the front panel.
Unless previously agreed to the contrary, the customer will be responsible for determining the
application-specific settings to be applied to the protection and for testing of any scheme logic
applied by external wiring and/or configuration of the protection’
s internal programmable scheme
logic.
11.9 Establishing Connection and Verifying Communication
This test should only be performed where the protection is to be accessed from a remote location
and will vary depending on the communications standard being adopted.
It is not the intention of the test to verify the operation of the complete system from the relay to the
remote location, just the protection’ s rear communications port and any protocol converter
necessary.
11.10 Verifying Settings by Secondary Injection
Required tools for testing of a protective device:
Minimum equipment required:
 Multifunctional dynamic current and voltage injection test set with interval timer.
 Multimeter with suitable AC current range and AC/DC voltage ranges of 0-440V and 0-250V
respectively.
 Continuity tester (if not included in the multimeter).
 Phase angle meter.
 Phase rotation meter.

NOTE: Modern test set may contain many of the above features in one unit.
Optional equipment:
 An electronic or brushless insulation tester with a DC output not exceeding 500 V (for
insulation resistance test when required).
 A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
 EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
 An EPSON® 300K printer.
 PCS-9780 serials dedicated protection tester HELP2000.
At the same time, the calculated settings, substation configuration diagram, the protective device
diagram and the instruction manual is essential to test the protective device.
The equipment has to be set before the testing can start. Only the functions that are used should
be tested.
The response from a test can be viewed in different ways:
 Binary output signals
 Service values in the local HMI
 A PC with PCS-PC software or SCADA or master station
All used setting groups should be tested. The user can release the functions to be tested and
prevent other functions from operation by setting the corresponding parameters. The user could
also energize the binary input [BI_BlkComm] to disable communication function to ensure that no
events are reported to remote station during the test.
The setting checks ensure that all of the application-specific protection settings (i.e. both the
protection’
s function and programmable scheme logic settings), for the particular installation, have
been correctly applied to the protection.
11.10.1 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
 Voltage transformer circuits
 DC power supply
 Optic-isolated control inputs
 Output contacts

 Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
11.10.2 Current Measurement Check
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the protection is 2.5% or 0.02In. However, an additional allowance
must be made for the accuracy of the test equipment being used.
NOTE: The closing circuit should remain isolated during these checks to prevent
accidental operation of the associated circuit breaker.
Input Measurement (on LCD)

Group No. Item
Value Angle Value Angle
Ia
Three-phase current 1 Ib
Ic
Ia
Ic
Ia
Ic
Ia
Three-phase current … . Ib
Ic
Zero-sequence current 1 3I0
Zero-sequence current … 3I0
11.10.3 Voltage Measurement
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the relay is 2.5% or 0.1V. However an additional allowance must be
made for the accuracy of the test equipment being used.

NOTE: The closing circuit should remain isolated during these checks to prevent
accidental operation of the associated circuit breaker.
Linearity and precision checkout

Input Measurement (on LCD)
Items
Value Angle Value Angle
Ua
Three-phase voltage 1 Ub
Uc
Ua
Three-phase voltage 2 Ub
Uc
Ua
Ub
Three-phase voltage 3
Uc
Uc
Zero-sequence voltage 1 3U0
11.10.4 Testing the Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
The status of each binary input can be viewed using relay menu. Sign “1”denotes an energized
input and sign “0”denotes a de-energized input.
Binary Inputs testing checkout
Terminal No. Signal Name BI Status on LCD Correct?
Test method:
To unplug all the terminals sockets of this protective device, and do the Insulation resistance test
for each circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected
to the protection.

11.10.5 Print Fault Report
In order to acquire the details of protection operation, it is convenient to print the fault report of
protection device. The printing work can be easily finished when operator presses the print button
on panel of protection device to energize binary input [BI_Print] or operate control menu. What
should be noticed is that only the latest fault report can be printed if operator presses the print
button. A complete fault report includes the content shown as follows.
1) Trip event report
2) Binary input when protection devices start
3) Self-check and the transition of binary input in the process of devices start
4) Fault wave forms compatible with COMTRADE
5) The setting value when the protection device trips
11.10.6 Final Check
After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the protection in order to perform the
wiring verification tests, it should be ensured that all connections are replaced in accordance with
the relevant external connection or scheme diagram.
Ensure that the protection has been restored to service.
If the protection is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the protection is put into service.
Ensure that all event records, fault records, disturbance records and alarms have been cleared
and LED’
s has been reset before leaving the protection.

Chapter 12 Maintenance
NR numerical relay PCS-978is designed to require no special maintenance. All measurement and
signal processing circuit are fully solid state. All input modules are also fully solid state. The output
relays are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
12.1 Appearance Check

The relay case should be clean without any dust stratification. Case cover should be sealed well.
No component has any mechanical damage and distortion, and they should be firmly fixed in the
case. Relay terminals should be in good condition. The keys on the front panel with very good
feeling can be operated flexibly.
It is only allowed to plug or withdraw relay board when the supply is reliably switched off. Never
allow the CT secondary circuit connected to this equipment to be opened while the primary system
is live when withdrawing an AC module. Never try to insert or withdraw the relay board when it is
unnecessary.
Check weld spots on PCB whether they are well soldered without any rosin joint. All dual inline
components must be well plugged.
12.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “ALM REPORT”screen on the LCD.
When a failure is detected during regular testing, confirm the following:
 Test circuit connections are correct
 Modules are securely inserted in position
 Correct power supply voltage is applied
 Correct analog inputs are applied
 Test procedures comply with those stated in the manual

12.3 Replace Failed Modules

If the failure is identified to be in the relay module and the user has spare modules, the user can
recover the protection by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, CPU, SIG, BI, BO,
etc.) and hardware type-form as the removed module. Furthermore, the CPU module replaced
should have the same software version. In addition, the AI module, PWR module, BI module, IO
module and RLY module replaced should have the same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “VERSION”.
CAUTION: When handling a module, take anti-static measures such as wearing an
earthed wrist band and placing modules on an earthed conductive mat. Otherwise, many
of the electronic components could suffer damage. After replacing the CPU module, check
the settings.
1) Replacing a module
 Switch off the power supply
 Disconnect the trip outputs
 Short circuit all AC current inputs and disconnect all AC voltage inputs
 Unscrew the module.
WARNING: Hazardous voltage can be present in the DC circuit just after switching off the
DC power supply. It takes approximately 30 seconds for the voltage to discharge.
2) Replacing the Human Machine Interface Module (front panel)
 Open the relay front panel
 Unplug the ribbon cable on the front panel by pushing the catch outside.
 Detach the HMI module from the relay
 Attach the replacement module in the reverse procedure.
3) Replacing the AI, PWR, CPU, BI, IO, BO module
 Unscrew the module connector
 Unplug the connector from the target module.
 Unscrew the module.
 Pull out the module

 Inset the replacement module in the reverser procedure.
 After replacing the CPU module, input the application-specific setting values again.
WARNING: Units and modules may only be replaced while the supply is switched off
and only by appropriately trained and qualified personnel. Strictly observe the basic
precautions to guard against electrostatic discharge.
WARNING: When handling a module, take anti-static measures such as wearing an
earthed wrist band and placing modules on an earthed conductive mat. Otherwise,
many of the electronic components could suffer damage. After replacing the CPU
module, check the settings.
DANGER: After replacing modules, be sure to check that the same configuration is set
as before the replacement. If this is not the case, there is a danger of the unintended
operation of switchgear taking place or of protections not functioning correctly. Persons
may also be put in danger.
12.4 Replace Button Battery

When the voltage of button Battery on CPU board is below 2.5 volts (nominal voltage is 3 volts),
please replace the button battery to ensure internal clock of CPU board running correctly.
12.5 Cleaning
Before cleaning the relay, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
12.6 Storage
The spare relay or module should be stored in a dry and clean room. Based on IEC standard
60255-6 the storage temperature should be from-40°C to 70°C, but the temperature of from -10°C
to 40°C is recommended for long-term storage.


Chapter 13 Decommissioning and Disposal
13.1 Decommissioning
13.1.1 Switching off
To switch off the PCS-978, switch off the external miniature circuit breaker of the power supply.
13.1.2 Disconnecting Cables

Disconnect the cables in accordance with the rules and recommendations made by relational
department.
DANGER: Before disconnecting the power supply cables that connected with the PWR
module of the PCS-978 make sure that the external miniature circuit breaker of the power
supply is switched off.
DANGER: Before disconnecting the cables that are used to connect analog input module
with the primary CTs, make sure that the primary CTs aren’
t in service.
13.1.3 Dismantling
The PCS-978rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
DANGER: When the station is in operation, make sure that there is an adequate safety
distance to live parts, especially as dismantling is often performed by unskilled personnel.
13.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
NOTE: Strictly observe all local and national regulations when disposing of the device.


Chapter 14 Manual Release History
Chapter 14 Manual Release History

The release histories of software and manual for PCS-978 are listed below.
Software Manual
Source Documentation
Release Release
PCS-978_Instruction Manual_General_R1.00
R1.00
(EN_YJBH5100.0086.0001).doc
R1.00
PCS-978_Instruction Manual_General_R1.01
R1.01
(EN_YJBH5100.0086.0002).doc
Modifying description of each manual version is shown below.
Manual
Section Page No. Description of change Note
Release
R1.00 Original release
Modify protection theory, settings and logic
R1.01 3.6 83~89 diagram of undervoltage protection and
underfrequence protection
Adding description of settings calculation and
3.13 148~152
configuration.
Modify the correction coefficient calculation
methods of current differential protection, restricted
Chapter 3 21~188
R1.01 earth fault protection and winding differential
protection.
The polarity of zero-sequence CT at neutral point is
All the
changed to be at transformer side and modify the
menu
corresponding figures and descriptions.

NR PCS-978 - Instruction - Manual - EN - General - X (NR)

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

NR PCS-978 - Instruction - Manual - EN - General - X (NR)

Uploaded by

Copyright:

Available Formats

PCS-978

NR Electric Co., Ltd.

Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

NR ELECTRIC CO., LTD. i

Instructions and Warnings

The following indicators and standard definitions are used:

ii NR ELECTRIC CO., LTD

The earthing terminal of the equipment must be securely earthed

 Printed circuit board

Carefully handle the connection cable without applying excessive force.

NR ELECTRIC CO., LTD. iii

iv NR ELECTRIC CO., LTD

Health and Safety ..................................................................................................................... i

Instructions and Warnings..................................................................................................... ii

Table of Contents ........................................................................................................................... v

Chapter 1 Introduction ................................................................................................................... 1

1.1 Application ......................................................................................................................... 1

1.2 Functions ........................................................................................................................... 2

1.3 Features ............................................................................................................................. 5

1.4 Ordering Options .............................................................................................................. 8

Chapter 2 Technical Data..............................................................................................................11

2.1 Electrical Specifications..................................................................................................11

2.1.1 Alternating Current Input ......................................................................................11

2.1.2 Alternating Voltage Input ......................................................................................11

2.1.3 Power Supply .........................................................................................................11

2.1.4 Binary Input ........................................................................................................... 12

2.1.5 Binary Output ........................................................................................................ 12

2.1.6 Power Supply Output for Opto-coupler ............................................................. 12

2.2 Mechanical Specifications ............................................................................................. 12

2.3 Ambient Temperature and Humidity Range ................................................................. 13

2.4 Communication Port....................................................................................................... 13

2.4.1 Communication Port for RTU/SCADA ................................................................ 13

2.4.2 Communication Port for Print ............................................................................. 14

2.4.3 RS-485 for Clock Synchronization...................................................................... 14

2.5 Type Tests ........................................................................................................................ 15

2.5.1 Environmental Tests............................................................................................. 15

2.5.2 Mechanical Tests .................................................................................................. 15

NR ELECTRIC CO., LTD. v

2.5.3 Electrical Tests ...................................................................................................... 15

2.5.4 Electromagnetic Compatibility............................................................................ 15

2.6 Certifications ................................................................................................................... 16

2.7 Protective Functions ...................................................................................................... 16

2.7.1 Conventional Current Differential Protection .................................................... 16

2.7.2 DPFC Current Differential Protection ................................................................. 17

2.7.3 Restricted Earth Fault Protection ....................................................................... 17

2.7.4 Winding Differential Protection........................................................................... 17

2.7.5 Overexcitation Protection .................................................................................... 17

2.7.6 Frequency Protection........................................................................................... 18

2.7.7 Mechanical Protection.......................................................................................... 18

2.7.8 Impedance Protection .......................................................................................... 18

2.7.9 Phase Overcurrent protection ............................................................................. 18

2.7.10 Zero-sequence Overcurrent Protection ........................................................... 19

2.7.11 Phase Overvoltage Protection........................................................................... 19

2.7.12 Zero-sequence Overvoltage Protection ........................................................... 19

2.7.13 Phase Undervoltage Protection ........................................................................ 20

2.7.14 Thermal Overload Protection ............................................................................ 20

2.7.15 Breaker Failure Initiation ................................................................................... 20

2.7.16 Overload Alarm Element .................................................................................... 20

2.7.17 Initiating Cooler Element ................................................................................... 21

2.7.18 Blocking On-Load Tap Change Element.......................................................... 21

2.7.19 Zero-Sequence Overvoltage Alarm Element ................................................... 21