Computer Organization

Homework05
1) (2 points) Exercise 5.1 in the chapter 5 of Textbook RISC-V edition

2) (2 points) Exercise 5.2 in the chapter 5 of Textbook RISC-V edition

3) (2 points) Exercise 5.3 (5.3.1 and 5.3.2) in the chapter 5 of Textbook

RISC-V edition

4) (2 points) Exercise 5.5 in the chapter 5 of Textbook RISC-V edition

5) (2 points) Exercise 5.11 (from 5.11.1 to 5.11.6) in the chapter 5 of

Textbook RISC-V edition

at pages 473, 474, 475, 478

HOMEWORK 5
CHAPTER 5

5.1 In this exercise we look at memory locality properties of matrix

computation. The following code is written in C, where elements within the
same row are stored contiguously. Assume each word is a 64-bit integer.
for (I=0; I<8; I++)
for (J=0; J<8000; J++)
A[I][J]=B[I][0]+A[J][I];
5.1.1 How many 64-bit integers can be stored in a 16-byte cache block?
-> In a 16-byte cache block can store 2 64-bit integers.
5.1.2 Which variable references exhibit temporal locality?
->Temporal locality: Items accessed recently are likely to be accessed again soon
such as instruction in a loop, induction variables so the answers is I,J,B[I][0].
5.1.3 Which variable references exhibit spatial locality?
-> Spatial locality: It tems near those accessed recently are likely to be accessed
soon such as sequential instruction access, array data so the answer is A[J][I].
Locality is affected by both the reference order and data layout. The same
computation can also be written below in Matlab, which differs from C in that it
stores matrix elements within the same column contiguously in memory.
for I=1:8
for J=1:8000
A(I,J)=B(I,0)+A(J,I);
end
end
5.1.4 Which variable references exhibit temporal locality ?
-> Temporal locality : I,J,B(I,0)
5.1.5 Which variable references exhibit spatial locality?
-> Spatial locality: B(I,0) and A(J,I)
5.1.6 How many 16-byte cache blocks are needed to store all 64-bit matrix
elements being referenced using Matlab’s matrix storage? How many using C’s
matrix storage? (Assume each row contains more than one element.)
-> The code references from matrix A: 8*8000 = 64,000 integers . At two integers
per 16-byte block,  we need 32,000 blocks.
So, 32,004 with Matlab and 32,008 with C.

5.2 Caches are important to providing a high-performance memory hierarchy to

processors. Below is a list of 64-bit memory address references, given as word
addresses. 0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, 0xbe, 0x0e, 0xb5, 0x2c, 0xba,
0xfd
5.2.1 [10] <§5.3> For each of these references, identify the binary word
address, the tag, and the index given a direct-mapped cache with 16 one-
word blocks. Also list whether each reference is a hit or a miss, assuming the
cache is initially empty.
5.2.2 [10] <§5.3> For each of these references, identify the binary word
address, the tag, the index, and the offset given a directmapped cache with
two-word blocks and a total size of eight blocks. Also list if each reference is a
hit or a miss, assuming the cache is initially empty.
5.2.3 [20] <§§5.3, 5.4> You are asked to optimize a cache design for the given
references. There are three direct-mapped cache designs possible, all with a
total of eight words of data: 
 C1 has 1-word blocks
   C2 has 2-word blocks
 and C3 has 4-word blocks
 5.2.1
Word Binary Address Ta index Hiss/Miss
Address g
0x03 0000 0011 0 3 M
0xb4 1011 0100 b 4 M
0x2b 0010 1011 2 b M
0x02 0000 0010 0 2 M
0xbf 1011 1111 b f M
0x58 0101 1000 5 8 M
0xbe 1011 1110 b e M
0x0e 0000 1110 0 e M
0xb5 1011 0101 b 5 M
0x2c 0010 1100 2 c M
0xba 1011 1010 b a M
0xfd 1111 1101 f d M
5.22
Word Binary Tag index Offset  Hiss/Miss
Address Address
0x03 0000 0011 0 1 1 M
0xb4 1011 0100 b 2 0 M
0x2b 0010 1011 2 5 1 M
0x02 0000 0010 0 1 0 H
0xbf 1011 1111 b 7 1 M
0x58 0101 1000 5 4 0 M
0xbe 1011 1110 b 6 0 H
0x0e 0000 1110 0 7 0 M
0xb5 1011 0101 b 2 1 H
0x2c 0010 1100 2 6 0 M
0xba 1011 1010 b 5 0 M
0xfd 1111 1101 f 6 1 M

5.2.3
C Binary Tag       Cache 1            Cache 2          Cache 3
Address Index Hiss/Mis Index Hiss/Mis Index Hiss/Miss
s s
0x03 0000 0011 0x00 3 M 1 M 0 M
0xb 1011 0100 0x16 4 M 2 M 1 M
4
 0x2 0010 1011 0x05 3 M 1 M 0 M
b
0x02 0000 0010 0x00 2 M 1 M 0 M
0xbf 1011 1111 0x17 7 m 3 M 1 M
0x58 0101 1000 0x0 0 M 0 M 0 M
b
0xbe 1011 1110 0x17 6 M 3 H 1 H
0x0e 0000 1110 0x01 6 M 3 M 1 M
0xb 1011 0101 0x16 5 M 2 H 1 M
5
0x2c 0010 1100 0x05 4 M 2 M 1 M
0xba 1011 1010 0x17 2 M 1 M 0 M
0xfd 1111 1101 0x0f 5 M 2 m 1 M
5.3 By convention, a cache is named according to the amount of data it contains
(i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM
to store metadata such as tags and valid bits. For this exercise, you will examine
how a cache’s configuration affects the total amount of SRAM needed to
implement it as well as the performance of the cache. For all parts, assume that
the caches are byte addressable, and that addresses and words are 64 bits.
5.3.1 [10] <§5.3> Calculate the total number of bits required to implement a
32 KiB cache with two-word blocks.
5.3.2 [10] <§5.3> Calculate the total number of bits required to implement a
64 KiB cache with 16-word blocks. How much bigger is this cache than the 32
KiB cache described in Exercise 5.3.1? (Notice that, by changing the block size,
we doubled the amount of data without doubling the total size of the cache.)
5.3.1 Total size is 364,544 bits/8 = 45,568 (bytes) 
Each word is 8 bytes; each block contains two words; thus, each block contains
16 = 2^4 (bytes).
The cache contains 32KiB = 32*1024=32678 (bytes)=2^15 (bytes) of data. Thus,
it has 2^15/2^4 = 2^11 lines of data.
Each 64-bit address is divided into:
1. A3-bit word off set,
2. 1-bit block off set,
3.  An 11-bit index (because there are 2^11 lines)
4.  A49-bit tag (64 − 3 − 1− 11 = 49).
 Th e cache is composed of= 2^15 * 8( bits of data) + 2^11*49 (bits of tag )+
2^11*1 (valid bits) = 364,544 bits.
5.3.2
Total size is 549,376 bits/8 = 68,672bytes.This is a =(68,672/45,568)*100-
100=50,7% increase
Each word is 8 bytes; each block contains 16 words; thus, each block contains
128 = 2^7 bytes.
Th e cache contains 64KiB =64*1024 (bytes)= 2^16 (bytes) of data. Thus, it has
2^16/2^7= 2^9 lines of data.
Each 64-bit address is divided into: 
1. A 3-bit word off set
2.  A 4-bit block off set
3. A 9-bit index (because there are 2^9 lines)
4. A 48-bit tag (64 − 3 − 4 − 9= 48).
The cache is composed of: 2^16 * 8 bits of data + 2^9*48 bits of tag + 2^9*1
valid bits = 549,376 bits
5.5 
 5.5.1 
 Each cache block consists of four 8-byte words. The total off set is 5 bits. Three of
those 5 bits is the word off set (the offset into an 8-byte word). The remaining two
bits are the block off set. Two bits allows us to enumerate 2^2   =   4 words. 
 5.5.2 
   There are five index bits. This tells us there are 2^5 =  32 lines in the cache. 
 5.5.3 
The ratio is 1.21. The cache stores a total of 32 lines * 4 words/block * 8 bytes
word  =  1024 bytes  =  8192 bits. 
 In addition to the data, each line contains 54 tag bits and 1 valid bit. Thus, the
total bits required =  8192 +  54*32   +  1 *32   =  9952 bits
5.5.4
Byte Binary Address Tag Index Offset Hit/Mis Byte replaced
Address s
0x00 0000 0000 0000 0x0 0x00 0x00 M
 0x04 0000 0000 0100 0x0 0x00 0x04 H
0x10 0000 0001 0000 0x0 0x00 0x10 H
0x84 0000 1000 0100 0x0 0x04 0x04 M
0xe8 0000 1110 1000 0x0 0x07 0x08 M
0xa0 0000 1010 0000 0x0 0x05 0x00 M
0x400 0100 0000 0000 0x1 0x00 0x00 M 0x00-0x1F
0x1e 0000 0001 1110 0x0 0x00 0x1e M 0x400-0x41F
0x8c 0000 1000 1100 0x0 0x04 0x0c H
0xc1c 1100 0001 1100 0x3 0x00 0x1c M 0x00-0x1F
0xb4 0000 1011 0100 0x0 0x05 0x14 H
0x884 1000 1000 0100 0x2 0x04 0x04 M 0x80-0x9f
5.5.5 
   4/12   =  3 3%. 
  5.5.6
 <index, tag, data> 
 <0, 3, Mem[0xC00]-Mem[0xC1F]> 
 <4, 2, Mem[0x880]-Mem[0x89f]>  
 <5, 0, Mem[0x0A0]-Mem[0x0Bf]> 
 <7, 0, Mem[0x0e0]-Mem[0x0ff]>
5.11 This exercise examines the effect of different cache designs, specifically
comparing associative caches to the direct-mapped caches from Section 5.4. For
these exercises, refer to the sequence of word address shown below. 0x03, 0xb4,
0x2b, 0x02, 0xbe, 0x58, 0xbf, 0x0e, 0x1f, 0xb5, 0xbf, 0xba, 0x2e, 0xce
5.11.1   Sketch the organization of a three-way set associative cache with two-
word blocks and a total size of 48 words. Your sketch should have a style similar
to Figure 5.18, but clearly show the width of the tag and data fields.
Mỗi dòng trong caches sẽ có tổng cộng 6 khối .Suy ra ta có:48/6=8 dòng.
5.11.2 Trace the behavior of the cache from Exercise 5.11.1. Assume a true LRU
replacement policy. For each reference, identify 
 the binary word address,
   the tag, 
 the index,
   the offset
   whether the reference is a hit or a miss, and 
  which tags are in each way of the cache after the reference has been
handled
Word Binary Ta Index Offset Hit/Mis Way  Way  Way Way
Address Address g s 0 1 2 3
0x03 0000 0011 0x0 3 1 Miss T(3)=0
0xb4 1011 0100 0xb 4 0 Miss T(3)=0
T(4)=b
0x2b 0010 1011 0x2 3 1 Miss T(3)=0 T(3)=2
T(4)=b

0x02 0000 0010 0x0 2 0 Miss T(3)=0 T(3)=2

T(4)=b
T(2)=0
0xbe 1011 1110 0xb 6 0 Miss T(3)=0 T(3)=2
T(4)=b
T(2)=0
T(6)=b
0x58 0101 1000 0x5 0 0 Miss T(3)=0 T(3)=2
T(4)=b
T(2)=0
T(6)=b
T(0)=5
0xbf 1011 1111 0xb 3 1 Miss T(3)=0 T(3)=2 T(3)=b
T(4)=b
T(2)=0
T(6)=b
T(0)=5
0x0e 0000 1110 0x0 6 0 Miss T(3)=0 T(3)=2 T(3)=b
T(4)=b T(6)=0
T(2)=0
T(6)=b
T(0)=5
0x1f 0001 1111 0x1 7 1 Miss T(3)=0 T(3)=2 T(3)=b
T(4)=b T(6)=0
T(2)=0
T(6)=b
T(0)=5
T(7)=1
0xb5 1011 0xb 5 1 Miss T(3)=0 T(3)=2 T(3)=b
0101  T(4)=b T(6)=0
T(2)=0
T(6)=b
T(0)=5
T(7)=1
T(5)=b
oxbf 1011 1111 0xb 3 1 Hiss T(3)=0 T(3)=2 T(3)=b
T(4)=b T(6)=0
T(2)=0
 T(6)=b
T(0)=5
T(7)=1
T(5)=b
0xba 1011 1010 0xb 2 Miss T(3)=0 T(3)=2 T(3)=b
T(4)=b T(6)=0
T(2)=0
T(6)=b
T(0)=5
T(7)=1
T(5)=b
0x2e 0010  0x2 6 Miss T(3)=0 T(3)=2 T(3)=b
1110 T(4)=b T(6)=0 T(6)=2
T(2)=0
T(6)=b
T(0)=5
T(7)=1
T(5)=b
0xce  1100 1110 0xc 6 0 Miss T(3)=0 T(3)=2 T(3)=b T(6)=c
T(4)=b T(6)=0 T(6)=2
T(2)=0
T(6)=b
T(0)=5
T(7)=1
T(5)=b

5.11.3   Sketch the organization of a fully associative cache with one-word

blocks and a total size of eight words. Your sketch should have a style similar
to Figure 5.18, but clearly show the width of the tag and data fields.
5.11.4   Trace the behavior of the cache from Exercise 5.11.3. Assume a true
LRU replacement policy. For each reference, identify 
 the binary word address,
   the tag, 
 the index,
   the offset
   whether the reference is a hit or a miss, and 
 the contents of the cache after each reference has been handled.
Word Binary Tag Mis/His Contents
Address Address s
0x03 0000 0011 0x03 M 3
0xb4 1011 0100 0xb M 3,b4
4
0x2b 0010 1011 0x2 M 3,b4,2b
b
 0x02 0000 0010 0x02 M 3,b4,2b,2
0xbe 1011 1110 0xbe M 3,b4,2b,2,be
0x58 0101 1000 0x58 M 3,b4,2b,2,be,58
0xbf 1011 1111 0xbf M 3,b4,2b,2,be,58,bf
0x0e 0000 1110 0x0e M 3,b4,2b,2,be,58,bf,e
0x1f 0001 1111 0x1f M b4,2b,2,be,58,bf,e,1f
0xb5 1011 0101 0xb M 2b,2,be,58,bf,e,1f,b5
5
Oxbf 1011 1111 oxbf H 2b,2,be,58,bf,e,1f,b5,bf
0xba 1011 1010 0xba M 2,be,58,bf,e,1f,b5,bf,ba
0x2e 0010 1110 0x2e M be,58,bf,e,1f,b5,bf,ba,2e
0xce 1100 1110 0xce M 58,bf,e,1f,b5,bf,ba,2e,ce
    5.11.5 Sketch the organization of a fully associative cache with two-word
blocks and a total size of eight words. 965 Your sketch should have a style
similar to Figure 5.18, but clearly show the width of the tag and data fields.
5.11.6 Trace the behavior of the cache from Exercise 5.11.5. Assume an LRU
replacement policy. For each reference, identify
 the binary word address,
   the tag, the index,
   the offset, 
 whether the reference is a hit or a miss, and 
 the contents of the cache after each reference has been handled.
Word Binary Tag Mis/His contents
Address Address s
0x03 0000 0011 0x03 M [2,3]
0xb4 1011 0100 0xb4 M [2,3],[b4,b5]
0x2b 0010 1011 0x2b M [2,3],[b4,b5],[2a,2b]
0x02 0000 0010 0x02 M [b4,b5],[2a,2b],[2,3]
0xbe 1011 1110 0xbe M [b4,b5],[2a,2b],[2,3],[be,bf]
0x58 0101 1000 0x58 M [2a,2b],[2,3],[be,bf],[58,59]
0xbf 1011 1111 0xbf M [2a,2b],[2,3],[58,59],[be,bf]
0x0e 0000 1110 0x0e M [2,3],[58,59],[be,bf],[e,f]
0x1f 0001 1111 0x1f M [58,59],[be,bf],[e,f],[1e,1f]
0xb5 1011 0101 0xb5 M [be,bf],[e,f],[1e,1f],[b4,b5]
oxbf 1011 1111 oxbf H [e,f],[1e,1f],[b4,b5],[be,bf]
0xba 1011 1010 0xba M [1e,1f],[b4,b5],[be,bf],[ba,bb]
0x2e 0010 1110 0x2e M [b4,b5],[be,bf],[ba,bb],[2e,2f]
0xce 1100 1110 0xce M [be,bf],[ba,bb],[2e,2f],[ce,cf]