STA508A

45V 4.5A QUAD POWER HALF BRIDGE

PRODUCT PREVIEW

1 FEATURES Figure 1. Package

■ MULTIPOWER BCD TECHNOLOGY
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
■ 200mΩ RdsON COMPLEMENTARY DMOS
( s ) PowerSO36

OUTPUT STAGE
c t Table 1. Order Codes
■ CMOS COMPATIBLE LOGIC INPUTS
d u Part Number Package
■ THERMAL PROTECTION
r o s) STA508A PowerSO36
■ THERMAL WARNING OUTPUT
P c t(
■ UNDER VOLTAGE PROTECTION
SHORT CIRCUIT PROTECTION
e t e u capability, and as half bridge (Binary mode) with half

l rod
■
current capability.The device is particularly designed
2 DESCRIPTION o
s P
to make the output stage of a stereo All-Digital High

b
O ete
STA508 is a monolithic quad half bridge stage in Mul-
Efficiency (DDX™) amplifier capable to deliver 80 +
80W @ THD = 10% at Vcc 36V output power on 8Ω
load. In single BTL configuration is also capable to

) -
tipower BCD Technology. The device can be used as

l
dual bridge or reconfigured, by connecting CONFIG deliver a peak of 160W @THD = 10% at VCC = 36V

t ( s s o
pin to Vdd pin, as single bridge with double current on 4Ω load. The input pins have threshold proportion-
al to VL pin voltage.

c
u -O b
Figure 2. Audio Application Circuit (Dual BTL)

d
o s)
P r (
VCC1A +VCC

t
15
IN1A 29 M3 C30 C55

e uc
IN1A 1µF 1000µF
17 L18 22µH

t
VL 23
+3.3V OUT1A
CONFIG 24 16 C20

e
100nF

l od
OUT1A
PWRDN PWRDN 25 M2 C52
C99

o
14 GND1A 330pF R98
PROTECTIONS 6 100nF

s Pr
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC
26 12 VCC1B 470nF

b
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1µF

O ete
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22µH

l
IN1B
M4
VDD 21 13 GND1B

s o VDD
VSS
22
33 REGULATORS
7 VCC2A

b
VSS 34
M17 C32
C58 C53 1µF

O
100nF 100nF VCCSIGN 8 L113 22µH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1µF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22µH
GNDSUB M14
1 5 GND2B

D00AU1148B

REV. 2
November 2004 1/10

This is preliminary information on a new product now in development. Details are subject to change without notice.
STA508A

Table 2. Pin Function

N° Pin Description

1 GND-SUB Substrate Ground

2;3 OUT2B Output Half Bridge 2B

4 VCC 2B Positive Supply

5 GND2B Negative Supply

6 GND2A Negative Supply

7 VCC 2A Positive Supply

8;9 OUT2A Output Half Bridge 2A

( s )
10 ; 11 OUT1B Output Half Bridge 1B
c t
12 VCC1B Positive Supply
d u
13 GND1B Negative Supply
r o s)
P c t(
14 GND1A Negative Supply

e t e u
15 VCC1A Positive Supply

o l rod
16 ; 17

18
OUT1A

NC Not Connected b s P
Output Half Bridge 1A

19 GND-clean
- O ete
Logical Ground

s ) o l
20

21 ; 22
GND-Reg

Vdd
c t ( b s
Ground for Regulator Vdd

5V Regulator Referred to Ground

23 VL
d u -O
High Logical State Setting Voltage

r o s)
(
24 CONFIG Configuration pin

25 P
e uc
PWRDN t Stand-by pin

26
e t
l od
TRI-STATE Hi-Z pin

27 o
s Pr FAULT Fault pin Advisor

b
O ete
28 TH-WAR Thermal Warning Advisor

o l
29 IN1A Input of Half Bridge 1A

bs
30 IN1B Input of Half Bridge 1B

31 IN2A Input of Half Bridge 2A

O 32 IN2B Input of Half Bridge 2B

33 ; 34 VSS 5V Regulator Referred to +VCC

35 ; 36 VCC Sign Signal Positive Supply

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 STA508A

Table 3. Functional Pin Status

PIN NAME Logical value IC -STATUS
FAULT 0 Fault detected (Short circuit, or Thermal ..)

FAULT (*) 1 Normal Operation

TRI-STATE 0 All powers in Hi-Z state

TRI-STATE 1 Normal operation
PWRDN 0 Low absorpion
PWRDN 1 Normal operation
THWAR 0 Temperature of the IC =130°C

THWAR(*) 1
( s ) Normal operation

CONFIG
c t 0 Normal Operation

CONFIG(**)
d u 1 OUT1A = OUT1B ; OUT2A=OUT2B

r o s) (IF IN1A = IN1B; IN2A = IN2B)

P t(
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)

c
e t e u
Table 4. Pin Connection

o l rod
b s P
O ete
VCCSign 36 1 GND-SUB

-
VCCSign

) l
35 2 OUT2B

t ( s
VSS

s
VSS o 34
33
3
4
OUT2B
VCC2B

c
u -O b
IN2B 32 5 GND2B

d
o s)
IN2A 31 6 GND2A

P r (
IN1B 30 7 VCC2A

t IN1A 29 8 OUT2A

e t e uc TH_WAR 28 9 OUT2A

o l od FAULT 27
26
10
11
OUT1B

s Pr
TRI-STATE OUT1B

b
O ete
PWRDN
CONFIG
VL
25
24
23
12
13
14
VCC1B
GND1B
GND1A

o l VDD 22 15 VCC1A

bs
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
O GND-Clean 19 18 N.C.

D01AU1273

Table 5. Thermal Data

Symbol Description Value Unit

Rth j-case Thermal Resistance Junction-case max 1.5 °C/W

3/10
STA508A

Table 6. Absolute Maximum Ratings

Symbol Parameter Value Unit

VCC DC Supply Voltage (Pin 4,7,12,15) 45 V

Vmax Maximum Voltage on pins 23 to 32 5.5 V

Ptot Power Dissipation (Tcase = 70°C) 50 W

Top Operating Temperature Range 0 to 70 °C

Tstg, Tj Storage and Junction Temperature -40 to 150 °C

s )
Table 7. Electrical Characteristcs (VL = 3.3V; VCC = 30V; Tamb = 25°C; fsw = 384KHz; unless othewise
(
specified)
c t
Symbol Parameter

d u
Test conditions Min. Typ. Max. Unit

RdsON Power Pchannel/Nchannel

MOSFET RdsON
r
Id=1A
o s) 200 270 mΩ

P c t(
Idss Power Pchannel/Nchannel
leakage Idss
e t e u
VCC =35V 50 µA

gN
o l rod
Power Pchannel RdsON Matching Id=1A 95 %

gP Power Nchannel RdsON

b s P Id=1A 95 %
Matching

- O ete
Dt_s

s ) o l
Low current Dead Time (static) see test circuit no.1; see fig. 4 10 20 ns

Dt_d

c t ( b s
High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω
Id=3.5A; see fig. 3
50 ns

td ON
d u -O
Turn-on delay time Resistive load 100 ns

td OFF
r o s)
Turn-off delay time Resistive load 100 ns

tr P
e uc t
Rise time( Resistive load; as fig.4 25 ns

tf
e t
l odFall time Resistive load; as fig. 4 25 ns

VCC
o
s Pr Supply voltage operating voltage 10 40 V

b
VIN-H
O ete
High level input voltage VL/2
+300mV
V

o l
VIN-L Low level input voltage VL/2 - V

bs
300mV

IIN-H Hi level Input current Pin Voltage = VL 1 µA

O IIN-L Low level input current Pin Voltage = 0.3V 1 µA

IPWRDN-H High level PWRDN pin input VL = 3.3V 35 µA

current

VLow Low logical state voltage VL (pin VL = 3.3V 0.8 V

PWRDN, TRISTATE) (note 1)

4/10
 STA508A

Table 7, (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VHigh High logical state voltage VH (pin VL = 3.3V 1.7 V

PWRDN, TRISTATE) (note 1)

IVCC- Supply CURRENT from Vcc in PWRDN = 0 3 mA

PWRDN Power Down

IFAULT Output Current pins

FAULT -TH-WARN when Vpin = 3.3V 1 mA
FAULT CONDITIONS

IVCC-hiz Supply Current from Vcc in Tri- VCC = 30V; Tri-state = 0 22 mA

state

( s )
IVCC Supply Current from Vcc in VCC =30V;
c t 50 mA
operation
both channel switching)
d u
Input Pulse width = 50% Duty;
Switching Frequency = 384KHz;

o s)
No LC filters;

r
IVCC-q Isc (short circuit current limit)
(note 2) P c t( 4.5 6 9 A

e t e u
l rod
VUV Undervoltage protection threshold 7 V

tpw-min Output minimum pulse width

o
s P No Load 70 150 ns

Table 8.
b
O ete
) - l
Notes: 1. The following table explains the VLow, VHigh variation with VL

VL VLmin
t ( s s
VHmaxo Unit

2.7 0.7
c
u -O b 1.5 V

3.3
d
0.8
o s)
1.7 V

5
P r (
0.85 1.85 V

t e uc t
o e
Note 2: See relevant Application Note AN1994
l od
s Pr
Table 9. Logic Truth Table (see fig. 5)
b
O ete
TRI-STATE INxA INxB Q1 Q2 Q3 Q4
OUTPUT
MODE

o l0 x x OFF OFF OFF OFF Hi-Z

O bs 1

1
0

0
0

1
OFF

OFF
OFF

ON
ON

ON
ON

OFF
DUMP

NEGATIVE

1 1 0 ON OFF OFF ON POSITIVE

1 1 1 ON ON OFF OFF Not used

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STA508A

Figure 3. Test Circuit.

OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

Duty cycle = 50%

( s ) DTr DTf
t

M58

c t
INxY
d u OUTxY R 8Ω

r o s)
M57 + V67 =

P (
-

e u c t vdc = Vcc/2

t
gnd
D03AU1458

o e
l rod
Figure 4.
b s P
- O ete +VCC

s ) o l
c t ( b s Q1 Q2

d u -O
INxA
OUTxA OUTxB
INxB

r o s) Q3 Q4

P
e uc t (
e t
l od
GND
D00AU1134

o
s Pr
Figure 5.

b
O ete High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

o l +VCC

bs
Duty cycle=A Duty cycle=B
DTout(A)

O
M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTA Rload=8Ω OUTB
INA INB
L67 22µ L68 22µ
Iout=4.5A Iout=4.5A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU1517

6/10
 STA508A

Figure 6. Typical Single BTL Configuration

VL
+3.3V 23 18 N.C.
100nF 10µH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 4Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
10µH

)
10K FAULT
27 VCC1A

s 15 32V

(
26

t
TRI-STATE 1µF 2200µF
100nF X7R 63V

c
IN1A VCC1B
29 12

u
IN1B
IN1A 30

d
IN2A VCC2A
31 7 32V

o s)
IN2B

r
IN1B 32 1µF
X7R
VSS VCC2B

P VSS

c t( 33
34
4
GND1A
100nF
X7R
t e u
VCCSIGN

e
14
GND1B

l rod
35 13

o
100nF VCCSIGN GND2A
X7R

s P
36 6
Add. GND2B

b
GNDSUB
1 5

O ete
D03AU1514

) - l
t ( s s o
Figure 7. Typical Quad Half Bridge Configuration

c b VCC1P +VCC

15

u -O
IN1A 29 M3 R61 C21
IN1A 5K C31 820µF 2200µF

d
17 L11 22µH
VL 23
+3.3V OUTPL

o s)
CONFIG 24 16 R41 C71

r
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1µF

P (
14 PGND1P R51 C81 R62
C41

t
PROTECTIONS 6 100nF 5K
R57 R59 FAULT 27 & 330pF

e uc
10K 10K LOGIC
26 12 VCC1N

e t
l od
C58
100nF
TRI-STATE

TH_WAR 28
M5
11
OUTNL
C51
1µF
C61
100nF
R63
5K C32 820µF

o
TH_WAR 10 L12 22µH

s Pr
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF

b
VDD 21 13 PGND1N C92 4Ω
1µF
VDD 22 R52 C82 R64
C42

O ete
6 100nF 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34

l
M17 R65
C58 C53 C33 820µF
L13 22µH 5K
100nF 100nF VCCSIGN 8

o
35
OUTPR

bs
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1µF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K

O
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1µF 100nF
R67
OUTNR 5K C34 820µF
IN2B 2 L14 22µH
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1µF
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474

For more information refer to the application notes AN1456 and AN1661

7/10
STA508A

Figure 8. PowerSO36 Mechanical Data & Package Dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.25 3.43 0.128 0.135 MECHANICAL DATA
A2 3.1 3.2 0.122 0.126
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a1 0.030 -0.040 0.0011 -0.0015
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039

( s )
E
E1
13.9
10.9
14.5
11.1
0.547
0.429
c t
0.57
0.437
E2
E3 5.8
2.9
6.2 0.228
d u 0.114
0.244
E4 2.9 3.2 0.114
r o s) 1.259
e
e3
0.65
11.05 P 0.026

c t
0.435(
G 0 0.075

e
0
t e u 0.003
H
h
15.5 15.9
1.1
o l rod
0.61 0.625
0.043

N
L 0.8 1.1

b
10˚ s P 0.031 0.043
10˚
s

- O
8˚

e e
PowerSO36 (SLUG UP)
t
(1) “D and E1” do not include mold flash or protusions.
8˚

)
s s o l
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.

t (
c Ob
u
r od s) -
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Obs

7183931 D

8/10
 STA508A

Table 10. Revision History

Date Revision Description of Changes

August 2004 1 First Issue

November 2004 2 Changed Vcc from 9 min to 10 min

( s )
c t
d u
r o s)
P c t(
e t e u
o l rod
b s P
- O ete
s ) o l
c t ( b s
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Obs

9/10
STA508A

( s )
c t
d u
r o s)
P c t(
e t e u
o l rod
b s P
- O ete
s ) o l
c t ( b s
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
l
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

o
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

bs
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

O The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

DDX is a trademark of Apogee tecnology inc.

© 2004 STMicroelectronics - All rights reserved

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