MCT-222 Embedded Systems

Lecture 6:
Finite state machines

7-1
 Finite State Machine (FSM)
❑Finite State Machines (FSMs)
❖Set of inputs, outputs, states and transitions
❖State graph defines input/output relationship

JK-Flip Flop is an example of state-machine

7-2
 Finite State Machine (FSM)

❑Finite State Machines (FSMs)

❖Set of inputs, outputs, states and transitions
❖State graph defines input/output relationship
❑What is a state?
❖Description of current conditions
❑What is a state graph?
❖Graphical interconnection between states
❑What is a controller?
❖Software that inputs, outputs, changes state
❖Accesses the state graph

7-3
 Finite State Machine (FSM)
❑What is a finite state machine?
❖Inputs (sensors)
❖Outputs (actuators)
❖Controller
❖State graph

7-4
Finite State Machine (FSM)

7-5
 Finite State Machine (FSM)
❑Moore FSM
❖output value depends ONLY on the current state,
❖inputs affect the state transitions
❖significance is being in a state
❑Input: when to change state
❑Output: definition of being in that state

7-6
 Finite State Machine (FSM)

❑ Moore FSM Execution Sequence

1. Perform output corresponding to the current
state
2. Wait a prescribed amount of time (optional)
3. Read inputs
4. Change state, which depends on the input and
the current state
5. Go back to 1. and repeat

7-7
 FSM Implementation
❑Data Structure embodies the FSM
❖multiple identically-structured nodes
❖statically-allocated fixed-size linked structures
❖one-to-one mapping FSM state graph and linked structure
❖one structure for each state
❑Linked Structure
❖pointer (or link) to other nodes (define next states)
❑Table structure
❖indices to other nodes (define next states)

7-8
 Traffic Light Control

PE1=0, PE0=0 means no cars exist on either road

PE1=0, PE0=1 means there are cars on the East road
PE1=1, PE0=0 means there are cars on the North road
PE1=1, PE0=1 means there are cars on both roads 7-9
 Traffic Light Control
PE1=0, PE0=0 means no cars exist on either road
PE1=0, PE0=1 means there are cars on the East road
PE1=1, PE0=0 means there are cars on the North road
PE1=1, PE0=1 means there are cars on both roads

goN, PB5-0 = 100001 makes it green on North and red on East

waitN, PB5-0 = 100010 makes it yellow on North and red on East
goE, PB5-0 = 001100 makes it red on North and green on East
waitE, PB5-0 = 010100 makes it red on North and yellow on East 7-10
Traffic Light Control

7-11
Traffic Light Control

7-12
 Linked Data Structure
goN DCD 0x21 ;North green, East red
DCD 3000 ;30 sec
DCD goN,waitN,goN,waitN

waitN DCD 0x22 ;North yellow, East red

DCD 500 ;5 sec
DCD goE,goE,goE,goE

goE DCD 0x0C ;North red, East green

In ROM
DCD 3000 ;30 sec
DCD goE,goE,waitE,waitE

waitE DCD 0x14 ;North red, East yellow

DCD 500 ;5 sec
DCD goN,goN,goN,goN 7-13
 Linked Data Structure
goN DCD 0x21 ;North green, East red
DCD 3000 ;30 sec
DCD goN,waitN,goN,waitN

waitN Base address

goN Base address+20
goN Base address
goN Base address+16
waitN Base address
goN Base address+12
goN Base address
goN Base address+8

goN Base address+4 3000

goN Base address 0x21

ROM Address ROM Data

7-14
 Linked Data Structure
goE DCD 0x0C ;North red, East green
DCD 3000 ;30 sec
DCD goE,goE,waitE,waitE

waitE Base address

goE Base address+20
waitE Base address
goE Base address+16
goE Base address
goE Base address+12
goE Base address
goE Base address+8

goE Base address+4 3000

goE Base address 0x0C

ROM Address ROM Data

7-15
 Linked Data Structure
waitN DCD 0x22 ;North yellow, East red
DCD 500 ;5 sec
DCD goE,goE,goE,goE

goE Base address

waitN Base address+20
goE Base address
waitN Base address+16
goE Base address
waitN Base address+12
goE Base address
waitN Base address+8

waitN Base address+4 500

waitN Base address 0x22

ROM Address ROM Data

7-16
 Linked Data Structure
waitE DCD 0x14 ;North red, East yellow
DCD 500 ;5 sec
DCD goN,goN,goN,goN

goN Base address

waitE Base address+20
goN Base address
waitE Base address+16
goN Base address
waitE Base address+12
goN Base address
waitE Base address+8

waitE Base address+4 500

waitE Base address 0x14

ROM Address ROM Data

7-17
 Linked Data Structure
waitE Base address+20 waitN Base address+20 goE Base address
goN Base address
waitE Base address+16 goN Base address waitN Base address+16 goE Base address

waitE Base address+12 goN Base address waitN Base address+12 goE Base address

waitE Base address+8 goN Base address waitN Base address+8 goE Base address

waitE Base address+4 500 waitN Base address+4 500

waitE Base address 0x14 waitN Base address 0x22

goE Base address+20 waitE Base address

goN Base address+20 waitN Base address In ROM
goE Base address+16 waitE Base address
goN Base address+16 goN Base address

goE Base address goN Base address+12 waitN Base address

goE Base address+12

goE Base address goN Base address+8 goN Base address

goE Base address+8

3000 goN Base address+4 3000

goE Base address+4

0x0C goN Base address 0x21

goE Base address
7-18
 Linked Data Structure
OUT EQU 0 ;offset for output
WAIT EQU 4 ;offset for time (10ms)
NEXT EQU 8 ;offset for next
goN DCD 0x21 ;North green, East red
DCD 3000 ;30 sec
DCD goN,waitN,goN,waitN
waitN DCD 0x22 ;North yellow, East red
DCD 500 ;5 sec
DCD goE,goE,goE,goE In ROM
goE DCD 0x0C ;North red, East green
DCD 3000 ;30 sec
DCD goE,goE,waitE,waitE
waitE DCD 0x14 ;North red, East yellow
DCD 500 ;5 sec
DCD goN,goN,goN,goN 7-19
 FSM Engine (Moore)
; PortE, PortB base addresses are in SENSOR, LIGHT resp
; Port and timer initialization

LDRR4,=goN ; state pointer

LDRR5,=SENSOR ; PortE
LDRR6,=LIGHT ; PortB
FSM LDRR0,[R4,#OUT] ; 1.output value
STRR0,[R6] ; set lights
LDRR0,[R4,#WAIT] ; 2. time delay
BL SysTick_Wait10ms
LDRR0,[R5] ; 3. read input
LSLR0,R0,#2 ; offset(index):
; 4 bytes/address
ADD R0,R0,#NEXT ; 8,12,16,20
LDR R4,[R4,R0] ; 4. go to next state
B FSM 7-20
 FSM Data Structure in C (Indexes)
const struct State {
uint32_t Out;
uint32_t Time; // 10 ms units
uint32_t Next[4]; // list of next states
};

#define goN 0
#define waitN 1
#define goE 2
#define waitE 3
State FSM[4] = {
{0x21,3000,{goN,waitN,goN,waitN}},
{0x22, 500,{goE,goE,goE,goE}},
{0x0C,3000,{goE,goE,waitE,waitE}},
{0x14, 500,{goN,goN,goN,goN}}
};
7-21
# define INPUT (*((volatile uint32_t *) 0x400243FC))

# define LIGHT (*((volatile uint32_t *) 0x400053FC))

Homework:
How would you redefine INPUT and LIGHT using bit specific addressing:
Bit 0 and 1 of PORTE
Bit 0,1,2,3,4,5,6 of PORTB

7-22
 address1
# define PORTE 0x400243FC
address2 0x400243FC
address3
# define PORTE (uint32_t *) 0x400243FC address4

address5

address6
# define PORTE (*((uint32_t *) 0x400243FC))
ROM

0x400243FC GPIO_PORTE_DATA_R

RAM

7-23
 # define PORTE (* ((uint32_t *) 0x400243FC))

Danger:
GPIO_POR RAM may contain
Processor RAM TE_DATA_ outdated copy
R of PORT E data

# define PORTE (* ((volatile uint32_t *) 0x400243FC))

GPIO_POR Always read

Processor RAM TE_DATA_
R updated data
from PORTE

7-24
 FSM Engine in C (Indexes)
void main(void) {
uint32 CS; // index of current state
uint32_t Input;

// initialize ports and timer

…

CS = goN; // start state

while(1) {
LIGHT = FSM[CS].Out; // set lights
SysTick_Wait10ms(FSM[CS].Time);
Input = SENSOR; // read sensors
CS = FSM[CS].Next[Input];
}
} 7-25
 FSM Data Structure in C (Pointers)
const struct State {
uint32_t Out;
uint32_t Time; // 10 ms units
const struct State *Next[4];
}; Next is an array containing four (4) pointers

Each pointer value is an address of data type

#define goN &FSM[0]
#define waitN &FSM[1] State
#define goE &FSM[2] which cannot be changed (i.e. const ) after
#define waitE &FSM[3] initialization
State FSM[4] = {
{0x21,3000,{goN,waitN,goN,waitN}},
{0x22, 500,{goE,goE,goE,goE}},
{0x0C,3000,{goE,goE,waitE,waitE}},
{0x14, 500,{goN,goN,goN,goN}}
}; 7-26
 Linked Data Structure
waitN waitE
goN waitE
waitN goE
goN goE
Time = 3000 Time = 3000
&FSM[0] = goN Out = 0x21 &FSM[2] = goE Out = 0x0C

&goE goN
&goE goN
&goE goN
&goE goN
Time = 500 Time = 500
&FSM[1] = waitN Out = 0x22 &FSM[3] = waitE Out = 0x14
7-27
 Food of thought

In C, we can easily work with pointers carrying base

addresses ONLY

Good news is that offsets addresses are not required ☺

for referencing elements of arrays or variables of data
types (e.g. State)

7-28
 FSM Engine in C (Pointers)
void main(void) {
State *Pt; // state pointer
uint32_t Input;
waitN
// initialize ports and timer goN
… waitN
Pt
goN
Pt = goN; // start state
Time = 3000
while(1) {
Out = 0x21
LIGHT = Pt->Out; // set lights
SysTick_Wait10ms(Pt->Time);
Input = SENSOR; // read sensors
Pt = Pt->Next[Input];
}
} 7-29
FSM for adjusting duty cycle of LED
waveform
❑ 1) The system starts with 90% duty-cyle
❑ 2) Turn the LED on/off at current duty-cycle
❑ 3) If the switch is pressed, then switch duty-cycle
❖Cycle: 50->70->90->10->30->50...
❑ 4) Steps 1 and 2 are repeated over and over

7-30
FSM for adjusting duty cycle of LED waveform
0
High Low
1 0
0
450ms 50ms

0
High Low
1 0
0
350ms 150ms

0
High Low
1 0
0
250ms 250ms

0
High Low
1 0
0
150ms 350ms

0
High Low
1 0
0
50ms 450ms
7-31
FSM for adjusting duty cycle of LED
waveform
0
High Low 1
1 0 0 1
450ms 50ms Change0
1
0
50ms
0 0
High Low
1 0 0
350ms 150ms

0
High Low
1 0 0
250ms 250ms

0
High Low
1 0 0
150ms 350ms

0
High Low
1 0 0
50ms 450ms
7-32
FSM for adjusting duty cycle of LED waveform
0
High Low 1
1 0 0 1
450ms 50ms Change0
1
0
50ms
0 0 1
High Low
1 1
0 0
350ms 150ms Change1
1
0
50ms
0 0
High Low
1 0 0
250ms 250ms

0
High Low
1 0 0
150ms 350ms

0
High Low
1 0 0
50ms 450ms
7-33
FSM for adjusting duty cycle of LED waveform
0
High Low 1
1 0 0 1
450ms 50ms Change0
1
0
50ms
0 0 1
High Low
1 1
0 0
350ms 150ms Change1
1
0
50ms
0 0
High Low 1
1 0 0 1
250ms 250ms Change2
1
0
50ms
0 0
High Low 1
1 0 1
0
150ms 350ms Change3
1
0
50ms 0 1
0 0
High Low
1 0 0 Change4
1
50ms 450ms 0
1 7-34
50ms
 Homework

Write C program for encoding FSM of LED duty cycle

problem

and use following main program …..

7-35
 FSM Engine in C (Pointers)
void main(void) {
State_t *Pt; // state pointer
uint32_t Input; Exact same
controller as
before
// initialize ports and timer
…

Pt = Low; // start state

while(1) {
GPIO_PORTE_DATA_R = Pt->Out; // set LED
SysTick_Wait1ms(Pt->Time);
Input = {GPIO_PORTE_DATA_R&0x04)>>2; // PE2
Pt = Pt->Next[Input];
}
} 7-36
To run the state machine of LED duty cycle problem

7-37
 Thank You

Q&A

Slides credit: Jonathan Volvano (http://users.ece.utexas.edu/~valvano/)

7-38
 SysTick Timer in C
#define NVIC_ST_CTRL_R(*((volatile uint32_t *)0xE000E010))
#define NVIC_ST_RELOAD_R(*((volatile uint32_t *)0xE000E014))
#define NVIC_ST_CURRENT_R(*((volatile uint32_t *)0xE000E018))

void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup
NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value
NVIC_ST_CURRENT_R = 0; // 3) any write to CURRENT clears it
NVIC_ST_CTRL_R = 0x00000005; // 4) enable SysTick with core clock
}

// The delay parameter is in units of the 80 MHz core clock(12.5 ns)

void SysTick_Wait(uint32_t delay){
NVIC_ST_RELOAD_R = delay-1; // number of counts
NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears
while((NVIC_ST_CTRL_R&0x00010000)==0){ // wait for flag
}
}
// Call this routine to wait for delay*10ms
void SysTick_Wait10ms(uint32_t delay){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(800000); // wait 10ms
Bard, Gerstlauer, Valvano, Yerraballi 7-39
}