This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2950510, IEEE
Transactions on Transportation Electrification
IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION
Double-Vector Model Predictive Control for
Single-Phase 5-Level Actively Clamped Converters
Yong Yang, Member, IEEE, Jianyu Pan, Member, IEEE, Huiqing Wen, Senior Member, IEEE, Zhiwei Zhang,
Member, IEEE, Ziwei Ke, Student Member, IEEE, Longya Xu, Fellow, IEEE
 converter, showing as a very promising topology [6].
Abstract—In this paper, a double-vector-based model
predictive control (MPC) method with efficient computation for
single-phase five-level active neutral-point clamped (5L-ANPC)
converters is proposed. It uses double voltage vectors per control
cycle rather than the single in the conventional MPC method,
resulting in reduced output current ripples and fixed switching
frequency. Firstly, the MPC method based on Lyapunov function
is optimized to select 2 voltage sectors rather than 25, reducing the
calculation complexity significantly. Then two current tracking
algorithms based on double voltage vectors are presented, which
are using the current cost function and current slope, respectively.
Lastly, a fast voltage balancing scheme for the dc-link and flying
capacitors is developed and embedded in the MPC method. Both
simulated and experimental results are used to validate the
correctness and feasibility of the proposed MPC method.
Index Terms—Model predictive control, single-phase 5L-ANPC
converters, fixed switching frequency, redundant switching states.
I. INTRODUCTION
Compared with two-level converters, multilevel converters
(MLCs) own significant advantages such as higher quality
of output currents, lower voltage stress on power devices,
improved system efficiency, and reduced electromagnetic
interference [1]. Especially, single-phase MLCs have gained
much attention in recent years because of their wide
applications such as in photovoltaic integration, active power
filters, EV charging stations and rail traction systems [2]. In
recent years, the single-phase neutral-point clamped (NPC)
converter has been widely applied in the AC traction
power-supply system [3]-[5]. Among different topologies of
MLCs, the five-level active neutral-point clamped (5L-ANPC)
converter combines the advantages of the traditional neutral
point clamped (NPC) converter and flying capacitor (FC)
Manuscript received July 11, 2019; revised August 25, 2019; accepted
October 21, 2019. This work was supported in part by the National Natural
Science Foundation of China (51977136, 51907137, 51707127), in part by the
Open Research Fund of Jiangsu Collaborative Innovation Center for Smart
Distribution Network, Nanjing Institute of Technology (XTCX201804), and in
part by the Research Enhancement fund of XJTLU (REF-17-01-02).
(Corresponding author: Jianyu Pan.)
Y. Yang is with the School of Rail Transportation, Soochow University,
Suzhou 215131, China (e-mail: yangy1981@suda.edu.cn)
J. Pan is with the School of Electrical Engineering, Chongqing University,
Chongqing 400044, China (e-mail: pan.452@osu.edu)
H. Wen is with the Xi’an Jiaotong-Liverpool University, Suzhou 215123,
China (e-mail: huiqing.wen@xjtlu.edu.cn)
Z. Zhang, Z. Ke, and L. Xu are with the Department of Electrical and
Computer Engineering, The Ohio State University, Columbus, OH 43210 USA
(e-mail: zwzhangieee@gmail.com, ke.123@osu.edu, xu.12@osu.edu).
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1
For single-phase converters, the well-known control method
is the hysteresis current control due to its easy implementation.
However, this method leads to irregular switching frequencies
and makes the output filter design of the converters difficult
[7]-[9]. Another popular control method is the proportional
integral (PI) controller combined with fixed-frequency pulse
width modulation (PWM) in the rotating reference frame.
Nevertheless, choosing proper PI parameters requires repetitive
trial-and-error tuning and the process is time-consuming [10],
[11]. Another widely used method is the proportional resonant
(PR) controller in the stationary reference frame. Although PR
method achieves high performance for single-phase converters,
the method is sensitive to the frequency changes of the
converter [12]-[14].
Model predictive control (MPC), an emerging non-linear
control technique, has gained much attention in power
converter controls due to its advantages of multi-objective
optimization, no PWM control block, and fast-dynamic
response to commands. So far, different MPC methods have
been proposed for different single-phase converters. For a
single-phase two-level grid-connected converter, the MPC
method based on the active and reactive powers has been
presented [15], [16], achieving decoupled control of the active
and reactive powers in steady-state and dynamic conditions.
MPC methods have also been applied to other single-phase
converters with more than two DC levels. For example, MPC
methods for single-phase three-level converters have been used
in active power filters in [17] and grid-connected converters in
[18]. Similarly, MPC methods for single-phase five-level
grid-connected converters [19],[20], and grid connected
packed-U-cells multilevel inverters [21],[22], were discussed,
simultaneously achieving both the current reference tracking
and capacitor voltage balancing. However, the MPC
approaches mentioned above only use one voltage vector per
control cycle, resulting in large output current ripples and none
fixed switching frequencies. The irregular switching frequency
of the converter leads to the difficulty in the output filter design.
To solve the issues of MPC methods using one voltage
vector, multi-vector MPCs have been proposed. The methods
utilizing two or more voltage vectors per control cycle are able
to achieve the reduced current ripples with a fixed switching
frequency (FSF). For example, for a two-level three-phase
converter, [23] and [24] proposed the FSF MPC using double
voltage vectors with the proven reduction of current ripple.
[25]-[27] use three voltage vectors to further improve the
current performance. The FSF MPC algorithms are also
developed for single-phase three-level NPC converters. In [28],
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a FSF MPC method using optimal switching sequences was P

presented. Similarly, a new FSF MPC using direct power S a1 Sb1

control was proposed in [29]. These two FSF MPCs achieve ic1
excellent steady-state and dynamic performance. Similarly, Vc1 C S a1 Sa 3 S b1 Sb 3
modulated model predictive control (M2PC) has been proposed,
iaf Sa 4 ibf
which achieves multi voltage vectors operation and FSF control. iN a
Sb 4
Vaf Ca Cb b
M2PC has been applied in shunt active filters [30], indirect VdcO Vbf
S a4 S b4
matrix converters [31], and three-phase three-level converters
ic 2
[32],[33]. However, all the aforementioned FSF MPC methods
are limited to the two-level or three-level converters. When the Vc 2 C Sa 2 S a3
Sb 2 S b3

output voltage level increases to five such as in a 5L-ANPC, the

S a2 S b2
complexity of the MPCs is dramatically increased due to more
ia ib
switching states. Moreover, a 5L-ANPC needs to consider N

capacitor voltage balancing issues in addition to the output L

R
current control. Thus, without new algorithms capable of
Fig. 1. Circuit structure of the single-phase 5L-ANPC converter.
dealing with capacitor balancing, the existing
multi-vector-based MPCs are not practical for a single-phase As shown in Table I, there are eight switching states. The
5L-ANPC. eight switching states will generate five output voltage levels
To the best of the authors' knowledge, there are little reports (-Vdc/2, -Vdc/4, 0, Vdc/4 and Vdc/2). The neutral point O of the
about MPC with fixed switching frequency for single-phase DC bus is considered as voltage reference. It is interesting to
five-level converters. This paper proposes a double-vector note that SWa1 generates the same voltage level as that of SWa2,
MPC control method with duty ratio calculation for the but has different influences on dc-link capacitor voltages and
single-phase 5L-ANPC converter. Two approaches, the current flying capacitor voltages. Thus, SWa1 and SWa2 can be treated
cost function, and the current slope one, are studied in as the redundant switching states to control the output current
optimization in the paper. Investigated by theoretical analysis and capacitor voltages. The redundant switching states can also
and validated by extensive experimental testing, the proposed be found in SWa5 and SWa6. It is obvious that if we apply the
MPC method shows salient advantages. It is further shown that same switching rule to Leg-B, a similar table to Table I can be
the algorithm using the current slope has a relatively longer obtained for Leg-B.
execution time but lower current harmonics compared to the TABLE Ⅰ
one using current cost function. Thus, with the proposed
SWITCHING COMBINATIONS OF THE PHASE-A LEG
double-vector MPC method, the single-phase 5-level ANPC Sa1 Sa2 Sa3 Sa4 uaO iN iaf States
achieves a fixed switching frequency, efficient computation, 0 0 0 0 -Vdc/2 0 0 SWa0
high-quality output current, and strong capacitor voltage 0 0 0 1 -Vdc/4 0 -ia SWa1
balancing. 0 0 1 0 -Vdc/4 ia ia SWa2
0 0 1 1 0 ia 0 SWa3
II. CIRCUIT STRUCTURE AND MATHEMATICAL MODEL 1 1 0 0 0 ia 0 SWa4
Fig. 1 shows the circuit structure of the single-phase 1 1 0 1 Vdc/4 ia -ia SWa5
5L-ANPC. The circuit consists of a DC-bus voltage split by two 1 1 1 0 Vdc/4 0 ia SWa6
DC capacitors. The equal voltages across the two capacitors 1 1 1 1 Vdc/2 0 0 SWa7
Vc1 and Vc2 are named the dc-link upper and lower respectively.
As shown in Fig. 2, an array of voltage vectors of a
To realize DC/AC conversion, Vc1 and Vc2 are shared by two
single-phase 5L-ANPC can be defined as the voltage difference,
identical legs, Leg-A and Leg-B. Each leg is composed of eight
Vab, between the outputs of Leg-A and Leg-B. Thus, 25 (52)
power switches and one flying capacitor. Vaf and Vbf are the two
voltage vectors can be created due to five output voltage levels
flying capacitor voltages. L and R represent the load inductor
from each leg, denoted as V0, V1, …, through V24. The α-axis
and resistor, respectively. ia and ib are the output currents from
represents the output voltage Vab of each voltage vector, and
each leg constrained by ia=-ib.
β-axis is only used to arrange the voltage vectors [34]. For each
For Leg-A, the power switches Sa1 and S operate in the voltage vector, the number in the round bracket, “0”, “1”, “2”,
complementary mode. That is, when Sa1 is in on-state, S is in “3” and “4”, represent that the output voltage level for one leg
off-state, and vice versa. The same rule applies to the other at -Vdc/2, -Vdc/4, 0, Vdc/4 and Vdc/2. Thus, the voltage vector Vab
three switch pairs (Sa2 and S , Sa3 and S , Sa4 and S ). The can be one of the nine levels between -Vdc and Vdc. Taking the
operation principle also applies to all switches in Leg-B. notation of V8 (43) as an example, we see that V8(43) represents
Assuming that Vc1 and Vc2 are clamped to a half of the the voltage difference (Vao-Vbo) between Leg-A and Leg-B at
DC-bus voltage (Vdc/2), and Vaf and Vbf to one-fourth (Vdc/4), all Vdc/2 and Vdc/4, respectively. Hence, the corresponding load
the possible switching states and the resultant output voltages voltage Vab is Vdc/4. All other voltage vectors follow the same
of Leg-A are summarized in Table I. In the table, the logic notation rule.
values “0” and “1” represent the off-state and on-state of the
switch.

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  ic1  ( Sa 2  Sa3  Sb 2  Sb3 )ia / 2
tb ta tb ta tb ta tb
Vdc 3Vdc / 4 Vdc / 2 Vdc / 4 Vdc / 4 Vdc / 2 3Vdc / 4
Fig. 2. Voltage vectors of a single-phase 5-ANPC converter.
Accordingly, we can further divide all possible output voltage
vectors into 8 sections by the 25 voltage vectors. Specifically, for
Sector I, the output voltage satisfies 3Vdc/4< Vab ≤ Vdc; Sector II,
Vdc/2< Vab≤ 3Vdc/4; Sector III, Vdc/4< Vab≤ Vdc/2; Sector IV, 0<
Vab≤ Vdc/4; Sector V: -Vdc/4<Vab≤ 0; Sector VI, -Vdc/2<Vab≤-Vdc/4;
7) Sector VII, -Vdc/2 < Vab≤-3Vdc/4; and finally Sector VIII,
-3Vdc/4<Vab≤-Vdc. Therefore, for a given voltage vector Vab we
can conveniently determine which sector the voltage vector
belongs to. In turn, we can further calculate the associated duty
ratio times of ta and tb within each sampling cycle in derivation of
Eqs. (40) and (41) later in the paper.
As shown in Table I, the output voltage per leg can be
expressed as
Vao  Vdc (Sa1  Sa 2  Sa 3  Sa 4  2) / 4
 (1)
Vbo  Vdc (Sb1  Sb 2  Sb3  Sb 4  2) / 4
Thus, the output voltage of the converter can be obtained as
Vab  Vao  Vbo  Vdc (Sa1  Sa 2  Sa 3  Sa 4  Sb1
(2)
Sb 2  Sb 3  Sb 4 ) / 4
Based on the load inductance and resistance, the dynamic
output voltage equation can be described as
Vab  Vao  Vbo  L dia dt  Ria (3)
Similarly, we can derive the capacitor voltages and currents
to reveal how the switching states might affect the capacitor
voltage balancing. The dc-link and flying capacitor voltages in
Fig. 1 can be expressed as
 V (t )  V (0)  t i ( ) d / C
 cx cx 0 x x  1, 2
(4)
 t
Vyf (t )  Vy (0)   i yf ( ) d / C yf y  a, b
 0
The flying capacitor currents of Leg-A and Leg-B are
 iaf  ( Sa 3  Sa 4 )ia
 (5)
ibf  ( Sb 3  Sb 4 )ib  ( Sb3  Sb 4 )ia
Based on the switching states and the output current, the
neutral point current iN is
iN  Sa 2  Sa3 ia  Sb 2  Sb3 ib  ( Sa 2  Sa3  Sb 2  Sb3 )ia
(6)
Assume the dc-link input voltage keeps constant, iN can be
obtained as
 ic1  C (dVc1 / dt )
 where δVab(k) represents the quantization error and the error
ic 2  C ( dVc 2 / dt )  C ( d (Vdc  Vc1 )) / dt  C (dVc1 / dt )
i  i  i
 N c1 c 2
Combining (6) and (7), it can be derived as
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3
(8)

ic 2  ( Sa 2  Sa3  Sb 2  Sb3 )ia / 2
In the following, we use the sampling time Ts (assuming very
small) and Euler approximation to establish the predictive
models for the dc-link and flying capacitor voltages at the
ta tb  (k+1)th instant based on (4), (5), and (8). We have
Vcx (k  1)  Vcx (k )  Ts ( Sa 2  Sa 3  Sb 2  Sb 3 )ix / 2C x  1,2
Vdc 
 Vyf (k  1)  Vyf (k )  Ts ( Sa 3  Sa 4 )iy / C yf y  a, b
(9)
Using Euler discretization and referring to (3), the predictive
model of the output current at the (k+1)th instant can also be
obtained as
ia (k  1)  Ts (Vab (k )  Ria (k )) / L  ia (k ) (10)
Substituting (2) into (10), the output current at the (k+1)th
instant can be transformed into
ia (k  1)  Ts (Vdc (Sa1  Sa 2  Sa 3  Sa 4  Sb1  Sb 2
(11)
Sb 3  Sb 4 ) / 4  Ria (k )) / L  ia (k )
III. MPC ALGORITHMS
A. MPC Method with the Simplified Computation
For single-phase 5L-ANPC converters, there are three
control objectives - the first objective is to track the current
reference, the second target is to stabilize the flying capacitor
voltages, and the last is to balance the dc-link capacitor voltages.
The cost function of the proposed 5L-ANPC gc(k) is
constructed as
g c (k )  ia* ( k  1)  ia (k  1)  dc Vx* (k  1)  Vx ( k  1) 
(12)
 f Vyf* (k  1)  Vyf (k  1) x  1, 2; y  a, b
where λdc and λf are the weighting factors of the dc-link
capacitor voltage control and the flying capacitor voltage
control, respectively.
According to predictive models for the load current tracking
of (11) and the capacitor voltage balancing of (9), the control
goal is to select proper switching states to minimize the cost
function (12). The switching state selection is done in the
current sampling cycle and applied to the next cycle. For
conventional MPC methods, there will be 64 (82) switching
states to select from for the five predictive models to optimize
control objectives in every control cycle. Obviously, the
computation process becomes very complicated and
time-consuming. Furthermore, the conventional MPC methods
only consider applying one voltage vector for each control
cycle, resulting in large current ripples and none FSF control
for the load.
In this section, we present a simplified scheme using the
Lyapunov function for voltage sector selection aiming at
significantly reduced computation complexity. First let the
desired single-phase voltage of the 5L-ANPC be
Vab (k )  Vab -conv (k )   Vab (k ) (13)
(7)
should satisfy
 Vab (k )   (14)
where ε is a predetermined positive constant. The current error
is defined as
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ierror ( k  1)  ia* ( k  1)  ia ( k  1) (15) t a g a ( k )  tb g b ( k )

*  (23)
where ia (k+1) is the desired output or the reference current.  ta  tb  Ts
The discrete Lyapunov function is chosen to be
From (23), the duty ratios ta and tb can be obtained as
1
L(k)= ierror (k )  ierror (k ) 
T
(16) ta  g b ( k )Ts / ( g a ( k )  g b (k )) 0  ta  Ts
2  (24)
bt  g ( k )T / ( g ( k )  g ( k )) 0  tb  Ts
According to (16), the change rate of the Lyapunov function a s a b

can be obtained as C. Double-vector MPC Using the Current Slope

L(k)=L(k +1)-L(k ) This section shows the second double-vector MPC method,
= ierror (k  1)  ierror (k  1)  / 2  ierror (k )  ierror (k )  / 2 which utilizes slopes of the output current to determine the duty
T T

T (17) ratio time. From (10), the slopes of the output current of
 ia* ( k  1)  ia ( k  1)  ia* ( k  1)  ia ( k  1)  / 2 different voltage vectors can be expressed as
T di
 ia* (k )  ia (k )  ia* ( k )  ia (k )  / 2 f i  a Vab  Vi i  0,1  24 (25)
dt
To achieve zero steady-state error for tracking the current According to (25), the output current at the (k+1)th sampling
reference, the change rate of (17) must be negative. Thus, the time can be obtained as
following expression should be satisfied as ia ( k  1)  ia ( k )  fi Ts (26)
ia* ( k  1)  ia ( k  1)  0 (18)
where ia(k) is the initial value of the output current and Ts is the
Combining (10) and (18), the desired output voltage can be sampling time.
obtained as The symmetrical switching sequence is adopted here based on
Vab* (k )  L(ia* (k  1)  ia (k )) / Ts  Ria (k ) (19) the slope of the output current. Thus, the symmetrical switching
where i*a(k+1) is the output current reference at the (k+1)th sequence based on two voltage vectors is shown in Fig. 3.
sampling time. Applying Lagrange extrapolation, we have According to (26) and Fig. 3, the output current at the end of the
control cycle can be obtained as
ia* (k  1)  3ia* (k )  3ia* (k 1)  ia* (k  2) (20)
ia (k  1)  ia (k )  f1ta / 4  f 2 tb / 2  f1ta / 2  f 2 tb / 2
According to the above derivations, the cost function with 
reduced complexity can be defined as  f1ta / 4  ia (k )  f1ta  f 2 tb (27)
 t t T
g v ( k )  Vab* ( k )  Vab ( k )  dc Vcx* ( k  1)  Vcx ( k  1)   a b s
(21) ia
 f V yf* ( k  1)  V yf ( k  1) x  1, 2; y  a , b ia*
Based on (21), the simplified MPC method only needs to f2 f1 f2 f1
f1
calculate one time for the desired output voltage. As compared
to the conventional MPC method, (12) needs 64 times of
t
computation for the predictive current. Therefore, the ta / 4 tb / 2 ta / 2 tb / 2 ta / 4
computation efficiency of MPC based on Lyapunov function is Ts
k k 1
significantly improved. Fig. 3. Output current tracking for the symmetrical switching sequence.
B. Double-vector MPC Using the Current Cost Function To reduce the output current error at the end of the control
This section develops the double-vectors MPC method based cycle, the cost function is defined as
on two different current tracking algorithms. Both algorithms
g s ( k )  (ia* ( k  1)  ia ( k  1)) 2  (ia* (k  1)  ia ( k )  f1ta  f 2 tb ) 2
adopt two voltage vectors per control cycle to track the output
current. Thus, the output current ripple is reduced, and the FSF (28)
is realized. The first algorithm is to use the cost function of the To minimize the value of the cost function (28) to zero, the
output current, and the cost function is expressed as duty ratio times of the first and second voltage vectors should
satisfy as following:
g ( k )  ia* ( k  1)  ia ( k  1) (22)
 g s
Assuming the location of the output voltage reference V*ab(k)  t  0
is known in Fig. 2, we synthesize the output voltage reference  a
 (29)
using the two nearest voltage vectors. These two nearest  g s  0
voltage vectors, named as the first and second voltage vectors.  tb
Then, the duty ratio time for each selected vector is calculated Solving (29), ta and tb can be calculated as
accordingly. Assuming the voltage reference is located in  ia* (k  1)  ia (k )  f 2Ts
Section Ⅰ in Fig. 2, the nearest voltage vectors are V14 and V12 ta  0  ta  Ts
 f1  f 2 (30)
(or V13). The cost function for V14 is ga(k), and the cost function  t  T t
for V12 and V13 is the same, which is denoted as gb(k). The duty  b s a 0  tb  Ts
ratio time for each voltage vector is inverse proportional to the
D. Balancing Control of the DC-link and Flying Capacitor
value of cost function. In this paper, Ts is the control cycle, and Voltages
ta and tb are the duty ratio times for the first and second voltage Once the duty ratio times for two voltage vectors are
vector. The following equation can be derived as determined by (24) or (30), the next step is to select proper

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switching states among the redundant switching states. Taking TABLE Ⅱ

the voltage vector V10 as an example, the corresponding SWITCHING STATE SELECTION FOR CONTROLLING FLYING CAPACITOR
VOLTAGES UNDER DIFFERENT CONDITIONS
switching states for V10 are shown in Fig. 4. “3” and “1”
Leg Output voltage Working conditions Switching state
represent that Leg-A and Leg-B output voltages are Vdc/4 and
Leg-A -Vdc/4 (Vaf - Vdc/4)ia ≥0 SWa1
-Vdc/4, respectively. It has four switching states which are Leg-A -Vdc/4 (Vaf - Vdc/4)ia＜0 SWa2
SWa5SWb1, SWa5SWb2, SWa6SWb1, and SWa6SWb2. Therefore, Leg-A Vdc/4 (Vaf - Vdc/4)ia ≥0 SWa5
the flying capacitor and dc-link capacitor voltages can be Leg-A Vdc/4 (Vaf - Vdc/4)ia＜0 SWa6
controlled by selecting the proper switching states. Leg-B -Vdc/4 (Vbf - Vdc/4)ib ≥0 SWb1
To control the flying capacitor voltage, a function is Leg-B -Vdc/4 (Vbf - Vdc/4)ib＜0 SWb2
Leg-B Vdc/4 (Vbf - Vdc/4)ib ≥0 SWb5
constructed as: Leg-B Vdc/4 SWb6
(Vbf - Vdc/4)ib＜0
1
J x  C xf (Vxf  Vdc / 4) 2 x  a, b (31)
2 For the dc-link capacitor voltage control, the redundant
To stabilize the flying capacitor voltage, the derivative of (31) switching states can be found for the voltage level at -Vdc/4, 0,
should satisfy as: and Vdc/4. Take Leg-A as an example, the redundant switching
J x Vxf states are SWa1 and SWa2, SWa3 and SWa4, SWa5 and SWa6,
 C xf (Vxf  Vdc / 4) 0 x  a, b (32) respectively. Since SW3 and SW4 have the same impact on
t t dc-link capacitor voltages based on Table I, we can choose
either one to generate voltage level at 0. However, for -Vdc/4,
SWa1 does not change dc-link capacitor voltages while the
SWa2 will discharge Vc2 if ia>0. Thus, SWa2 will be selected if
Vc2 > Vdc/2 and ia>0. Otherwise, SWa1 is used to make the
neutral point current zero. As a result, the dc-link capacitor
voltages are actively controlled to Vdc/2. The same rules are
applied to SWa5 and SWa6 for the output voltage level at Vdc/4.
Fig. 5 illustrates the impacts of different switching states on
 

dc-link capacitor voltages based on the output current direction.

The symbol “↓” means the Vc2 will be discharged, and “↑” is the
Fig. 4. Corresponding switching states for the voltage vector V10. charging effect.
As shown in Fig. 1, the relationship between the flying
Current

capacitor voltage and current should be satisfied as followings:

Vxf 1
 ixf x  a, b (33)
t C xf
Substituting (5) and (33) into (32), it can be obtained as
(Vxf  Vdc / 4)( S x 3  S x 4 )ix  0 x  a, b (34)
As listed in Table I, it can be found as: 1) SWa0 and SWa7
have no influence on the dc-link and flying capacitor voltages.
2) SWa3 and SWa4 have no influence on the flying capacitor
voltages, but they exert the same impact on the dc-link
capacitor voltages. 3) SWa1 and SWa2, SWa5 and SWa6 have
different impacts on the dc-link and flying capacitor voltages,
which can be utilized to control the capacitor voltages. The
characteristic of switching states for Leg-B is the same with
Leg-A.
From Fig. 1 and Table I, it can be further found as follows: 1)
The flying capacitor voltage for each leg only depends on the
switching states for the same phase. In other words, the
switching states of Leg-B cannot affect the flying capacitor
voltage of the Leg-A. 2) The two legs share the common dc-link
voltages. Thus, dc-link capacitor voltages are related to the
switching states from both Leg-A and Leg-B.
Table Ⅱ shows the switching state selection to control flying
capacitor voltages under different conditions. Switching states
which satisfy the equation (34) are selected. Take Leg-A for
instance, suppose Leg-A output voltage is Vdc/4 and the output
current ia is positive, the switching state SWa5 is chosen when
Leg-A flying capacitor voltage Vaf is higher than Vdc/4.
Otherwise, the corresponding redundant switching state SWa6
will be utilized.
Fig. 5. Impact on the dc-link capacitor voltages for different switching states.
Based on rules aforementioned, we propose an integrated
scheme to balance the flying and dc-link capacitor voltages
together. Fig.6 shows the corresponding implementation
diagram for Leg-A, where ΔVf is the allowable fluctuation of
flying capacitor voltages. This paper sets ±5% of the base
capacitor voltage (50 V) as the boundary, which is ΔVf=2.5 V
[35].
As shown in Fig.6, the left block is the control scheme to
balance the flying capacitor voltage. The right block illustrates
the scheme to stabilize the dc-link capacitor voltages. “1” and
“3” mean the output voltages of Leg-A and Leg-B are -Vdc/4
and Vdc/4, respectively. First, the flying capacitor voltage is
controlled by utilizing respective redundant switching states
from each leg. Once the flying capacitor voltage is stabilized,
the dc-link capacitor voltages will also be controlled by
selecting the proper switching states. The same control scheme
is used for Leg-B of the converter.

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F. Control Delay Compensation and Overall Control Diagram

 
Vaf  Vdc / 4  V f
(Vaf  Vdc / 4)ia  0
(Vc 2  Vdc / 2)ia  0
There is a control delay when the proposed algorithm is
implemented by the digital signal processors (DSP). The
commanded voltage vectors at the (k)th instant will be applied at
the (k+1)th instant. Therefore, a two-step prediction is used to
compensate for the control delay [36], and the cost function for
the proposed MPC method is changed as (35),
 g ( k  1)  ia* ( k  2)  ia ( k  2)

 g s ( k  1)  (ia ( k  2)  ia ( k  2))  (ia ( k  2)  ia ( k  1)  f1ta  f 2tb )
* 2 * 2

Fig. 6. Voltage balancing scheme of the flying and dc-link capacitors for the
Leg-A.
E. Duty ratio times and voltage vector sequences
As Fig. 2 shows, there are many redundant voltage vectors
which generate the same output voltage. For example, when the
output voltage is Vdc/4, there are four redundant voltage vectors
denoted as V5(10), V6(21), V7(32) and V8(43). To further
improve the computation efficiency, only those redundant
voltage vectors with the capability of capacitor voltage control
are selected. Thus, Table III illustrates the voltage sequence for
the full-range output voltage based on different sectors. Fig. 7
shows the corresponding duty ratio times based on the selected
voltage vector sequence for all the sectors.
TABLE Ⅲ
(35)
According to (10), the predictive output current at the (k+2)th
instant is expressed as
ia (k  2)  Ts (Vab (k  1)  Ria (k  1)) / L  ia (k  1) (36)
where the predictive current ia(k+1) at the (k+1)th instant can be
obtained through (10). The output voltage Vab(k) can be
obtained based on the principal of voltage-second equilibrium.
It can be written as
Vab (k )  (Vab1 (k )ta  Vab 2 (k )tb ) / Ts (37)
where Vab1(k) and Vab2(k) are the output voltages of the selected
double voltage vectors in the previous control cycle.
Similarly, the desired output voltage at the (k+1)th instant can
also be obtained as
Vab* (k  1)  Ts (ia* (k  2)  ia (k  1)) / L  Ria (k  1) (38)
where i a(k+2) is the output current reference at the (k+2)th
*

VOLTAGE VECTOR SEQUENCES OF DIFFERENT SECTORS instant. It can be derived as

Sector Voltage vector sequences Sector Voltage vector sequences
Ⅰ 30-40-41-40-30 Ⅴ 12-22-23-22-12
ia* (k  2)  3ia* (k  1)  3ia* (k )  ia* (k 1) (39)
Ⅱ 30-31-41-31-30 Ⅵ 12-13-23-13-12 In terms of (24), the duty ratio times with control delay
Ⅲ 21-31-32-31-21 Ⅶ 03-13-14-13-03 compensation using output current cost function are obtained as
Ⅳ 21-22-32-22-21 Ⅷ 03-04-14-04-03
ta  gb ( k  1)Ts / ( g a (k  1)  gb ( k  1)) 0  ta  Ts
 (40)
V12 V14 V13 V14 V12 V12 V10 V13 V10 V12 tb  g a ( k  1)Ts / ( g a ( k  1)  gb ( k  1)) 0  tb  Ts
Similarly, for the proposed MPC using the output current
slope, the duty ratio times can be written as
 ia* (k  2)  ia ( k  1)  f 2Ts
t
a  0  ta  Ts
(a) (b)  f1  f 2 (41)
t  T t 0  tb  Ts
 b s a
V6 V10 V7 V10 V6 V6 V2 V7 V2 V6
To summarize all the control functions in the proposed
double-vector MPC method, the overall control diagram of the
single-phase 5L-ANPC converter is shown in Fig. 8.
P ib L
(c) (d)

Vc1 ic1 R
V16 V2 V17 V2 V16 V16 V20 V17 V20 V16 io ia
Vdc

Vc 2 ic 2 ia (k )
Sop (k  1)
N
(e) (f) Vc1 (k ) Vaf (k ) ia* (k  2)
Vbf (k )
Vc 2 (k ) ia (k )
V22 V20 V23 V20 V22 V22 V24 V23 V24 V22

Vab* (k +1)
ta  g b (k  1)Ts / ( g a (k  1)  gb (k  1)) ia* (k )

tb  g a (k  1)Ts / ( g a (k  1)  gb (k  1)) ia (k +1)
 ia* (k  2)  ia (k  1)  f 2Ts
ta 
 f1  f 2
(g) (h) 
ia* ( k  2)
Fig. 7. Voltage vector duty ratio times and voltage vector sequences. (a) Sector I.  tb  Ts  ta
(b) Sector II. (c) Sector III. (d) Sector IV. (e) Sector Ⅴ. (f) Sector Ⅵ. (g) Sector Fig. 8. Overall control diagram of the proposed MPC method with the control
Ⅶ. (h) Sector Ⅷ. delay compensation.

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IV. SIMULATED EVALUATION

[V]

[V]
TO verify the effectiveness of the proposed MPC method, a
5L-ANPC system is simulated in Matlab/Simulink. The

[A]

[A]
simulated parameters are listed in Table Ⅳ. In order to directly
transplant C-code program to DSPs, all MPC algorithms are
achieved by S-function of Matlab/Simulink. The two MPC

[V]

[V]
current tracking control algorithms, Algorithms 1 and 2, are
defined as following.
Algorithm 1: The algorithm uses the current cost function to
track the command current.

[V]

[V]
Algorithm 2: The algorithm uses the current slope to track
the command current.
TABLE Ⅳ
MAIN PARAMETERS
Parameter Description Simulation Experiment
Vdc DC-bus voltage 3600 V 200 V
C DC-link voltage capacitors 1000 μF 500 μF (a) (b)
Caf, Cbf Flying capacitors 500 μF 500 μF
L Filter inductance 3 mH 8 mH

[V]

[V]
R Load resistance 15 Ω 36 Ω
fs Sampling frequency 10 kHz 10 kHz

[A]

[A]
A. Evaluation of Steady-state Performance
Steady-state performance is evaluated by two cases as
following:
[V]

[V]
Case 1: The amplitude and the frequency of the output
current are set to 100 A and 50 Hz in the simulation, and 2 A
and 50 Hz in the experimental test.
[V]

[V]
Case 2: The amplitude and the frequency of the output
current are set to 200 A and 50 Hz in the simulation, and 4 A
and 50 Hz in the experimental test.
Fig. 9 displays the simulated results of output voltage Vab,
output current ia, flying capacitor voltages, dc-link capacitor
voltages and frequency spectrum of output current of the
5L-ANPC in Case 1 and Case 2. As seen in Fig. 9, it can be (c) (d)
clearly observed as : 1) The output voltage for two MPC Fig. 9. Steady-state simulated results. (a) Algorithm 1 in Case 1. (b) Algorithm
algorithms is a five-step sinusoidal output in Case 1, and a 2 in Case 1. (c) Algorithm 1 in Case 2. (d) Algorithm 2 in Case 2.

nine-step sinusoidal output in Case 2. The results are similar
compared with the conventional pulse width modulation
(PWM). 2) The output current presents high-quality sinusoidal
feature. Especially, its total harmonic distortions (THDs) are
1.31% and 0.71% for Algorithm 1 in Case 1 and Case 2,
respectively. And corresponding THDs for Algorithm 2 are
1.27% and 0.68%. 3) High-order harmonics of the output
current for the two MPC algorithms are mainly concentrated on
the two times of sampling frequency switching. It verifies that
the constant switching frequency control is achieved. 4)
Voltages across flying capacitors are well controlled around
900 V (Vdc/4) for two MPC algorithms, and the peak-peak
ripple is only about 30 V (3.3% of the rated voltage). It
illustrates that two MPC algorithms have strong capability in
controlling flying capacitor voltages. 5) DC-link upper and
lower capacitor voltages are balanced at 1800 V (Vdc/2), and the
peak-peak ripple is only 15 V (1.65% of the rated voltage). It
means that the proposed MPC algorithms can effectively
balance dc-link capacitor voltages. In addition, it can be clearly
found that the two MPC algorithms have very similar
steady-state performance, and Algorithm 2 is slightly better
than Algorithm 1 in the output current quality.
B. Evaluation of Imbalanced DC-link and Flying Capacitor
Voltages
To investigate the effectiveness of the proposed MPC
method in imbalanced dc-link and capacitor voltages, two cases
are evaluated as following:
Case 3: The imbalanced dc-link capacitor voltage with 125%
of the rated capacitor voltage is examined, and the amplitude
and the frequency of the output current are set to 200 A and 50
Hz.
Case 4: The imbalanced flying capacitor voltage of Leg-A
with 33% initial voltage deviation is examined, and the
amplitude and the frequency of the output current are given as
200 A and 50 Hz.
Fig. 10 shows simulated results for the two proposed MPC
algorithms in Case 3 and Case 4. It can be found that: 1) The
dc-link capacitor voltages can recover to the rated voltage when
the imbalanced condition happens. The recovery time is around
87 ms. 2) The similar phenomenon can be observed for the
flying capacitor voltage when the imbalanced condition occurs.
The recovery time is even faster within 20 ms. 3) The output
current THDs in Case 3 and Case 4 are very similar with Case 2
when the capacitor voltages are recovered to the rated value. 4)

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The two MPC algorithms have basically similar performance A. Execution Time
for the imbalanced conditions. Thus, results in Fig. 10 illustrate To compare the complexity of the proposed MPC method
that the two MPC algorithms have strong capability in actively using two current tracking algorithms, execution time in the
controlling dc-link and flying capacitor voltages under DSP is evaluated, and results are shown in Table V.
imbalanced conditions. TABLE V
EXECUTION TIME FOR ALGORITHMS
[V]

[V]
Execution time
Algorithms Measurement and FSF MPC Total
other tasks Calculation
[A]

[A]
Algorithm 1 6.5 µs 5.2µs 11.7µs
Algorithm 2 6.5 µs 8.2µs 14.7µs
The total execution time is divided into two parts. The first
[V]

[V]

part is the measurement and initialization, including the A/D

sampling, parameters setting, system protection, and other
tasks. The second part is the execution time to realize the
double-vector MPC algorithm. Table V shows that the total
[V]

[V]

execution time of the proposed MPC method using Algorithm 1

and Algorithm 2 is very small. Compared with the sampling
(a) (b) period (100 µs) per control cycle, their execution times are less
than 15%. Algorithm 2 has a relatively longer execution time
[V]

[V]

than Algorithm 1. This is because the calculation of current

slopes needs more steps than the current cost function. Thus,
the proposed double-vector MPC method using current
[A]

[A]

tracking algorithm presents fast and efficient computation

capability.
[V]

[V]

B. Steady-state and Dynamic Results

The proposed double-vector MPC method is extensively
examined under testing conditions, as shown below.
Case 5: The amplitude and the frequency of the output
[V]

[V]

current are set to 2 A and 5 Hz.

Case 6: The amplitude and the frequency of the output
(c) (d) current are given 4 A and 5 Hz.
Fig. 10. Simulated results of imbalanced dc-link and flying capacitor voltages. Case 7: The amplitude of the output current is controlled in a
(a) Algorithm 1 in Case 3. (b) Algorithm 2 in Case 3. (c) Algorithm 1 in Case step change from 2 A to 4 A with frequency kept at 50 Hz.
4. (d) Algorithm 2 in Case 4.
Case 8: The frequency of the output current is controlled in a
V. EXPERIMENTAL EVALUATION step change from 25 Hz to 50 Hz with current amplitude kept at
To verify the feasibility and effectiveness of the proposed 4 A.
MPC method, an experimental platform of a 5L-ANPC is set up Figs. 12 to Fig. 15 show the steady-state performance of the
as shown in Fig. 11. The 32-bit floating DSP TMS320F28337D proposed MPC method using two current tracking algorithms.
The high-frequency operation (50 Hz) is conducted in Cases 1
is utilized for implementing MPC algorithms, and the field
and 2, while the low-frequency operation (5 Hz) in Cases 5 and
programmable gate array (FPGA) Cyclone
6. Vab, ia, Vaf and Vc1 are the output voltage, output current,
ⅣEP4CE115F29C7N is used for implementing PWM signal
Leg-A flying capacitor voltage, and the dc-link upper capacitor
generation. The main experimental parameters are listed in voltage respectively. Fast Fourier Transform (FFT) is
Table IV. performed in each case and results shown accordingly in the
figures.
The summarized steady-state experimental results of the
measured fundamental current amplitude Imf and the total
harmonic distortion (THD) of output current under different
conditions are listed in Table Ⅵ.
  TABLE Ⅵ
STEADY-STATE EXPERIMENTAL RESULTS
Algorithms Case 1 Case 2
Imf THD Imf THD
Algorithm 1 1.981 A 5.48% 3.921 A 2.76%
  Algorithm 2 1.983 A 5.21% 3.935 A 2.65%
Algorithms Case 5 Case 6
Imf THD Imf THD
Algorithm 1 1.969 A 5.55% 3.923 A 2.93%
Fig. 11. Experimental platform of the 5L-ANPC converter. Algorithm 2 1.972 A 5.46% 3.927 A 2.90%

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(c) (d)
Fig. 15. Steady-state experimental waveforms in Case 6. (a) Algorithm 1. (b)
Algorithm 2. (c) FFT of Algorithm 1. (d) FFT of Algorithm 2.
(a) (b) From the steady-state experimental results, it is clearly
demonstrated that: 1) The flying capacitor voltage is stabilized
at 50 V (Vdc/4) and the dc-link upper capacitor voltage well
balanced at 100 V (Vdc/2) for both algorithms. The peak-peak
ripples of the flying and dc-link capacitor voltages are always
less than 5 V. 2) High-order harmonics of the output current for
(c) (d) the two current tracking algorithms are mainly concentrated on
Fig. 12. Steady-state experimental waveforms in Case 1. (a) Algorithm 1. (b) the two times of sampling frequency switching due to two times
Algorithm 2. (c) FFT of Algorithm 1. (d) FFT of Algorithm 2. of output voltage changes in every sampling period. The
aforementioned steady-state experimental results are obtained
based on one-step MPC. In order to further improve the
steady-state performance for the proposed MPC algorithm,
multi-step MPC is considered as a new choice [37]. However,
multi-step MPC will greatly increase computational burden.
Therefore, multi-step MPC with FSF and reducing
computational burden will be further studied in the future.
Figs. 16 and 17 show the dynamic performance of the
(a) (b) proposed MPC method using Algorithms 1 and 2. In the
experimental testing, a step change of the current is applied in
Case 7, and frequency Case 8. From experimental results, it is
evident that both algorithms have excellent dynamic
performance with a responding time less than 1 ms to the
command in a step change of amplitude/frequency. Also
(c) (d) evident is that during the dynamic changes to the output current
Fig. 13. Steady-state experimental waveforms in Case 2. (a) Algorithm 1. (b)
amplitude or frequency, all capacitor voltages are well
Algorithm 2. (c) FFT of Algorithm 1. (d) FFT of Algorithm 2.
balanced.

(a) (b) (a) (b)

Fig. 16. Dynamic experimental waveforms In Case 7. (a) Agorithm 1. (b)
Algorithm 2.

(c) (d)
Fig. 14. Steady-state experimental waveforms in Case 5. (a) Algorithm 1. (b)
Algorithm 2. (c) FFT of Algorithm 1. (d) FFT of Algorithm 2.

(a) (b)
Fig. 17. Dynamic experimental waveforms in Case 8. (a) Algorithm 1. (b)
Algorithm 2.

V. CONCLUSIONS
In the paper, a double-vector MPC method with two current
tracking algorithms is presented for single-phase 5L-ANPC
(a) (b)
converters. Investigated by theoretical analysis and validated by

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extensive experimental results, the proposed MPC method
shows salient advantages:
1) Selection of voltage vectors is reduced from 25 to 2
compared to the conventional MPC method, resulting in
dramatically improved computation efficiency.
2) Fixed switching frequency control is achieved to facilitate
the converter output filter design.
3) Accurate and fast current tracking achieved ensures the
output current with much reduced harmonics distortion in both
steady-state and dynamic conditions.
4) Effective capacitor voltage balancing is achieved for both
high and low output frequencies, with no instability issue during
a step change to the output current amplitude and frequency.
We also made it evident that both current tracking algorithms,
the current cost function and the current slope, work well for the
MPC method. Compared with the current tracking algorithm
using the current cost function, the one using the current slope
has a bit longer execution time but lower current harmonics. We
conclude that the presented double-vector MPC method is
successfully applied to a 5L-ANPC with efficient computation,
fixed frequency switching, high-quality output current, and
satisfactory capacitor voltage balancing.
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IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION 11

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Yong Yang (M’15) received the B.S. degree in
automation from Xiangtan University, Xiangtan, China,
in 2003, the M.S. degree in Electrical Engineering from
Guizhou University, Guiyang, China, in 2006, and the
Ph.D. degree in Electrical Engineering from Shanghai
University, Shanghai, China, in 2010.
He is currently an associate professor with the
School of Rail Transportation, Soochow University.
From December 2017 to December 2018, he was a
Visiting Scholar with Center for High Performance Power Electronics (CHPPE)
of The Ohio State University, Columbus, USA. His current research interests
include model predictive control in power electronic converters, distributed
energy resource interfacing and high-performance motor drive control.
Jianyu Pan (S’14-M’19) received his B.S. and M.S.
degrees from Chongqing University, Chongqing, China,
in 2011, and 2014, respectively, and the Ph.D. degree
from The Ohio State University, Columbus, OH, USA,
in 2019, all in electrical engineering. Currently, he is an
assistant professor with the School of Electrical
Engineering, Chongqing University, Chongqing, China.
His main research interests include power electronic
converters, control of variable speed drives, application
of wide band gap semiconductors, and high-voltage engineering.
Zhiwei Zhang (M’18) received the Ph.D. degree in
Electrical Engineering from Huazhong University of
Science and Technology, Wuhan, China, in 2016. He is
currently a visiting scholar at the Department of
Electrical and Computer Engineering, The Ohio State
University, Columbus, OH, USA.
His current research interests include design and
analysis of high-performance electric machines,
variable-speed AC drives, transportation electrification,
and renewable energy conversion systems.
Ziwei Ke (S’14) received the B.S. degree from the
Zhejiang University of Technology, Hangzhou, China,
in 2012, the M.Sc. degree from Oregon State
University, Corvallis, OR, USA, in 2015, and the Ph.D.
degree from The Ohio State University, Columbus, OH,
USA, in electrical engineering, in 2019.
His research interests include electric machine
control, power electronics, embedded system hardware
design, and software programming.
Longya Xu (F’04) received his M.S. and Ph.D.
degrees from the University of Wisconsin-Madison, in
1986 and 1990 both in Electrical Engineering. He is
presently a professor and director of Center for High
Performance Power Electronics at The Ohio State
University. His research interests include design and
control of novel electric machines, power electronics,
and digital technology for electrified transportation
and renewable energy systems. Dr. Xu is an IEEE
Fellow and he has received several IEEE prestigious awards, including the
“First Prize Paper Award” 1992 from Industry Drive Committee IEEE/IAS,
“Best Transaction Paper Award” 2013 and “Outstanding Achievement Award”
2014, the highest society award, from IEEE Industry Application Society. Dr.
Xu is the recipient of the “Nikola Tesla Award” for his outstanding
contributions to the generation and utilization of electric power.
Dr. Xu has served as the chairperson of Electric Machine Committee of
IEEE/IAS and an Associate Editor of IEEE Transactions on Power Electronics
over the past two decades. Dr. Xu was a member-at-large on IEEE/IAS
Executive Board and the Conference Co-Chair for IEEE Transportation
Electrification Conference and Expo, AP 2014, 2016 and 2019.

Huiqing Wen (M’13-SM’17) received his B.S. and M.S.

degrees in Electrical Engineering from Zhejiang
University, Hangzhou, China, in 2002 and 2006,
respectively; and his Ph.D. degree in Electrical
Engineering from the Chinese Academy of Sciences,
Beijing, China, in 2009. From 2009 to 2010, he was an
Electrical Engineer working in the Research and
Development Center, GE (China) Co., Ltd., Shanghai,
China. From 2010 to 2011, he was an Engineer at the
China Coal Research Institute, Beijing, China. From
2011 to 2012, he was a Postdoctoral Fellow at the Masdar
Institute of Science and Technology, Abu Dhabi, United Arab Emirates.
He is presently working as an Associate Professor at the Xi’an
Jiaotong-Liverpool University, Suzhou, China. His current research interests
include bidirectional DC-DC converters, power electronics in flexible AC
transmission applications, electrical vehicles, and high-power, three-level
electrical driving systems.

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