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1. General description
The 74LVC2G08 provides a 2-input AND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is powered
down.
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC2G08DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
74LVC2G08DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74LVC2G08GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 x 1.95 x 0.5 mm
74LVC2G08GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1089
8 terminals; body 1.35 x 1 x 0.5 mm
74LVC2G08GM -40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads; SOT902-2
8 terminals; body 1.6 x 1.6 x 0.5 mm
74LVC2G08GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1116
8 terminals; body 1.2 x 1.0 x 0.35 mm
74LVC2G08GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1203
8 terminals; body 1.35 x 1.0 x 0.35 mm
74LVC2G08GX -40 °C to +125 °C X2SON8 plastic thermal enhanced extremely thin small outline SOT1233
package; no leads; 8 terminals; body 1.35 x 0.8 x 0.35 mm
4. Marking
Table 2. Marking codes
Type number Marking code[1]
74LVC2G08DP V08
74LVC2G08DC V08
74LVC2G08GT V08
74LVC2G08GF VE
74LVC2G08GM V08
74LVC2G08GN VE
74LVC2G08GS VE
74LVC2G08GX VE
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
&
1A
1Y
1B
A
2A
2Y & Y
2B
B
001aah788 001aah789 mna221
Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate)
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6. Pinning information
6.1. Pinning
74LVC2G08
1A 1 8 VCC
1B 2 7 1Y
74LVC2G08
2Y 3 6 2B
1A 1 8 VCC
1B 2 7 1Y GND 4 5 2A
2Y 3 6 2B
001aae982
GND 4 5 2A
Transparent top view
001aae981
Fig. 5. Pin configuration SOT833-1, SOT1089, SOT1116
Fig. 4. Pin configuration SOT505-2 and SOT765-1 and SOT1203
74LVC2G08
terminal 1
VCC
index area
74LVC2G08
8
1Y 1 7 1A
1A 1 7 1Y
8
2B 2 6 1B
VCC
1B 2 6 2B
2A 3 5 2Y 4
4
GND
2Y 3 5 2A
GND
001aae983
aaa-023982
Transparent top view Transparent top view
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input Output
nA nB nY
L X L
X L L
H H H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +6.5 V
VI input voltage [1] -0.5 +6.5 V
VO output voltage Active mode [1] -0.5 VCC + 0.5 V
Power-down mode [1] -0.5 +6.5 V
IIK input clamping current VI < 0 V -50 - mA
IOK output clamping current VO < 0 V or VO > VCC - ±50 mA
IO output current VO = 0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 250 mW
Tamb = -40 °C to +125 °C [3] - 300 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT505-2 (TSSOP8) packages: Ptot derates linearly with 4.6 mW/K above 96 °C.
For SOT765-1 (VSSOP8) packages: Ptot derates linearly with 4.9 mW/K above 99 °C.
For SOT833-1 (XSON8) packages: Ptot derates linearly with 3.1 mW/K above 68 °C.
For SOT1089 (XSON8) packages: Ptot derates linearly with 4.0 mW/K above 88 °C.
For SOT902-2 (XQFN8) packages: Ptot derates linearly with 4.1 mW/K above 89 °C.
For SOT1116 (XSON8) packages: Ptot derates linearly with 4.2 mW/K above 90 °C.
For SOT1203 (XSON8) packages: Ptot derates linearly with 3.6 mW/K above 81 °C.
[3] For SOT1233 (X2SON8) packages: Ptot derates linearly with 7.7 mW/K above 118 °C.
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
∑(CL x VCC x fo) = sum of outputs.
nA, nB input VM
GND
t PHL t PLH
VOH
nY output VM
VOL
mna224
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tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VEXT
VCC
RL
VI VO
PULSE
DUT
GENERATOR
RT CL RL
001aae235
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D E A
X
y HE v M A
8 5
A2
A (A3)
A1
pin 1 index
θ
Lp
1 4 detail X
e w M
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
D E A
X
y HE v A
8 5
A2
A
A1 (A3)
pin 1 index
θ
Lp
1 4 detail X L
e w
bp
0 5 mm
scale
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1
b
1 2 3 4
4×
L (2)
L1
8 7 6 5
e1 e1 e1
8× A
(2)
A1
terminal 1
index area
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A(1) A1 b D E e e1 L L1
max max
0.25 2.0 1.05 0.35 0.40
mm 0.5 0.04 0.6 0.5
0.17 1.9 0.95 0.27 0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
07-11-14
SOT833-1 --- MO-252 ---
07-12-07
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terminal 1
index area
D A
A1
detail X
(4×)(2)
e
L
(8×)(2)
b 4 5
e1
1 8
terminal 1
index area L1 X
0 0.5 1 mm
Dimensions scale
Unit A(1) A1 b D E e e1 L L1
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D B A
terminal 1
index area
E A
A1
detail X
e
C
v C A B
b
w C y1 C y
4
3 5
e1
terminal 1
index area 2 6
L 1 7
8
metal area
L2 not for soldering
L k L3
L1
0 1 2 mm
Dimensions scale
Unit(1) A A1 b D E e e1 k L L1 L2 L3 v w y y1
max 0.5 0.05 0.25 1.65 1.65 0.35 0.15 0.25 0.35
mm nom 0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.20 0.30 0.1 0.05 0.05 0.05
min 0.00 0.15 1.55 1.55 0.2 0.25 0.05 0.15 0.25
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot902-2_po
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b
1 2 3 4 (4×)(2)
L1 L
8 7 6 5
e1 e1 e1
(8×)(2)
A1 A
terminal 1
index area
0 0.5 1 mm
Dimensions scale
Unit A(1) A1 b D E e e1 L L1
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b
1 2 3 4 (4×)(2)
L1 L
8 7 6 5
e1 e1 e1
(8×)(2)
A1 A
terminal 1
index area
0 0.5 1 mm
Dimensions scale
Unit A(1) A1 b D E e e1 L L1
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
X2SON8: plastic thermal enhanced extremely thin small outline package; no leads;
8 terminals; body 1.35 x 0.8 x 0.35 mm SOT1233
A D B
A1
detail X
pin 1
index area
e e C
v C A B
b y
(6x) w C
1 2 3
pin 1
index area 8 4
Dh
L
(6x)
7 6 5
b1
y1 C
(2x)
e1
0 1 mm
scale
Dimensions (mm are the original dimensions)
Unit A A1 b b1 D Dh E e e1 L v w y y1
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
13. Abbreviations
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
15. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
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Quick reference data — The Quick reference data is an extract of the
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document, and as such is not complete, exhaustive or legally binding.
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Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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of an Nexperia product can reasonably be expected to result in personal
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Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking.......................................................................... 2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 3
7. Functional description................................................. 4
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................5
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 7
12. Package outline.......................................................... 9
13. Abbreviations............................................................ 17
14. Revision history........................................................17
15. Legal information......................................................18
74LVC2G08 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved