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SAP 1 - Architecture

This is an organized bus computer where in all data that is being transferred is
passed through a common data bus, which is sometimes referred to as an information
superhighway. Everything that comes in and out from all the registers pass through
it.

Wbus means - Wired (can be addresses or data)

The selection of the devices from the address is sent through a common address bus.
depends upon the generated control signal that come from the given data. the data
is being inputed or written into a given register will be read from a particilar
register. every register that we have, the purpose is to store a single data. kapag
may laman na si register or address, when a new data comes along, the old data on
the registers will be overwritten

B register - auxillary register, tumatanggap ng pangalang iniistore na dta

Register A - accumulator A

output register receives the answers and data to be displayed in the inary display

Instruction register holds the instructions

memory 16x8 - static ram 16 bytes * buts

Input & MAR - holds the input, memory address register

All registers in the WBus are tristate. Why? Place an important role in dealing
with the bus organization of computer systems

three terminal device, input output control

it can be available as active high or active low modes that can be used in the
output register which are all connected to a common data bus

the three states that is connected allows the transfer of data, exchanging of
states will allow the from one register to another

For this reason, cannot be driven out by the other register.

RAM 16 bytes
address lines are from 0000H to 1111H 0H - FH

MAR - store memory address, generates the address para alam nila kung san pupunta
ung instruction or san ipapasa

for SAP1, only has control and Arithmitic unit, no logic unit. Ang kaya lang gawin
is add and substracts. 5 instructions sets for sap (LDA, ADD, SUBTRACT, OUT, HALT
(Halt/Stop) NO-operation)

6 machine states

T1 - T3 - Fetch of data
T4 - T6 - execution
The output is very simple. SAP1 can only cater 16 instructions. This include the
data. only holds 8 bits per address

The first 4 bits opcode, last 4 bits operand

Machine Language
Assembly Language

BUFFER REGISTER
- made of flip flops, stores binary , stores data. mag loload ng data at mag reread
lang ng data. buffer registers helps the control signal. The one that controls the
SAP is the control sequencer. Remember, in every pulse, upon the arrive of the
clock edge, we generating the signal, doon pa lang nag sstart mag work si flip
flop. Since lahat ng itoay flip flop, kailangan natin ng control sequencer, para
hindi magulo, at para mag work ung sap1. counter is a special type of register that
is only intended to count the number of operations or instructions.

END AT 21:18

DISCRETE COMPONENTS
SAP1 is made up of IC. Integrated Circuitry. One integrated component composed of
several discrete components. Minimum of 4, maximum of 16.

Program Counter
1. counting purposes. Binary address ang kinacount. Kung pang ilang 1 macro
instructions, holds about 2 address lines at the same time (can be one address and
one dta. Nagbibigay ng signal pag nagbigay na ng first clock edge.
from 0000 up to 1111.
part of the control unit - kapag nakapag receive na ng clock edge. It will be
sending the signal towards the input NMAR.

0000H, will go to input N Mar. it will generate an address where the first
instruction will be placed. for example, the first instruction is LDA to address
8H. after generating the address, both
0000 and 1000 will be sent to the RAM. 8 bits composed of the input and the address
generated by N MAR. babalik sa Wbus then ipapasok sa instruction register.
8 bits ang papasok sa instruction register. mahahati sya, ung upper nibble
(instruction) ay mapupunta sa controller sequencer.

0000 upper nibble


1000 - lower nibble

yung lower nibble, pupunta ulit kay inpunt NMAR.

Then next instruction from the program counter 0001, puputa kay input NMAR, since
may address pa rin 1000, un na ung katandem nya, pupunta sya kay accumulator.

Primary Register (Accumulator/REgister A)


Holds the immediate answer and the first data.

B Register (Auxillary Input)

+1, next step, program counter

pag may laman na parehas si si register A and register B. mag sesend ngayon yung
naiwan doon kay controller sequencer ng isa control word kung ano ang gagawin
operation, kung add or subtract (arithmitic unit) Adder Subtracter Su or Eu. if
high ung EU, add pag high ung SU, subtract (isa lang ang pwede mag high).

Mapupunta ung saagot kay accumulator: mapapalitan ung current na laman nito into A
= A+B or A-B. This will be operate. For example ang laman ng
For example ang laman na data ng 8H is 0001 and ang laman ng 9H is AH, then ang nag
high is ung adder, then ang bagong magiging value ni Accumulator (with address 8H)
is BH (AH+1H).

What if gusto ko mag out put sa binary display?

Mag gegenerate ng instruction again si program counter, pupunta sa nmar, mag


bibigay ng address si nmar, ireread ni ram, mapapaunta sa unstruction register,
upper nibble pupunta sa controller sequencer, maglalabas si contrller sequencyer ng
instruction lower nibble pupunta ulit kay NMAR, then after nun program counter,
tapos fefetch ulit kay inpunt NMAR ung address, then after pag kalabas sa RAM,
matic na pupunta na sa output register. Susunduin ang laman ni accumulator. copies
the content in one register.

Input and MAR


2 entities in 2 registers
input, ung sumasalo ng dta na nagenerate ni counter. Input and MAR are always
latched together, naghihiwalay lang sya pag

RAM
temporary repository.
bakit sa address hinahanap ungdata.

Instruction Register - generates the control signal


12 control signals

controller sequencer
- mag gegenerate ng control word, clock will send (normally low) low value to

control word

Accumulator
first input and immediate answer

complementary addition

LDA 9H - It is not the value that is loaded to the accumulator but the address
where the dta is stored. LDA 9H - 9H is the address in which the data is stored.
the data of 9H is AH.

ADD A = A + B,

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