PE 1EEPC353 Laboratory

Annasaheb Dange College of Engineering
& Technology, Ashta

(An Autonomous Institute)
Department of Electrical Engineering
[1EEPC353] Power Electronics Laboratory
Class: - T. Y. B. Tech.
Name: - Prof. Vishal B. Patil

(Designation: - Asst. Professor)
Academic Year: 2021-22
INSTRUCTIONS TO THE CANDIDATE
SAFETY:
You are doing experiments in Power Electronics lab with high voltage and high current
electric power. It may cause even a fatal or loss of energy of your body system. To avoid this please
keep in mind the followings
In case of any wrong observations, you have to SWITCH OFF the power supply related with
it. You have to tuck in your shirts or wear an overcoat. You have to wear shoes compulsorily and
stand on mats made by insulating materials to electrically isolate your body from the earth.
ATTENDANCE:
Attendance for the laboratory practice is mandatory. If you absent for a lab practice, you have
to face the strict action. Laboratory should be treated as temple, which will decide your life. So don’t
fail to make your presence with your record notebook having completed experiments, observation
with completed experiments, day’s experiment particulars with required knowledge about it and
stationeries.
RECORD:
Record shows the performance of equipment and yourself. It will be very useful for future
reference. So keep it as follows.
Write neatly; as they have to be preserved enter the readings in the record notebook those have
been written in your observation. Units should be written for all quantities.
Draw necessary graphs and complete the record before coming to the next lab class. Don’t
forget to write the theory with precaution and inference of each experiment.
MAY I HELP YOU
1. Device ratings should be noted.

2. Moving coil meters should be used for DC measurements.
3. Moving iron meters should be used for AC measurements.
4. Use isolated supply for the CRO.
5. Use attenuation probe for high voltage measurements in CRO.
-2-
INDEX
Performed Submitted
Sr. No. Title Page No.
Date Date
1. I-V characteristics of SCR
2. Output characteristics. of MOSFET and IGBT
3. SCR gate triggering methods.
4. Single Phase Semi- Converter.
5. Single Phase Full- Converter.
6. Three Phase Full Converter.
7. DC chopper using Power MOSFET
8. To study of single bridge inverter.
*Simulation of Three 1 ph, 3 ph, AC TO DC

9.
Uncontrolled rectifiers.
10. Step down MOSFET based chopper
-3-
SantDnyaneshwarShikshanSanstha’s
Annasaheb Dange College of Engineering and Technology,
Ashta
Course: [1EEPC353] Power Electronics Laboratory
Name:
Class: Div: Batch
Title of the
Experiment:
Date of Conduction: Date of Submission:
Grade/CAS Marks: Signature of Course Instructor/Teacher
-4-
Experiment No. 01
Title:
To understand and plot the I-V characteristics of SCR and to determine the latching current, holding
current and the forward break over voltage.
Apparatus:
Experimental kit, DC power supply, DC milli-ammeters, DC voltmeters etc..
Theory:
Silicon Controlled Rectifier (SCR):
1. SCR is a three terminal, three junctions, 4-layer, p-n-p-n semiconductor device that allows the current
to flow in one direction only.
2. It is the member of the thyristor family.
Structure:
-5-
Forward break over voltage
1. It is the forward anode voltage at which SCR switches ON and begins to conduct, when gate current
is zero.
2. SCR is in the Forward Blocking Region when the forward anode voltage is less than V FBO and little
forward leakage current flows through SCR.
Gate Control
1. The gate terminal controls the forward break over voltage and hence the forward bias level at which
the SCR is turned ON.
2. The higher the value of the gate current, the lower is the anode voltage requires turning SCR ON.
Once the SCR is turned ON, gate looses control and its removal does not affect the conduction of the
SCR.
3. The anode voltage and the external load then determine the anode current, solely.
Latching Current
Latching current is the forward anode current requires turning SCR ON. SCR remains OFF as long as
the anode current is less than the latching current.
-6-
Holding Current:
1. Holding Current is the minimum forward anode current required to be maintained to keep SCR ON,
once it is conducting.
2. If SCR is conducting and if the anode current falls below the holding level, then it turns OFF.
I-V Characteristics of SCR:
1. I-V characteristic is the plot, which shows the variation of anode current w. r. t. Anode voltage at
different biasing condition.
2. Reverse characteristics - Small leakage current called reverse blocking current flows.
3. When the SCR is reversed biased (anode is negative w.r.t. cathode). At peak reverse voltage, reverse
current increases sharply. This is called reverse break over or reverse avalanche region.
4. Forward Characteristics - Small Forward leakage current flows when SCR is forward biased (anode
is positive w. r. t. cathode) and anode voltage is less than forward break over voltage. When Anode
current exceeds latching current, SCR switches ON. Anode current increases sharply and anode
voltage drops. The gate current controls the forward break over voltage.
-7-
Circuit Diagram:
Procedure:
(A) For finding Forward break over voltage:
1. Make connections as shown in circuit diagram (a)
2. Keep gate open
3. Increase anode voltage gradually. Observe change in anode current and voltage.
4. Stop increasing anode voltage as soon as anode current increases sharply and voltage drops.
5. Record the anode voltage just before it drops.
Note: Reduce anode voltage, immediately after SCR is turned ON to avoid damage to it.
(B) Measurement of Latching current:

1. Make connections as shown in diagram (b).
2. Apply suitable anode voltage less than VFBO
3. Keep pot P1 at minimum resistance position.
4. Gradually increase gate voltage till SCR is turned ON.
5. Note gate voltage and gate current required to turn SCR ON.
6. Reduce anode voltage to turn SCR OFF.
7. Adjust gate voltage slightly higher than noted in step 5
8. Set pot P1 at maximum resistance position.
9. Increase anode current gradually till SCR is turned ON.
10. Record anode current just before it is turned ON.
(C) Measurement of Holding current:

1. Connect as per circuit diagram (b)
2. Apply suitable anode voltage less than VFBO
3. Keep pot P1 at minimum resistance position
4. Gradually increase gate voltage till SCR is turned ON.
5. Open gate circuit by opening switch S1.
6. Gradually decrease anode current, by adjusting pot P1, till SCR is turned OFF.
7. Record anode current, just before it is turned OFF.
(D) I - V characteristics of SCR.

1. Make connections as per circuit diagram (b).
2. Adjust anode voltage to minimum.
3. Adjust pot P1 at minimum resistance position.
4. Adjust gate current to 1 mA
5. Increase anode voltage gradually till SCR is turned ON. Record anode voltage6. Reduce anode
voltage to minimum to turn SCR Off.
7. Repeat Step 5 and 6 for Ig =…..mA & Ig = ……mA, respectively and anode current just before
and after break over.
-8-
Observations:
A. Forward Break over voltage, VFBO =...........Volts.
B. Latching current, IL = ............mA
C. Holding current, IH =.............mA
Ig1 (mA) =……. Ig2 =…….mA

Sr. No. VA(Volt) IA (mA) VA(Volt) IA (mA)
1.
2.
3.
4.
5.
6.
7.
8.
Result:
a. Break over voltage at lg1 = …. …mA is ............................................. volts.

b. Break over voltage at lg2 =……. mA is .............................................. volts.
c. Break over voltage at lg3 =…….. mA is ............................................. volts.
d. Break over voltage at lg4=………mA is .............................................. volts.
e. Before forward break over............................. (large/small) leakage current flows.
f. After break over, the anode current...……………………..(increases/decreases)
g. After Break over the anode voltage............................. (increases/ decreases).
Conclusion:
Questions:
1. State difference between p-n junction diode & SCR.
2. How the gate terminal in SCR can be used to obtain controlled rectification?
3. State the significance of the holding current.
4. State the significance of the latching current.
5. State the function of gate terminal in SCR.
-9-
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 10 -
Experiment No: - 02
Aim: - To Study and plot output characteristics of MOSFET and IGBT.
Apparatus: - Experimental kit, Patch chord, multimeter etc.
Theory:-
Insulated Gate Bi-polar Junction Transistor (IGBT):
An IGBT Insulated Gate Bipolar Transistor combines advantages of both BJT and MOSFET. An
IGBT have high input impedance like MOSFET and low on state conduction loses like BJT.
It has three terminals namely Gate, Collector and Emitter instead of Gate, Drain and Source as in
MOSFET. The parameters and their symbols are similar to that of MOSFET except that the subscript D and S
have been changed. The current rating of single IGBT can be up to 400A, 1200V and switching frequency can
be up to 20 KHz. An IGBT is inherently faster than a BJT. The structure of IGBT is quite similar to MOSFET.
The IGBT conducts in two modes reverse blocking mode and forward blocking mode. If gate – emitter voltage
applied is of sufficient magnitude to surface the base region under gate, device switches to its positive forward
conduction state and current can flow from collector N-region to base N- region.
Constructional structure
Symbol Photograph
- 11 -
Fig: Static characteristics of an IGBT (a) Output characteristics; (b) Transfer characteristics
The V-I characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear qualitatively
similar to those of a logic level BJT except that the controlling parameter is not a base current but the
gate-emitter voltage.
When the gate emitter voltage is below the threshold voltage only a very small leakage current
flows though the device while the collector – emitter voltage almost equals the supply voltage (point
C in Fig (a)). The device, under this condition is said to be operating in the cut off region. The
maximum forward voltage the device can withstand in this mode (marked V in Fig (a)) is
CES
determined by the avalanche break down voltage of the body – drain p-n junction. Unlike a BJT,
however, this break down voltage is independent of the collector current as shown in Fig.(a). IGBTs
of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut
off mode. However, for Punch through IGBTs VRM is negligible (only a few tens of volts) due the
presence of the heavily doped n+ drain buffer layer.
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the
active region of operation. In this mode, the collector current ic is determined by the transfer
characteristics of the device as shown in Fig (b). This characteristic is qualitatively similar to that of
a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to
(V – v ) is called the forward transconductance (g ) of the device and is an important parameter
ge ge(th) fs
in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the
external load line ABC as shown in Fig (a).
As the gate emitter voltage is increased further i also increases and for a given load resistance
c
(R ) v decreases. At one point v becomes less than VGE – v (th). Under this condition the driving
L CE CE GE
MOSFET part of the IGBT enters into the ohmic region and drives the output p-n-p transistor to
saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode
the voltage drop across the IGBT remains almost constant reducing only slightly with increasing v gE.
- 12 -
Metal-Oxide Semiconductor Field Effect Transistor (MOSFET):

At first glance it would appear that there is no path for any current to flow between the source
and the drain terminals since at least one of the p n junctions (source – body and body-Drain) will be reverse
biased for either polarity of the applied voltage between the source and the drain. There is no possibility of
current injection from the gate terminal either since the gate oxide is a very good insulator. However,
application of a positive voltage at the gate terminal with respect to the source will convert the silicon surface
beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to the Drain as explained
next. The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer
and the p-body silicon forms a high quality capacitor. When a small voltage is application to this capacitor
structure with gate terminal positive with respect to the source (note that body and source are shorted) a
depletion region forms at the interface between the SiO .
2
The positive charge induced on the gate metallization repels the majority hole carriers from the
interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors
and a depletion region is created. Further increase in V causes the depletion layer to grow in thickness. At
GS
the same time the electric field at the oxide-silicon interface gets larger and begins to attract free electrons as
shown in Fig (b). The immediate source of electron is electron-hole generation by thermal ionization. The
holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized
by electrons from the source.
As V increases further the density of free electrons at the interface becomes equal to the free hole
GS
density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is
called the inversion layer and is shown in Fig. The inversion layer has all the properties of an n type
semiconductor and is a conductive path or “channel” between the drain and the source which permits flow of
current between the drain and the source. Since current conduction in this device takes place through an n-
type “channel” created by the electric field due to gate source voltage it is called “Enhancement type n-channel
MOSFET”. The value of V at which the inversion layer is considered to have formed is called the “Gate –
GS
Source threshold voltage V (th)”. As V is increased beyond V (th) the inversion layer gets somewhat
GS GS GS
thicker and more conductive, since the density of free electrons increases further with increase in V . The
GS
inversion layer screens the depletion layer adjacent to it from increasing V . The depletion layer thickness
GS
now remains constant.
- 13 -
Circuit Diagram:-
Procedure:-
1. Make connections as shown in circuit diagram.
2. Apply same positive collector to emitter voltage keeping collector at higher potential with gate.
3. Apply gate to emitter voltage at constant VCE and base different values of ICE for Constant value
VCE.
4. Plot graph of VGE VS ICE for constant value of VCE.
5. For dynamic characteristics, apply suitable gate to emitter voltage keeping its constant V GE and
examining the readings VCE and ICE.
6. Plot graph of VCE vs. ICE.
7. Same procedure has to apply for MOSFET characteristics, only terminals are changed.
- 14 -
Observations: -
➢ IGBT:
Transfer characteristics:
VCE = ………….
Sr. No. VGE ICE
1.
2.
3.
4.
5.
Output Characteristics:
VGE = const= ……..
Sr. No. VCE ICE
1.
2.
3.
4.
5.
➢ MOSFET:
Transfer characteristics:
VDS =const= ………….
Sr. No. VGS IDS
1.
2.
3.
4.
5.
Output Characteristics:
VGS = constant=……..
Sr. No. VDS IDS
1.
2.
3.
4.
5.
Result: -
- 15 -
Conclusion:-
Questions:-
i. From the input side the IGBT behaves essentially as a __________________.
ii. When the gate emitter voltage is below __________________ no __________________ layer is
formed in the p type body region.
iii. Electrons arriving through the drive MOSFET causes __________________ injection from the
__________________ to the drain drift region.
iv. In an IGBT most of the collector current flows through the __________________ and not through the
__________________.
v. When the gate-emitter voltage of an IGBT is below threshold if operates in the __________________
region.
vi. In the active region of operation the collector current of an IGBT is determined by the
__________________ characteristics which is reasonably __________________ over most of the
collector current range.
vii. For the same load resistance as the v of an IGBT is increased it enters __________________ region.
gE
viii. The maximum voltage a MOSFET can with stand is ________________ of drain current.
ix. The FBSOA and RBSOA of a MOSFET are ________________.
x. The gate source threshold voltage of a MOSFET ________________ with junction temperature while
the on state resistance ________________ with junction temperature.
xi. The gate oxide of a MOSFET can be damaged by ________________ electricity.
xii. The reverse break down voltage of the body diode of a MOSFET is equal to ________________ while
its RMS forward current rating is equal to ________________.
- 16 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 17 -
Experiment No. 3
Aim: - Study of SCR Gate triggering methods.
Apparatus: Experimental kit, patch chords, CRO, multi-meter etc.
Theory:
1. Resistance gate triggering method:
When connected to an alternating current AC supply, the thyristor behaves differently from
the previous DC connected circuit. Because AC power reverses polarity periodically, any thyristor
used in an AC circuit will automatically be reverse-biased causing it to turn-”OFF” during one-half
of each cycle. Consider the AC thyristor circuit below.
The above circuit is similar in design to the DC SCR circuit except for the omission of an
additional “OFF” switch and the inclusion of diode D1 which prevents reverse bias being applied to
the Gate. During the positive half-cycle of the sinusoidal waveform, the device is forward biased but
with switch S1 open, zero gate current is applied to the thyristor and it remains “OFF”. On the
negative half-cycle, the device is reverse biased and will remain “OFF” regardless of the condition
of switch S1.
If switch S1 is closed, at the beginning of each positive half-cycle the thyristor is fully “OFF”
but shortly after there will be sufficient positive trigger voltage and therefore current present at the
Gate to turn the thyristor and the lamp “ON”. The thyristor is now latched-”ON” for the duration of
the positive half-cycle and will automatically turn “OFF” again when the positive half-cycle ends and
the Anode current falls below the holding current value. During the next negative half-cycle the
device is fully “OFF” anyway until the following positive half-cycle when the process repeats itself
and the thyristor conducts again as long as the switch is closed. Then in this condition the lamp will
receive only half of the available power from the AC source as the thyristor acts like a rectifying
diode, and conducts current only during the positive half-cycles when it is forward biased. The
thyristor continues to supply half power to the lamp until the switch is opened.
If it were possible to rapidly turn switch S1 ON and OFF, so that the thyristor received its Gate
signal at the “peak” (90o) point of each positive half-cycle, the device would only conduct for one
half of the positive half-cycle. In other words, conduction would only take place during one-half of
- 18 -
one-half of a sine wave and this condition would cause the lamp to receive “one-fourth” or a quarter
of the total power available from the AC source. By accurately varying the timing relationship
between the Gate pulse and the positive half-cycle, the Thyristor could be made to supply any
percentage of power desired to the load, between 0% and 50%. Obviously, using this circuit
configuration it cannot supply more than 50% power to the lamp, because it cannot conduct during
the negative half-cycles when it is reverse biased.
Observation Table:
Firing Angle () Output Voltage in Volt
2. RC gate triggering method:
Phase control is the most common form of thyristor AC power control and a basic phase-
control circuit can be constructed as shown above. Here the thyristors Gate voltage is derived from
the RC charging circuit via the trigger diode, D1. During the positive half-cycle when the thyristor is
forward biased, capacitor, C charges up via resistor R1 following the AC supply voltage. The Gate is
activated only when the voltage at point A has risen enough to cause the trigger diode D1, to conduct
and the capacitor discharges into the Gate of the thyristor turning it “ON”. The time duration in the
positive half of the cycle at which conduction starts is controlled by RC time constant set by the
variable resistor, R1. Increasing the value of R1 has the effect of delaying the triggering voltage and
current supplied to the thyristors Gate which in turn causes a lag in the devices conduction time. As
a result, the fraction of the cycle over which the device conducts can be controlled between 0 and
180o, which means that the average power dissipated by lamp can be adjusted. However, the thyristor
is a unidirectional device so only a maximum of 50% power can be supplied.
There are a variety of ways to achieve 100% full-wave AC control using “thyristors”. One
way is to include a single thyristor within a diode bridge rectifier circuit which converts AC to a
unidirectional current through the thyristor while the more common method is to use two thyristors
connected in inverse parallel. A more practical approach is to use a single Triac as this device can be
triggered in both directions, therefore making them suitable for AC switching applications.
- 19 -
Observation Table:
Firing Angle () Output Voltage in Volt
Conclusion:
Questions:
1. What is the use of capacitor in relaxation oscillator?
2. Discuss the application of ramp and pedestal gate triggering method?
- 20 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 21 -
Experiment No: 4
Aim: - Study of Single Phase Semi- Converter.
Apparatus: Experiment kit, CRO, Patch chord, etc.
Theory:
Single Phase Semi- Converter
Single phase fully controlled bridge converters are widely used in many industrial
applications. They can supply unidirectional current with both positive and negative voltage polarity.
Thus they can operate either as a controlled rectifier or an inverter. However, many of the industrial
application do not utilize the inverter mode operation capability of the fully controlled converter. In
such situations a fully controlled converter with four thyristors and their associated control and gate
drive circuit is definitely a more complex and expensive proposition. Single phase fully controlled
converters have other disadvantages as well such as relatively poor output voltage (and current for
lightly inductive load) form factor and input power factor.
The inverter mode of operation of a single phase fully controlled converter is made possible
by the forward voltage blocking capability of the thyristors which allows the output voltage to go
negative. The disadvantages of the single phase fully controlled converter are also related to the same
capability. In order to improve the output voltage and current form factor the negative excursion of
the output voltage may be prevented by connecting a diode across the output as shown in Fig; here
as the output voltage tries to go negative the diode across the load becomes forward bias and clamp
the load voltage to zero. Of course this circuit will not be able to operate in the inverter mode. The
complexity of the circuit is not reduced, however. For that, two of the thyristors of a single phase
fully controlled converter has to be replaced by two diodes as shown in Fig and the resulting
converters are called single phase half controlled converters. The operation of the converter can be
explained as follows when T1 is fired in the positive half cycle of the input voltage. Load current
flows through T1 and D2. If at the negative going zero crossing of the input voltage load current is
still positive it commutates from D2 to D4 and the load voltage becomes zero. If the load current
further continuous till T3 is fired current commutates from T1 to T3. This mode of conduction when
the load current always remains above zero is called the continuous conduction mode. Otherwise the
mode of conduction becomes discontinuous.
Circuit Diagram:
Fig: Single phase half controlled converter
- 22 -
Observation Table:
Firing Angle () Average output voltage (Vo)
Conclusion:
Questions:
i. In a half controlled converter two ___________________ of a fully controlled converter are
replaced by two ___________________
ii. Depending on the positions of the ___________________ the half controlled converter can have
___________________ different circuit topologies.
iii. The input/output waveforms of the two different circuit topologies of a half controlled converter
are ___________________ while the device ratings are ___________________.
iv. A half controlled converter has better output voltage ___________________ compared to a fully
controlled converter.
v. A half controlled converter has improved input ___________________ compared to a fully
controlled converter.
- 23 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 24 -
Experiment No:-05
Aim: -
To study and perform Single Phase Full Controlled Converter
Apparatus:
Experimental kit, Digital Multi-meter, Power Scope. Etc.
Theory: -
Single Phase Full Controlled Converter: -
The single phase fully controlled bridge converter is obtained by replacing all the diode of the
corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together while and T4 are
fired 180° after T1 and T2 for any load current to flow at least one thyristor from the top group (T1,T3) and
one thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1 T3 nor T2
T4can conduct simultaneously. For example whenever T3 and T4 are in the forward blocking state and a gate
pulse is applied to them, they turn ON and at the same time a negative voltage is applied across T1 and T2
commutating them immediately. Similar argument holds for T1 and T2.
For the same reason T1 T4 or T2 T3 cannot conduct simultaneously. Therefore, the only possible
conduction modes when the current i0 can flow are T1 T2 and T3 T4. Of course it is possible that at a given
moment none of the thyristors conduct. This situation will typically occur when the load current becomes zero
in between the firings of T1 T2 and T3 T4. Once the load current becomes zero all thyristors remain off. In
this mode the load current remains zero. Consequently the converter is said to be operating in the discontinuous
conduction mode.
The voltage across different devices and the dc output voltage during each of these conduction modes.
It is to be noted that whenever T1 and T2 conducts, the voltage across T3 and T4 becomes -Vi. Therefore T3
and T4 can be fired only when Vi is negative i.e, over the negative half cycle of the input supply voltage.
Similarly T1 and T2can be fired only over the positive half cycle of the input supply. The voltage across the
devices when none of the thyristors conduct depends on the off state impedance of each device.
- 25 -
Under normal operating condition of the converter the load current may or may not remain zero over
some interval of the input voltage cycle. If I0 is always greater than zero then the converter is said to be
operating in the continuous conduction mode. In this mode of operation of the converter T1 T2 and T3 T4
conducts for alternate half cycle of the input supply.
The average output dc voltage can be obtained as,

2∗𝑉𝑚
Vdc = ×COSα
𝜋
Vm
Vrms = =Vs
√2
Observation Table:
Firing Angle in Degree DC Output Voltage in Volt
Conclusion:
Questions:
1) What is single-phase half controlled converter?

2) What are the different types of single-phase half controlled bride converter?
3) What is inversion and rectification mode 1 phase full converter?
- 26 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 27 -
Experiment No. 06
Aim: -
To study 3 – phase full wave controlled rectifier with R and RL load and to plot input and
output waveforms. .
Apparatus:
Experimental kit, 3-phase variac, DC voltmeter
Theory:
Three phase Controlled Rectifier

Three phase Controlled Rectifier is the circuit which convert 3-phase ac input into fixed or
variable dc output. It is also called converter. SCR is used to obtain controlled rectification.
Freewheeling Diode:
Freewheeling Diode is the diode connected across the inductive load of the rectifier to dissipate
energy stored in the inductor during positive half cycle of the input.
Circuit Diagram:
- 28 -
Procedure:
1. Make Connections as per circuit diagram.
2. Connect resistive load at the output.
3. Switch on the circuit.
4. Observe and plot input and output waveform on oscilloscope.
5. Measure output dc voltage for different firing angles.
6. Replace resistive load with RL load without freewheel diode.
7. Repeat step 4.
8. Connect freewheel diode and repeat step 4.
Observations:
Firing Angle () Average Output Voltage (Vdc= 3Vml/ *
cos)
Conclusions:
Questions:
1. Define line commutation.
2. List the types of three phase-controlled rectifiers with respect to pulse.
3. State why three phase controlled rectifier use line commutation.
4. List advantages of three phase controlled rectifier over single phase- controlled Rectifier.
5. Complete the following diagram.
6. Identify the circuit given in the question 5.
7. Draw the output waveforms for the circuit in question 5.
8. Differentiate three phase full wave controlled rectifier having R load and RL load with respect
to output voltage.
9. Draw the six pulse three phase controlled rectifier.
10. A three-phase full wave rectifier is operated from a three phase Y connected 208 Volts 60 hz
supply and load resistance R = 10 ohms. To obtained 50% of the maximum possible output
voltage, calculate firing angle and rectification efficiency.
11. State the principle of phase control.
12. Justify the statement that the commutation angle depends on the firing angle of rectifiers.
13. List five applications of phase controlled rectifier.
14. Draw the three phase M - 3 rectifier with R load.
15. Describe the effect of source inductance on the performance of three phase full wave rectifier
with the help of phase voltage waveform.
- 29 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 30 -
Experiment No.07
Aim:
To study of armature voltage speed control method of dc shunt motor using MOSFET DC
chopper.
Apparatus:
Experiment Kit, CRO, Patch chords, etc.
Theory:
The speed of a DC Motor is directly proportional to the line voltage applied to it. Given a
fixed DC source, VS, and a Power MOSFET to act as a switch, it is possible to control the
average voltage applied to the motor using a technique called Pulse-Width Modulation
(PWM).
In the circuit shown in Figure 9-1 below, the source voltage, Vs, is “chopped” to
produce an average voltage somewhere between 0% and 100% of Vs. Thus the average value
of the voltage applied to the Motor, Vm, is controlled by closing and opening the “switch”,
Q1. To close the switch, a firing signal is delivered to the gate of the MOSFET, causing it to
conduct between source and drain. To open the switch, the firing signal is removed and the
MOSFET is self-biased to stop conducting. In PWM, the switch is closed and opened every
modulation period.
Circuit Diagram:
- 31 -
The load current is continuous. During Ton, load current rises whereas during Toff, load current
decays. The average load voltage Vo is given by,
𝑇𝑜𝑛
𝑉0 = 𝑉
𝑇𝑜𝑛 + 𝑇𝑜𝑓𝑓 𝑠
𝑇𝑜𝑛
𝑉𝑜 = 𝑇
𝑉 =  Vs
𝑇𝑜𝑛
= 𝑇
; T= Ton + Toff
Switching frequency= F= 1/ T
Vo= F* Ton * Vs
Observation Table:
Sr. T(on) T(off) T=T(on)+T(off) Duty Vo= Vs F= 1/T Speed

No. Cycle() rpm
1.
2.
3.
4.
5.
Calculations:
- 32 -
Conclusion:
Question:
Q1. Classify the DC to DC to converter?
Q2. Draw the four quadrant operation of chopper?
Q3. Q1 SCRs having turn-off times of 8 μsecs is connected in a load-commutated chopper. The load
current is 10 amperes, level. What is the minimum value of commutating capacitor necessary for
successful commutation and what is the corresponding switching frequency? Supply voltage is 20 V DC.
- 33 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 34 -
Experiment No. 08
Aim: To study of single bridge inverter.
Apparatus: Experiment Kit, CRO, Lamp load, Motor load, probes etc.
Theory:
The bipolar junction transistors are current controlled devices. Field effect transistor, on the
other hand do not normally require any input current and are unipolar devices. They involve a single
conducting channel which can be of either N or P type material. The FETs offer advantages in
switching service since they do not suffer the delays associated with minority carrier storage. Because
they also demand no input current, they are easier to drive. They are also less temperature sensitive
and less susceptible to second to drive. They are also less temperature sensitive and less susceptible
to second breakdown in high power applications. All JFETs are operated with reverse bias on their
gate leads to prevent gate current. However a large input signal may momentarily overcome the revere
bias and turn on gate diodes drawing appreciable current from the source. These disadvantages are
overcome by insulating the gate terminal from the channel with a thin layer of silicon dioxide
(metallic oxide). Those FETs that use this technique are known as metallic oxide semiconductor field
effect transistor or MOSFETs.
MOSFETs are operated in depletion mode as do JFETs with negative voltage on the gate terminal for
N channel device. Depletion mode operated devices are normally in ON condition. The MOSFETs
may also be operated in the enhancement mode. In this mode the device is normally in OFF condition
and a sufficiently large positive voltage on the gate terminal can turn on the device. In this mode the
device is normally in OFF condition and a sufficiently large positive voltage on the gate terminal can
turn on the device. Generally power enhancement MOSFETs are used in power electronics circuits.
Its structure with normal biasing of N channel enhancement MOSFET is shown in figure 1 with the
circuit symbol. A metallic gate is deposited on the thin layer of metal oxide (insulator) which is
deposited on the channel opposite to the substrate. Due to insulated gate, negligible gate current flows.
The power enhancement MOSFT has anti parallel fast turn on diode which permits reverse current
of the same magnitude as that of the main MOSFET, so that drain substrate so that drain substrate
junction will not be damaged when drain and source has reverse biasing.
Applications:
The enhancement MOSFET is used as a switch in power electronics by keeping sufficient
gate voltage (Vgs) so that it conducts in the constant resistance region. The conduction lost of the
MOSFET is high due to large value of device resistance in the ON state. The MOSFET can be
triggered directly from the COMS or other gate due to high input impedance. Switching times (Turn
ON and Turn OFF) are very low and switching loss is almost nil. The gate drive power is also
negligible. They have larger gains and simple and cheaper triggering circuits. It has only one
disadvantage i. e. higher conduction drop generally five times more than the power transistor of the
same rating.
Description of the set up:
This set up is designed to demonstrate the working of a typical single phase inverter using
power MOSFETs in bridge configuration. The inverter works at low frequency (typically 50 Hz or
so) and around 500 Hz. This frequency is variable. For low frequency output, i. e. 50 Hz, 230 volt,
- 35 -
40 watt lamp load is provided through step up transformer. For higher frequency application only a
resistance load of 25 ohms is provided. The panel layout is shown in figure 2.
The set up has built in D.C. power supply at 18 volts, 3 ampere and this D.C. power supplies 5 volts
for logic gates, 12 volts,12 volts and 12 volts (all isolated) for opt isolator operated driver circuits.TR1
is main step down transformer, TR2 for auxiliary power supplies and TR3 is step up output
transformer. The power MOSFET are arranged in bridge configuration and driven by appropriate
driver stages. The entire system is mounted on a neatly labeled anodized plate indicating various
controls very clearly. Appropriate test points are provided.
Operation of the set up:

Fig shows the power circuit of the MOSFEET driven single phase inverter. The MOSFETs
are in bridge configuration. Fig No.3 A shows the gate to drain voltage waveforms (Vg1, Vg2, Vg3
and Vg4) required by the power MOSFET for necessary operation. When T1 and T3 are turned ON
by the gate signals VG1 and Vg3, the current flows through point B to A and results in a positive half
cycle of the output.
In order to avoid the shorting of the D.C. power supply with all T1, T2, T3 and T4 power
MOSFETs in ON condition, a special trick is used to remove the gate drives before. 15 msec. just
before the transition takes place i. e. at the time of expected turn ON, all the gate drives are removed.
This delay is generated by mono stable IC 74121. The logic generated by IC 7486 Exclusive OR gate
provides the necessary gate drive for all the power MOSFETs. Refer Fig.4 for details of gate driven
circuitry. By changing the timing capacitor of unstable multi vibrator (555) we can gate two
frequencies (around 50 Hz and around 500Hz) variable by potentiometer P1. Switch SW2 offers
changeover from high frequency (upward position), with simultaneous switching of load also. For
low frequency (50Hz) transformer load with 40 watt lamp is placed on the output of the inverter. For
high frequency only resistance load is applied. You can observe basic clock signal at TP1 with respect
to the ground and gate drives for T1and T3 at TP2 and the same for T2 and T4 atTP3. If you observe
waveforms across TP2 and TP3, low voltage version of the output waveform is seen on the C.R.O.
Control signals are continuously generated as soon as mains power is switched ON. But D.
C. power is supplied to the inverter, only when the link across the binding posts on the panel is used.
Operating Instructions-
1. Get yourself conversant with the various blocks of the entire system. Try to understand
the function of the various controls on the panel board of the system.
2. Ensure that the link between the binding posts marked (LINK OR AMMETER) is open.
This link provides main D. C. power as input to the inverter.
3. Keep the switch SW2 in upward position (high frequency position). Connect the C. R.
O. betweenTP1 and ground.
4. Now switch ON the mains supply and observe the waveforms for the basic clock
frequency for the inverter, switching waveforms for transistors T1 & T3 and T2 & T4
at test points TP2 &TP3 respectively.
5. Now keep the switch SW2 in upward position and connect the C. R. O. across the
binding post for output (lower right corner).
6. Now place the link across the binding post marked (LINK or Ammeter). The D.C.
power is supplied to the inverter and inversion operation starts indicated by the output
waveforms across the C. R. O. screen. Note that already a load resistance of 25 ohms/
25watts is internally connected across the output.
- 36 -
7. Change the frequency of the output by operating the potentiometer P1. Observe the
discontinuity in the waveform at zero transition.
8. Now remove the link and switch on the SW2 in lower position. Ensure that the lamp
40 watt/230volts is in place. Now if the D. C. link is put ON, the lamp glows with full
intensity. You may observe the waveforms across the output terminals marked lamp
load. Lamp load is in operation only for low frequency operation.
9. Study the operation of opt isolator circuitry provided for isolation of triggering source
and he gate and drain circuits of transistor T1 & T2. Note that the 12 volts supplies for
T1 and T2 driven are completely isolated as S1 and S2 (drains for T1 & T2) are
completely isolated with respect to the main ground. For T3 & T4, we note that triggers
source ground and main supply ground are the same.
Precautions
1. Do not short the D. C. power supply by placing a link across the input binding posts
(Red and black). Do not short the test points by the links provided.
2. While changing the SW2, always disconnect the D. C. power input to the inverter and
only then effect the change.
3. Note that waveform on low voltage side are to be observed for protection of C.R. O.
Circuit Diagram:
Observation Table:
Sr. No. Wavelength(T) F= 1/T in Hz Vo in volt
- 37 -
Conclusion:
Questions:
Q1. Explain PWM technique?
Q2. How harmonics can be removed at the output of inverter?
Q3. How can control the output voltage of inverter?
Q4. What is the difference between single phase half and full bridge inverter?
- 38 -
Ashta
Name:
Class: Div: Batch
Title of the
Experiment:
- 39 -
Experiment No. 09
Title: Simulation of Three Phase AC TO DC Half wave uncontrolled rectifier.
Circuit Diagram for R Load:
Circuit Description
A 10 ohm load is fed in DC through a three-phase rectifier from an inductive source (5 mH; 120 V
rms). The rectified current is filtered by a 200mH inductance.
Diodes are connected in parallel with RC snubbers (1000 ohms-0.1 uF) The measurement outputs of
Diode2 and Diode3 is used to observe the diode voltage and current.
Demonstration
1. Simulation with continuous integration method
Check the simulation parameters in the Simulation/Configuration Parameters menu The following
integration algorithm should be used: Variable time step ode23tb with default parameters. Start the
simulation and observe waveforms on the four-trace Scope block.
- 40 -
After a transient period the load current Id stabilizes at 12.7 A. Note that most of the third harmonic
which can be seen in the rectified voltage Vd (mean value 127 V) is filtered out by the smoothing
reactor.
Observe also the commutation period due to the source inductances. The 3.3 degrees overlap is clearly
seen on trace 3 of the scope showing currents in diodes 2 and 3.
Zoom on the Diode3 voltage (trace 4) during the conduction period. The voltage magnitude is the
sum of the specified forward voltage (0.8 V) and the voltage developed across the diode resistance
(0.01 ohm).
2. Simulation with discretized system
Open the Powergui block menu. Select discrete electrical model and specify a sample time of 50e-
6 secs. Restart the simulation.
Your system is now discretized and simulated at fixed time steps. Compare waveforms with those
obtained with the continuous integration algorithm (ode23tb)
Results:
Questions:
1. What is inversion mode of operation?
2. When we connect a freewheeling diode in full converter, what will be the output?
3. Why the inversion mode is not possible in semi converter?
4. Why the power factor of full converter is lower than semi converter?
5. What is the function of scope in MATLAB?
6. Why inductors are connected in series with voltage source?
- 41 -

PE 1EEPC353 Laboratory

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

PE 1EEPC353 Laboratory

Uploaded by

Copyright:

Available Formats

Annasaheb Dange College of Engineering

& Technology, Ashta

Department of Electrical Engineering

[1EEPC353] Power Electronics Laboratory

Name: - Prof. Vishal B. Patil

INSTRUCTIONS TO THE CANDIDATE

MAY I HELP YOU

1. Device ratings should be noted.

1. I-V characteristics of SCR

2. Output characteristics. of MOSFET and IGBT

3. SCR gate triggering methods.

4. Single Phase Semi- Converter.

5. Single Phase Full- Converter.

6. Three Phase Full Converter.

7. DC chopper using Power MOSFET

8. To study of single bridge inverter.

*Simulation of Three 1 ph, 3 ph, AC TO DC

10. Step down MOSFET based chopper

Course: [1EEPC353] Power Electronics Laboratory

Class: Div: Batch

Date of Conduction: Date of Submission:

Grade/CAS Marks: Signature of Course Instructor/Teacher

Silicon Controlled Rectifier (SCR):

Forward break over voltage

I-V Characteristics of SCR:

(B) Measurement of Latching current:

(C) Measurement of Holding current:

(D) I - V characteristics of SCR.

Ig1 (mA) =……. Ig2 =…….mA

a. Break over voltage at lg1 = …. …mA is ............................................. volts.

Course: [1EEPC353] Power Electronics Laboratory

Class: Div: Batch

Date of Conduction: Date of Submission:

Grade/CAS Marks: Signature of Course Instructor/Teacher

Aim: - To Study and plot output characteristics of MOSFET and IGBT.

Apparatus: - Experimental kit, Patch chord, multimeter etc.

Metal-Oxide Semiconductor Field Effect Transistor (MOSFET):

ix. The FBSOA and RBSOA of a MOSFET are ________________.

xi. The gate oxide of a MOSFET can be damaged by ________________ electricity.

Course: [1EEPC353] Power Electronics Laboratory

Class: Div: Batch

Date of Conduction: Date of Submission:

Grade/CAS Marks: Signature of Course Instructor/Teacher

Aim: - Study of SCR Gate triggering methods.

Apparatus: Experimental kit, patch chords, CRO, multi-meter etc.

1. Resistance gate triggering method:

Firing Angle () Output Voltage in Volt

2. RC gate triggering method:

Firing Angle () Output Voltage in Volt

Course: [1EEPC353] Power Electronics Laboratory

Class: Div: Batch

Date of Conduction: Date of Submission:

Grade/CAS Marks: Signature of Course Instructor/Teacher

Apparatus: Experiment kit, CRO, Patch chord, etc.

Single Phase Semi- Converter

Fig: Single phase half controlled converter

Firing Angle () Average output voltage (Vo)

Course: [1EEPC353] Power Electronics Laboratory

Class: Div: Batch

Date of Conduction: Date of Submission:

Grade/CAS Marks: Signature of Course Instructor/Teacher

Single Phase Full Controlled Converter: -

The average output dc voltage can be obtained as,

1) What is single-phase half controlled converter?